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[mirror_ubuntu-bionic-kernel.git] / drivers / ata / sata_promise.c
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.05"
50
51
52 enum {
53 /* register offsets */
54 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
55 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
56 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
57 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
58 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
59 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
60 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
61 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
62 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
63 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
64 PDC_FLASH_CTL = 0x44, /* Flash control register */
65 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
66 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
67 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
68 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
69 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
70 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
71
72 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
73 (1<<8) | (1<<9) | (1<<10),
74
75 board_2037x = 0, /* FastTrak S150 TX2plus */
76 board_20319 = 1, /* FastTrak S150 TX4 */
77 board_20619 = 2, /* FastTrak TX4000 */
78 board_2057x = 3, /* SATAII150 Tx2plus */
79 board_40518 = 4, /* SATAII150 Tx4 */
80
81 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
82
83 /* Sequence counter control registers bit definitions */
84 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
85
86 /* Feature register values */
87 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
88 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
89
90 /* Device/Head register values */
91 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
92
93 /* PDC_CTLSTAT bit definitions */
94 PDC_DMA_ENABLE = (1 << 7),
95 PDC_IRQ_DISABLE = (1 << 10),
96 PDC_RESET = (1 << 11), /* HDMA reset */
97
98 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
99 ATA_FLAG_MMIO |
100 ATA_FLAG_PIO_POLLING,
101
102 /* hp->flags bits */
103 PDC_FLAG_GEN_II = (1 << 0),
104 };
105
106
107 struct pdc_port_priv {
108 u8 *pkt;
109 dma_addr_t pkt_dma;
110 };
111
112 struct pdc_host_priv {
113 unsigned long flags;
114 unsigned long port_flags[ATA_MAX_PORTS];
115 };
116
117 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
118 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
119 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
120 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
121 static void pdc_eng_timeout(struct ata_port *ap);
122 static int pdc_port_start(struct ata_port *ap);
123 static void pdc_pata_phy_reset(struct ata_port *ap);
124 static void pdc_qc_prep(struct ata_queued_cmd *qc);
125 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
126 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
127 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
128 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc);
129 static void pdc_irq_clear(struct ata_port *ap);
130 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
131 static void pdc_freeze(struct ata_port *ap);
132 static void pdc_thaw(struct ata_port *ap);
133 static void pdc_error_handler(struct ata_port *ap);
134 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
135
136
137 static struct scsi_host_template pdc_ata_sht = {
138 .module = THIS_MODULE,
139 .name = DRV_NAME,
140 .ioctl = ata_scsi_ioctl,
141 .queuecommand = ata_scsi_queuecmd,
142 .can_queue = ATA_DEF_QUEUE,
143 .this_id = ATA_SHT_THIS_ID,
144 .sg_tablesize = LIBATA_MAX_PRD,
145 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
146 .emulated = ATA_SHT_EMULATED,
147 .use_clustering = ATA_SHT_USE_CLUSTERING,
148 .proc_name = DRV_NAME,
149 .dma_boundary = ATA_DMA_BOUNDARY,
150 .slave_configure = ata_scsi_slave_config,
151 .slave_destroy = ata_scsi_slave_destroy,
152 .bios_param = ata_std_bios_param,
153 };
154
155 static const struct ata_port_operations pdc_sata_ops = {
156 .port_disable = ata_port_disable,
157 .tf_load = pdc_tf_load_mmio,
158 .tf_read = ata_tf_read,
159 .check_status = ata_check_status,
160 .exec_command = pdc_exec_command_mmio,
161 .dev_select = ata_std_dev_select,
162 .check_atapi_dma = pdc_check_atapi_dma,
163
164 .qc_prep = pdc_qc_prep,
165 .qc_issue = pdc_qc_issue_prot,
166 .freeze = pdc_freeze,
167 .thaw = pdc_thaw,
168 .error_handler = pdc_error_handler,
169 .post_internal_cmd = pdc_post_internal_cmd,
170 .data_xfer = ata_mmio_data_xfer,
171 .irq_handler = pdc_interrupt,
172 .irq_clear = pdc_irq_clear,
173
174 .scr_read = pdc_sata_scr_read,
175 .scr_write = pdc_sata_scr_write,
176 .port_start = pdc_port_start,
177 };
178
179 /* First-generation chips need a more restrictive ->check_atapi_dma op */
180 static const struct ata_port_operations pdc_old_sata_ops = {
181 .port_disable = ata_port_disable,
182 .tf_load = pdc_tf_load_mmio,
183 .tf_read = ata_tf_read,
184 .check_status = ata_check_status,
185 .exec_command = pdc_exec_command_mmio,
186 .dev_select = ata_std_dev_select,
187 .check_atapi_dma = pdc_old_check_atapi_dma,
188
189 .qc_prep = pdc_qc_prep,
190 .qc_issue = pdc_qc_issue_prot,
191 .freeze = pdc_freeze,
192 .thaw = pdc_thaw,
193 .error_handler = pdc_error_handler,
194 .post_internal_cmd = pdc_post_internal_cmd,
195 .data_xfer = ata_mmio_data_xfer,
196 .irq_handler = pdc_interrupt,
197 .irq_clear = pdc_irq_clear,
198
199 .scr_read = pdc_sata_scr_read,
200 .scr_write = pdc_sata_scr_write,
201 .port_start = pdc_port_start,
202 };
203
204 static const struct ata_port_operations pdc_pata_ops = {
205 .port_disable = ata_port_disable,
206 .tf_load = pdc_tf_load_mmio,
207 .tf_read = ata_tf_read,
208 .check_status = ata_check_status,
209 .exec_command = pdc_exec_command_mmio,
210 .dev_select = ata_std_dev_select,
211 .check_atapi_dma = pdc_check_atapi_dma,
212
213 .phy_reset = pdc_pata_phy_reset,
214
215 .qc_prep = pdc_qc_prep,
216 .qc_issue = pdc_qc_issue_prot,
217 .data_xfer = ata_mmio_data_xfer,
218 .eng_timeout = pdc_eng_timeout,
219 .irq_handler = pdc_interrupt,
220 .irq_clear = pdc_irq_clear,
221
222 .port_start = pdc_port_start,
223 };
224
225 static const struct ata_port_info pdc_port_info[] = {
226 /* board_2037x */
227 {
228 .sht = &pdc_ata_sht,
229 .flags = PDC_COMMON_FLAGS,
230 .pio_mask = 0x1f, /* pio0-4 */
231 .mwdma_mask = 0x07, /* mwdma0-2 */
232 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
233 .port_ops = &pdc_old_sata_ops,
234 },
235
236 /* board_20319 */
237 {
238 .sht = &pdc_ata_sht,
239 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
240 .pio_mask = 0x1f, /* pio0-4 */
241 .mwdma_mask = 0x07, /* mwdma0-2 */
242 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
243 .port_ops = &pdc_old_sata_ops,
244 },
245
246 /* board_20619 */
247 {
248 .sht = &pdc_ata_sht,
249 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
250 .pio_mask = 0x1f, /* pio0-4 */
251 .mwdma_mask = 0x07, /* mwdma0-2 */
252 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
253 .port_ops = &pdc_pata_ops,
254 },
255
256 /* board_2057x */
257 {
258 .sht = &pdc_ata_sht,
259 .flags = PDC_COMMON_FLAGS,
260 .pio_mask = 0x1f, /* pio0-4 */
261 .mwdma_mask = 0x07, /* mwdma0-2 */
262 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
263 .port_ops = &pdc_sata_ops,
264 },
265
266 /* board_40518 */
267 {
268 .sht = &pdc_ata_sht,
269 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
270 .pio_mask = 0x1f, /* pio0-4 */
271 .mwdma_mask = 0x07, /* mwdma0-2 */
272 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
273 .port_ops = &pdc_sata_ops,
274 },
275 };
276
277 static const struct pci_device_id pdc_ata_pci_tbl[] = {
278 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
279 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
280 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
281 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
282 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
283 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
284 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
285 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
286 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
287 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
288
289 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
290 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
291 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
292 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
293 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
294 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
295
296 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
297
298 { } /* terminate list */
299 };
300
301
302 static struct pci_driver pdc_ata_pci_driver = {
303 .name = DRV_NAME,
304 .id_table = pdc_ata_pci_tbl,
305 .probe = pdc_ata_init_one,
306 .remove = ata_pci_remove_one,
307 };
308
309
310 static int pdc_port_start(struct ata_port *ap)
311 {
312 struct device *dev = ap->host->dev;
313 struct pdc_host_priv *hp = ap->host->private_data;
314 struct pdc_port_priv *pp;
315 int rc;
316
317 /* fix up port flags and cable type for SATA+PATA chips */
318 ap->flags |= hp->port_flags[ap->port_no];
319 if (ap->flags & ATA_FLAG_SATA)
320 ap->cbl = ATA_CBL_SATA;
321
322 rc = ata_port_start(ap);
323 if (rc)
324 return rc;
325
326 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
327 if (!pp)
328 return -ENOMEM;
329
330 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
331 if (!pp->pkt)
332 return -ENOMEM;
333
334 ap->private_data = pp;
335
336 /* fix up PHYMODE4 align timing */
337 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
338 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
339 unsigned int tmp;
340
341 tmp = readl(mmio + 0x014);
342 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
343 writel(tmp, mmio + 0x014);
344 }
345
346 return 0;
347 }
348
349 static void pdc_reset_port(struct ata_port *ap)
350 {
351 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
352 unsigned int i;
353 u32 tmp;
354
355 for (i = 11; i > 0; i--) {
356 tmp = readl(mmio);
357 if (tmp & PDC_RESET)
358 break;
359
360 udelay(100);
361
362 tmp |= PDC_RESET;
363 writel(tmp, mmio);
364 }
365
366 tmp &= ~PDC_RESET;
367 writel(tmp, mmio);
368 readl(mmio); /* flush */
369 }
370
371 static void pdc_pata_cbl_detect(struct ata_port *ap)
372 {
373 u8 tmp;
374 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
375
376 tmp = readb(mmio);
377
378 if (tmp & 0x01) {
379 ap->cbl = ATA_CBL_PATA40;
380 ap->udma_mask &= ATA_UDMA_MASK_40C;
381 } else
382 ap->cbl = ATA_CBL_PATA80;
383 }
384
385 static void pdc_pata_phy_reset(struct ata_port *ap)
386 {
387 pdc_pata_cbl_detect(ap);
388 pdc_reset_port(ap);
389 ata_port_probe(ap);
390 ata_bus_reset(ap);
391 }
392
393 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
394 {
395 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
396 return 0xffffffffU;
397 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
398 }
399
400
401 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
402 u32 val)
403 {
404 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
405 return;
406 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
407 }
408
409 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
410 {
411 struct ata_port *ap = qc->ap;
412 dma_addr_t sg_table = ap->prd_dma;
413 unsigned int cdb_len = qc->dev->cdb_len;
414 u8 *cdb = qc->cdb;
415 struct pdc_port_priv *pp = ap->private_data;
416 u8 *buf = pp->pkt;
417 u32 *buf32 = (u32 *) buf;
418 unsigned int dev_sel, feature, nbytes;
419
420 /* set control bits (byte 0), zero delay seq id (byte 3),
421 * and seq id (byte 2)
422 */
423 switch (qc->tf.protocol) {
424 case ATA_PROT_ATAPI_DMA:
425 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
426 buf32[0] = cpu_to_le32(PDC_PKT_READ);
427 else
428 buf32[0] = 0;
429 break;
430 case ATA_PROT_ATAPI_NODATA:
431 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
432 break;
433 default:
434 BUG();
435 break;
436 }
437 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
438 buf32[2] = 0; /* no next-packet */
439
440 /* select drive */
441 if (sata_scr_valid(ap)) {
442 dev_sel = PDC_DEVICE_SATA;
443 } else {
444 dev_sel = ATA_DEVICE_OBS;
445 if (qc->dev->devno != 0)
446 dev_sel |= ATA_DEV1;
447 }
448 buf[12] = (1 << 5) | ATA_REG_DEVICE;
449 buf[13] = dev_sel;
450 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
451 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
452
453 buf[16] = (1 << 5) | ATA_REG_NSECT;
454 buf[17] = 0x00;
455 buf[18] = (1 << 5) | ATA_REG_LBAL;
456 buf[19] = 0x00;
457
458 /* set feature and byte counter registers */
459 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
460 feature = PDC_FEATURE_ATAPI_PIO;
461 /* set byte counter register to real transfer byte count */
462 nbytes = qc->nbytes;
463 if (nbytes > 0xffff)
464 nbytes = 0xffff;
465 } else {
466 feature = PDC_FEATURE_ATAPI_DMA;
467 /* set byte counter register to 0 */
468 nbytes = 0;
469 }
470 buf[20] = (1 << 5) | ATA_REG_FEATURE;
471 buf[21] = feature;
472 buf[22] = (1 << 5) | ATA_REG_BYTEL;
473 buf[23] = nbytes & 0xFF;
474 buf[24] = (1 << 5) | ATA_REG_BYTEH;
475 buf[25] = (nbytes >> 8) & 0xFF;
476
477 /* send ATAPI packet command 0xA0 */
478 buf[26] = (1 << 5) | ATA_REG_CMD;
479 buf[27] = ATA_CMD_PACKET;
480
481 /* select drive and check DRQ */
482 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
483 buf[29] = dev_sel;
484
485 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
486 BUG_ON(cdb_len & ~0x1E);
487
488 /* append the CDB as the final part */
489 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
490 memcpy(buf+31, cdb, cdb_len);
491 }
492
493 static void pdc_qc_prep(struct ata_queued_cmd *qc)
494 {
495 struct pdc_port_priv *pp = qc->ap->private_data;
496 unsigned int i;
497
498 VPRINTK("ENTER\n");
499
500 switch (qc->tf.protocol) {
501 case ATA_PROT_DMA:
502 ata_qc_prep(qc);
503 /* fall through */
504
505 case ATA_PROT_NODATA:
506 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
507 qc->dev->devno, pp->pkt);
508
509 if (qc->tf.flags & ATA_TFLAG_LBA48)
510 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
511 else
512 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
513
514 pdc_pkt_footer(&qc->tf, pp->pkt, i);
515 break;
516
517 case ATA_PROT_ATAPI:
518 ata_qc_prep(qc);
519 break;
520
521 case ATA_PROT_ATAPI_DMA:
522 ata_qc_prep(qc);
523 /*FALLTHROUGH*/
524 case ATA_PROT_ATAPI_NODATA:
525 pdc_atapi_pkt(qc);
526 break;
527
528 default:
529 break;
530 }
531 }
532
533 static void pdc_freeze(struct ata_port *ap)
534 {
535 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
536 u32 tmp;
537
538 tmp = readl(mmio + PDC_CTLSTAT);
539 tmp |= PDC_IRQ_DISABLE;
540 tmp &= ~PDC_DMA_ENABLE;
541 writel(tmp, mmio + PDC_CTLSTAT);
542 readl(mmio + PDC_CTLSTAT); /* flush */
543 }
544
545 static void pdc_thaw(struct ata_port *ap)
546 {
547 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
548 u32 tmp;
549
550 /* clear IRQ */
551 readl(mmio + PDC_INT_SEQMASK);
552
553 /* turn IRQ back on */
554 tmp = readl(mmio + PDC_CTLSTAT);
555 tmp &= ~PDC_IRQ_DISABLE;
556 writel(tmp, mmio + PDC_CTLSTAT);
557 readl(mmio + PDC_CTLSTAT); /* flush */
558 }
559
560 static void pdc_error_handler(struct ata_port *ap)
561 {
562 ata_reset_fn_t hardreset;
563
564 if (!(ap->pflags & ATA_PFLAG_FROZEN))
565 pdc_reset_port(ap);
566
567 hardreset = NULL;
568 if (sata_scr_valid(ap))
569 hardreset = sata_std_hardreset;
570
571 /* perform recovery */
572 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
573 ata_std_postreset);
574 }
575
576 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
577 {
578 struct ata_port *ap = qc->ap;
579
580 if (qc->flags & ATA_QCFLAG_FAILED)
581 qc->err_mask |= AC_ERR_OTHER;
582
583 /* make DMA engine forget about the failed command */
584 if (qc->err_mask)
585 pdc_reset_port(ap);
586 }
587
588 static void pdc_eng_timeout(struct ata_port *ap)
589 {
590 struct ata_host *host = ap->host;
591 u8 drv_stat;
592 struct ata_queued_cmd *qc;
593 unsigned long flags;
594
595 DPRINTK("ENTER\n");
596
597 spin_lock_irqsave(&host->lock, flags);
598
599 qc = ata_qc_from_tag(ap, ap->active_tag);
600
601 switch (qc->tf.protocol) {
602 case ATA_PROT_DMA:
603 case ATA_PROT_NODATA:
604 ata_port_printk(ap, KERN_ERR, "command timeout\n");
605 drv_stat = ata_wait_idle(ap);
606 qc->err_mask |= __ac_err_mask(drv_stat);
607 break;
608
609 default:
610 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
611
612 ata_port_printk(ap, KERN_ERR,
613 "unknown timeout, cmd 0x%x stat 0x%x\n",
614 qc->tf.command, drv_stat);
615
616 qc->err_mask |= ac_err_mask(drv_stat);
617 break;
618 }
619
620 spin_unlock_irqrestore(&host->lock, flags);
621 ata_eh_qc_complete(qc);
622 DPRINTK("EXIT\n");
623 }
624
625 static inline unsigned int pdc_host_intr( struct ata_port *ap,
626 struct ata_queued_cmd *qc)
627 {
628 unsigned int handled = 0;
629 u32 tmp;
630 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
631
632 tmp = readl(mmio);
633 if (tmp & PDC_ERR_MASK) {
634 qc->err_mask |= AC_ERR_DEV;
635 pdc_reset_port(ap);
636 }
637
638 switch (qc->tf.protocol) {
639 case ATA_PROT_DMA:
640 case ATA_PROT_NODATA:
641 case ATA_PROT_ATAPI_DMA:
642 case ATA_PROT_ATAPI_NODATA:
643 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
644 ata_qc_complete(qc);
645 handled = 1;
646 break;
647
648 default:
649 ap->stats.idle_irq++;
650 break;
651 }
652
653 return handled;
654 }
655
656 static void pdc_irq_clear(struct ata_port *ap)
657 {
658 struct ata_host *host = ap->host;
659 void __iomem *mmio = host->mmio_base;
660
661 readl(mmio + PDC_INT_SEQMASK);
662 }
663
664 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
665 {
666 struct ata_host *host = dev_instance;
667 struct ata_port *ap;
668 u32 mask = 0;
669 unsigned int i, tmp;
670 unsigned int handled = 0;
671 void __iomem *mmio_base;
672
673 VPRINTK("ENTER\n");
674
675 if (!host || !host->mmio_base) {
676 VPRINTK("QUICK EXIT\n");
677 return IRQ_NONE;
678 }
679
680 mmio_base = host->mmio_base;
681
682 /* reading should also clear interrupts */
683 mask = readl(mmio_base + PDC_INT_SEQMASK);
684
685 if (mask == 0xffffffff) {
686 VPRINTK("QUICK EXIT 2\n");
687 return IRQ_NONE;
688 }
689
690 spin_lock(&host->lock);
691
692 mask &= 0xffff; /* only 16 tags possible */
693 if (!mask) {
694 VPRINTK("QUICK EXIT 3\n");
695 goto done_irq;
696 }
697
698 writel(mask, mmio_base + PDC_INT_SEQMASK);
699
700 for (i = 0; i < host->n_ports; i++) {
701 VPRINTK("port %u\n", i);
702 ap = host->ports[i];
703 tmp = mask & (1 << (i + 1));
704 if (tmp && ap &&
705 !(ap->flags & ATA_FLAG_DISABLED)) {
706 struct ata_queued_cmd *qc;
707
708 qc = ata_qc_from_tag(ap, ap->active_tag);
709 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
710 handled += pdc_host_intr(ap, qc);
711 }
712 }
713
714 VPRINTK("EXIT\n");
715
716 done_irq:
717 spin_unlock(&host->lock);
718 return IRQ_RETVAL(handled);
719 }
720
721 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
722 {
723 struct ata_port *ap = qc->ap;
724 struct pdc_port_priv *pp = ap->private_data;
725 unsigned int port_no = ap->port_no;
726 u8 seq = (u8) (port_no + 1);
727
728 VPRINTK("ENTER, ap %p\n", ap);
729
730 writel(0x00000001, ap->host->mmio_base + (seq * 4));
731 readl(ap->host->mmio_base + (seq * 4)); /* flush */
732
733 pp->pkt[2] = seq;
734 wmb(); /* flush PRD, pkt writes */
735 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
736 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
737 }
738
739 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
740 {
741 switch (qc->tf.protocol) {
742 case ATA_PROT_ATAPI_NODATA:
743 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
744 break;
745 /*FALLTHROUGH*/
746 case ATA_PROT_ATAPI_DMA:
747 case ATA_PROT_DMA:
748 case ATA_PROT_NODATA:
749 pdc_packet_start(qc);
750 return 0;
751
752 default:
753 break;
754 }
755
756 return ata_qc_issue_prot(qc);
757 }
758
759 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
760 {
761 WARN_ON (tf->protocol == ATA_PROT_DMA ||
762 tf->protocol == ATA_PROT_NODATA);
763 ata_tf_load(ap, tf);
764 }
765
766
767 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
768 {
769 WARN_ON (tf->protocol == ATA_PROT_DMA ||
770 tf->protocol == ATA_PROT_NODATA);
771 ata_exec_command(ap, tf);
772 }
773
774 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
775 {
776 u8 *scsicmd = qc->scsicmd->cmnd;
777 int pio = 1; /* atapi dma off by default */
778
779 /* Whitelist commands that may use DMA. */
780 switch (scsicmd[0]) {
781 case WRITE_12:
782 case WRITE_10:
783 case WRITE_6:
784 case READ_12:
785 case READ_10:
786 case READ_6:
787 case 0xad: /* READ_DVD_STRUCTURE */
788 case 0xbe: /* READ_CD */
789 pio = 0;
790 }
791 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
792 if (scsicmd[0] == WRITE_10) {
793 unsigned int lba;
794 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
795 if (lba >= 0xFFFF4FA2)
796 pio = 1;
797 }
798 return pio;
799 }
800
801 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc)
802 {
803 struct ata_port *ap = qc->ap;
804
805 /* First generation chips cannot use ATAPI DMA on SATA ports */
806 if (sata_scr_valid(ap))
807 return 1;
808 return pdc_check_atapi_dma(qc);
809 }
810
811 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
812 {
813 port->cmd_addr = base;
814 port->data_addr = base;
815 port->feature_addr =
816 port->error_addr = base + 0x4;
817 port->nsect_addr = base + 0x8;
818 port->lbal_addr = base + 0xc;
819 port->lbam_addr = base + 0x10;
820 port->lbah_addr = base + 0x14;
821 port->device_addr = base + 0x18;
822 port->command_addr =
823 port->status_addr = base + 0x1c;
824 port->altstatus_addr =
825 port->ctl_addr = base + 0x38;
826 }
827
828
829 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
830 {
831 void __iomem *mmio = pe->mmio_base;
832 struct pdc_host_priv *hp = pe->private_data;
833 int hotplug_offset;
834 u32 tmp;
835
836 if (hp->flags & PDC_FLAG_GEN_II)
837 hotplug_offset = PDC2_SATA_PLUG_CSR;
838 else
839 hotplug_offset = PDC_SATA_PLUG_CSR;
840
841 /*
842 * Except for the hotplug stuff, this is voodoo from the
843 * Promise driver. Label this entire section
844 * "TODO: figure out why we do this"
845 */
846
847 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
848 tmp = readl(mmio + PDC_FLASH_CTL);
849 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
850 if (!(hp->flags & PDC_FLAG_GEN_II))
851 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
852 writel(tmp, mmio + PDC_FLASH_CTL);
853
854 /* clear plug/unplug flags for all ports */
855 tmp = readl(mmio + hotplug_offset);
856 writel(tmp | 0xff, mmio + hotplug_offset);
857
858 /* mask plug/unplug ints */
859 tmp = readl(mmio + hotplug_offset);
860 writel(tmp | 0xff0000, mmio + hotplug_offset);
861
862 /* don't initialise TBG or SLEW on 2nd generation chips */
863 if (hp->flags & PDC_FLAG_GEN_II)
864 return;
865
866 /* reduce TBG clock to 133 Mhz. */
867 tmp = readl(mmio + PDC_TBG_MODE);
868 tmp &= ~0x30000; /* clear bit 17, 16*/
869 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
870 writel(tmp, mmio + PDC_TBG_MODE);
871
872 readl(mmio + PDC_TBG_MODE); /* flush */
873 msleep(10);
874
875 /* adjust slew rate control register. */
876 tmp = readl(mmio + PDC_SLEW_CTL);
877 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
878 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
879 writel(tmp, mmio + PDC_SLEW_CTL);
880 }
881
882 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
883 {
884 static int printed_version;
885 struct ata_probe_ent *probe_ent;
886 struct pdc_host_priv *hp;
887 unsigned long base;
888 void __iomem *mmio_base;
889 unsigned int board_idx = (unsigned int) ent->driver_data;
890 int rc;
891 u8 tmp;
892
893 if (!printed_version++)
894 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
895
896 rc = pcim_enable_device(pdev);
897 if (rc)
898 return rc;
899
900 rc = pci_request_regions(pdev, DRV_NAME);
901 if (rc) {
902 pcim_pin_device(pdev);
903 return rc;
904 }
905
906 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
907 if (rc)
908 return rc;
909 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
910 if (rc)
911 return rc;
912
913 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
914 if (probe_ent == NULL)
915 return -ENOMEM;
916
917 probe_ent->dev = pci_dev_to_dev(pdev);
918 INIT_LIST_HEAD(&probe_ent->node);
919
920 mmio_base = pcim_iomap(pdev, 3, 0);
921 if (mmio_base == NULL)
922 return -ENOMEM;
923 base = (unsigned long) mmio_base;
924
925 hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL);
926 if (hp == NULL)
927 return -ENOMEM;
928
929 probe_ent->private_data = hp;
930
931 probe_ent->sht = pdc_port_info[board_idx].sht;
932 probe_ent->port_flags = pdc_port_info[board_idx].flags;
933 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
934 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
935 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
936 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
937
938 probe_ent->irq = pdev->irq;
939 probe_ent->irq_flags = IRQF_SHARED;
940 probe_ent->mmio_base = mmio_base;
941
942 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
943 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
944
945 probe_ent->port[0].scr_addr = base + 0x400;
946 probe_ent->port[1].scr_addr = base + 0x500;
947
948 /* notice 4-port boards */
949 switch (board_idx) {
950 case board_40518:
951 hp->flags |= PDC_FLAG_GEN_II;
952 /* Fall through */
953 case board_20319:
954 probe_ent->n_ports = 4;
955
956 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
957 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
958
959 probe_ent->port[2].scr_addr = base + 0x600;
960 probe_ent->port[3].scr_addr = base + 0x700;
961 break;
962 case board_2057x:
963 hp->flags |= PDC_FLAG_GEN_II;
964 /* Fall through */
965 case board_2037x:
966 /* TX2plus boards also have a PATA port */
967 tmp = readb(mmio_base + PDC_FLASH_CTL+1);
968 if (!(tmp & 0x80)) {
969 probe_ent->n_ports = 3;
970 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
971 hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
972 printk(KERN_INFO DRV_NAME " PATA port found\n");
973 } else
974 probe_ent->n_ports = 2;
975 hp->port_flags[0] = ATA_FLAG_SATA;
976 hp->port_flags[1] = ATA_FLAG_SATA;
977 break;
978 case board_20619:
979 probe_ent->n_ports = 4;
980
981 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
982 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
983
984 probe_ent->port[2].scr_addr = base + 0x600;
985 probe_ent->port[3].scr_addr = base + 0x700;
986 break;
987 default:
988 BUG();
989 break;
990 }
991
992 pci_set_master(pdev);
993
994 /* initialize adapter */
995 pdc_host_init(board_idx, probe_ent);
996
997 if (!ata_device_add(probe_ent))
998 return -ENODEV;
999
1000 devm_kfree(&pdev->dev, probe_ent);
1001 return 0;
1002 }
1003
1004
1005 static int __init pdc_ata_init(void)
1006 {
1007 return pci_register_driver(&pdc_ata_pci_driver);
1008 }
1009
1010
1011 static void __exit pdc_ata_exit(void)
1012 {
1013 pci_unregister_driver(&pdc_ata_pci_driver);
1014 }
1015
1016
1017 MODULE_AUTHOR("Jeff Garzik");
1018 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1019 MODULE_LICENSE("GPL");
1020 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1021 MODULE_VERSION(DRV_VERSION);
1022
1023 module_init(pdc_ata_init);
1024 module_exit(pdc_ata_exit);
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