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sata_promise: fix endianess bug in ASIC PRD bug workaround
[mirror_ubuntu-hirsute-kernel.git] / drivers / ata / sata_promise.c
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Mikael Pettersson <mikpe@it.uu.se>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003-2004 Red Hat, Inc.
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware information only available under NDA.
31 *
32 */
33
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/device.h>
42 #include <scsi/scsi.h>
43 #include <scsi/scsi_host.h>
44 #include <scsi/scsi_cmnd.h>
45 #include <linux/libata.h>
46 #include "sata_promise.h"
47
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "2.11"
50
51 enum {
52 PDC_MAX_PORTS = 4,
53 PDC_MMIO_BAR = 3,
54 PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
55
56 /* register offsets */
57 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
58 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
59 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
60 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
61 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
62 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
63 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
64 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
65 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
66 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
67 PDC_FLASH_CTL = 0x44, /* Flash control register */
68 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
69 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
70 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
71 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
72 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
73 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
74
75 /* PDC_GLOBAL_CTL bit definitions */
76 PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */
77 PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */
78 PDC_DH_ERR = (1 << 10), /* PCI error while loading data */
79 PDC2_HTO_ERR = (1 << 12), /* host bus timeout */
80 PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */
81 PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */
82 PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */
83 PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */
84 PDC_DRIVE_ERR = (1 << 21), /* drive error */
85 PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */
86 PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */
87 PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
88 PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
89 PDC2_ATA_DMA_CNT_ERR,
90 PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
91 PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
92 PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
93 PDC1_ERR_MASK | PDC2_ERR_MASK,
94
95 board_2037x = 0, /* FastTrak S150 TX2plus */
96 board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */
97 board_20319 = 2, /* FastTrak S150 TX4 */
98 board_20619 = 3, /* FastTrak TX4000 */
99 board_2057x = 4, /* SATAII150 Tx2plus */
100 board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */
101 board_40518 = 6, /* SATAII150 Tx4 */
102
103 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
104
105 /* Sequence counter control registers bit definitions */
106 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
107
108 /* Feature register values */
109 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
110 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
111
112 /* Device/Head register values */
113 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
114
115 /* PDC_CTLSTAT bit definitions */
116 PDC_DMA_ENABLE = (1 << 7),
117 PDC_IRQ_DISABLE = (1 << 10),
118 PDC_RESET = (1 << 11), /* HDMA reset */
119
120 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
121 ATA_FLAG_MMIO |
122 ATA_FLAG_PIO_POLLING,
123
124 /* ap->flags bits */
125 PDC_FLAG_GEN_II = (1 << 24),
126 PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */
127 PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */
128 };
129
130 struct pdc_port_priv {
131 u8 *pkt;
132 dma_addr_t pkt_dma;
133 };
134
135 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
136 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
137 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
138 static int pdc_common_port_start(struct ata_port *ap);
139 static int pdc_sata_port_start(struct ata_port *ap);
140 static void pdc_qc_prep(struct ata_queued_cmd *qc);
141 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
142 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
143 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
144 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
145 static void pdc_irq_clear(struct ata_port *ap);
146 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
147 static void pdc_freeze(struct ata_port *ap);
148 static void pdc_thaw(struct ata_port *ap);
149 static void pdc_pata_error_handler(struct ata_port *ap);
150 static void pdc_sata_error_handler(struct ata_port *ap);
151 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
152 static int pdc_pata_cable_detect(struct ata_port *ap);
153 static int pdc_sata_cable_detect(struct ata_port *ap);
154
155 static struct scsi_host_template pdc_ata_sht = {
156 .module = THIS_MODULE,
157 .name = DRV_NAME,
158 .ioctl = ata_scsi_ioctl,
159 .queuecommand = ata_scsi_queuecmd,
160 .can_queue = ATA_DEF_QUEUE,
161 .this_id = ATA_SHT_THIS_ID,
162 .sg_tablesize = PDC_MAX_PRD,
163 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
164 .emulated = ATA_SHT_EMULATED,
165 .use_clustering = ATA_SHT_USE_CLUSTERING,
166 .proc_name = DRV_NAME,
167 .dma_boundary = ATA_DMA_BOUNDARY,
168 .slave_configure = ata_scsi_slave_config,
169 .slave_destroy = ata_scsi_slave_destroy,
170 .bios_param = ata_std_bios_param,
171 };
172
173 static const struct ata_port_operations pdc_sata_ops = {
174 .tf_load = pdc_tf_load_mmio,
175 .tf_read = ata_tf_read,
176 .check_status = ata_check_status,
177 .exec_command = pdc_exec_command_mmio,
178 .dev_select = ata_std_dev_select,
179 .check_atapi_dma = pdc_check_atapi_dma,
180
181 .qc_prep = pdc_qc_prep,
182 .qc_issue = pdc_qc_issue_prot,
183 .freeze = pdc_freeze,
184 .thaw = pdc_thaw,
185 .error_handler = pdc_sata_error_handler,
186 .post_internal_cmd = pdc_post_internal_cmd,
187 .cable_detect = pdc_sata_cable_detect,
188 .data_xfer = ata_data_xfer,
189 .irq_clear = pdc_irq_clear,
190 .irq_on = ata_irq_on,
191
192 .scr_read = pdc_sata_scr_read,
193 .scr_write = pdc_sata_scr_write,
194 .port_start = pdc_sata_port_start,
195 };
196
197 /* First-generation chips need a more restrictive ->check_atapi_dma op */
198 static const struct ata_port_operations pdc_old_sata_ops = {
199 .tf_load = pdc_tf_load_mmio,
200 .tf_read = ata_tf_read,
201 .check_status = ata_check_status,
202 .exec_command = pdc_exec_command_mmio,
203 .dev_select = ata_std_dev_select,
204 .check_atapi_dma = pdc_old_sata_check_atapi_dma,
205
206 .qc_prep = pdc_qc_prep,
207 .qc_issue = pdc_qc_issue_prot,
208 .freeze = pdc_freeze,
209 .thaw = pdc_thaw,
210 .error_handler = pdc_sata_error_handler,
211 .post_internal_cmd = pdc_post_internal_cmd,
212 .cable_detect = pdc_sata_cable_detect,
213 .data_xfer = ata_data_xfer,
214 .irq_clear = pdc_irq_clear,
215 .irq_on = ata_irq_on,
216
217 .scr_read = pdc_sata_scr_read,
218 .scr_write = pdc_sata_scr_write,
219 .port_start = pdc_sata_port_start,
220 };
221
222 static const struct ata_port_operations pdc_pata_ops = {
223 .tf_load = pdc_tf_load_mmio,
224 .tf_read = ata_tf_read,
225 .check_status = ata_check_status,
226 .exec_command = pdc_exec_command_mmio,
227 .dev_select = ata_std_dev_select,
228 .check_atapi_dma = pdc_check_atapi_dma,
229
230 .qc_prep = pdc_qc_prep,
231 .qc_issue = pdc_qc_issue_prot,
232 .freeze = pdc_freeze,
233 .thaw = pdc_thaw,
234 .error_handler = pdc_pata_error_handler,
235 .post_internal_cmd = pdc_post_internal_cmd,
236 .cable_detect = pdc_pata_cable_detect,
237 .data_xfer = ata_data_xfer,
238 .irq_clear = pdc_irq_clear,
239 .irq_on = ata_irq_on,
240
241 .port_start = pdc_common_port_start,
242 };
243
244 static const struct ata_port_info pdc_port_info[] = {
245 [board_2037x] =
246 {
247 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
248 PDC_FLAG_SATA_PATA,
249 .pio_mask = 0x1f, /* pio0-4 */
250 .mwdma_mask = 0x07, /* mwdma0-2 */
251 .udma_mask = ATA_UDMA6,
252 .port_ops = &pdc_old_sata_ops,
253 },
254
255 [board_2037x_pata] =
256 {
257 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
258 .pio_mask = 0x1f, /* pio0-4 */
259 .mwdma_mask = 0x07, /* mwdma0-2 */
260 .udma_mask = ATA_UDMA6,
261 .port_ops = &pdc_pata_ops,
262 },
263
264 [board_20319] =
265 {
266 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
267 PDC_FLAG_4_PORTS,
268 .pio_mask = 0x1f, /* pio0-4 */
269 .mwdma_mask = 0x07, /* mwdma0-2 */
270 .udma_mask = ATA_UDMA6,
271 .port_ops = &pdc_old_sata_ops,
272 },
273
274 [board_20619] =
275 {
276 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
277 PDC_FLAG_4_PORTS,
278 .pio_mask = 0x1f, /* pio0-4 */
279 .mwdma_mask = 0x07, /* mwdma0-2 */
280 .udma_mask = ATA_UDMA6,
281 .port_ops = &pdc_pata_ops,
282 },
283
284 [board_2057x] =
285 {
286 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
287 PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
288 .pio_mask = 0x1f, /* pio0-4 */
289 .mwdma_mask = 0x07, /* mwdma0-2 */
290 .udma_mask = ATA_UDMA6,
291 .port_ops = &pdc_sata_ops,
292 },
293
294 [board_2057x_pata] =
295 {
296 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
297 PDC_FLAG_GEN_II,
298 .pio_mask = 0x1f, /* pio0-4 */
299 .mwdma_mask = 0x07, /* mwdma0-2 */
300 .udma_mask = ATA_UDMA6,
301 .port_ops = &pdc_pata_ops,
302 },
303
304 [board_40518] =
305 {
306 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
307 PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
308 .pio_mask = 0x1f, /* pio0-4 */
309 .mwdma_mask = 0x07, /* mwdma0-2 */
310 .udma_mask = ATA_UDMA6,
311 .port_ops = &pdc_sata_ops,
312 },
313 };
314
315 static const struct pci_device_id pdc_ata_pci_tbl[] = {
316 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
317 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
318 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
319 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
320 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
321 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
322 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
323 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
324 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
325 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
326
327 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
328 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
329 { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
330 { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
331 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
332 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
333
334 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
335
336 { } /* terminate list */
337 };
338
339 static struct pci_driver pdc_ata_pci_driver = {
340 .name = DRV_NAME,
341 .id_table = pdc_ata_pci_tbl,
342 .probe = pdc_ata_init_one,
343 .remove = ata_pci_remove_one,
344 };
345
346 static int pdc_common_port_start(struct ata_port *ap)
347 {
348 struct device *dev = ap->host->dev;
349 struct pdc_port_priv *pp;
350 int rc;
351
352 rc = ata_port_start(ap);
353 if (rc)
354 return rc;
355
356 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
357 if (!pp)
358 return -ENOMEM;
359
360 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
361 if (!pp->pkt)
362 return -ENOMEM;
363
364 ap->private_data = pp;
365
366 return 0;
367 }
368
369 static int pdc_sata_port_start(struct ata_port *ap)
370 {
371 int rc;
372
373 rc = pdc_common_port_start(ap);
374 if (rc)
375 return rc;
376
377 /* fix up PHYMODE4 align timing */
378 if (ap->flags & PDC_FLAG_GEN_II) {
379 void __iomem *mmio = ap->ioaddr.scr_addr;
380 unsigned int tmp;
381
382 tmp = readl(mmio + 0x014);
383 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
384 writel(tmp, mmio + 0x014);
385 }
386
387 return 0;
388 }
389
390 static void pdc_reset_port(struct ata_port *ap)
391 {
392 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
393 unsigned int i;
394 u32 tmp;
395
396 for (i = 11; i > 0; i--) {
397 tmp = readl(mmio);
398 if (tmp & PDC_RESET)
399 break;
400
401 udelay(100);
402
403 tmp |= PDC_RESET;
404 writel(tmp, mmio);
405 }
406
407 tmp &= ~PDC_RESET;
408 writel(tmp, mmio);
409 readl(mmio); /* flush */
410 }
411
412 static int pdc_pata_cable_detect(struct ata_port *ap)
413 {
414 u8 tmp;
415 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
416
417 tmp = readb(mmio);
418 if (tmp & 0x01)
419 return ATA_CBL_PATA40;
420 return ATA_CBL_PATA80;
421 }
422
423 static int pdc_sata_cable_detect(struct ata_port *ap)
424 {
425 return ATA_CBL_SATA;
426 }
427
428 static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
429 {
430 if (sc_reg > SCR_CONTROL)
431 return -EINVAL;
432 *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
433 return 0;
434 }
435
436 static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
437 {
438 if (sc_reg > SCR_CONTROL)
439 return -EINVAL;
440 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
441 return 0;
442 }
443
444 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
445 {
446 struct ata_port *ap = qc->ap;
447 dma_addr_t sg_table = ap->prd_dma;
448 unsigned int cdb_len = qc->dev->cdb_len;
449 u8 *cdb = qc->cdb;
450 struct pdc_port_priv *pp = ap->private_data;
451 u8 *buf = pp->pkt;
452 u32 *buf32 = (u32 *) buf;
453 unsigned int dev_sel, feature, nbytes;
454
455 /* set control bits (byte 0), zero delay seq id (byte 3),
456 * and seq id (byte 2)
457 */
458 switch (qc->tf.protocol) {
459 case ATA_PROT_ATAPI_DMA:
460 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
461 buf32[0] = cpu_to_le32(PDC_PKT_READ);
462 else
463 buf32[0] = 0;
464 break;
465 case ATA_PROT_ATAPI_NODATA:
466 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
467 break;
468 default:
469 BUG();
470 break;
471 }
472 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
473 buf32[2] = 0; /* no next-packet */
474
475 /* select drive */
476 if (sata_scr_valid(&ap->link)) {
477 dev_sel = PDC_DEVICE_SATA;
478 } else {
479 dev_sel = ATA_DEVICE_OBS;
480 if (qc->dev->devno != 0)
481 dev_sel |= ATA_DEV1;
482 }
483 buf[12] = (1 << 5) | ATA_REG_DEVICE;
484 buf[13] = dev_sel;
485 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
486 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
487
488 buf[16] = (1 << 5) | ATA_REG_NSECT;
489 buf[17] = 0x00;
490 buf[18] = (1 << 5) | ATA_REG_LBAL;
491 buf[19] = 0x00;
492
493 /* set feature and byte counter registers */
494 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
495 feature = PDC_FEATURE_ATAPI_PIO;
496 /* set byte counter register to real transfer byte count */
497 nbytes = qc->nbytes;
498 if (nbytes > 0xffff)
499 nbytes = 0xffff;
500 } else {
501 feature = PDC_FEATURE_ATAPI_DMA;
502 /* set byte counter register to 0 */
503 nbytes = 0;
504 }
505 buf[20] = (1 << 5) | ATA_REG_FEATURE;
506 buf[21] = feature;
507 buf[22] = (1 << 5) | ATA_REG_BYTEL;
508 buf[23] = nbytes & 0xFF;
509 buf[24] = (1 << 5) | ATA_REG_BYTEH;
510 buf[25] = (nbytes >> 8) & 0xFF;
511
512 /* send ATAPI packet command 0xA0 */
513 buf[26] = (1 << 5) | ATA_REG_CMD;
514 buf[27] = ATA_CMD_PACKET;
515
516 /* select drive and check DRQ */
517 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
518 buf[29] = dev_sel;
519
520 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
521 BUG_ON(cdb_len & ~0x1E);
522
523 /* append the CDB as the final part */
524 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
525 memcpy(buf+31, cdb, cdb_len);
526 }
527
528 /**
529 * pdc_fill_sg - Fill PCI IDE PRD table
530 * @qc: Metadata associated with taskfile to be transferred
531 *
532 * Fill PCI IDE PRD (scatter-gather) table with segments
533 * associated with the current disk command.
534 * Make sure hardware does not choke on it.
535 *
536 * LOCKING:
537 * spin_lock_irqsave(host lock)
538 *
539 */
540 static void pdc_fill_sg(struct ata_queued_cmd *qc)
541 {
542 struct ata_port *ap = qc->ap;
543 struct scatterlist *sg;
544 unsigned int idx;
545 const u32 SG_COUNT_ASIC_BUG = 41*4;
546
547 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
548 return;
549
550 WARN_ON(qc->__sg == NULL);
551 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
552
553 idx = 0;
554 ata_for_each_sg(sg, qc) {
555 u32 addr, offset;
556 u32 sg_len, len;
557
558 /* determine if physical DMA addr spans 64K boundary.
559 * Note h/w doesn't support 64-bit, so we unconditionally
560 * truncate dma_addr_t to u32.
561 */
562 addr = (u32) sg_dma_address(sg);
563 sg_len = sg_dma_len(sg);
564
565 while (sg_len) {
566 offset = addr & 0xffff;
567 len = sg_len;
568 if ((offset + sg_len) > 0x10000)
569 len = 0x10000 - offset;
570
571 ap->prd[idx].addr = cpu_to_le32(addr);
572 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
573 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
574
575 idx++;
576 sg_len -= len;
577 addr += len;
578 }
579 }
580
581 if (idx) {
582 u32 len = le32_to_cpu(ap->prd[idx - 1].flags_len);
583
584 if (len > SG_COUNT_ASIC_BUG) {
585 u32 addr;
586
587 VPRINTK("Splitting last PRD.\n");
588
589 addr = le32_to_cpu(ap->prd[idx - 1].addr);
590 ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
591 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
592
593 addr = addr + len - SG_COUNT_ASIC_BUG;
594 len = SG_COUNT_ASIC_BUG;
595 ap->prd[idx].addr = cpu_to_le32(addr);
596 ap->prd[idx].flags_len = cpu_to_le32(len);
597 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
598
599 idx++;
600 }
601
602 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
603 }
604 }
605
606 static void pdc_qc_prep(struct ata_queued_cmd *qc)
607 {
608 struct pdc_port_priv *pp = qc->ap->private_data;
609 unsigned int i;
610
611 VPRINTK("ENTER\n");
612
613 switch (qc->tf.protocol) {
614 case ATA_PROT_DMA:
615 pdc_fill_sg(qc);
616 /* fall through */
617
618 case ATA_PROT_NODATA:
619 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
620 qc->dev->devno, pp->pkt);
621
622 if (qc->tf.flags & ATA_TFLAG_LBA48)
623 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
624 else
625 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
626
627 pdc_pkt_footer(&qc->tf, pp->pkt, i);
628 break;
629
630 case ATA_PROT_ATAPI:
631 pdc_fill_sg(qc);
632 break;
633
634 case ATA_PROT_ATAPI_DMA:
635 pdc_fill_sg(qc);
636 /*FALLTHROUGH*/
637 case ATA_PROT_ATAPI_NODATA:
638 pdc_atapi_pkt(qc);
639 break;
640
641 default:
642 break;
643 }
644 }
645
646 static void pdc_freeze(struct ata_port *ap)
647 {
648 void __iomem *mmio = ap->ioaddr.cmd_addr;
649 u32 tmp;
650
651 tmp = readl(mmio + PDC_CTLSTAT);
652 tmp |= PDC_IRQ_DISABLE;
653 tmp &= ~PDC_DMA_ENABLE;
654 writel(tmp, mmio + PDC_CTLSTAT);
655 readl(mmio + PDC_CTLSTAT); /* flush */
656 }
657
658 static void pdc_thaw(struct ata_port *ap)
659 {
660 void __iomem *mmio = ap->ioaddr.cmd_addr;
661 u32 tmp;
662
663 /* clear IRQ */
664 readl(mmio + PDC_INT_SEQMASK);
665
666 /* turn IRQ back on */
667 tmp = readl(mmio + PDC_CTLSTAT);
668 tmp &= ~PDC_IRQ_DISABLE;
669 writel(tmp, mmio + PDC_CTLSTAT);
670 readl(mmio + PDC_CTLSTAT); /* flush */
671 }
672
673 static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
674 {
675 if (!(ap->pflags & ATA_PFLAG_FROZEN))
676 pdc_reset_port(ap);
677
678 /* perform recovery */
679 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
680 ata_std_postreset);
681 }
682
683 static void pdc_pata_error_handler(struct ata_port *ap)
684 {
685 pdc_common_error_handler(ap, NULL);
686 }
687
688 static void pdc_sata_error_handler(struct ata_port *ap)
689 {
690 pdc_common_error_handler(ap, sata_std_hardreset);
691 }
692
693 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
694 {
695 struct ata_port *ap = qc->ap;
696
697 /* make DMA engine forget about the failed command */
698 if (qc->flags & ATA_QCFLAG_FAILED)
699 pdc_reset_port(ap);
700 }
701
702 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
703 u32 port_status, u32 err_mask)
704 {
705 struct ata_eh_info *ehi = &ap->link.eh_info;
706 unsigned int ac_err_mask = 0;
707
708 ata_ehi_clear_desc(ehi);
709 ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
710 port_status &= err_mask;
711
712 if (port_status & PDC_DRIVE_ERR)
713 ac_err_mask |= AC_ERR_DEV;
714 if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
715 ac_err_mask |= AC_ERR_HSM;
716 if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
717 ac_err_mask |= AC_ERR_ATA_BUS;
718 if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
719 | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
720 ac_err_mask |= AC_ERR_HOST_BUS;
721
722 if (sata_scr_valid(&ap->link)) {
723 u32 serror;
724
725 pdc_sata_scr_read(ap, SCR_ERROR, &serror);
726 ehi->serror |= serror;
727 }
728
729 qc->err_mask |= ac_err_mask;
730
731 pdc_reset_port(ap);
732
733 ata_port_abort(ap);
734 }
735
736 static inline unsigned int pdc_host_intr(struct ata_port *ap,
737 struct ata_queued_cmd *qc)
738 {
739 unsigned int handled = 0;
740 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
741 u32 port_status, err_mask;
742
743 err_mask = PDC_ERR_MASK;
744 if (ap->flags & PDC_FLAG_GEN_II)
745 err_mask &= ~PDC1_ERR_MASK;
746 else
747 err_mask &= ~PDC2_ERR_MASK;
748 port_status = readl(port_mmio + PDC_GLOBAL_CTL);
749 if (unlikely(port_status & err_mask)) {
750 pdc_error_intr(ap, qc, port_status, err_mask);
751 return 1;
752 }
753
754 switch (qc->tf.protocol) {
755 case ATA_PROT_DMA:
756 case ATA_PROT_NODATA:
757 case ATA_PROT_ATAPI_DMA:
758 case ATA_PROT_ATAPI_NODATA:
759 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
760 ata_qc_complete(qc);
761 handled = 1;
762 break;
763
764 default:
765 ap->stats.idle_irq++;
766 break;
767 }
768
769 return handled;
770 }
771
772 static void pdc_irq_clear(struct ata_port *ap)
773 {
774 struct ata_host *host = ap->host;
775 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
776
777 readl(mmio + PDC_INT_SEQMASK);
778 }
779
780 static int pdc_is_sataii_tx4(unsigned long flags)
781 {
782 const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
783 return (flags & mask) == mask;
784 }
785
786 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
787 int is_sataii_tx4)
788 {
789 static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
790 return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
791 }
792
793 static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
794 {
795 struct ata_host *host = dev_instance;
796 struct ata_port *ap;
797 u32 mask = 0;
798 unsigned int i, tmp;
799 unsigned int handled = 0;
800 void __iomem *mmio_base;
801 unsigned int hotplug_offset, ata_no;
802 u32 hotplug_status;
803 int is_sataii_tx4;
804
805 VPRINTK("ENTER\n");
806
807 if (!host || !host->iomap[PDC_MMIO_BAR]) {
808 VPRINTK("QUICK EXIT\n");
809 return IRQ_NONE;
810 }
811
812 mmio_base = host->iomap[PDC_MMIO_BAR];
813
814 /* read and clear hotplug flags for all ports */
815 if (host->ports[0]->flags & PDC_FLAG_GEN_II)
816 hotplug_offset = PDC2_SATA_PLUG_CSR;
817 else
818 hotplug_offset = PDC_SATA_PLUG_CSR;
819 hotplug_status = readl(mmio_base + hotplug_offset);
820 if (hotplug_status & 0xff)
821 writel(hotplug_status | 0xff, mmio_base + hotplug_offset);
822 hotplug_status &= 0xff; /* clear uninteresting bits */
823
824 /* reading should also clear interrupts */
825 mask = readl(mmio_base + PDC_INT_SEQMASK);
826
827 if (mask == 0xffffffff && hotplug_status == 0) {
828 VPRINTK("QUICK EXIT 2\n");
829 return IRQ_NONE;
830 }
831
832 spin_lock(&host->lock);
833
834 mask &= 0xffff; /* only 16 tags possible */
835 if (mask == 0 && hotplug_status == 0) {
836 VPRINTK("QUICK EXIT 3\n");
837 goto done_irq;
838 }
839
840 writel(mask, mmio_base + PDC_INT_SEQMASK);
841
842 is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
843
844 for (i = 0; i < host->n_ports; i++) {
845 VPRINTK("port %u\n", i);
846 ap = host->ports[i];
847
848 /* check for a plug or unplug event */
849 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
850 tmp = hotplug_status & (0x11 << ata_no);
851 if (tmp && ap &&
852 !(ap->flags & ATA_FLAG_DISABLED)) {
853 struct ata_eh_info *ehi = &ap->link.eh_info;
854 ata_ehi_clear_desc(ehi);
855 ata_ehi_hotplugged(ehi);
856 ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
857 ata_port_freeze(ap);
858 ++handled;
859 continue;
860 }
861
862 /* check for a packet interrupt */
863 tmp = mask & (1 << (i + 1));
864 if (tmp && ap &&
865 !(ap->flags & ATA_FLAG_DISABLED)) {
866 struct ata_queued_cmd *qc;
867
868 qc = ata_qc_from_tag(ap, ap->link.active_tag);
869 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
870 handled += pdc_host_intr(ap, qc);
871 }
872 }
873
874 VPRINTK("EXIT\n");
875
876 done_irq:
877 spin_unlock(&host->lock);
878 return IRQ_RETVAL(handled);
879 }
880
881 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
882 {
883 struct ata_port *ap = qc->ap;
884 struct pdc_port_priv *pp = ap->private_data;
885 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
886 unsigned int port_no = ap->port_no;
887 u8 seq = (u8) (port_no + 1);
888
889 VPRINTK("ENTER, ap %p\n", ap);
890
891 writel(0x00000001, mmio + (seq * 4));
892 readl(mmio + (seq * 4)); /* flush */
893
894 pp->pkt[2] = seq;
895 wmb(); /* flush PRD, pkt writes */
896 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
897 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
898 }
899
900 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
901 {
902 switch (qc->tf.protocol) {
903 case ATA_PROT_ATAPI_NODATA:
904 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
905 break;
906 /*FALLTHROUGH*/
907 case ATA_PROT_NODATA:
908 if (qc->tf.flags & ATA_TFLAG_POLLING)
909 break;
910 /*FALLTHROUGH*/
911 case ATA_PROT_ATAPI_DMA:
912 case ATA_PROT_DMA:
913 pdc_packet_start(qc);
914 return 0;
915
916 default:
917 break;
918 }
919
920 return ata_qc_issue_prot(qc);
921 }
922
923 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
924 {
925 WARN_ON(tf->protocol == ATA_PROT_DMA ||
926 tf->protocol == ATA_PROT_ATAPI_DMA);
927 ata_tf_load(ap, tf);
928 }
929
930 static void pdc_exec_command_mmio(struct ata_port *ap,
931 const struct ata_taskfile *tf)
932 {
933 WARN_ON(tf->protocol == ATA_PROT_DMA ||
934 tf->protocol == ATA_PROT_ATAPI_DMA);
935 ata_exec_command(ap, tf);
936 }
937
938 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
939 {
940 u8 *scsicmd = qc->scsicmd->cmnd;
941 int pio = 1; /* atapi dma off by default */
942
943 /* Whitelist commands that may use DMA. */
944 switch (scsicmd[0]) {
945 case WRITE_12:
946 case WRITE_10:
947 case WRITE_6:
948 case READ_12:
949 case READ_10:
950 case READ_6:
951 case 0xad: /* READ_DVD_STRUCTURE */
952 case 0xbe: /* READ_CD */
953 pio = 0;
954 }
955 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
956 if (scsicmd[0] == WRITE_10) {
957 unsigned int lba =
958 (scsicmd[2] << 24) |
959 (scsicmd[3] << 16) |
960 (scsicmd[4] << 8) |
961 scsicmd[5];
962 if (lba >= 0xFFFF4FA2)
963 pio = 1;
964 }
965 return pio;
966 }
967
968 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
969 {
970 /* First generation chips cannot use ATAPI DMA on SATA ports */
971 return 1;
972 }
973
974 static void pdc_ata_setup_port(struct ata_port *ap,
975 void __iomem *base, void __iomem *scr_addr)
976 {
977 ap->ioaddr.cmd_addr = base;
978 ap->ioaddr.data_addr = base;
979 ap->ioaddr.feature_addr =
980 ap->ioaddr.error_addr = base + 0x4;
981 ap->ioaddr.nsect_addr = base + 0x8;
982 ap->ioaddr.lbal_addr = base + 0xc;
983 ap->ioaddr.lbam_addr = base + 0x10;
984 ap->ioaddr.lbah_addr = base + 0x14;
985 ap->ioaddr.device_addr = base + 0x18;
986 ap->ioaddr.command_addr =
987 ap->ioaddr.status_addr = base + 0x1c;
988 ap->ioaddr.altstatus_addr =
989 ap->ioaddr.ctl_addr = base + 0x38;
990 ap->ioaddr.scr_addr = scr_addr;
991 }
992
993 static void pdc_host_init(struct ata_host *host)
994 {
995 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
996 int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
997 int hotplug_offset;
998 u32 tmp;
999
1000 if (is_gen2)
1001 hotplug_offset = PDC2_SATA_PLUG_CSR;
1002 else
1003 hotplug_offset = PDC_SATA_PLUG_CSR;
1004
1005 /*
1006 * Except for the hotplug stuff, this is voodoo from the
1007 * Promise driver. Label this entire section
1008 * "TODO: figure out why we do this"
1009 */
1010
1011 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1012 tmp = readl(mmio + PDC_FLASH_CTL);
1013 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1014 if (!is_gen2)
1015 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1016 writel(tmp, mmio + PDC_FLASH_CTL);
1017
1018 /* clear plug/unplug flags for all ports */
1019 tmp = readl(mmio + hotplug_offset);
1020 writel(tmp | 0xff, mmio + hotplug_offset);
1021
1022 /* unmask plug/unplug ints */
1023 tmp = readl(mmio + hotplug_offset);
1024 writel(tmp & ~0xff0000, mmio + hotplug_offset);
1025
1026 /* don't initialise TBG or SLEW on 2nd generation chips */
1027 if (is_gen2)
1028 return;
1029
1030 /* reduce TBG clock to 133 Mhz. */
1031 tmp = readl(mmio + PDC_TBG_MODE);
1032 tmp &= ~0x30000; /* clear bit 17, 16*/
1033 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
1034 writel(tmp, mmio + PDC_TBG_MODE);
1035
1036 readl(mmio + PDC_TBG_MODE); /* flush */
1037 msleep(10);
1038
1039 /* adjust slew rate control register. */
1040 tmp = readl(mmio + PDC_SLEW_CTL);
1041 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1042 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1043 writel(tmp, mmio + PDC_SLEW_CTL);
1044 }
1045
1046 static int pdc_ata_init_one(struct pci_dev *pdev,
1047 const struct pci_device_id *ent)
1048 {
1049 static int printed_version;
1050 const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1051 const struct ata_port_info *ppi[PDC_MAX_PORTS];
1052 struct ata_host *host;
1053 void __iomem *base;
1054 int n_ports, i, rc;
1055 int is_sataii_tx4;
1056
1057 if (!printed_version++)
1058 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1059
1060 /* enable and acquire resources */
1061 rc = pcim_enable_device(pdev);
1062 if (rc)
1063 return rc;
1064
1065 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1066 if (rc == -EBUSY)
1067 pcim_pin_device(pdev);
1068 if (rc)
1069 return rc;
1070 base = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1071
1072 /* determine port configuration and setup host */
1073 n_ports = 2;
1074 if (pi->flags & PDC_FLAG_4_PORTS)
1075 n_ports = 4;
1076 for (i = 0; i < n_ports; i++)
1077 ppi[i] = pi;
1078
1079 if (pi->flags & PDC_FLAG_SATA_PATA) {
1080 u8 tmp = readb(base + PDC_FLASH_CTL+1);
1081 if (!(tmp & 0x80))
1082 ppi[n_ports++] = pi + 1;
1083 }
1084
1085 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1086 if (!host) {
1087 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
1088 return -ENOMEM;
1089 }
1090 host->iomap = pcim_iomap_table(pdev);
1091
1092 is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1093 for (i = 0; i < host->n_ports; i++) {
1094 struct ata_port *ap = host->ports[i];
1095 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1096 unsigned int port_offset = 0x200 + ata_no * 0x80;
1097 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1098
1099 pdc_ata_setup_port(ap, base + port_offset, base + scr_offset);
1100
1101 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1102 ata_port_pbar_desc(ap, PDC_MMIO_BAR, port_offset, "port");
1103 }
1104
1105 /* initialize adapter */
1106 pdc_host_init(host);
1107
1108 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1109 if (rc)
1110 return rc;
1111 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1112 if (rc)
1113 return rc;
1114
1115 /* start host, request IRQ and attach */
1116 pci_set_master(pdev);
1117 return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1118 &pdc_ata_sht);
1119 }
1120
1121 static int __init pdc_ata_init(void)
1122 {
1123 return pci_register_driver(&pdc_ata_pci_driver);
1124 }
1125
1126 static void __exit pdc_ata_exit(void)
1127 {
1128 pci_unregister_driver(&pdc_ata_pci_driver);
1129 }
1130
1131 MODULE_AUTHOR("Jeff Garzik");
1132 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1133 MODULE_LICENSE("GPL");
1134 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1135 MODULE_VERSION(DRV_VERSION);
1136
1137 module_init(pdc_ata_init);
1138 module_exit(pdc_ata_exit);
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