]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/ata/sata_sil.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:


00f2465dcdce7ee9bb013076d816462c4dc51d4e
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / sata_sil.c
1 /*
2 * sata_sil.c - Silicon Image SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2005 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Documentation for SiI 3112:
31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
32 *
33 * Other errata and documentation available under NDA.
34 *
35 */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
47
48 #define DRV_NAME "sata_sil"
49 #define DRV_VERSION "2.0"
50
51 enum {
52 /*
53 * host flags
54 */
55 SIL_FLAG_NO_SATA_IRQ = (1 << 28),
56 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
57 SIL_FLAG_MOD15WRITE = (1 << 30),
58
59 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
60 ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME,
61
62 /*
63 * Controller IDs
64 */
65 sil_3112 = 0,
66 sil_3112_no_sata_irq = 1,
67 sil_3512 = 2,
68 sil_3114 = 3,
69
70 /*
71 * Register offsets
72 */
73 SIL_SYSCFG = 0x48,
74
75 /*
76 * Register bits
77 */
78 /* SYSCFG */
79 SIL_MASK_IDE0_INT = (1 << 22),
80 SIL_MASK_IDE1_INT = (1 << 23),
81 SIL_MASK_IDE2_INT = (1 << 24),
82 SIL_MASK_IDE3_INT = (1 << 25),
83 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
84 SIL_MASK_4PORT = SIL_MASK_2PORT |
85 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
86
87 /* BMDMA/BMDMA2 */
88 SIL_INTR_STEERING = (1 << 1),
89
90 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */
91 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */
92 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */
93 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */
94 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */
95 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */
96 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */
97 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */
98 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */
99 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */
100
101 /* SIEN */
102 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */
103
104 /*
105 * Others
106 */
107 SIL_QUIRK_MOD15WRITE = (1 << 0),
108 SIL_QUIRK_UDMA5MAX = (1 << 1),
109 };
110
111 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
112 #ifdef CONFIG_PM
113 static int sil_pci_device_resume(struct pci_dev *pdev);
114 #endif
115 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
116 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
117 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
118 static void sil_post_set_mode (struct ata_port *ap);
119 static irqreturn_t sil_interrupt(int irq, void *dev_instance);
120 static void sil_freeze(struct ata_port *ap);
121 static void sil_thaw(struct ata_port *ap);
122
123
124 static const struct pci_device_id sil_pci_tbl[] = {
125 { PCI_VDEVICE(CMD, 0x3112), sil_3112 },
126 { PCI_VDEVICE(CMD, 0x0240), sil_3112 },
127 { PCI_VDEVICE(CMD, 0x3512), sil_3512 },
128 { PCI_VDEVICE(CMD, 0x3114), sil_3114 },
129 { PCI_VDEVICE(ATI, 0x436e), sil_3112 },
130 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq },
131 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq },
132
133 { } /* terminate list */
134 };
135
136
137 /* TODO firmware versions should be added - eric */
138 static const struct sil_drivelist {
139 const char * product;
140 unsigned int quirk;
141 } sil_blacklist [] = {
142 { "ST320012AS", SIL_QUIRK_MOD15WRITE },
143 { "ST330013AS", SIL_QUIRK_MOD15WRITE },
144 { "ST340017AS", SIL_QUIRK_MOD15WRITE },
145 { "ST360015AS", SIL_QUIRK_MOD15WRITE },
146 { "ST380023AS", SIL_QUIRK_MOD15WRITE },
147 { "ST3120023AS", SIL_QUIRK_MOD15WRITE },
148 { "ST340014ASL", SIL_QUIRK_MOD15WRITE },
149 { "ST360014ASL", SIL_QUIRK_MOD15WRITE },
150 { "ST380011ASL", SIL_QUIRK_MOD15WRITE },
151 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
152 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
153 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
154 { }
155 };
156
157 static struct pci_driver sil_pci_driver = {
158 .name = DRV_NAME,
159 .id_table = sil_pci_tbl,
160 .probe = sil_init_one,
161 .remove = ata_pci_remove_one,
162 #ifdef CONFIG_PM
163 .suspend = ata_pci_device_suspend,
164 .resume = sil_pci_device_resume,
165 #endif
166 };
167
168 static struct scsi_host_template sil_sht = {
169 .module = THIS_MODULE,
170 .name = DRV_NAME,
171 .ioctl = ata_scsi_ioctl,
172 .queuecommand = ata_scsi_queuecmd,
173 .can_queue = ATA_DEF_QUEUE,
174 .this_id = ATA_SHT_THIS_ID,
175 .sg_tablesize = LIBATA_MAX_PRD,
176 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
177 .emulated = ATA_SHT_EMULATED,
178 .use_clustering = ATA_SHT_USE_CLUSTERING,
179 .proc_name = DRV_NAME,
180 .dma_boundary = ATA_DMA_BOUNDARY,
181 .slave_configure = ata_scsi_slave_config,
182 .slave_destroy = ata_scsi_slave_destroy,
183 .bios_param = ata_std_bios_param,
184 .suspend = ata_scsi_device_suspend,
185 .resume = ata_scsi_device_resume,
186 };
187
188 static const struct ata_port_operations sil_ops = {
189 .port_disable = ata_port_disable,
190 .dev_config = sil_dev_config,
191 .tf_load = ata_tf_load,
192 .tf_read = ata_tf_read,
193 .check_status = ata_check_status,
194 .exec_command = ata_exec_command,
195 .dev_select = ata_std_dev_select,
196 .post_set_mode = sil_post_set_mode,
197 .bmdma_setup = ata_bmdma_setup,
198 .bmdma_start = ata_bmdma_start,
199 .bmdma_stop = ata_bmdma_stop,
200 .bmdma_status = ata_bmdma_status,
201 .qc_prep = ata_qc_prep,
202 .qc_issue = ata_qc_issue_prot,
203 .data_xfer = ata_mmio_data_xfer,
204 .freeze = sil_freeze,
205 .thaw = sil_thaw,
206 .error_handler = ata_bmdma_error_handler,
207 .post_internal_cmd = ata_bmdma_post_internal_cmd,
208 .irq_handler = sil_interrupt,
209 .irq_clear = ata_bmdma_irq_clear,
210 .scr_read = sil_scr_read,
211 .scr_write = sil_scr_write,
212 .port_start = ata_port_start,
213 };
214
215 static const struct ata_port_info sil_port_info[] = {
216 /* sil_3112 */
217 {
218 .sht = &sil_sht,
219 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE,
220 .pio_mask = 0x1f, /* pio0-4 */
221 .mwdma_mask = 0x07, /* mwdma0-2 */
222 .udma_mask = 0x3f, /* udma0-5 */
223 .port_ops = &sil_ops,
224 },
225 /* sil_3112_no_sata_irq */
226 {
227 .sht = &sil_sht,
228 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE |
229 SIL_FLAG_NO_SATA_IRQ,
230 .pio_mask = 0x1f, /* pio0-4 */
231 .mwdma_mask = 0x07, /* mwdma0-2 */
232 .udma_mask = 0x3f, /* udma0-5 */
233 .port_ops = &sil_ops,
234 },
235 /* sil_3512 */
236 {
237 .sht = &sil_sht,
238 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
239 .pio_mask = 0x1f, /* pio0-4 */
240 .mwdma_mask = 0x07, /* mwdma0-2 */
241 .udma_mask = 0x3f, /* udma0-5 */
242 .port_ops = &sil_ops,
243 },
244 /* sil_3114 */
245 {
246 .sht = &sil_sht,
247 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
248 .pio_mask = 0x1f, /* pio0-4 */
249 .mwdma_mask = 0x07, /* mwdma0-2 */
250 .udma_mask = 0x3f, /* udma0-5 */
251 .port_ops = &sil_ops,
252 },
253 };
254
255 /* per-port register offsets */
256 /* TODO: we can probably calculate rather than use a table */
257 static const struct {
258 unsigned long tf; /* ATA taskfile register block */
259 unsigned long ctl; /* ATA control/altstatus register block */
260 unsigned long bmdma; /* DMA register block */
261 unsigned long bmdma2; /* DMA register block #2 */
262 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
263 unsigned long scr; /* SATA control register block */
264 unsigned long sien; /* SATA Interrupt Enable register */
265 unsigned long xfer_mode;/* data transfer mode register */
266 unsigned long sfis_cfg; /* SATA FIS reception config register */
267 } sil_port[] = {
268 /* port 0 ... */
269 { 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c },
270 { 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
271 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
272 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
273 /* ... port 3 */
274 };
275
276 MODULE_AUTHOR("Jeff Garzik");
277 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
278 MODULE_LICENSE("GPL");
279 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
280 MODULE_VERSION(DRV_VERSION);
281
282 static int slow_down = 0;
283 module_param(slow_down, int, 0444);
284 MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
285
286
287 static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
288 {
289 u8 cache_line = 0;
290 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
291 return cache_line;
292 }
293
294 static void sil_post_set_mode (struct ata_port *ap)
295 {
296 struct ata_host *host = ap->host;
297 struct ata_device *dev;
298 void __iomem *addr = host->mmio_base + sil_port[ap->port_no].xfer_mode;
299 u32 tmp, dev_mode[2];
300 unsigned int i;
301
302 for (i = 0; i < 2; i++) {
303 dev = &ap->device[i];
304 if (!ata_dev_enabled(dev))
305 dev_mode[i] = 0; /* PIO0/1/2 */
306 else if (dev->flags & ATA_DFLAG_PIO)
307 dev_mode[i] = 1; /* PIO3/4 */
308 else
309 dev_mode[i] = 3; /* UDMA */
310 /* value 2 indicates MDMA */
311 }
312
313 tmp = readl(addr);
314 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
315 tmp |= dev_mode[0];
316 tmp |= (dev_mode[1] << 4);
317 writel(tmp, addr);
318 readl(addr); /* flush */
319 }
320
321 static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
322 {
323 unsigned long offset = ap->ioaddr.scr_addr;
324
325 switch (sc_reg) {
326 case SCR_STATUS:
327 return offset + 4;
328 case SCR_ERROR:
329 return offset + 8;
330 case SCR_CONTROL:
331 return offset;
332 default:
333 /* do nothing */
334 break;
335 }
336
337 return 0;
338 }
339
340 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
341 {
342 void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
343 if (mmio)
344 return readl(mmio);
345 return 0xffffffffU;
346 }
347
348 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
349 {
350 void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
351 if (mmio)
352 writel(val, mmio);
353 }
354
355 static void sil_host_intr(struct ata_port *ap, u32 bmdma2)
356 {
357 struct ata_eh_info *ehi = &ap->eh_info;
358 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
359 u8 status;
360
361 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) {
362 u32 serror;
363
364 /* SIEN doesn't mask SATA IRQs on some 3112s. Those
365 * controllers continue to assert IRQ as long as
366 * SError bits are pending. Clear SError immediately.
367 */
368 serror = sil_scr_read(ap, SCR_ERROR);
369 sil_scr_write(ap, SCR_ERROR, serror);
370
371 /* Trigger hotplug and accumulate SError only if the
372 * port isn't already frozen. Otherwise, PHY events
373 * during hardreset makes controllers with broken SIEN
374 * repeat probing needlessly.
375 */
376 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
377 ata_ehi_hotplugged(&ap->eh_info);
378 ap->eh_info.serror |= serror;
379 }
380
381 goto freeze;
382 }
383
384 if (unlikely(!qc || qc->tf.ctl & ATA_NIEN))
385 goto freeze;
386
387 /* Check whether we are expecting interrupt in this state */
388 switch (ap->hsm_task_state) {
389 case HSM_ST_FIRST:
390 /* Some pre-ATAPI-4 devices assert INTRQ
391 * at this state when ready to receive CDB.
392 */
393
394 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
395 * The flag was turned on only for atapi devices.
396 * No need to check is_atapi_taskfile(&qc->tf) again.
397 */
398 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
399 goto err_hsm;
400 break;
401 case HSM_ST_LAST:
402 if (qc->tf.protocol == ATA_PROT_DMA ||
403 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
404 /* clear DMA-Start bit */
405 ap->ops->bmdma_stop(qc);
406
407 if (bmdma2 & SIL_DMA_ERROR) {
408 qc->err_mask |= AC_ERR_HOST_BUS;
409 ap->hsm_task_state = HSM_ST_ERR;
410 }
411 }
412 break;
413 case HSM_ST:
414 break;
415 default:
416 goto err_hsm;
417 }
418
419 /* check main status, clearing INTRQ */
420 status = ata_chk_status(ap);
421 if (unlikely(status & ATA_BUSY))
422 goto err_hsm;
423
424 /* ack bmdma irq events */
425 ata_bmdma_irq_clear(ap);
426
427 /* kick HSM in the ass */
428 ata_hsm_move(ap, qc, status, 0);
429
430 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
431 qc->tf.protocol == ATA_PROT_ATAPI_DMA))
432 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2);
433
434 return;
435
436 err_hsm:
437 qc->err_mask |= AC_ERR_HSM;
438 freeze:
439 ata_port_freeze(ap);
440 }
441
442 static irqreturn_t sil_interrupt(int irq, void *dev_instance)
443 {
444 struct ata_host *host = dev_instance;
445 void __iomem *mmio_base = host->mmio_base;
446 int handled = 0;
447 int i;
448
449 spin_lock(&host->lock);
450
451 for (i = 0; i < host->n_ports; i++) {
452 struct ata_port *ap = host->ports[i];
453 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2);
454
455 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED))
456 continue;
457
458 /* turn off SATA_IRQ if not supported */
459 if (ap->flags & SIL_FLAG_NO_SATA_IRQ)
460 bmdma2 &= ~SIL_DMA_SATA_IRQ;
461
462 if (bmdma2 == 0xffffffff ||
463 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ)))
464 continue;
465
466 sil_host_intr(ap, bmdma2);
467 handled = 1;
468 }
469
470 spin_unlock(&host->lock);
471
472 return IRQ_RETVAL(handled);
473 }
474
475 static void sil_freeze(struct ata_port *ap)
476 {
477 void __iomem *mmio_base = ap->host->mmio_base;
478 u32 tmp;
479
480 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */
481 writel(0, mmio_base + sil_port[ap->port_no].sien);
482
483 /* plug IRQ */
484 tmp = readl(mmio_base + SIL_SYSCFG);
485 tmp |= SIL_MASK_IDE0_INT << ap->port_no;
486 writel(tmp, mmio_base + SIL_SYSCFG);
487 readl(mmio_base + SIL_SYSCFG); /* flush */
488 }
489
490 static void sil_thaw(struct ata_port *ap)
491 {
492 void __iomem *mmio_base = ap->host->mmio_base;
493 u32 tmp;
494
495 /* clear IRQ */
496 ata_chk_status(ap);
497 ata_bmdma_irq_clear(ap);
498
499 /* turn on SATA IRQ if supported */
500 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ))
501 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien);
502
503 /* turn on IRQ */
504 tmp = readl(mmio_base + SIL_SYSCFG);
505 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
506 writel(tmp, mmio_base + SIL_SYSCFG);
507 }
508
509 /**
510 * sil_dev_config - Apply device/host-specific errata fixups
511 * @ap: Port containing device to be examined
512 * @dev: Device to be examined
513 *
514 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
515 * device is known to be present, this function is called.
516 * We apply two errata fixups which are specific to Silicon Image,
517 * a Seagate and a Maxtor fixup.
518 *
519 * For certain Seagate devices, we must limit the maximum sectors
520 * to under 8K.
521 *
522 * For certain Maxtor devices, we must not program the drive
523 * beyond udma5.
524 *
525 * Both fixups are unfairly pessimistic. As soon as I get more
526 * information on these errata, I will create a more exhaustive
527 * list, and apply the fixups to only the specific
528 * devices/hosts/firmwares that need it.
529 *
530 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
531 * The Maxtor quirk is in the blacklist, but I'm keeping the original
532 * pessimistic fix for the following reasons...
533 * - There seems to be less info on it, only one device gleaned off the
534 * Windows driver, maybe only one is affected. More info would be greatly
535 * appreciated.
536 * - But then again UDMA5 is hardly anything to complain about
537 */
538 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
539 {
540 int print_info = ap->eh_context.i.flags & ATA_EHI_PRINTINFO;
541 unsigned int n, quirks = 0;
542 unsigned char model_num[ATA_ID_PROD_LEN + 1];
543
544 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
545
546 for (n = 0; sil_blacklist[n].product; n++)
547 if (!strcmp(sil_blacklist[n].product, model_num)) {
548 quirks = sil_blacklist[n].quirk;
549 break;
550 }
551
552 /* limit requests to 15 sectors */
553 if (slow_down ||
554 ((ap->flags & SIL_FLAG_MOD15WRITE) &&
555 (quirks & SIL_QUIRK_MOD15WRITE))) {
556 if (print_info)
557 ata_dev_printk(dev, KERN_INFO, "applying Seagate "
558 "errata fix (mod15write workaround)\n");
559 dev->max_sectors = 15;
560 return;
561 }
562
563 /* limit to udma5 */
564 if (quirks & SIL_QUIRK_UDMA5MAX) {
565 if (print_info)
566 ata_dev_printk(dev, KERN_INFO, "applying Maxtor "
567 "errata fix %s\n", model_num);
568 dev->udma_mask &= ATA_UDMA5;
569 return;
570 }
571 }
572
573 static void sil_init_controller(struct pci_dev *pdev,
574 int n_ports, unsigned long port_flags,
575 void __iomem *mmio_base)
576 {
577 u8 cls;
578 u32 tmp;
579 int i;
580
581 /* Initialize FIFO PCI bus arbitration */
582 cls = sil_get_device_cache_line(pdev);
583 if (cls) {
584 cls >>= 3;
585 cls++; /* cls = (line_size/8)+1 */
586 for (i = 0; i < n_ports; i++)
587 writew(cls << 8 | cls,
588 mmio_base + sil_port[i].fifo_cfg);
589 } else
590 dev_printk(KERN_WARNING, &pdev->dev,
591 "cache line size not set. Driver may not function\n");
592
593 /* Apply R_ERR on DMA activate FIS errata workaround */
594 if (port_flags & SIL_FLAG_RERR_ON_DMA_ACT) {
595 int cnt;
596
597 for (i = 0, cnt = 0; i < n_ports; i++) {
598 tmp = readl(mmio_base + sil_port[i].sfis_cfg);
599 if ((tmp & 0x3) != 0x01)
600 continue;
601 if (!cnt)
602 dev_printk(KERN_INFO, &pdev->dev,
603 "Applying R_ERR on DMA activate "
604 "FIS errata fix\n");
605 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
606 cnt++;
607 }
608 }
609
610 if (n_ports == 4) {
611 /* flip the magic "make 4 ports work" bit */
612 tmp = readl(mmio_base + sil_port[2].bmdma);
613 if ((tmp & SIL_INTR_STEERING) == 0)
614 writel(tmp | SIL_INTR_STEERING,
615 mmio_base + sil_port[2].bmdma);
616 }
617 }
618
619 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
620 {
621 static int printed_version;
622 struct device *dev = &pdev->dev;
623 struct ata_probe_ent *probe_ent;
624 unsigned long base;
625 void __iomem *mmio_base;
626 int rc;
627 unsigned int i;
628
629 if (!printed_version++)
630 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
631
632 rc = pcim_enable_device(pdev);
633 if (rc)
634 return rc;
635
636 rc = pci_request_regions(pdev, DRV_NAME);
637 if (rc) {
638 pcim_pin_device(pdev);
639 return rc;
640 }
641
642 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
643 if (rc)
644 return rc;
645 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
646 if (rc)
647 return rc;
648
649 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
650 if (probe_ent == NULL)
651 return -ENOMEM;
652
653 INIT_LIST_HEAD(&probe_ent->node);
654 probe_ent->dev = pci_dev_to_dev(pdev);
655 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
656 probe_ent->sht = sil_port_info[ent->driver_data].sht;
657 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
658 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
659 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
660 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
661 probe_ent->irq = pdev->irq;
662 probe_ent->irq_flags = IRQF_SHARED;
663 probe_ent->port_flags = sil_port_info[ent->driver_data].flags;
664
665 mmio_base = pcim_iomap(pdev, 5, 0);
666 if (mmio_base == NULL)
667 return -ENOMEM;
668
669 probe_ent->mmio_base = mmio_base;
670
671 base = (unsigned long) mmio_base;
672
673 for (i = 0; i < probe_ent->n_ports; i++) {
674 probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
675 probe_ent->port[i].altstatus_addr =
676 probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
677 probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
678 probe_ent->port[i].scr_addr = base + sil_port[i].scr;
679 ata_std_ports(&probe_ent->port[i]);
680 }
681
682 sil_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags,
683 mmio_base);
684
685 pci_set_master(pdev);
686
687 if (!ata_device_add(probe_ent))
688 return -ENODEV;
689
690 devm_kfree(dev, probe_ent);
691 return 0;
692 }
693
694 #ifdef CONFIG_PM
695 static int sil_pci_device_resume(struct pci_dev *pdev)
696 {
697 struct ata_host *host = dev_get_drvdata(&pdev->dev);
698 int rc;
699
700 rc = ata_pci_device_do_resume(pdev);
701 if (rc)
702 return rc;
703
704 sil_init_controller(pdev, host->n_ports, host->ports[0]->flags,
705 host->mmio_base);
706 ata_host_resume(host);
707
708 return 0;
709 }
710 #endif
711
712 static int __init sil_init(void)
713 {
714 return pci_register_driver(&sil_pci_driver);
715 }
716
717 static void __exit sil_exit(void)
718 {
719 pci_unregister_driver(&sil_pci_driver);
720 }
721
722
723 module_init(sil_init);
724 module_exit(sil_exit);
ubuntu-bionic-kernel mirror