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libata: convert to iomap
[mirror_ubuntu-bionic-kernel.git] / drivers / ata / sata_sx4.c
1 /*
2 * sata_sx4.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include "sata_promise.h"
46
47 #define DRV_NAME "sata_sx4"
48 #define DRV_VERSION "0.9"
49
50
51 enum {
52 PDC_MMIO_BAR = 3,
53 PDC_DIMM_BAR = 4,
54
55 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
56
57 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
58 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
59 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
60 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
61
62 PDC_20621_SEQCTL = 0x400,
63 PDC_20621_SEQMASK = 0x480,
64 PDC_20621_GENERAL_CTL = 0x484,
65 PDC_20621_PAGE_SIZE = (32 * 1024),
66
67 /* chosen, not constant, values; we design our own DIMM mem map */
68 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
69 PDC_20621_DIMM_BASE = 0x00200000,
70 PDC_20621_DIMM_DATA = (64 * 1024),
71 PDC_DIMM_DATA_STEP = (256 * 1024),
72 PDC_DIMM_WINDOW_STEP = (8 * 1024),
73 PDC_DIMM_HOST_PRD = (6 * 1024),
74 PDC_DIMM_HOST_PKT = (128 * 0),
75 PDC_DIMM_HPKT_PRD = (128 * 1),
76 PDC_DIMM_ATA_PKT = (128 * 2),
77 PDC_DIMM_APKT_PRD = (128 * 3),
78 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
79 PDC_PAGE_WINDOW = 0x40,
80 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
81 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
82 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
83
84 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
85
86 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
87 (1<<23),
88
89 board_20621 = 0, /* FastTrak S150 SX4 */
90
91 PDC_RESET = (1 << 11), /* HDMA reset */
92
93 PDC_MAX_HDMA = 32,
94 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
95
96 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
97 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
98 PDC_MAX_DIMM_MODULE = 0x02,
99 PDC_I2C_CONTROL_OFFSET = 0x48,
100 PDC_I2C_ADDR_DATA_OFFSET = 0x4C,
101 PDC_DIMM0_CONTROL_OFFSET = 0x80,
102 PDC_DIMM1_CONTROL_OFFSET = 0x84,
103 PDC_SDRAM_CONTROL_OFFSET = 0x88,
104 PDC_I2C_WRITE = 0x00000000,
105 PDC_I2C_READ = 0x00000040,
106 PDC_I2C_START = 0x00000080,
107 PDC_I2C_MASK_INT = 0x00000020,
108 PDC_I2C_COMPLETE = 0x00010000,
109 PDC_I2C_NO_ACK = 0x00100000,
110 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
111 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
112 PDC_DIMM_SPD_ROW_NUM = 3,
113 PDC_DIMM_SPD_COLUMN_NUM = 4,
114 PDC_DIMM_SPD_MODULE_ROW = 5,
115 PDC_DIMM_SPD_TYPE = 11,
116 PDC_DIMM_SPD_FRESH_RATE = 12,
117 PDC_DIMM_SPD_BANK_NUM = 17,
118 PDC_DIMM_SPD_CAS_LATENCY = 18,
119 PDC_DIMM_SPD_ATTRIBUTE = 21,
120 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
121 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
122 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
123 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
124 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
125 PDC_CTL_STATUS = 0x08,
126 PDC_DIMM_WINDOW_CTLR = 0x0C,
127 PDC_TIME_CONTROL = 0x3C,
128 PDC_TIME_PERIOD = 0x40,
129 PDC_TIME_COUNTER = 0x44,
130 PDC_GENERAL_CTLR = 0x484,
131 PCI_PLL_INIT = 0x8A531824,
132 PCI_X_TCOUNT = 0xEE1E5CFF
133 };
134
135
136 struct pdc_port_priv {
137 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
138 u8 *pkt;
139 dma_addr_t pkt_dma;
140 };
141
142 struct pdc_host_priv {
143 unsigned int doing_hdma;
144 unsigned int hdma_prod;
145 unsigned int hdma_cons;
146 struct {
147 struct ata_queued_cmd *qc;
148 unsigned int seq;
149 unsigned long pkt_ofs;
150 } hdma[32];
151 };
152
153
154 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
155 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance);
156 static void pdc_eng_timeout(struct ata_port *ap);
157 static void pdc_20621_phy_reset (struct ata_port *ap);
158 static int pdc_port_start(struct ata_port *ap);
159 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
160 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
161 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
162 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
163 static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
164 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
165 u32 device, u32 subaddr, u32 *pdata);
166 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
167 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
168 #ifdef ATA_VERBOSE_DEBUG
169 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
170 void *psource, u32 offset, u32 size);
171 #endif
172 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
173 void *psource, u32 offset, u32 size);
174 static void pdc20621_irq_clear(struct ata_port *ap);
175 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
176
177
178 static struct scsi_host_template pdc_sata_sht = {
179 .module = THIS_MODULE,
180 .name = DRV_NAME,
181 .ioctl = ata_scsi_ioctl,
182 .queuecommand = ata_scsi_queuecmd,
183 .can_queue = ATA_DEF_QUEUE,
184 .this_id = ATA_SHT_THIS_ID,
185 .sg_tablesize = LIBATA_MAX_PRD,
186 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
187 .emulated = ATA_SHT_EMULATED,
188 .use_clustering = ATA_SHT_USE_CLUSTERING,
189 .proc_name = DRV_NAME,
190 .dma_boundary = ATA_DMA_BOUNDARY,
191 .slave_configure = ata_scsi_slave_config,
192 .slave_destroy = ata_scsi_slave_destroy,
193 .bios_param = ata_std_bios_param,
194 };
195
196 static const struct ata_port_operations pdc_20621_ops = {
197 .port_disable = ata_port_disable,
198 .tf_load = pdc_tf_load_mmio,
199 .tf_read = ata_tf_read,
200 .check_status = ata_check_status,
201 .exec_command = pdc_exec_command_mmio,
202 .dev_select = ata_std_dev_select,
203 .phy_reset = pdc_20621_phy_reset,
204 .qc_prep = pdc20621_qc_prep,
205 .qc_issue = pdc20621_qc_issue_prot,
206 .data_xfer = ata_data_xfer,
207 .eng_timeout = pdc_eng_timeout,
208 .irq_handler = pdc20621_interrupt,
209 .irq_clear = pdc20621_irq_clear,
210 .port_start = pdc_port_start,
211 };
212
213 static const struct ata_port_info pdc_port_info[] = {
214 /* board_20621 */
215 {
216 .sht = &pdc_sata_sht,
217 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
218 ATA_FLAG_SRST | ATA_FLAG_MMIO |
219 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING,
220 .pio_mask = 0x1f, /* pio0-4 */
221 .mwdma_mask = 0x07, /* mwdma0-2 */
222 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
223 .port_ops = &pdc_20621_ops,
224 },
225
226 };
227
228 static const struct pci_device_id pdc_sata_pci_tbl[] = {
229 { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
230
231 { } /* terminate list */
232 };
233
234 static struct pci_driver pdc_sata_pci_driver = {
235 .name = DRV_NAME,
236 .id_table = pdc_sata_pci_tbl,
237 .probe = pdc_sata_init_one,
238 .remove = ata_pci_remove_one,
239 };
240
241
242 static int pdc_port_start(struct ata_port *ap)
243 {
244 struct device *dev = ap->host->dev;
245 struct pdc_port_priv *pp;
246 int rc;
247
248 rc = ata_port_start(ap);
249 if (rc)
250 return rc;
251
252 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
253 if (!pp)
254 return -ENOMEM;
255
256 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
257 if (!pp->pkt)
258 return -ENOMEM;
259
260 ap->private_data = pp;
261
262 return 0;
263 }
264
265 static void pdc_20621_phy_reset (struct ata_port *ap)
266 {
267 VPRINTK("ENTER\n");
268 ap->cbl = ATA_CBL_SATA;
269 ata_port_probe(ap);
270 ata_bus_reset(ap);
271 }
272
273 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
274 unsigned int portno,
275 unsigned int total_len)
276 {
277 u32 addr;
278 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
279 u32 *buf32 = (u32 *) buf;
280
281 /* output ATA packet S/G table */
282 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
283 (PDC_DIMM_DATA_STEP * portno);
284 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
285 buf32[dw] = cpu_to_le32(addr);
286 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
287
288 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
289 PDC_20621_DIMM_BASE +
290 (PDC_DIMM_WINDOW_STEP * portno) +
291 PDC_DIMM_APKT_PRD,
292 buf32[dw], buf32[dw + 1]);
293 }
294
295 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
296 unsigned int portno,
297 unsigned int total_len)
298 {
299 u32 addr;
300 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
301 u32 *buf32 = (u32 *) buf;
302
303 /* output Host DMA packet S/G table */
304 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
305 (PDC_DIMM_DATA_STEP * portno);
306
307 buf32[dw] = cpu_to_le32(addr);
308 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
309
310 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
311 PDC_20621_DIMM_BASE +
312 (PDC_DIMM_WINDOW_STEP * portno) +
313 PDC_DIMM_HPKT_PRD,
314 buf32[dw], buf32[dw + 1]);
315 }
316
317 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
318 unsigned int devno, u8 *buf,
319 unsigned int portno)
320 {
321 unsigned int i, dw;
322 u32 *buf32 = (u32 *) buf;
323 u8 dev_reg;
324
325 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
326 (PDC_DIMM_WINDOW_STEP * portno) +
327 PDC_DIMM_APKT_PRD;
328 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
329
330 i = PDC_DIMM_ATA_PKT;
331
332 /*
333 * Set up ATA packet
334 */
335 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
336 buf[i++] = PDC_PKT_READ;
337 else if (tf->protocol == ATA_PROT_NODATA)
338 buf[i++] = PDC_PKT_NODATA;
339 else
340 buf[i++] = 0;
341 buf[i++] = 0; /* reserved */
342 buf[i++] = portno + 1; /* seq. id */
343 buf[i++] = 0xff; /* delay seq. id */
344
345 /* dimm dma S/G, and next-pkt */
346 dw = i >> 2;
347 if (tf->protocol == ATA_PROT_NODATA)
348 buf32[dw] = 0;
349 else
350 buf32[dw] = cpu_to_le32(dimm_sg);
351 buf32[dw + 1] = 0;
352 i += 8;
353
354 if (devno == 0)
355 dev_reg = ATA_DEVICE_OBS;
356 else
357 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
358
359 /* select device */
360 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
361 buf[i++] = dev_reg;
362
363 /* device control register */
364 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
365 buf[i++] = tf->ctl;
366
367 return i;
368 }
369
370 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
371 unsigned int portno)
372 {
373 unsigned int dw;
374 u32 tmp, *buf32 = (u32 *) buf;
375
376 unsigned int host_sg = PDC_20621_DIMM_BASE +
377 (PDC_DIMM_WINDOW_STEP * portno) +
378 PDC_DIMM_HOST_PRD;
379 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
380 (PDC_DIMM_WINDOW_STEP * portno) +
381 PDC_DIMM_HPKT_PRD;
382 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
383 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
384
385 dw = PDC_DIMM_HOST_PKT >> 2;
386
387 /*
388 * Set up Host DMA packet
389 */
390 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
391 tmp = PDC_PKT_READ;
392 else
393 tmp = 0;
394 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
395 tmp |= (0xff << 24); /* delay seq. id */
396 buf32[dw + 0] = cpu_to_le32(tmp);
397 buf32[dw + 1] = cpu_to_le32(host_sg);
398 buf32[dw + 2] = cpu_to_le32(dimm_sg);
399 buf32[dw + 3] = 0;
400
401 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
402 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
403 PDC_DIMM_HOST_PKT,
404 buf32[dw + 0],
405 buf32[dw + 1],
406 buf32[dw + 2],
407 buf32[dw + 3]);
408 }
409
410 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
411 {
412 struct scatterlist *sg;
413 struct ata_port *ap = qc->ap;
414 struct pdc_port_priv *pp = ap->private_data;
415 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
416 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
417 unsigned int portno = ap->port_no;
418 unsigned int i, idx, total_len = 0, sgt_len;
419 u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
420
421 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
422
423 VPRINTK("ata%u: ENTER\n", ap->id);
424
425 /* hard-code chip #0 */
426 mmio += PDC_CHIP0_OFS;
427
428 /*
429 * Build S/G table
430 */
431 idx = 0;
432 ata_for_each_sg(sg, qc) {
433 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
434 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
435 total_len += sg_dma_len(sg);
436 }
437 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
438 sgt_len = idx * 4;
439
440 /*
441 * Build ATA, host DMA packets
442 */
443 pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
444 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
445
446 pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
447 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
448
449 if (qc->tf.flags & ATA_TFLAG_LBA48)
450 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
451 else
452 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
453
454 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
455
456 /* copy three S/G tables and two packets to DIMM MMIO window */
457 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
458 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
459 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
460 PDC_DIMM_HOST_PRD,
461 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
462
463 /* force host FIFO dump */
464 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
465
466 readl(dimm_mmio); /* MMIO PCI posting flush */
467
468 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
469 }
470
471 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
472 {
473 struct ata_port *ap = qc->ap;
474 struct pdc_port_priv *pp = ap->private_data;
475 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
476 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
477 unsigned int portno = ap->port_no;
478 unsigned int i;
479
480 VPRINTK("ata%u: ENTER\n", ap->id);
481
482 /* hard-code chip #0 */
483 mmio += PDC_CHIP0_OFS;
484
485 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
486
487 if (qc->tf.flags & ATA_TFLAG_LBA48)
488 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
489 else
490 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
491
492 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
493
494 /* copy three S/G tables and two packets to DIMM MMIO window */
495 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
496 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
497
498 /* force host FIFO dump */
499 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
500
501 readl(dimm_mmio); /* MMIO PCI posting flush */
502
503 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
504 }
505
506 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
507 {
508 switch (qc->tf.protocol) {
509 case ATA_PROT_DMA:
510 pdc20621_dma_prep(qc);
511 break;
512 case ATA_PROT_NODATA:
513 pdc20621_nodata_prep(qc);
514 break;
515 default:
516 break;
517 }
518 }
519
520 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
521 unsigned int seq,
522 u32 pkt_ofs)
523 {
524 struct ata_port *ap = qc->ap;
525 struct ata_host *host = ap->host;
526 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
527
528 /* hard-code chip #0 */
529 mmio += PDC_CHIP0_OFS;
530
531 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
532 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
533
534 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
535 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
536 }
537
538 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
539 unsigned int seq,
540 u32 pkt_ofs)
541 {
542 struct ata_port *ap = qc->ap;
543 struct pdc_host_priv *pp = ap->host->private_data;
544 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
545
546 if (!pp->doing_hdma) {
547 __pdc20621_push_hdma(qc, seq, pkt_ofs);
548 pp->doing_hdma = 1;
549 return;
550 }
551
552 pp->hdma[idx].qc = qc;
553 pp->hdma[idx].seq = seq;
554 pp->hdma[idx].pkt_ofs = pkt_ofs;
555 pp->hdma_prod++;
556 }
557
558 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
559 {
560 struct ata_port *ap = qc->ap;
561 struct pdc_host_priv *pp = ap->host->private_data;
562 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
563
564 /* if nothing on queue, we're done */
565 if (pp->hdma_prod == pp->hdma_cons) {
566 pp->doing_hdma = 0;
567 return;
568 }
569
570 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
571 pp->hdma[idx].pkt_ofs);
572 pp->hdma_cons++;
573 }
574
575 #ifdef ATA_VERBOSE_DEBUG
576 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
577 {
578 struct ata_port *ap = qc->ap;
579 unsigned int port_no = ap->port_no;
580 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
581
582 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
583 dimm_mmio += PDC_DIMM_HOST_PKT;
584
585 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
586 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
587 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
588 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
589 }
590 #else
591 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
592 #endif /* ATA_VERBOSE_DEBUG */
593
594 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
595 {
596 struct ata_port *ap = qc->ap;
597 struct ata_host *host = ap->host;
598 unsigned int port_no = ap->port_no;
599 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
600 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
601 u8 seq = (u8) (port_no + 1);
602 unsigned int port_ofs;
603
604 /* hard-code chip #0 */
605 mmio += PDC_CHIP0_OFS;
606
607 VPRINTK("ata%u: ENTER\n", ap->id);
608
609 wmb(); /* flush PRD, pkt writes */
610
611 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
612
613 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
614 if (rw && qc->tf.protocol == ATA_PROT_DMA) {
615 seq += 4;
616
617 pdc20621_dump_hdma(qc);
618 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
619 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
620 port_ofs + PDC_DIMM_HOST_PKT,
621 port_ofs + PDC_DIMM_HOST_PKT,
622 seq);
623 } else {
624 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
625 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
626
627 writel(port_ofs + PDC_DIMM_ATA_PKT,
628 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
629 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
630 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
631 port_ofs + PDC_DIMM_ATA_PKT,
632 port_ofs + PDC_DIMM_ATA_PKT,
633 seq);
634 }
635 }
636
637 static unsigned int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
638 {
639 switch (qc->tf.protocol) {
640 case ATA_PROT_DMA:
641 case ATA_PROT_NODATA:
642 pdc20621_packet_start(qc);
643 return 0;
644
645 case ATA_PROT_ATAPI_DMA:
646 BUG();
647 break;
648
649 default:
650 break;
651 }
652
653 return ata_qc_issue_prot(qc);
654 }
655
656 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
657 struct ata_queued_cmd *qc,
658 unsigned int doing_hdma,
659 void __iomem *mmio)
660 {
661 unsigned int port_no = ap->port_no;
662 unsigned int port_ofs =
663 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
664 u8 status;
665 unsigned int handled = 0;
666
667 VPRINTK("ENTER\n");
668
669 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
670 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
671
672 /* step two - DMA from DIMM to host */
673 if (doing_hdma) {
674 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
675 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
676 /* get drive status; clear intr; complete txn */
677 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
678 ata_qc_complete(qc);
679 pdc20621_pop_hdma(qc);
680 }
681
682 /* step one - exec ATA command */
683 else {
684 u8 seq = (u8) (port_no + 1 + 4);
685 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
686 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
687
688 /* submit hdma pkt */
689 pdc20621_dump_hdma(qc);
690 pdc20621_push_hdma(qc, seq,
691 port_ofs + PDC_DIMM_HOST_PKT);
692 }
693 handled = 1;
694
695 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
696
697 /* step one - DMA from host to DIMM */
698 if (doing_hdma) {
699 u8 seq = (u8) (port_no + 1);
700 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
701 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
702
703 /* submit ata pkt */
704 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
705 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
706 writel(port_ofs + PDC_DIMM_ATA_PKT,
707 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
708 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
709 }
710
711 /* step two - execute ATA command */
712 else {
713 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
714 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
715 /* get drive status; clear intr; complete txn */
716 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
717 ata_qc_complete(qc);
718 pdc20621_pop_hdma(qc);
719 }
720 handled = 1;
721
722 /* command completion, but no data xfer */
723 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
724
725 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
726 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
727 qc->err_mask |= ac_err_mask(status);
728 ata_qc_complete(qc);
729 handled = 1;
730
731 } else {
732 ap->stats.idle_irq++;
733 }
734
735 return handled;
736 }
737
738 static void pdc20621_irq_clear(struct ata_port *ap)
739 {
740 struct ata_host *host = ap->host;
741 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
742
743 mmio += PDC_CHIP0_OFS;
744
745 readl(mmio + PDC_20621_SEQMASK);
746 }
747
748 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance)
749 {
750 struct ata_host *host = dev_instance;
751 struct ata_port *ap;
752 u32 mask = 0;
753 unsigned int i, tmp, port_no;
754 unsigned int handled = 0;
755 void __iomem *mmio_base;
756
757 VPRINTK("ENTER\n");
758
759 if (!host || !host->iomap[PDC_MMIO_BAR]) {
760 VPRINTK("QUICK EXIT\n");
761 return IRQ_NONE;
762 }
763
764 mmio_base = host->iomap[PDC_MMIO_BAR];
765
766 /* reading should also clear interrupts */
767 mmio_base += PDC_CHIP0_OFS;
768 mask = readl(mmio_base + PDC_20621_SEQMASK);
769 VPRINTK("mask == 0x%x\n", mask);
770
771 if (mask == 0xffffffff) {
772 VPRINTK("QUICK EXIT 2\n");
773 return IRQ_NONE;
774 }
775 mask &= 0xffff; /* only 16 tags possible */
776 if (!mask) {
777 VPRINTK("QUICK EXIT 3\n");
778 return IRQ_NONE;
779 }
780
781 spin_lock(&host->lock);
782
783 for (i = 1; i < 9; i++) {
784 port_no = i - 1;
785 if (port_no > 3)
786 port_no -= 4;
787 if (port_no >= host->n_ports)
788 ap = NULL;
789 else
790 ap = host->ports[port_no];
791 tmp = mask & (1 << i);
792 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
793 if (tmp && ap &&
794 !(ap->flags & ATA_FLAG_DISABLED)) {
795 struct ata_queued_cmd *qc;
796
797 qc = ata_qc_from_tag(ap, ap->active_tag);
798 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
799 handled += pdc20621_host_intr(ap, qc, (i > 4),
800 mmio_base);
801 }
802 }
803
804 spin_unlock(&host->lock);
805
806 VPRINTK("mask == 0x%x\n", mask);
807
808 VPRINTK("EXIT\n");
809
810 return IRQ_RETVAL(handled);
811 }
812
813 static void pdc_eng_timeout(struct ata_port *ap)
814 {
815 u8 drv_stat;
816 struct ata_host *host = ap->host;
817 struct ata_queued_cmd *qc;
818 unsigned long flags;
819
820 DPRINTK("ENTER\n");
821
822 spin_lock_irqsave(&host->lock, flags);
823
824 qc = ata_qc_from_tag(ap, ap->active_tag);
825
826 switch (qc->tf.protocol) {
827 case ATA_PROT_DMA:
828 case ATA_PROT_NODATA:
829 ata_port_printk(ap, KERN_ERR, "command timeout\n");
830 qc->err_mask |= __ac_err_mask(ata_wait_idle(ap));
831 break;
832
833 default:
834 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
835
836 ata_port_printk(ap, KERN_ERR,
837 "unknown timeout, cmd 0x%x stat 0x%x\n",
838 qc->tf.command, drv_stat);
839
840 qc->err_mask |= ac_err_mask(drv_stat);
841 break;
842 }
843
844 spin_unlock_irqrestore(&host->lock, flags);
845 ata_eh_qc_complete(qc);
846 DPRINTK("EXIT\n");
847 }
848
849 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
850 {
851 WARN_ON (tf->protocol == ATA_PROT_DMA ||
852 tf->protocol == ATA_PROT_NODATA);
853 ata_tf_load(ap, tf);
854 }
855
856
857 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
858 {
859 WARN_ON (tf->protocol == ATA_PROT_DMA ||
860 tf->protocol == ATA_PROT_NODATA);
861 ata_exec_command(ap, tf);
862 }
863
864
865 static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
866 {
867 port->cmd_addr = base;
868 port->data_addr = base;
869 port->feature_addr =
870 port->error_addr = base + 0x4;
871 port->nsect_addr = base + 0x8;
872 port->lbal_addr = base + 0xc;
873 port->lbam_addr = base + 0x10;
874 port->lbah_addr = base + 0x14;
875 port->device_addr = base + 0x18;
876 port->command_addr =
877 port->status_addr = base + 0x1c;
878 port->altstatus_addr =
879 port->ctl_addr = base + 0x38;
880 }
881
882
883 #ifdef ATA_VERBOSE_DEBUG
884 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
885 u32 offset, u32 size)
886 {
887 u32 window_size;
888 u16 idx;
889 u8 page_mask;
890 long dist;
891 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
892 void __iomem *dimm_mmio = pe->iomap[PDC_DIMM_BAR];
893
894 /* hard-code chip #0 */
895 mmio += PDC_CHIP0_OFS;
896
897 page_mask = 0x00;
898 window_size = 0x2000 * 4; /* 32K byte uchar size */
899 idx = (u16) (offset / window_size);
900
901 writel(0x01, mmio + PDC_GENERAL_CTLR);
902 readl(mmio + PDC_GENERAL_CTLR);
903 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
904 readl(mmio + PDC_DIMM_WINDOW_CTLR);
905
906 offset -= (idx * window_size);
907 idx++;
908 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
909 (long) (window_size - offset);
910 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
911 dist);
912
913 psource += dist;
914 size -= dist;
915 for (; (long) size >= (long) window_size ;) {
916 writel(0x01, mmio + PDC_GENERAL_CTLR);
917 readl(mmio + PDC_GENERAL_CTLR);
918 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
919 readl(mmio + PDC_DIMM_WINDOW_CTLR);
920 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
921 window_size / 4);
922 psource += window_size;
923 size -= window_size;
924 idx ++;
925 }
926
927 if (size) {
928 writel(0x01, mmio + PDC_GENERAL_CTLR);
929 readl(mmio + PDC_GENERAL_CTLR);
930 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
931 readl(mmio + PDC_DIMM_WINDOW_CTLR);
932 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
933 size / 4);
934 }
935 }
936 #endif
937
938
939 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
940 u32 offset, u32 size)
941 {
942 u32 window_size;
943 u16 idx;
944 u8 page_mask;
945 long dist;
946 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
947 void __iomem *dimm_mmio = pe->iomap[PDC_DIMM_BAR];
948
949 /* hard-code chip #0 */
950 mmio += PDC_CHIP0_OFS;
951
952 page_mask = 0x00;
953 window_size = 0x2000 * 4; /* 32K byte uchar size */
954 idx = (u16) (offset / window_size);
955
956 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
957 readl(mmio + PDC_DIMM_WINDOW_CTLR);
958 offset -= (idx * window_size);
959 idx++;
960 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
961 (long) (window_size - offset);
962 memcpy_toio(dimm_mmio + offset / 4, psource, dist);
963 writel(0x01, mmio + PDC_GENERAL_CTLR);
964 readl(mmio + PDC_GENERAL_CTLR);
965
966 psource += dist;
967 size -= dist;
968 for (; (long) size >= (long) window_size ;) {
969 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
970 readl(mmio + PDC_DIMM_WINDOW_CTLR);
971 memcpy_toio(dimm_mmio, psource, window_size / 4);
972 writel(0x01, mmio + PDC_GENERAL_CTLR);
973 readl(mmio + PDC_GENERAL_CTLR);
974 psource += window_size;
975 size -= window_size;
976 idx ++;
977 }
978
979 if (size) {
980 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
981 readl(mmio + PDC_DIMM_WINDOW_CTLR);
982 memcpy_toio(dimm_mmio, psource, size / 4);
983 writel(0x01, mmio + PDC_GENERAL_CTLR);
984 readl(mmio + PDC_GENERAL_CTLR);
985 }
986 }
987
988
989 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
990 u32 subaddr, u32 *pdata)
991 {
992 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
993 u32 i2creg = 0;
994 u32 status;
995 u32 count =0;
996
997 /* hard-code chip #0 */
998 mmio += PDC_CHIP0_OFS;
999
1000 i2creg |= device << 24;
1001 i2creg |= subaddr << 16;
1002
1003 /* Set the device and subaddress */
1004 writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1005 readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1006
1007 /* Write Control to perform read operation, mask int */
1008 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1009 mmio + PDC_I2C_CONTROL_OFFSET);
1010
1011 for (count = 0; count <= 1000; count ++) {
1012 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1013 if (status & PDC_I2C_COMPLETE) {
1014 status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1015 break;
1016 } else if (count == 1000)
1017 return 0;
1018 }
1019
1020 *pdata = (status >> 8) & 0x000000ff;
1021 return 1;
1022 }
1023
1024
1025 static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1026 {
1027 u32 data=0 ;
1028 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1029 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1030 if (data == 100)
1031 return 100;
1032 } else
1033 return 0;
1034
1035 if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1036 if(data <= 0x75)
1037 return 133;
1038 } else
1039 return 0;
1040
1041 return 0;
1042 }
1043
1044
1045 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1046 {
1047 u32 spd0[50];
1048 u32 data = 0;
1049 int size, i;
1050 u8 bdimmsize;
1051 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
1052 static const struct {
1053 unsigned int reg;
1054 unsigned int ofs;
1055 } pdc_i2c_read_data [] = {
1056 { PDC_DIMM_SPD_TYPE, 11 },
1057 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1058 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1059 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1060 { PDC_DIMM_SPD_ROW_NUM, 3 },
1061 { PDC_DIMM_SPD_BANK_NUM, 17 },
1062 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1063 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1064 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1065 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1066 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1067 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1068 };
1069
1070 /* hard-code chip #0 */
1071 mmio += PDC_CHIP0_OFS;
1072
1073 for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1074 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1075 pdc_i2c_read_data[i].reg,
1076 &spd0[pdc_i2c_read_data[i].ofs]);
1077
1078 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1079 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1080 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1081 data |= (((((spd0[29] > spd0[28])
1082 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1083 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1084
1085 if (spd0[18] & 0x08)
1086 data |= ((0x03) << 14);
1087 else if (spd0[18] & 0x04)
1088 data |= ((0x02) << 14);
1089 else if (spd0[18] & 0x01)
1090 data |= ((0x01) << 14);
1091 else
1092 data |= (0 << 14);
1093
1094 /*
1095 Calculate the size of bDIMMSize (power of 2) and
1096 merge the DIMM size by program start/end address.
1097 */
1098
1099 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1100 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1101 data |= (((size / 16) - 1) << 16);
1102 data |= (0 << 23);
1103 data |= 8;
1104 writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1105 readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1106 return size;
1107 }
1108
1109
1110 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1111 {
1112 u32 data, spd0;
1113 int error, i;
1114 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
1115
1116 /* hard-code chip #0 */
1117 mmio += PDC_CHIP0_OFS;
1118
1119 /*
1120 Set To Default : DIMM Module Global Control Register (0x022259F1)
1121 DIMM Arbitration Disable (bit 20)
1122 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1123 Refresh Enable (bit 17)
1124 */
1125
1126 data = 0x022259F1;
1127 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1128 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1129
1130 /* Turn on for ECC */
1131 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1132 PDC_DIMM_SPD_TYPE, &spd0);
1133 if (spd0 == 0x02) {
1134 data |= (0x01 << 16);
1135 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1136 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1137 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1138 }
1139
1140 /* DIMM Initialization Select/Enable (bit 18/19) */
1141 data &= (~(1<<18));
1142 data |= (1<<19);
1143 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1144
1145 error = 1;
1146 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
1147 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1148 if (!(data & (1<<19))) {
1149 error = 0;
1150 break;
1151 }
1152 msleep(i*100);
1153 }
1154 return error;
1155 }
1156
1157
1158 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1159 {
1160 int speed, size, length;
1161 u32 addr,spd0,pci_status;
1162 u32 tmp=0;
1163 u32 time_period=0;
1164 u32 tcount=0;
1165 u32 ticks=0;
1166 u32 clock=0;
1167 u32 fparam=0;
1168 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
1169
1170 /* hard-code chip #0 */
1171 mmio += PDC_CHIP0_OFS;
1172
1173 /* Initialize PLL based upon PCI Bus Frequency */
1174
1175 /* Initialize Time Period Register */
1176 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1177 time_period = readl(mmio + PDC_TIME_PERIOD);
1178 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1179
1180 /* Enable timer */
1181 writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1182 readl(mmio + PDC_TIME_CONTROL);
1183
1184 /* Wait 3 seconds */
1185 msleep(3000);
1186
1187 /*
1188 When timer is enabled, counter is decreased every internal
1189 clock cycle.
1190 */
1191
1192 tcount = readl(mmio + PDC_TIME_COUNTER);
1193 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1194
1195 /*
1196 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1197 register should be >= (0xffffffff - 3x10^8).
1198 */
1199 if(tcount >= PCI_X_TCOUNT) {
1200 ticks = (time_period - tcount);
1201 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1202
1203 clock = (ticks / 300000);
1204 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1205
1206 clock = (clock * 33);
1207 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1208
1209 /* PLL F Param (bit 22:16) */
1210 fparam = (1400000 / clock) - 2;
1211 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1212
1213 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1214 pci_status = (0x8a001824 | (fparam << 16));
1215 } else
1216 pci_status = PCI_PLL_INIT;
1217
1218 /* Initialize PLL. */
1219 VPRINTK("pci_status: 0x%x\n", pci_status);
1220 writel(pci_status, mmio + PDC_CTL_STATUS);
1221 readl(mmio + PDC_CTL_STATUS);
1222
1223 /*
1224 Read SPD of DIMM by I2C interface,
1225 and program the DIMM Module Controller.
1226 */
1227 if (!(speed = pdc20621_detect_dimm(pe))) {
1228 printk(KERN_ERR "Detect Local DIMM Fail\n");
1229 return 1; /* DIMM error */
1230 }
1231 VPRINTK("Local DIMM Speed = %d\n", speed);
1232
1233 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1234 size = pdc20621_prog_dimm0(pe);
1235 VPRINTK("Local DIMM Size = %dMB\n",size);
1236
1237 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1238 if (pdc20621_prog_dimm_global(pe)) {
1239 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1240 return 1;
1241 }
1242
1243 #ifdef ATA_VERBOSE_DEBUG
1244 {
1245 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1246 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1247 '1','.','1','0',
1248 '9','8','0','3','1','6','1','2',0,0};
1249 u8 test_parttern2[40] = {0};
1250
1251 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1252 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1253
1254 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1255 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1256 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1257 test_parttern2[1], &(test_parttern2[2]));
1258 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1259 40);
1260 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1261 test_parttern2[1], &(test_parttern2[2]));
1262
1263 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1264 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1265 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1266 test_parttern2[1], &(test_parttern2[2]));
1267 }
1268 #endif
1269
1270 /* ECC initiliazation. */
1271
1272 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1273 PDC_DIMM_SPD_TYPE, &spd0);
1274 if (spd0 == 0x02) {
1275 VPRINTK("Start ECC initialization\n");
1276 addr = 0;
1277 length = size * 1024 * 1024;
1278 while (addr < length) {
1279 pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1280 sizeof(u32));
1281 addr += sizeof(u32);
1282 }
1283 VPRINTK("Finish ECC initialization\n");
1284 }
1285 return 0;
1286 }
1287
1288
1289 static void pdc_20621_init(struct ata_probe_ent *pe)
1290 {
1291 u32 tmp;
1292 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
1293
1294 /* hard-code chip #0 */
1295 mmio += PDC_CHIP0_OFS;
1296
1297 /*
1298 * Select page 0x40 for our 32k DIMM window
1299 */
1300 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1301 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1302 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1303
1304 /*
1305 * Reset Host DMA
1306 */
1307 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1308 tmp |= PDC_RESET;
1309 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1310 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1311
1312 udelay(10);
1313
1314 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1315 tmp &= ~PDC_RESET;
1316 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1317 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1318 }
1319
1320 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1321 {
1322 static int printed_version;
1323 struct ata_probe_ent *probe_ent;
1324 void __iomem *base;
1325 struct pdc_host_priv *hpriv;
1326 unsigned int board_idx = (unsigned int) ent->driver_data;
1327 int rc;
1328
1329 if (!printed_version++)
1330 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1331
1332 rc = pcim_enable_device(pdev);
1333 if (rc)
1334 return rc;
1335
1336 rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR),
1337 DRV_NAME);
1338 if (rc == -EBUSY)
1339 pcim_pin_device(pdev);
1340 if (rc)
1341 return rc;
1342
1343 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1344 if (rc)
1345 return rc;
1346 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1347 if (rc)
1348 return rc;
1349
1350 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
1351 if (probe_ent == NULL)
1352 return -ENOMEM;
1353
1354 probe_ent->dev = pci_dev_to_dev(pdev);
1355 INIT_LIST_HEAD(&probe_ent->node);
1356
1357 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1358 if (!hpriv)
1359 return -ENOMEM;
1360
1361 probe_ent->sht = pdc_port_info[board_idx].sht;
1362 probe_ent->port_flags = pdc_port_info[board_idx].flags;
1363 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
1364 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
1365 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
1366 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
1367
1368 probe_ent->irq = pdev->irq;
1369 probe_ent->irq_flags = IRQF_SHARED;
1370 probe_ent->iomap = pcim_iomap_table(pdev);
1371
1372 probe_ent->private_data = hpriv;
1373 base = probe_ent->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
1374
1375 probe_ent->n_ports = 4;
1376 pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1377 pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1378 pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1379 pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1380
1381 pci_set_master(pdev);
1382
1383 /* initialize adapter */
1384 /* initialize local dimm */
1385 if (pdc20621_dimm_init(probe_ent))
1386 return -ENOMEM;
1387 pdc_20621_init(probe_ent);
1388
1389 if (!ata_device_add(probe_ent))
1390 return -ENODEV;
1391
1392 devm_kfree(&pdev->dev, probe_ent);
1393 return 0;
1394 }
1395
1396
1397 static int __init pdc_sata_init(void)
1398 {
1399 return pci_register_driver(&pdc_sata_pci_driver);
1400 }
1401
1402
1403 static void __exit pdc_sata_exit(void)
1404 {
1405 pci_unregister_driver(&pdc_sata_pci_driver);
1406 }
1407
1408
1409 MODULE_AUTHOR("Jeff Garzik");
1410 MODULE_DESCRIPTION("Promise SATA low-level driver");
1411 MODULE_LICENSE("GPL");
1412 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1413 MODULE_VERSION(DRV_VERSION);
1414
1415 module_init(pdc_sata_init);
1416 module_exit(pdc_sata_exit);
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