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1 /*
2 * sata_via.c - VIA Serial ATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available under NDA.
31 *
32 *
33 *
34 */
35
36 #include <linux/kernel.h>
37 #include <linux/module.h>
38 #include <linux/pci.h>
39 #include <linux/init.h>
40 #include <linux/blkdev.h>
41 #include <linux/delay.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
45
46 #define DRV_NAME "sata_via"
47 #define DRV_VERSION "2.3"
48
49 enum board_ids_enum {
50 vt6420,
51 vt6421,
52 };
53
54 enum {
55 SATA_CHAN_ENAB = 0x40, /* SATA channel enable */
56 SATA_INT_GATE = 0x41, /* SATA interrupt gating */
57 SATA_NATIVE_MODE = 0x42, /* Native mode enable */
58 PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */
59 PATA_PIO_TIMING = 0xAB, /* PATA timing register */
60
61 PORT0 = (1 << 1),
62 PORT1 = (1 << 0),
63 ALL_PORTS = PORT0 | PORT1,
64
65 NATIVE_MODE_ALL = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4),
66
67 SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */
68 };
69
70 static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
71 static int svia_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
72 static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
73 static void svia_noop_freeze(struct ata_port *ap);
74 static void vt6420_error_handler(struct ata_port *ap);
75 static int vt6421_pata_cable_detect(struct ata_port *ap);
76 static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev);
77 static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev);
78
79 static const struct pci_device_id svia_pci_tbl[] = {
80 { PCI_VDEVICE(VIA, 0x5337), vt6420 },
81 { PCI_VDEVICE(VIA, 0x0591), vt6420 },
82 { PCI_VDEVICE(VIA, 0x3149), vt6420 },
83 { PCI_VDEVICE(VIA, 0x3249), vt6421 },
84 { PCI_VDEVICE(VIA, 0x5287), vt6420 },
85 { PCI_VDEVICE(VIA, 0x5372), vt6420 },
86 { PCI_VDEVICE(VIA, 0x7372), vt6420 },
87
88 { } /* terminate list */
89 };
90
91 static struct pci_driver svia_pci_driver = {
92 .name = DRV_NAME,
93 .id_table = svia_pci_tbl,
94 .probe = svia_init_one,
95 #ifdef CONFIG_PM
96 .suspend = ata_pci_device_suspend,
97 .resume = ata_pci_device_resume,
98 #endif
99 .remove = ata_pci_remove_one,
100 };
101
102 static struct scsi_host_template svia_sht = {
103 ATA_BMDMA_SHT(DRV_NAME),
104 };
105
106 static const struct ata_port_operations vt6420_sata_ops = {
107 .mode_filter = ata_pci_default_filter,
108
109 .tf_load = ata_tf_load,
110 .tf_read = ata_tf_read,
111 .check_status = ata_check_status,
112 .exec_command = ata_exec_command,
113 .dev_select = ata_std_dev_select,
114
115 .bmdma_setup = ata_bmdma_setup,
116 .bmdma_start = ata_bmdma_start,
117 .bmdma_stop = ata_bmdma_stop,
118 .bmdma_status = ata_bmdma_status,
119
120 .qc_prep = ata_qc_prep,
121 .qc_issue = ata_qc_issue_prot,
122 .data_xfer = ata_data_xfer,
123
124 .freeze = svia_noop_freeze,
125 .thaw = ata_bmdma_thaw,
126 .error_handler = vt6420_error_handler,
127 .post_internal_cmd = ata_bmdma_post_internal_cmd,
128
129 .irq_clear = ata_bmdma_irq_clear,
130 .irq_on = ata_irq_on,
131
132 .port_start = ata_sff_port_start,
133 };
134
135 static const struct ata_port_operations vt6421_pata_ops = {
136 .set_piomode = vt6421_set_pio_mode,
137 .set_dmamode = vt6421_set_dma_mode,
138 .mode_filter = ata_pci_default_filter,
139
140 .tf_load = ata_tf_load,
141 .tf_read = ata_tf_read,
142 .check_status = ata_check_status,
143 .exec_command = ata_exec_command,
144 .dev_select = ata_std_dev_select,
145
146 .bmdma_setup = ata_bmdma_setup,
147 .bmdma_start = ata_bmdma_start,
148 .bmdma_stop = ata_bmdma_stop,
149 .bmdma_status = ata_bmdma_status,
150
151 .qc_prep = ata_qc_prep,
152 .qc_issue = ata_qc_issue_prot,
153 .data_xfer = ata_data_xfer,
154
155 .freeze = ata_bmdma_freeze,
156 .thaw = ata_bmdma_thaw,
157 .error_handler = ata_bmdma_error_handler,
158 .post_internal_cmd = ata_bmdma_post_internal_cmd,
159 .cable_detect = vt6421_pata_cable_detect,
160
161 .irq_clear = ata_bmdma_irq_clear,
162 .irq_on = ata_irq_on,
163
164 .port_start = ata_sff_port_start,
165 };
166
167 static const struct ata_port_operations vt6421_sata_ops = {
168 .mode_filter = ata_pci_default_filter,
169
170 .tf_load = ata_tf_load,
171 .tf_read = ata_tf_read,
172 .check_status = ata_check_status,
173 .exec_command = ata_exec_command,
174 .dev_select = ata_std_dev_select,
175
176 .bmdma_setup = ata_bmdma_setup,
177 .bmdma_start = ata_bmdma_start,
178 .bmdma_stop = ata_bmdma_stop,
179 .bmdma_status = ata_bmdma_status,
180
181 .qc_prep = ata_qc_prep,
182 .qc_issue = ata_qc_issue_prot,
183 .data_xfer = ata_data_xfer,
184
185 .freeze = ata_bmdma_freeze,
186 .thaw = ata_bmdma_thaw,
187 .error_handler = ata_bmdma_error_handler,
188 .post_internal_cmd = ata_bmdma_post_internal_cmd,
189
190 .irq_clear = ata_bmdma_irq_clear,
191 .irq_on = ata_irq_on,
192
193 .scr_read = svia_scr_read,
194 .scr_write = svia_scr_write,
195
196 .port_start = ata_sff_port_start,
197 };
198
199 static const struct ata_port_info vt6420_port_info = {
200 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
201 .pio_mask = 0x1f,
202 .mwdma_mask = 0x07,
203 .udma_mask = ATA_UDMA6,
204 .port_ops = &vt6420_sata_ops,
205 };
206
207 static struct ata_port_info vt6421_sport_info = {
208 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
209 .pio_mask = 0x1f,
210 .mwdma_mask = 0x07,
211 .udma_mask = ATA_UDMA6,
212 .port_ops = &vt6421_sata_ops,
213 };
214
215 static struct ata_port_info vt6421_pport_info = {
216 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_LEGACY,
217 .pio_mask = 0x1f,
218 .mwdma_mask = 0,
219 .udma_mask = ATA_UDMA6,
220 .port_ops = &vt6421_pata_ops,
221 };
222
223 MODULE_AUTHOR("Jeff Garzik");
224 MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers");
225 MODULE_LICENSE("GPL");
226 MODULE_DEVICE_TABLE(pci, svia_pci_tbl);
227 MODULE_VERSION(DRV_VERSION);
228
229 static int svia_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
230 {
231 if (sc_reg > SCR_CONTROL)
232 return -EINVAL;
233 *val = ioread32(ap->ioaddr.scr_addr + (4 * sc_reg));
234 return 0;
235 }
236
237 static int svia_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
238 {
239 if (sc_reg > SCR_CONTROL)
240 return -EINVAL;
241 iowrite32(val, ap->ioaddr.scr_addr + (4 * sc_reg));
242 return 0;
243 }
244
245 static void svia_noop_freeze(struct ata_port *ap)
246 {
247 /* Some VIA controllers choke if ATA_NIEN is manipulated in
248 * certain way. Leave it alone and just clear pending IRQ.
249 */
250 ata_chk_status(ap);
251 ata_bmdma_irq_clear(ap);
252 }
253
254 /**
255 * vt6420_prereset - prereset for vt6420
256 * @link: target ATA link
257 * @deadline: deadline jiffies for the operation
258 *
259 * SCR registers on vt6420 are pieces of shit and may hang the
260 * whole machine completely if accessed with the wrong timing.
261 * To avoid such catastrophe, vt6420 doesn't provide generic SCR
262 * access operations, but uses SStatus and SControl only during
263 * boot probing in controlled way.
264 *
265 * As the old (pre EH update) probing code is proven to work, we
266 * strictly follow the access pattern.
267 *
268 * LOCKING:
269 * Kernel thread context (may sleep)
270 *
271 * RETURNS:
272 * 0 on success, -errno otherwise.
273 */
274 static int vt6420_prereset(struct ata_link *link, unsigned long deadline)
275 {
276 struct ata_port *ap = link->ap;
277 struct ata_eh_context *ehc = &ap->link.eh_context;
278 unsigned long timeout = jiffies + (HZ * 5);
279 u32 sstatus, scontrol;
280 int online;
281
282 /* don't do any SCR stuff if we're not loading */
283 if (!(ap->pflags & ATA_PFLAG_LOADING))
284 goto skip_scr;
285
286 /* Resume phy. This is the old SATA resume sequence */
287 svia_scr_write(ap, SCR_CONTROL, 0x300);
288 svia_scr_read(ap, SCR_CONTROL, &scontrol); /* flush */
289
290 /* wait for phy to become ready, if necessary */
291 do {
292 msleep(200);
293 svia_scr_read(ap, SCR_STATUS, &sstatus);
294 if ((sstatus & 0xf) != 1)
295 break;
296 } while (time_before(jiffies, timeout));
297
298 /* open code sata_print_link_status() */
299 svia_scr_read(ap, SCR_STATUS, &sstatus);
300 svia_scr_read(ap, SCR_CONTROL, &scontrol);
301
302 online = (sstatus & 0xf) == 0x3;
303
304 ata_port_printk(ap, KERN_INFO,
305 "SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n",
306 online ? "up" : "down", sstatus, scontrol);
307
308 /* SStatus is read one more time */
309 svia_scr_read(ap, SCR_STATUS, &sstatus);
310
311 if (!online) {
312 /* tell EH to bail */
313 ehc->i.action &= ~ATA_EH_RESET;
314 return 0;
315 }
316
317 skip_scr:
318 /* wait for !BSY */
319 ata_wait_ready(ap, deadline);
320
321 return 0;
322 }
323
324 static void vt6420_error_handler(struct ata_port *ap)
325 {
326 ata_bmdma_drive_eh(ap, vt6420_prereset, ata_std_softreset, NULL,
327 ata_std_postreset);
328 }
329
330 static int vt6421_pata_cable_detect(struct ata_port *ap)
331 {
332 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
333 u8 tmp;
334
335 pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp);
336 if (tmp & 0x10)
337 return ATA_CBL_PATA40;
338 return ATA_CBL_PATA80;
339 }
340
341 static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
342 {
343 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
344 static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 };
345 pci_write_config_byte(pdev, PATA_PIO_TIMING, pio_bits[adev->pio_mode - XFER_PIO_0]);
346 }
347
348 static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
349 {
350 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
351 static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 };
352 pci_write_config_byte(pdev, PATA_UDMA_TIMING, udma_bits[adev->dma_mode - XFER_UDMA_0]);
353 }
354
355 static const unsigned int svia_bar_sizes[] = {
356 8, 4, 8, 4, 16, 256
357 };
358
359 static const unsigned int vt6421_bar_sizes[] = {
360 16, 16, 16, 16, 32, 128
361 };
362
363 static void __iomem *svia_scr_addr(void __iomem *addr, unsigned int port)
364 {
365 return addr + (port * 128);
366 }
367
368 static void __iomem *vt6421_scr_addr(void __iomem *addr, unsigned int port)
369 {
370 return addr + (port * 64);
371 }
372
373 static void vt6421_init_addrs(struct ata_port *ap)
374 {
375 void __iomem * const * iomap = ap->host->iomap;
376 void __iomem *reg_addr = iomap[ap->port_no];
377 void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8);
378 struct ata_ioports *ioaddr = &ap->ioaddr;
379
380 ioaddr->cmd_addr = reg_addr;
381 ioaddr->altstatus_addr =
382 ioaddr->ctl_addr = (void __iomem *)
383 ((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS);
384 ioaddr->bmdma_addr = bmdma_addr;
385 ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no);
386
387 ata_std_ports(ioaddr);
388
389 ata_port_pbar_desc(ap, ap->port_no, -1, "port");
390 ata_port_pbar_desc(ap, 4, ap->port_no * 8, "bmdma");
391 }
392
393 static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
394 {
395 const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL };
396 struct ata_host *host;
397 int rc;
398
399 rc = ata_pci_prepare_sff_host(pdev, ppi, &host);
400 if (rc)
401 return rc;
402 *r_host = host;
403
404 rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
405 if (rc) {
406 dev_printk(KERN_ERR, &pdev->dev, "failed to iomap PCI BAR 5\n");
407 return rc;
408 }
409
410 host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0);
411 host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1);
412
413 return 0;
414 }
415
416 static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host)
417 {
418 const struct ata_port_info *ppi[] =
419 { &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info };
420 struct ata_host *host;
421 int i, rc;
422
423 *r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi));
424 if (!host) {
425 dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
426 return -ENOMEM;
427 }
428
429 rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME);
430 if (rc) {
431 dev_printk(KERN_ERR, &pdev->dev, "failed to request/iomap "
432 "PCI BARs (errno=%d)\n", rc);
433 return rc;
434 }
435 host->iomap = pcim_iomap_table(pdev);
436
437 for (i = 0; i < host->n_ports; i++)
438 vt6421_init_addrs(host->ports[i]);
439
440 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
441 if (rc)
442 return rc;
443 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
444 if (rc)
445 return rc;
446
447 return 0;
448 }
449
450 static void svia_configure(struct pci_dev *pdev)
451 {
452 u8 tmp8;
453
454 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8);
455 dev_printk(KERN_INFO, &pdev->dev, "routed to hard irq line %d\n",
456 (int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f);
457
458 /* make sure SATA channels are enabled */
459 pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8);
460 if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
461 dev_printk(KERN_DEBUG, &pdev->dev,
462 "enabling SATA channels (0x%x)\n",
463 (int) tmp8);
464 tmp8 |= ALL_PORTS;
465 pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8);
466 }
467
468 /* make sure interrupts for each channel sent to us */
469 pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8);
470 if ((tmp8 & ALL_PORTS) != ALL_PORTS) {
471 dev_printk(KERN_DEBUG, &pdev->dev,
472 "enabling SATA channel interrupts (0x%x)\n",
473 (int) tmp8);
474 tmp8 |= ALL_PORTS;
475 pci_write_config_byte(pdev, SATA_INT_GATE, tmp8);
476 }
477
478 /* make sure native mode is enabled */
479 pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8);
480 if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) {
481 dev_printk(KERN_DEBUG, &pdev->dev,
482 "enabling SATA channel native mode (0x%x)\n",
483 (int) tmp8);
484 tmp8 |= NATIVE_MODE_ALL;
485 pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8);
486 }
487 }
488
489 static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
490 {
491 static int printed_version;
492 unsigned int i;
493 int rc;
494 struct ata_host *host;
495 int board_id = (int) ent->driver_data;
496 const unsigned *bar_sizes;
497
498 if (!printed_version++)
499 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
500
501 rc = pcim_enable_device(pdev);
502 if (rc)
503 return rc;
504
505 if (board_id == vt6420)
506 bar_sizes = &svia_bar_sizes[0];
507 else
508 bar_sizes = &vt6421_bar_sizes[0];
509
510 for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++)
511 if ((pci_resource_start(pdev, i) == 0) ||
512 (pci_resource_len(pdev, i) < bar_sizes[i])) {
513 dev_printk(KERN_ERR, &pdev->dev,
514 "invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n",
515 i,
516 (unsigned long long)pci_resource_start(pdev, i),
517 (unsigned long long)pci_resource_len(pdev, i));
518 return -ENODEV;
519 }
520
521 if (board_id == vt6420)
522 rc = vt6420_prepare_host(pdev, &host);
523 else
524 rc = vt6421_prepare_host(pdev, &host);
525 if (rc)
526 return rc;
527
528 svia_configure(pdev);
529
530 pci_set_master(pdev);
531 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
532 &svia_sht);
533 }
534
535 static int __init svia_init(void)
536 {
537 return pci_register_driver(&svia_pci_driver);
538 }
539
540 static void __exit svia_exit(void)
541 {
542 pci_unregister_driver(&svia_pci_driver);
543 }
544
545 module_init(svia_init);
546 module_exit(svia_exit);