1 /*******************************************************************
3 * Copyright (c) 2000 ATecoM GmbH
5 * The author may be reached at ecd@atecom.com.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 *******************************************************************/
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/poison.h>
32 #include <linux/skbuff.h>
33 #include <linux/kernel.h>
34 #include <linux/vmalloc.h>
35 #include <linux/netdevice.h>
36 #include <linux/atmdev.h>
37 #include <linux/atm.h>
38 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/interrupt.h>
41 #include <linux/bitops.h>
42 #include <linux/wait.h>
43 #include <linux/jiffies.h>
44 #include <linux/mutex.h>
45 #include <linux/slab.h>
48 #include <linux/uaccess.h>
49 #include <linux/atomic.h>
50 #include <asm/byteorder.h>
52 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
54 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
58 #include "idt77252_tables.h"
60 static unsigned int vpibits
= 1;
63 #define ATM_IDT77252_SEND_IDLE 1
69 #define DEBUG_MODULE 1
70 #undef HAVE_EEPROM /* does not work, yet. */
72 #ifdef CONFIG_ATM_IDT77252_DEBUG
73 static unsigned long debug
= DBG_GENERAL
;
77 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
83 static struct scq_info
*alloc_scq(struct idt77252_dev
*, int);
84 static void free_scq(struct idt77252_dev
*, struct scq_info
*);
85 static int queue_skb(struct idt77252_dev
*, struct vc_map
*,
86 struct sk_buff
*, int oam
);
87 static void drain_scq(struct idt77252_dev
*, struct vc_map
*);
88 static unsigned long get_free_scd(struct idt77252_dev
*, struct vc_map
*);
89 static void fill_scd(struct idt77252_dev
*, struct scq_info
*, int);
94 static int push_rx_skb(struct idt77252_dev
*,
95 struct sk_buff
*, int queue
);
96 static void recycle_rx_skb(struct idt77252_dev
*, struct sk_buff
*);
97 static void flush_rx_pool(struct idt77252_dev
*, struct rx_pool
*);
98 static void recycle_rx_pool_skb(struct idt77252_dev
*,
100 static void add_rx_skb(struct idt77252_dev
*, int queue
,
101 unsigned int size
, unsigned int count
);
106 static int init_rsq(struct idt77252_dev
*);
107 static void deinit_rsq(struct idt77252_dev
*);
108 static void idt77252_rx(struct idt77252_dev
*);
113 static int init_tsq(struct idt77252_dev
*);
114 static void deinit_tsq(struct idt77252_dev
*);
115 static void idt77252_tx(struct idt77252_dev
*);
121 static void idt77252_dev_close(struct atm_dev
*dev
);
122 static int idt77252_open(struct atm_vcc
*vcc
);
123 static void idt77252_close(struct atm_vcc
*vcc
);
124 static int idt77252_send(struct atm_vcc
*vcc
, struct sk_buff
*skb
);
125 static int idt77252_send_oam(struct atm_vcc
*vcc
, void *cell
,
127 static void idt77252_phy_put(struct atm_dev
*dev
, unsigned char value
,
129 static unsigned char idt77252_phy_get(struct atm_dev
*dev
, unsigned long addr
);
130 static int idt77252_change_qos(struct atm_vcc
*vcc
, struct atm_qos
*qos
,
132 static int idt77252_proc_read(struct atm_dev
*dev
, loff_t
* pos
,
134 static void idt77252_softint(struct work_struct
*work
);
137 static const struct atmdev_ops idt77252_ops
=
139 .dev_close
= idt77252_dev_close
,
140 .open
= idt77252_open
,
141 .close
= idt77252_close
,
142 .send
= idt77252_send
,
143 .send_oam
= idt77252_send_oam
,
144 .phy_put
= idt77252_phy_put
,
145 .phy_get
= idt77252_phy_get
,
146 .change_qos
= idt77252_change_qos
,
147 .proc_read
= idt77252_proc_read
,
151 static struct idt77252_dev
*idt77252_chain
= NULL
;
152 static unsigned int idt77252_sram_write_errors
= 0;
154 /*****************************************************************************/
156 /* I/O and Utility Bus */
158 /*****************************************************************************/
161 waitfor_idle(struct idt77252_dev
*card
)
165 stat
= readl(SAR_REG_STAT
);
166 while (stat
& SAR_STAT_CMDBZ
)
167 stat
= readl(SAR_REG_STAT
);
171 read_sram(struct idt77252_dev
*card
, unsigned long addr
)
176 spin_lock_irqsave(&card
->cmd_lock
, flags
);
177 writel(SAR_CMD_READ_SRAM
| (addr
<< 2), SAR_REG_CMD
);
179 value
= readl(SAR_REG_DR0
);
180 spin_unlock_irqrestore(&card
->cmd_lock
, flags
);
185 write_sram(struct idt77252_dev
*card
, unsigned long addr
, u32 value
)
189 if ((idt77252_sram_write_errors
== 0) &&
190 (((addr
> card
->tst
[0] + card
->tst_size
- 2) &&
191 (addr
< card
->tst
[0] + card
->tst_size
)) ||
192 ((addr
> card
->tst
[1] + card
->tst_size
- 2) &&
193 (addr
< card
->tst
[1] + card
->tst_size
)))) {
194 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
195 card
->name
, addr
, value
);
198 spin_lock_irqsave(&card
->cmd_lock
, flags
);
199 writel(value
, SAR_REG_DR0
);
200 writel(SAR_CMD_WRITE_SRAM
| (addr
<< 2), SAR_REG_CMD
);
202 spin_unlock_irqrestore(&card
->cmd_lock
, flags
);
206 read_utility(void *dev
, unsigned long ubus_addr
)
208 struct idt77252_dev
*card
= dev
;
213 printk("Error: No such device.\n");
217 spin_lock_irqsave(&card
->cmd_lock
, flags
);
218 writel(SAR_CMD_READ_UTILITY
+ ubus_addr
, SAR_REG_CMD
);
220 value
= readl(SAR_REG_DR0
);
221 spin_unlock_irqrestore(&card
->cmd_lock
, flags
);
226 write_utility(void *dev
, unsigned long ubus_addr
, u8 value
)
228 struct idt77252_dev
*card
= dev
;
232 printk("Error: No such device.\n");
236 spin_lock_irqsave(&card
->cmd_lock
, flags
);
237 writel((u32
) value
, SAR_REG_DR0
);
238 writel(SAR_CMD_WRITE_UTILITY
+ ubus_addr
, SAR_REG_CMD
);
240 spin_unlock_irqrestore(&card
->cmd_lock
, flags
);
244 static u32 rdsrtab
[] =
246 SAR_GP_EECS
| SAR_GP_EESCLK
,
248 SAR_GP_EESCLK
, /* 0 */
250 SAR_GP_EESCLK
, /* 0 */
252 SAR_GP_EESCLK
, /* 0 */
254 SAR_GP_EESCLK
, /* 0 */
256 SAR_GP_EESCLK
, /* 0 */
258 SAR_GP_EESCLK
| SAR_GP_EEDO
, /* 1 */
260 SAR_GP_EESCLK
, /* 0 */
262 SAR_GP_EESCLK
| SAR_GP_EEDO
/* 1 */
265 static u32 wrentab
[] =
267 SAR_GP_EECS
| SAR_GP_EESCLK
,
269 SAR_GP_EESCLK
, /* 0 */
271 SAR_GP_EESCLK
, /* 0 */
273 SAR_GP_EESCLK
, /* 0 */
275 SAR_GP_EESCLK
, /* 0 */
277 SAR_GP_EESCLK
| SAR_GP_EEDO
, /* 1 */
279 SAR_GP_EESCLK
| SAR_GP_EEDO
, /* 1 */
281 SAR_GP_EESCLK
, /* 0 */
283 SAR_GP_EESCLK
/* 0 */
288 SAR_GP_EECS
| SAR_GP_EESCLK
,
290 SAR_GP_EESCLK
, /* 0 */
292 SAR_GP_EESCLK
, /* 0 */
294 SAR_GP_EESCLK
, /* 0 */
296 SAR_GP_EESCLK
, /* 0 */
298 SAR_GP_EESCLK
, /* 0 */
300 SAR_GP_EESCLK
, /* 0 */
302 SAR_GP_EESCLK
| SAR_GP_EEDO
, /* 1 */
304 SAR_GP_EESCLK
| SAR_GP_EEDO
/* 1 */
309 SAR_GP_EECS
| SAR_GP_EESCLK
,
311 SAR_GP_EESCLK
, /* 0 */
313 SAR_GP_EESCLK
, /* 0 */
315 SAR_GP_EESCLK
, /* 0 */
317 SAR_GP_EESCLK
, /* 0 */
319 SAR_GP_EESCLK
, /* 0 */
321 SAR_GP_EESCLK
, /* 0 */
323 SAR_GP_EESCLK
| SAR_GP_EEDO
, /* 1 */
325 SAR_GP_EESCLK
/* 0 */
328 static u32 clktab
[] =
350 idt77252_read_gp(struct idt77252_dev
*card
)
354 gp
= readl(SAR_REG_GP
);
356 printk("RD: %s\n", gp
& SAR_GP_EEDI
? "1" : "0");
362 idt77252_write_gp(struct idt77252_dev
*card
, u32 value
)
367 printk("WR: %s %s %s\n", value
& SAR_GP_EECS
? " " : "/CS",
368 value
& SAR_GP_EESCLK
? "HIGH" : "LOW ",
369 value
& SAR_GP_EEDO
? "1" : "0");
372 spin_lock_irqsave(&card
->cmd_lock
, flags
);
374 writel(value
, SAR_REG_GP
);
375 spin_unlock_irqrestore(&card
->cmd_lock
, flags
);
379 idt77252_eeprom_read_status(struct idt77252_dev
*card
)
385 gp
= idt77252_read_gp(card
) & ~(SAR_GP_EESCLK
|SAR_GP_EECS
|SAR_GP_EEDO
);
387 for (i
= 0; i
< ARRAY_SIZE(rdsrtab
); i
++) {
388 idt77252_write_gp(card
, gp
| rdsrtab
[i
]);
391 idt77252_write_gp(card
, gp
| SAR_GP_EECS
);
395 for (i
= 0, j
= 0; i
< 8; i
++) {
398 idt77252_write_gp(card
, gp
| clktab
[j
++]);
401 byte
|= idt77252_read_gp(card
) & SAR_GP_EEDI
? 1 : 0;
403 idt77252_write_gp(card
, gp
| clktab
[j
++]);
406 idt77252_write_gp(card
, gp
| SAR_GP_EECS
);
413 idt77252_eeprom_read_byte(struct idt77252_dev
*card
, u8 offset
)
419 gp
= idt77252_read_gp(card
) & ~(SAR_GP_EESCLK
|SAR_GP_EECS
|SAR_GP_EEDO
);
421 for (i
= 0; i
< ARRAY_SIZE(rdtab
); i
++) {
422 idt77252_write_gp(card
, gp
| rdtab
[i
]);
425 idt77252_write_gp(card
, gp
| SAR_GP_EECS
);
428 for (i
= 0, j
= 0; i
< 8; i
++) {
429 idt77252_write_gp(card
, gp
| clktab
[j
++] |
430 (offset
& 1 ? SAR_GP_EEDO
: 0));
433 idt77252_write_gp(card
, gp
| clktab
[j
++] |
434 (offset
& 1 ? SAR_GP_EEDO
: 0));
439 idt77252_write_gp(card
, gp
| SAR_GP_EECS
);
443 for (i
= 0, j
= 0; i
< 8; i
++) {
446 idt77252_write_gp(card
, gp
| clktab
[j
++]);
449 byte
|= idt77252_read_gp(card
) & SAR_GP_EEDI
? 1 : 0;
451 idt77252_write_gp(card
, gp
| clktab
[j
++]);
454 idt77252_write_gp(card
, gp
| SAR_GP_EECS
);
461 idt77252_eeprom_write_byte(struct idt77252_dev
*card
, u8 offset
, u8 data
)
466 gp
= idt77252_read_gp(card
) & ~(SAR_GP_EESCLK
|SAR_GP_EECS
|SAR_GP_EEDO
);
468 for (i
= 0; i
< ARRAY_SIZE(wrentab
); i
++) {
469 idt77252_write_gp(card
, gp
| wrentab
[i
]);
472 idt77252_write_gp(card
, gp
| SAR_GP_EECS
);
475 for (i
= 0; i
< ARRAY_SIZE(wrtab
); i
++) {
476 idt77252_write_gp(card
, gp
| wrtab
[i
]);
479 idt77252_write_gp(card
, gp
| SAR_GP_EECS
);
482 for (i
= 0, j
= 0; i
< 8; i
++) {
483 idt77252_write_gp(card
, gp
| clktab
[j
++] |
484 (offset
& 1 ? SAR_GP_EEDO
: 0));
487 idt77252_write_gp(card
, gp
| clktab
[j
++] |
488 (offset
& 1 ? SAR_GP_EEDO
: 0));
493 idt77252_write_gp(card
, gp
| SAR_GP_EECS
);
496 for (i
= 0, j
= 0; i
< 8; i
++) {
497 idt77252_write_gp(card
, gp
| clktab
[j
++] |
498 (data
& 1 ? SAR_GP_EEDO
: 0));
501 idt77252_write_gp(card
, gp
| clktab
[j
++] |
502 (data
& 1 ? SAR_GP_EEDO
: 0));
507 idt77252_write_gp(card
, gp
| SAR_GP_EECS
);
512 idt77252_eeprom_init(struct idt77252_dev
*card
)
516 gp
= idt77252_read_gp(card
) & ~(SAR_GP_EESCLK
|SAR_GP_EECS
|SAR_GP_EEDO
);
518 idt77252_write_gp(card
, gp
| SAR_GP_EECS
| SAR_GP_EESCLK
);
520 idt77252_write_gp(card
, gp
| SAR_GP_EECS
);
522 idt77252_write_gp(card
, gp
| SAR_GP_EECS
| SAR_GP_EESCLK
);
524 idt77252_write_gp(card
, gp
| SAR_GP_EECS
);
527 #endif /* HAVE_EEPROM */
530 #ifdef CONFIG_ATM_IDT77252_DEBUG
532 dump_tct(struct idt77252_dev
*card
, int index
)
537 tct
= (unsigned long) (card
->tct_base
+ index
* SAR_SRAM_TCT_SIZE
);
539 printk("%s: TCT %x:", card
->name
, index
);
540 for (i
= 0; i
< 8; i
++) {
541 printk(" %08x", read_sram(card
, tct
+ i
));
547 idt77252_tx_dump(struct idt77252_dev
*card
)
553 printk("%s\n", __func__
);
554 for (i
= 0; i
< card
->tct_size
; i
++) {
568 printk("%s: Connection %d:\n", card
->name
, vc
->index
);
569 dump_tct(card
, vc
->index
);
575 /*****************************************************************************/
579 /*****************************************************************************/
582 sb_pool_add(struct idt77252_dev
*card
, struct sk_buff
*skb
, int queue
)
584 struct sb_pool
*pool
= &card
->sbpool
[queue
];
588 while (pool
->skb
[index
]) {
589 index
= (index
+ 1) & FBQ_MASK
;
590 if (index
== pool
->index
)
594 pool
->skb
[index
] = skb
;
595 IDT77252_PRV_POOL(skb
) = POOL_HANDLE(queue
, index
);
597 pool
->index
= (index
+ 1) & FBQ_MASK
;
602 sb_pool_remove(struct idt77252_dev
*card
, struct sk_buff
*skb
)
604 unsigned int queue
, index
;
607 handle
= IDT77252_PRV_POOL(skb
);
609 queue
= POOL_QUEUE(handle
);
613 index
= POOL_INDEX(handle
);
614 if (index
> FBQ_SIZE
- 1)
617 card
->sbpool
[queue
].skb
[index
] = NULL
;
620 static struct sk_buff
*
621 sb_pool_skb(struct idt77252_dev
*card
, u32 handle
)
623 unsigned int queue
, index
;
625 queue
= POOL_QUEUE(handle
);
629 index
= POOL_INDEX(handle
);
630 if (index
> FBQ_SIZE
- 1)
633 return card
->sbpool
[queue
].skb
[index
];
636 static struct scq_info
*
637 alloc_scq(struct idt77252_dev
*card
, int class)
639 struct scq_info
*scq
;
641 scq
= kzalloc(sizeof(struct scq_info
), GFP_KERNEL
);
644 scq
->base
= dma_alloc_coherent(&card
->pcidev
->dev
, SCQ_SIZE
,
645 &scq
->paddr
, GFP_KERNEL
);
646 if (scq
->base
== NULL
) {
651 scq
->next
= scq
->base
;
652 scq
->last
= scq
->base
+ (SCQ_ENTRIES
- 1);
653 atomic_set(&scq
->used
, 0);
655 spin_lock_init(&scq
->lock
);
656 spin_lock_init(&scq
->skblock
);
658 skb_queue_head_init(&scq
->transmit
);
659 skb_queue_head_init(&scq
->pending
);
661 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
662 scq
->base
, scq
->next
, scq
->last
, (unsigned long long)scq
->paddr
);
668 free_scq(struct idt77252_dev
*card
, struct scq_info
*scq
)
673 dma_free_coherent(&card
->pcidev
->dev
, SCQ_SIZE
,
674 scq
->base
, scq
->paddr
);
676 while ((skb
= skb_dequeue(&scq
->transmit
))) {
677 dma_unmap_single(&card
->pcidev
->dev
, IDT77252_PRV_PADDR(skb
),
678 skb
->len
, DMA_TO_DEVICE
);
680 vcc
= ATM_SKB(skb
)->vcc
;
687 while ((skb
= skb_dequeue(&scq
->pending
))) {
688 dma_unmap_single(&card
->pcidev
->dev
, IDT77252_PRV_PADDR(skb
),
689 skb
->len
, DMA_TO_DEVICE
);
691 vcc
= ATM_SKB(skb
)->vcc
;
703 push_on_scq(struct idt77252_dev
*card
, struct vc_map
*vc
, struct sk_buff
*skb
)
705 struct scq_info
*scq
= vc
->scq
;
710 TXPRINTK("%s: SCQ: next 0x%p\n", card
->name
, scq
->next
);
712 atomic_inc(&scq
->used
);
713 entries
= atomic_read(&scq
->used
);
714 if (entries
> (SCQ_ENTRIES
- 1)) {
715 atomic_dec(&scq
->used
);
719 skb_queue_tail(&scq
->transmit
, skb
);
721 spin_lock_irqsave(&vc
->lock
, flags
);
723 struct atm_vcc
*vcc
= vc
->tx_vcc
;
724 struct sock
*sk
= sk_atm(vcc
);
726 vc
->estimator
->cells
+= (skb
->len
+ 47) / 48;
727 if (refcount_read(&sk
->sk_wmem_alloc
) >
728 (sk
->sk_sndbuf
>> 1)) {
729 u32 cps
= vc
->estimator
->maxcps
;
731 vc
->estimator
->cps
= cps
;
732 vc
->estimator
->avcps
= cps
<< 5;
733 if (vc
->lacr
< vc
->init_er
) {
734 vc
->lacr
= vc
->init_er
;
735 writel(TCMDQ_LACR
| (vc
->lacr
<< 16) |
736 vc
->index
, SAR_REG_TCMDQ
);
740 spin_unlock_irqrestore(&vc
->lock
, flags
);
742 tbd
= &IDT77252_PRV_TBD(skb
);
744 spin_lock_irqsave(&scq
->lock
, flags
);
745 scq
->next
->word_1
= cpu_to_le32(tbd
->word_1
|
746 SAR_TBD_TSIF
| SAR_TBD_GTSI
);
747 scq
->next
->word_2
= cpu_to_le32(tbd
->word_2
);
748 scq
->next
->word_3
= cpu_to_le32(tbd
->word_3
);
749 scq
->next
->word_4
= cpu_to_le32(tbd
->word_4
);
751 if (scq
->next
== scq
->last
)
752 scq
->next
= scq
->base
;
756 write_sram(card
, scq
->scd
,
758 (u32
)((unsigned long)scq
->next
- (unsigned long)scq
->base
));
759 spin_unlock_irqrestore(&scq
->lock
, flags
);
761 scq
->trans_start
= jiffies
;
763 if (test_and_clear_bit(VCF_IDLE
, &vc
->flags
)) {
764 writel(TCMDQ_START_LACR
| (vc
->lacr
<< 16) | vc
->index
,
768 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq
->used
));
770 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
771 card
->name
, atomic_read(&scq
->used
),
772 read_sram(card
, scq
->scd
+ 1), scq
->next
);
777 if (time_after(jiffies
, scq
->trans_start
+ HZ
)) {
778 printk("%s: Error pushing TBD for %d.%d\n",
779 card
->name
, vc
->tx_vcc
->vpi
, vc
->tx_vcc
->vci
);
780 #ifdef CONFIG_ATM_IDT77252_DEBUG
781 idt77252_tx_dump(card
);
783 scq
->trans_start
= jiffies
;
791 drain_scq(struct idt77252_dev
*card
, struct vc_map
*vc
)
793 struct scq_info
*scq
= vc
->scq
;
797 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
798 card
->name
, atomic_read(&scq
->used
), scq
->next
);
800 skb
= skb_dequeue(&scq
->transmit
);
802 TXPRINTK("%s: freeing skb at %p.\n", card
->name
, skb
);
804 dma_unmap_single(&card
->pcidev
->dev
, IDT77252_PRV_PADDR(skb
),
805 skb
->len
, DMA_TO_DEVICE
);
807 vcc
= ATM_SKB(skb
)->vcc
;
814 atomic_inc(&vcc
->stats
->tx
);
817 atomic_dec(&scq
->used
);
819 spin_lock(&scq
->skblock
);
820 while ((skb
= skb_dequeue(&scq
->pending
))) {
821 if (push_on_scq(card
, vc
, skb
)) {
822 skb_queue_head(&vc
->scq
->pending
, skb
);
826 spin_unlock(&scq
->skblock
);
830 queue_skb(struct idt77252_dev
*card
, struct vc_map
*vc
,
831 struct sk_buff
*skb
, int oam
)
841 printk("%s: invalid skb->len (%d)\n", card
->name
, skb
->len
);
845 TXPRINTK("%s: Sending %d bytes of data.\n",
846 card
->name
, skb
->len
);
848 tbd
= &IDT77252_PRV_TBD(skb
);
849 vcc
= ATM_SKB(skb
)->vcc
;
850 word4
= (skb
->data
[0] << 24) | (skb
->data
[1] << 16) |
851 (skb
->data
[2] << 8) | (skb
->data
[3] << 0);
853 IDT77252_PRV_PADDR(skb
) = dma_map_single(&card
->pcidev
->dev
, skb
->data
,
854 skb
->len
, DMA_TO_DEVICE
);
862 tbd
->word_1
= SAR_TBD_OAM
| ATM_CELL_PAYLOAD
| SAR_TBD_EPDU
;
863 tbd
->word_2
= IDT77252_PRV_PADDR(skb
) + 4;
864 tbd
->word_3
= 0x00000000;
867 if (test_bit(VCF_RSV
, &vc
->flags
))
873 if (test_bit(VCF_RSV
, &vc
->flags
)) {
874 printk("%s: Trying to transmit on reserved VC\n", card
->name
);
887 tbd
->word_1
= SAR_TBD_EPDU
| SAR_TBD_AAL0
|
890 tbd
->word_1
= SAR_TBD_EPDU
| SAR_TBD_AAL34
|
893 tbd
->word_2
= IDT77252_PRV_PADDR(skb
) + 4;
894 tbd
->word_3
= 0x00000000;
899 tbd
->word_1
= SAR_TBD_EPDU
| SAR_TBD_AAL5
| skb
->len
;
900 tbd
->word_2
= IDT77252_PRV_PADDR(skb
);
901 tbd
->word_3
= skb
->len
;
902 tbd
->word_4
= (vcc
->vpi
<< SAR_TBD_VPI_SHIFT
) |
903 (vcc
->vci
<< SAR_TBD_VCI_SHIFT
);
909 printk("%s: Traffic type not supported.\n", card
->name
);
910 error
= -EPROTONOSUPPORT
;
915 spin_lock_irqsave(&vc
->scq
->skblock
, flags
);
916 skb_queue_tail(&vc
->scq
->pending
, skb
);
918 while ((skb
= skb_dequeue(&vc
->scq
->pending
))) {
919 if (push_on_scq(card
, vc
, skb
)) {
920 skb_queue_head(&vc
->scq
->pending
, skb
);
924 spin_unlock_irqrestore(&vc
->scq
->skblock
, flags
);
929 dma_unmap_single(&card
->pcidev
->dev
, IDT77252_PRV_PADDR(skb
),
930 skb
->len
, DMA_TO_DEVICE
);
935 get_free_scd(struct idt77252_dev
*card
, struct vc_map
*vc
)
939 for (i
= 0; i
< card
->scd_size
; i
++) {
940 if (!card
->scd2vc
[i
]) {
941 card
->scd2vc
[i
] = vc
;
943 return card
->scd_base
+ i
* SAR_SRAM_SCD_SIZE
;
950 fill_scd(struct idt77252_dev
*card
, struct scq_info
*scq
, int class)
952 write_sram(card
, scq
->scd
, scq
->paddr
);
953 write_sram(card
, scq
->scd
+ 1, 0x00000000);
954 write_sram(card
, scq
->scd
+ 2, 0xffffffff);
955 write_sram(card
, scq
->scd
+ 3, 0x00000000);
959 clear_scd(struct idt77252_dev
*card
, struct scq_info
*scq
, int class)
964 /*****************************************************************************/
968 /*****************************************************************************/
971 init_rsq(struct idt77252_dev
*card
)
973 struct rsq_entry
*rsqe
;
975 card
->rsq
.base
= dma_alloc_coherent(&card
->pcidev
->dev
, RSQSIZE
,
976 &card
->rsq
.paddr
, GFP_KERNEL
);
977 if (card
->rsq
.base
== NULL
) {
978 printk("%s: can't allocate RSQ.\n", card
->name
);
982 card
->rsq
.last
= card
->rsq
.base
+ RSQ_NUM_ENTRIES
- 1;
983 card
->rsq
.next
= card
->rsq
.last
;
984 for (rsqe
= card
->rsq
.base
; rsqe
<= card
->rsq
.last
; rsqe
++)
987 writel((unsigned long) card
->rsq
.last
- (unsigned long) card
->rsq
.base
,
989 writel(card
->rsq
.paddr
, SAR_REG_RSQB
);
991 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card
->name
,
992 (unsigned long) card
->rsq
.base
,
993 readl(SAR_REG_RSQB
));
994 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
998 readl(SAR_REG_RSQT
));
1004 deinit_rsq(struct idt77252_dev
*card
)
1006 dma_free_coherent(&card
->pcidev
->dev
, RSQSIZE
,
1007 card
->rsq
.base
, card
->rsq
.paddr
);
1011 dequeue_rx(struct idt77252_dev
*card
, struct rsq_entry
*rsqe
)
1013 struct atm_vcc
*vcc
;
1014 struct sk_buff
*skb
;
1015 struct rx_pool
*rpp
;
1017 u32 header
, vpi
, vci
;
1021 stat
= le32_to_cpu(rsqe
->word_4
);
1023 if (stat
& SAR_RSQE_IDLE
) {
1024 RXPRINTK("%s: message about inactive connection.\n",
1029 skb
= sb_pool_skb(card
, le32_to_cpu(rsqe
->word_2
));
1031 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1032 card
->name
, __func__
,
1033 le32_to_cpu(rsqe
->word_1
), le32_to_cpu(rsqe
->word_2
),
1034 le32_to_cpu(rsqe
->word_3
), le32_to_cpu(rsqe
->word_4
));
1038 header
= le32_to_cpu(rsqe
->word_1
);
1039 vpi
= (header
>> 16) & 0x00ff;
1040 vci
= (header
>> 0) & 0xffff;
1042 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1043 card
->name
, vpi
, vci
, skb
, skb
->data
);
1045 if ((vpi
>= (1 << card
->vpibits
)) || (vci
!= (vci
& card
->vcimask
))) {
1046 printk("%s: SDU received for out-of-range vc %u.%u\n",
1047 card
->name
, vpi
, vci
);
1048 recycle_rx_skb(card
, skb
);
1052 vc
= card
->vcs
[VPCI2VC(card
, vpi
, vci
)];
1053 if (!vc
|| !test_bit(VCF_RX
, &vc
->flags
)) {
1054 printk("%s: SDU received on non RX vc %u.%u\n",
1055 card
->name
, vpi
, vci
);
1056 recycle_rx_skb(card
, skb
);
1062 dma_sync_single_for_cpu(&card
->pcidev
->dev
, IDT77252_PRV_PADDR(skb
),
1063 skb_end_pointer(skb
) - skb
->data
,
1066 if ((vcc
->qos
.aal
== ATM_AAL0
) ||
1067 (vcc
->qos
.aal
== ATM_AAL34
)) {
1069 unsigned char *cell
;
1073 for (i
= (stat
& SAR_RSQE_CELLCNT
); i
; i
--) {
1074 if ((sb
= dev_alloc_skb(64)) == NULL
) {
1075 printk("%s: Can't allocate buffers for aal0.\n",
1077 atomic_add(i
, &vcc
->stats
->rx_drop
);
1080 if (!atm_charge(vcc
, sb
->truesize
)) {
1081 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1083 atomic_add(i
- 1, &vcc
->stats
->rx_drop
);
1087 aal0
= (vpi
<< ATM_HDR_VPI_SHIFT
) |
1088 (vci
<< ATM_HDR_VCI_SHIFT
);
1089 aal0
|= (stat
& SAR_RSQE_EPDU
) ? 0x00000002 : 0;
1090 aal0
|= (stat
& SAR_RSQE_CLP
) ? 0x00000001 : 0;
1092 *((u32
*) sb
->data
) = aal0
;
1093 skb_put(sb
, sizeof(u32
));
1094 skb_put_data(sb
, cell
, ATM_CELL_PAYLOAD
);
1096 ATM_SKB(sb
)->vcc
= vcc
;
1097 __net_timestamp(sb
);
1099 atomic_inc(&vcc
->stats
->rx
);
1101 cell
+= ATM_CELL_PAYLOAD
;
1104 recycle_rx_skb(card
, skb
);
1107 if (vcc
->qos
.aal
!= ATM_AAL5
) {
1108 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1109 card
->name
, vcc
->qos
.aal
);
1110 recycle_rx_skb(card
, skb
);
1113 skb
->len
= (stat
& SAR_RSQE_CELLCNT
) * ATM_CELL_PAYLOAD
;
1115 rpp
= &vc
->rcv
.rx_pool
;
1117 __skb_queue_tail(&rpp
->queue
, skb
);
1118 rpp
->len
+= skb
->len
;
1120 if (stat
& SAR_RSQE_EPDU
) {
1121 unsigned char *l1l2
;
1124 l1l2
= (unsigned char *) ((unsigned long) skb
->data
+ skb
->len
- 6);
1126 len
= (l1l2
[0] << 8) | l1l2
[1];
1127 len
= len
? len
: 0x10000;
1129 RXPRINTK("%s: PDU has %d bytes.\n", card
->name
, len
);
1131 if ((len
+ 8 > rpp
->len
) || (len
+ (47 + 8) < rpp
->len
)) {
1132 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1134 card
->name
, len
, rpp
->len
, readl(SAR_REG_CDC
));
1135 recycle_rx_pool_skb(card
, rpp
);
1136 atomic_inc(&vcc
->stats
->rx_err
);
1139 if (stat
& SAR_RSQE_CRC
) {
1140 RXPRINTK("%s: AAL5 CRC error.\n", card
->name
);
1141 recycle_rx_pool_skb(card
, rpp
);
1142 atomic_inc(&vcc
->stats
->rx_err
);
1145 if (skb_queue_len(&rpp
->queue
) > 1) {
1148 skb
= dev_alloc_skb(rpp
->len
);
1150 RXPRINTK("%s: Can't alloc RX skb.\n",
1152 recycle_rx_pool_skb(card
, rpp
);
1153 atomic_inc(&vcc
->stats
->rx_err
);
1156 if (!atm_charge(vcc
, skb
->truesize
)) {
1157 recycle_rx_pool_skb(card
, rpp
);
1161 skb_queue_walk(&rpp
->queue
, sb
)
1162 skb_put_data(skb
, sb
->data
, sb
->len
);
1164 recycle_rx_pool_skb(card
, rpp
);
1167 ATM_SKB(skb
)->vcc
= vcc
;
1168 __net_timestamp(skb
);
1170 vcc
->push(vcc
, skb
);
1171 atomic_inc(&vcc
->stats
->rx
);
1176 flush_rx_pool(card
, rpp
);
1178 if (!atm_charge(vcc
, skb
->truesize
)) {
1179 recycle_rx_skb(card
, skb
);
1183 dma_unmap_single(&card
->pcidev
->dev
, IDT77252_PRV_PADDR(skb
),
1184 skb_end_pointer(skb
) - skb
->data
,
1186 sb_pool_remove(card
, skb
);
1189 ATM_SKB(skb
)->vcc
= vcc
;
1190 __net_timestamp(skb
);
1192 vcc
->push(vcc
, skb
);
1193 atomic_inc(&vcc
->stats
->rx
);
1195 if (skb
->truesize
> SAR_FB_SIZE_3
)
1196 add_rx_skb(card
, 3, SAR_FB_SIZE_3
, 1);
1197 else if (skb
->truesize
> SAR_FB_SIZE_2
)
1198 add_rx_skb(card
, 2, SAR_FB_SIZE_2
, 1);
1199 else if (skb
->truesize
> SAR_FB_SIZE_1
)
1200 add_rx_skb(card
, 1, SAR_FB_SIZE_1
, 1);
1202 add_rx_skb(card
, 0, SAR_FB_SIZE_0
, 1);
1208 idt77252_rx(struct idt77252_dev
*card
)
1210 struct rsq_entry
*rsqe
;
1212 if (card
->rsq
.next
== card
->rsq
.last
)
1213 rsqe
= card
->rsq
.base
;
1215 rsqe
= card
->rsq
.next
+ 1;
1217 if (!(le32_to_cpu(rsqe
->word_4
) & SAR_RSQE_VALID
)) {
1218 RXPRINTK("%s: no entry in RSQ.\n", card
->name
);
1223 dequeue_rx(card
, rsqe
);
1225 card
->rsq
.next
= rsqe
;
1226 if (card
->rsq
.next
== card
->rsq
.last
)
1227 rsqe
= card
->rsq
.base
;
1229 rsqe
= card
->rsq
.next
+ 1;
1230 } while (le32_to_cpu(rsqe
->word_4
) & SAR_RSQE_VALID
);
1232 writel((unsigned long) card
->rsq
.next
- (unsigned long) card
->rsq
.base
,
1237 idt77252_rx_raw(struct idt77252_dev
*card
)
1239 struct sk_buff
*queue
;
1241 struct atm_vcc
*vcc
;
1245 if (card
->raw_cell_head
== NULL
) {
1246 u32 handle
= le32_to_cpu(*(card
->raw_cell_hnd
+ 1));
1247 card
->raw_cell_head
= sb_pool_skb(card
, handle
);
1250 queue
= card
->raw_cell_head
;
1254 head
= IDT77252_PRV_PADDR(queue
) + (queue
->data
- queue
->head
- 16);
1255 tail
= readl(SAR_REG_RAWCT
);
1257 dma_sync_single_for_cpu(&card
->pcidev
->dev
, IDT77252_PRV_PADDR(queue
),
1258 skb_end_offset(queue
) - 16,
1261 while (head
!= tail
) {
1262 unsigned int vpi
, vci
;
1265 header
= le32_to_cpu(*(u32
*) &queue
->data
[0]);
1267 vpi
= (header
& ATM_HDR_VPI_MASK
) >> ATM_HDR_VPI_SHIFT
;
1268 vci
= (header
& ATM_HDR_VCI_MASK
) >> ATM_HDR_VCI_SHIFT
;
1270 #ifdef CONFIG_ATM_IDT77252_DEBUG
1271 if (debug
& DBG_RAW_CELL
) {
1274 printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1275 card
->name
, (header
>> 28) & 0x000f,
1276 (header
>> 20) & 0x00ff,
1277 (header
>> 4) & 0xffff,
1278 (header
>> 1) & 0x0007,
1279 (header
>> 0) & 0x0001);
1280 for (i
= 16; i
< 64; i
++)
1281 printk(" %02x", queue
->data
[i
]);
1286 if (vpi
>= (1<<card
->vpibits
) || vci
>= (1<<card
->vcibits
)) {
1287 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1288 card
->name
, vpi
, vci
);
1292 vc
= card
->vcs
[VPCI2VC(card
, vpi
, vci
)];
1293 if (!vc
|| !test_bit(VCF_RX
, &vc
->flags
)) {
1294 RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1295 card
->name
, vpi
, vci
);
1301 if (vcc
->qos
.aal
!= ATM_AAL0
) {
1302 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1303 card
->name
, vpi
, vci
);
1304 atomic_inc(&vcc
->stats
->rx_drop
);
1308 if ((sb
= dev_alloc_skb(64)) == NULL
) {
1309 printk("%s: Can't allocate buffers for AAL0.\n",
1311 atomic_inc(&vcc
->stats
->rx_err
);
1315 if (!atm_charge(vcc
, sb
->truesize
)) {
1316 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1322 *((u32
*) sb
->data
) = header
;
1323 skb_put(sb
, sizeof(u32
));
1324 skb_put_data(sb
, &(queue
->data
[16]), ATM_CELL_PAYLOAD
);
1326 ATM_SKB(sb
)->vcc
= vcc
;
1327 __net_timestamp(sb
);
1329 atomic_inc(&vcc
->stats
->rx
);
1332 skb_pull(queue
, 64);
1334 head
= IDT77252_PRV_PADDR(queue
)
1335 + (queue
->data
- queue
->head
- 16);
1337 if (queue
->len
< 128) {
1338 struct sk_buff
*next
;
1341 head
= le32_to_cpu(*(u32
*) &queue
->data
[0]);
1342 handle
= le32_to_cpu(*(u32
*) &queue
->data
[4]);
1344 next
= sb_pool_skb(card
, handle
);
1345 recycle_rx_skb(card
, queue
);
1348 card
->raw_cell_head
= next
;
1349 queue
= card
->raw_cell_head
;
1350 dma_sync_single_for_cpu(&card
->pcidev
->dev
,
1351 IDT77252_PRV_PADDR(queue
),
1352 (skb_end_pointer(queue
) -
1356 card
->raw_cell_head
= NULL
;
1357 printk("%s: raw cell queue overrun\n",
1366 /*****************************************************************************/
1370 /*****************************************************************************/
1373 init_tsq(struct idt77252_dev
*card
)
1375 struct tsq_entry
*tsqe
;
1377 card
->tsq
.base
= dma_alloc_coherent(&card
->pcidev
->dev
, RSQSIZE
,
1378 &card
->tsq
.paddr
, GFP_KERNEL
);
1379 if (card
->tsq
.base
== NULL
) {
1380 printk("%s: can't allocate TSQ.\n", card
->name
);
1384 card
->tsq
.last
= card
->tsq
.base
+ TSQ_NUM_ENTRIES
- 1;
1385 card
->tsq
.next
= card
->tsq
.last
;
1386 for (tsqe
= card
->tsq
.base
; tsqe
<= card
->tsq
.last
; tsqe
++)
1387 tsqe
->word_2
= cpu_to_le32(SAR_TSQE_INVALID
);
1389 writel(card
->tsq
.paddr
, SAR_REG_TSQB
);
1390 writel((unsigned long) card
->tsq
.next
- (unsigned long) card
->tsq
.base
,
1397 deinit_tsq(struct idt77252_dev
*card
)
1399 dma_free_coherent(&card
->pcidev
->dev
, TSQSIZE
,
1400 card
->tsq
.base
, card
->tsq
.paddr
);
1404 idt77252_tx(struct idt77252_dev
*card
)
1406 struct tsq_entry
*tsqe
;
1407 unsigned int vpi
, vci
;
1411 if (card
->tsq
.next
== card
->tsq
.last
)
1412 tsqe
= card
->tsq
.base
;
1414 tsqe
= card
->tsq
.next
+ 1;
1416 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe
,
1417 card
->tsq
.base
, card
->tsq
.next
, card
->tsq
.last
);
1418 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1419 readl(SAR_REG_TSQB
),
1420 readl(SAR_REG_TSQT
),
1421 readl(SAR_REG_TSQH
));
1423 stat
= le32_to_cpu(tsqe
->word_2
);
1425 if (stat
& SAR_TSQE_INVALID
)
1429 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe
,
1430 le32_to_cpu(tsqe
->word_1
),
1431 le32_to_cpu(tsqe
->word_2
));
1433 switch (stat
& SAR_TSQE_TYPE
) {
1434 case SAR_TSQE_TYPE_TIMER
:
1435 TXPRINTK("%s: Timer RollOver detected.\n", card
->name
);
1438 case SAR_TSQE_TYPE_IDLE
:
1440 conn
= le32_to_cpu(tsqe
->word_1
);
1442 if (SAR_TSQE_TAG(stat
) == 0x10) {
1444 printk("%s: Connection %d halted.\n",
1446 le32_to_cpu(tsqe
->word_1
) & 0x1fff);
1451 vc
= card
->vcs
[conn
& 0x1fff];
1453 printk("%s: could not find VC from conn %d\n",
1454 card
->name
, conn
& 0x1fff);
1458 printk("%s: Connection %d IDLE.\n",
1459 card
->name
, vc
->index
);
1461 set_bit(VCF_IDLE
, &vc
->flags
);
1464 case SAR_TSQE_TYPE_TSR
:
1466 conn
= le32_to_cpu(tsqe
->word_1
);
1468 vc
= card
->vcs
[conn
& 0x1fff];
1470 printk("%s: no VC at index %d\n",
1472 le32_to_cpu(tsqe
->word_1
) & 0x1fff);
1476 drain_scq(card
, vc
);
1479 case SAR_TSQE_TYPE_TBD_COMP
:
1481 conn
= le32_to_cpu(tsqe
->word_1
);
1483 vpi
= (conn
>> SAR_TBD_VPI_SHIFT
) & 0x00ff;
1484 vci
= (conn
>> SAR_TBD_VCI_SHIFT
) & 0xffff;
1486 if (vpi
>= (1 << card
->vpibits
) ||
1487 vci
>= (1 << card
->vcibits
)) {
1488 printk("%s: TBD complete: "
1489 "out of range VPI.VCI %u.%u\n",
1490 card
->name
, vpi
, vci
);
1494 vc
= card
->vcs
[VPCI2VC(card
, vpi
, vci
)];
1496 printk("%s: TBD complete: "
1497 "no VC at VPI.VCI %u.%u\n",
1498 card
->name
, vpi
, vci
);
1502 drain_scq(card
, vc
);
1506 tsqe
->word_2
= cpu_to_le32(SAR_TSQE_INVALID
);
1508 card
->tsq
.next
= tsqe
;
1509 if (card
->tsq
.next
== card
->tsq
.last
)
1510 tsqe
= card
->tsq
.base
;
1512 tsqe
= card
->tsq
.next
+ 1;
1514 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe
,
1515 card
->tsq
.base
, card
->tsq
.next
, card
->tsq
.last
);
1517 stat
= le32_to_cpu(tsqe
->word_2
);
1519 } while (!(stat
& SAR_TSQE_INVALID
));
1521 writel((unsigned long)card
->tsq
.next
- (unsigned long)card
->tsq
.base
,
1524 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1525 card
->index
, readl(SAR_REG_TSQH
),
1526 readl(SAR_REG_TSQT
), card
->tsq
.next
);
1531 tst_timer(struct timer_list
*t
)
1533 struct idt77252_dev
*card
= from_timer(card
, t
, tst_timer
);
1534 unsigned long base
, idle
, jump
;
1535 unsigned long flags
;
1539 spin_lock_irqsave(&card
->tst_lock
, flags
);
1541 base
= card
->tst
[card
->tst_index
];
1542 idle
= card
->tst
[card
->tst_index
^ 1];
1544 if (test_bit(TST_SWITCH_WAIT
, &card
->tst_state
)) {
1545 jump
= base
+ card
->tst_size
- 2;
1547 pc
= readl(SAR_REG_NOW
) >> 2;
1548 if ((pc
^ idle
) & ~(card
->tst_size
- 1)) {
1549 mod_timer(&card
->tst_timer
, jiffies
+ 1);
1553 clear_bit(TST_SWITCH_WAIT
, &card
->tst_state
);
1555 card
->tst_index
^= 1;
1556 write_sram(card
, jump
, TSTE_OPC_JMP
| (base
<< 2));
1558 base
= card
->tst
[card
->tst_index
];
1559 idle
= card
->tst
[card
->tst_index
^ 1];
1561 for (e
= 0; e
< card
->tst_size
- 2; e
++) {
1562 if (card
->soft_tst
[e
].tste
& TSTE_PUSH_IDLE
) {
1563 write_sram(card
, idle
+ e
,
1564 card
->soft_tst
[e
].tste
& TSTE_MASK
);
1565 card
->soft_tst
[e
].tste
&= ~(TSTE_PUSH_IDLE
);
1570 if (test_and_clear_bit(TST_SWITCH_PENDING
, &card
->tst_state
)) {
1572 for (e
= 0; e
< card
->tst_size
- 2; e
++) {
1573 if (card
->soft_tst
[e
].tste
& TSTE_PUSH_ACTIVE
) {
1574 write_sram(card
, idle
+ e
,
1575 card
->soft_tst
[e
].tste
& TSTE_MASK
);
1576 card
->soft_tst
[e
].tste
&= ~(TSTE_PUSH_ACTIVE
);
1577 card
->soft_tst
[e
].tste
|= TSTE_PUSH_IDLE
;
1581 jump
= base
+ card
->tst_size
- 2;
1583 write_sram(card
, jump
, TSTE_OPC_NULL
);
1584 set_bit(TST_SWITCH_WAIT
, &card
->tst_state
);
1586 mod_timer(&card
->tst_timer
, jiffies
+ 1);
1590 spin_unlock_irqrestore(&card
->tst_lock
, flags
);
1594 __fill_tst(struct idt77252_dev
*card
, struct vc_map
*vc
,
1595 int n
, unsigned int opc
)
1597 unsigned long cl
, avail
;
1602 avail
= card
->tst_size
- 2;
1603 for (e
= 0; e
< avail
; e
++) {
1604 if (card
->soft_tst
[e
].vc
== NULL
)
1608 printk("%s: No free TST entries found\n", card
->name
);
1612 NPRINTK("%s: conn %d: first TST entry at %d.\n",
1613 card
->name
, vc
? vc
->index
: -1, e
);
1617 data
= opc
& TSTE_OPC_MASK
;
1618 if (vc
&& (opc
!= TSTE_OPC_NULL
))
1619 data
= opc
| vc
->index
;
1621 idle
= card
->tst
[card
->tst_index
^ 1];
1627 if ((cl
>= avail
) && (card
->soft_tst
[e
].vc
== NULL
)) {
1629 card
->soft_tst
[e
].vc
= vc
;
1631 card
->soft_tst
[e
].vc
= (void *)-1;
1633 card
->soft_tst
[e
].tste
= data
;
1634 if (timer_pending(&card
->tst_timer
))
1635 card
->soft_tst
[e
].tste
|= TSTE_PUSH_ACTIVE
;
1637 write_sram(card
, idle
+ e
, data
);
1638 card
->soft_tst
[e
].tste
|= TSTE_PUSH_IDLE
;
1641 cl
-= card
->tst_size
;
1654 fill_tst(struct idt77252_dev
*card
, struct vc_map
*vc
, int n
, unsigned int opc
)
1656 unsigned long flags
;
1659 spin_lock_irqsave(&card
->tst_lock
, flags
);
1661 res
= __fill_tst(card
, vc
, n
, opc
);
1663 set_bit(TST_SWITCH_PENDING
, &card
->tst_state
);
1664 if (!timer_pending(&card
->tst_timer
))
1665 mod_timer(&card
->tst_timer
, jiffies
+ 1);
1667 spin_unlock_irqrestore(&card
->tst_lock
, flags
);
1672 __clear_tst(struct idt77252_dev
*card
, struct vc_map
*vc
)
1677 idle
= card
->tst
[card
->tst_index
^ 1];
1679 for (e
= 0; e
< card
->tst_size
- 2; e
++) {
1680 if (card
->soft_tst
[e
].vc
== vc
) {
1681 card
->soft_tst
[e
].vc
= NULL
;
1683 card
->soft_tst
[e
].tste
= TSTE_OPC_VAR
;
1684 if (timer_pending(&card
->tst_timer
))
1685 card
->soft_tst
[e
].tste
|= TSTE_PUSH_ACTIVE
;
1687 write_sram(card
, idle
+ e
, TSTE_OPC_VAR
);
1688 card
->soft_tst
[e
].tste
|= TSTE_PUSH_IDLE
;
1697 clear_tst(struct idt77252_dev
*card
, struct vc_map
*vc
)
1699 unsigned long flags
;
1702 spin_lock_irqsave(&card
->tst_lock
, flags
);
1704 res
= __clear_tst(card
, vc
);
1706 set_bit(TST_SWITCH_PENDING
, &card
->tst_state
);
1707 if (!timer_pending(&card
->tst_timer
))
1708 mod_timer(&card
->tst_timer
, jiffies
+ 1);
1710 spin_unlock_irqrestore(&card
->tst_lock
, flags
);
1715 change_tst(struct idt77252_dev
*card
, struct vc_map
*vc
,
1716 int n
, unsigned int opc
)
1718 unsigned long flags
;
1721 spin_lock_irqsave(&card
->tst_lock
, flags
);
1723 __clear_tst(card
, vc
);
1724 res
= __fill_tst(card
, vc
, n
, opc
);
1726 set_bit(TST_SWITCH_PENDING
, &card
->tst_state
);
1727 if (!timer_pending(&card
->tst_timer
))
1728 mod_timer(&card
->tst_timer
, jiffies
+ 1);
1730 spin_unlock_irqrestore(&card
->tst_lock
, flags
);
1736 set_tct(struct idt77252_dev
*card
, struct vc_map
*vc
)
1740 tct
= (unsigned long) (card
->tct_base
+ vc
->index
* SAR_SRAM_TCT_SIZE
);
1742 switch (vc
->class) {
1744 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1745 card
->name
, tct
, vc
->scq
->scd
);
1747 write_sram(card
, tct
+ 0, TCT_CBR
| vc
->scq
->scd
);
1748 write_sram(card
, tct
+ 1, 0);
1749 write_sram(card
, tct
+ 2, 0);
1750 write_sram(card
, tct
+ 3, 0);
1751 write_sram(card
, tct
+ 4, 0);
1752 write_sram(card
, tct
+ 5, 0);
1753 write_sram(card
, tct
+ 6, 0);
1754 write_sram(card
, tct
+ 7, 0);
1758 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1759 card
->name
, tct
, vc
->scq
->scd
);
1761 write_sram(card
, tct
+ 0, TCT_UBR
| vc
->scq
->scd
);
1762 write_sram(card
, tct
+ 1, 0);
1763 write_sram(card
, tct
+ 2, TCT_TSIF
);
1764 write_sram(card
, tct
+ 3, TCT_HALT
| TCT_IDLE
);
1765 write_sram(card
, tct
+ 4, 0);
1766 write_sram(card
, tct
+ 5, vc
->init_er
);
1767 write_sram(card
, tct
+ 6, 0);
1768 write_sram(card
, tct
+ 7, TCT_FLAG_UBR
);
1780 /*****************************************************************************/
1784 /*****************************************************************************/
1786 static __inline__
int
1787 idt77252_fbq_full(struct idt77252_dev
*card
, int queue
)
1789 return (readl(SAR_REG_STAT
) >> (16 + (queue
<< 2))) == 0x0f;
1793 push_rx_skb(struct idt77252_dev
*card
, struct sk_buff
*skb
, int queue
)
1795 unsigned long flags
;
1799 skb
->data
= skb
->head
;
1800 skb_reset_tail_pointer(skb
);
1803 skb_reserve(skb
, 16);
1807 skb_put(skb
, SAR_FB_SIZE_0
);
1810 skb_put(skb
, SAR_FB_SIZE_1
);
1813 skb_put(skb
, SAR_FB_SIZE_2
);
1816 skb_put(skb
, SAR_FB_SIZE_3
);
1822 if (idt77252_fbq_full(card
, queue
))
1825 memset(&skb
->data
[(skb
->len
& ~(0x3f)) - 64], 0, 2 * sizeof(u32
));
1827 handle
= IDT77252_PRV_POOL(skb
);
1828 addr
= IDT77252_PRV_PADDR(skb
);
1830 spin_lock_irqsave(&card
->cmd_lock
, flags
);
1831 writel(handle
, card
->fbq
[queue
]);
1832 writel(addr
, card
->fbq
[queue
]);
1833 spin_unlock_irqrestore(&card
->cmd_lock
, flags
);
1839 add_rx_skb(struct idt77252_dev
*card
, int queue
,
1840 unsigned int size
, unsigned int count
)
1842 struct sk_buff
*skb
;
1847 skb
= dev_alloc_skb(size
);
1851 if (sb_pool_add(card
, skb
, queue
)) {
1852 printk("%s: SB POOL full\n", __func__
);
1856 paddr
= dma_map_single(&card
->pcidev
->dev
, skb
->data
,
1857 skb_end_pointer(skb
) - skb
->data
,
1859 IDT77252_PRV_PADDR(skb
) = paddr
;
1861 if (push_rx_skb(card
, skb
, queue
)) {
1862 printk("%s: FB QUEUE full\n", __func__
);
1870 dma_unmap_single(&card
->pcidev
->dev
, IDT77252_PRV_PADDR(skb
),
1871 skb_end_pointer(skb
) - skb
->data
, DMA_FROM_DEVICE
);
1873 handle
= IDT77252_PRV_POOL(skb
);
1874 card
->sbpool
[POOL_QUEUE(handle
)].skb
[POOL_INDEX(handle
)] = NULL
;
1882 recycle_rx_skb(struct idt77252_dev
*card
, struct sk_buff
*skb
)
1884 u32 handle
= IDT77252_PRV_POOL(skb
);
1887 dma_sync_single_for_device(&card
->pcidev
->dev
, IDT77252_PRV_PADDR(skb
),
1888 skb_end_pointer(skb
) - skb
->data
,
1891 err
= push_rx_skb(card
, skb
, POOL_QUEUE(handle
));
1893 dma_unmap_single(&card
->pcidev
->dev
, IDT77252_PRV_PADDR(skb
),
1894 skb_end_pointer(skb
) - skb
->data
,
1896 sb_pool_remove(card
, skb
);
1902 flush_rx_pool(struct idt77252_dev
*card
, struct rx_pool
*rpp
)
1904 skb_queue_head_init(&rpp
->queue
);
1909 recycle_rx_pool_skb(struct idt77252_dev
*card
, struct rx_pool
*rpp
)
1911 struct sk_buff
*skb
, *tmp
;
1913 skb_queue_walk_safe(&rpp
->queue
, skb
, tmp
)
1914 recycle_rx_skb(card
, skb
);
1916 flush_rx_pool(card
, rpp
);
1919 /*****************************************************************************/
1923 /*****************************************************************************/
1926 idt77252_phy_put(struct atm_dev
*dev
, unsigned char value
, unsigned long addr
)
1928 write_utility(dev
->dev_data
, 0x100 + (addr
& 0x1ff), value
);
1931 static unsigned char
1932 idt77252_phy_get(struct atm_dev
*dev
, unsigned long addr
)
1934 return read_utility(dev
->dev_data
, 0x100 + (addr
& 0x1ff));
1938 idt77252_send_skb(struct atm_vcc
*vcc
, struct sk_buff
*skb
, int oam
)
1940 struct atm_dev
*dev
= vcc
->dev
;
1941 struct idt77252_dev
*card
= dev
->dev_data
;
1942 struct vc_map
*vc
= vcc
->dev_data
;
1946 printk("%s: NULL connection in send().\n", card
->name
);
1947 atomic_inc(&vcc
->stats
->tx_err
);
1951 if (!test_bit(VCF_TX
, &vc
->flags
)) {
1952 printk("%s: Trying to transmit on a non-tx VC.\n", card
->name
);
1953 atomic_inc(&vcc
->stats
->tx_err
);
1958 switch (vcc
->qos
.aal
) {
1964 printk("%s: Unsupported AAL: %d\n", card
->name
, vcc
->qos
.aal
);
1965 atomic_inc(&vcc
->stats
->tx_err
);
1970 if (skb_shinfo(skb
)->nr_frags
!= 0) {
1971 printk("%s: No scatter-gather yet.\n", card
->name
);
1972 atomic_inc(&vcc
->stats
->tx_err
);
1976 ATM_SKB(skb
)->vcc
= vcc
;
1978 err
= queue_skb(card
, vc
, skb
, oam
);
1980 atomic_inc(&vcc
->stats
->tx_err
);
1988 static int idt77252_send(struct atm_vcc
*vcc
, struct sk_buff
*skb
)
1990 return idt77252_send_skb(vcc
, skb
, 0);
1994 idt77252_send_oam(struct atm_vcc
*vcc
, void *cell
, int flags
)
1996 struct atm_dev
*dev
= vcc
->dev
;
1997 struct idt77252_dev
*card
= dev
->dev_data
;
1998 struct sk_buff
*skb
;
2000 skb
= dev_alloc_skb(64);
2002 printk("%s: Out of memory in send_oam().\n", card
->name
);
2003 atomic_inc(&vcc
->stats
->tx_err
);
2006 refcount_add(skb
->truesize
, &sk_atm(vcc
)->sk_wmem_alloc
);
2008 skb_put_data(skb
, cell
, 52);
2010 return idt77252_send_skb(vcc
, skb
, 1);
2013 static __inline__
unsigned int
2014 idt77252_fls(unsigned int x
)
2020 if (x
& 0xffff0000) {
2042 idt77252_int_to_atmfp(unsigned int rate
)
2048 e
= idt77252_fls(rate
) - 1;
2050 m
= (rate
- (1 << e
)) << (9 - e
);
2052 m
= (rate
- (1 << e
));
2054 m
= (rate
- (1 << e
)) >> (e
- 9);
2055 return 0x4000 | (e
<< 9) | m
;
2059 idt77252_rate_logindex(struct idt77252_dev
*card
, int pcr
)
2063 afp
= idt77252_int_to_atmfp(pcr
< 0 ? -pcr
: pcr
);
2065 return rate_to_log
[(afp
>> 5) & 0x1ff];
2066 return rate_to_log
[((afp
>> 5) + 1) & 0x1ff];
2070 idt77252_est_timer(struct timer_list
*t
)
2072 struct rate_estimator
*est
= from_timer(est
, t
, timer
);
2073 struct vc_map
*vc
= est
->vc
;
2074 struct idt77252_dev
*card
= vc
->card
;
2075 unsigned long flags
;
2080 spin_lock_irqsave(&vc
->lock
, flags
);
2083 ncells
= est
->cells
;
2085 rate
= ((u32
)(ncells
- est
->last_cells
)) << (7 - est
->interval
);
2086 est
->last_cells
= ncells
;
2087 est
->avcps
+= ((long)rate
- (long)est
->avcps
) >> est
->ewma_log
;
2088 est
->cps
= (est
->avcps
+ 0x1f) >> 5;
2091 if (cps
< (est
->maxcps
>> 4))
2092 cps
= est
->maxcps
>> 4;
2094 lacr
= idt77252_rate_logindex(card
, cps
);
2095 if (lacr
> vc
->max_er
)
2098 if (lacr
!= vc
->lacr
) {
2100 writel(TCMDQ_LACR
|(vc
->lacr
<< 16)|vc
->index
, SAR_REG_TCMDQ
);
2103 est
->timer
.expires
= jiffies
+ ((HZ
/ 4) << est
->interval
);
2104 add_timer(&est
->timer
);
2107 spin_unlock_irqrestore(&vc
->lock
, flags
);
2110 static struct rate_estimator
*
2111 idt77252_init_est(struct vc_map
*vc
, int pcr
)
2113 struct rate_estimator
*est
;
2115 est
= kzalloc(sizeof(struct rate_estimator
), GFP_KERNEL
);
2118 est
->maxcps
= pcr
< 0 ? -pcr
: pcr
;
2119 est
->cps
= est
->maxcps
;
2120 est
->avcps
= est
->cps
<< 5;
2123 est
->interval
= 2; /* XXX: make this configurable */
2124 est
->ewma_log
= 2; /* XXX: make this configurable */
2125 timer_setup(&est
->timer
, idt77252_est_timer
, 0);
2126 mod_timer(&est
->timer
, jiffies
+ ((HZ
/ 4) << est
->interval
));
2132 idt77252_init_cbr(struct idt77252_dev
*card
, struct vc_map
*vc
,
2133 struct atm_vcc
*vcc
, struct atm_qos
*qos
)
2135 int tst_free
, tst_used
, tst_entries
;
2136 unsigned long tmpl
, modl
;
2139 if ((qos
->txtp
.max_pcr
== 0) &&
2140 (qos
->txtp
.pcr
== 0) && (qos
->txtp
.min_pcr
== 0)) {
2141 printk("%s: trying to open a CBR VC with cell rate = 0\n",
2147 tst_free
= card
->tst_free
;
2148 if (test_bit(VCF_TX
, &vc
->flags
))
2149 tst_used
= vc
->ntste
;
2150 tst_free
+= tst_used
;
2152 tcr
= atm_pcr_goal(&qos
->txtp
);
2153 tcra
= tcr
>= 0 ? tcr
: -tcr
;
2155 TXPRINTK("%s: CBR target cell rate = %d\n", card
->name
, tcra
);
2157 tmpl
= (unsigned long) tcra
* ((unsigned long) card
->tst_size
- 2);
2158 modl
= tmpl
% (unsigned long)card
->utopia_pcr
;
2160 tst_entries
= (int) (tmpl
/ card
->utopia_pcr
);
2164 } else if (tcr
== 0) {
2165 tst_entries
= tst_free
- SAR_TST_RESERVED
;
2166 if (tst_entries
<= 0) {
2167 printk("%s: no CBR bandwidth free.\n", card
->name
);
2172 if (tst_entries
== 0) {
2173 printk("%s: selected CBR bandwidth < granularity.\n",
2178 if (tst_entries
> (tst_free
- SAR_TST_RESERVED
)) {
2179 printk("%s: not enough CBR bandwidth free.\n", card
->name
);
2183 vc
->ntste
= tst_entries
;
2185 card
->tst_free
= tst_free
- tst_entries
;
2186 if (test_bit(VCF_TX
, &vc
->flags
)) {
2187 if (tst_used
== tst_entries
)
2190 OPRINTK("%s: modify %d -> %d entries in TST.\n",
2191 card
->name
, tst_used
, tst_entries
);
2192 change_tst(card
, vc
, tst_entries
, TSTE_OPC_CBR
);
2196 OPRINTK("%s: setting %d entries in TST.\n", card
->name
, tst_entries
);
2197 fill_tst(card
, vc
, tst_entries
, TSTE_OPC_CBR
);
2202 idt77252_init_ubr(struct idt77252_dev
*card
, struct vc_map
*vc
,
2203 struct atm_vcc
*vcc
, struct atm_qos
*qos
)
2205 struct rate_estimator
*est
= NULL
;
2206 unsigned long flags
;
2209 spin_lock_irqsave(&vc
->lock
, flags
);
2210 if (vc
->estimator
) {
2211 est
= vc
->estimator
;
2212 vc
->estimator
= NULL
;
2214 spin_unlock_irqrestore(&vc
->lock
, flags
);
2216 del_timer_sync(&est
->timer
);
2220 tcr
= atm_pcr_goal(&qos
->txtp
);
2222 tcr
= card
->link_pcr
;
2224 vc
->estimator
= idt77252_init_est(vc
, tcr
);
2226 vc
->class = SCHED_UBR
;
2227 vc
->init_er
= idt77252_rate_logindex(card
, tcr
);
2228 vc
->lacr
= vc
->init_er
;
2230 vc
->max_er
= vc
->init_er
;
2238 idt77252_init_tx(struct idt77252_dev
*card
, struct vc_map
*vc
,
2239 struct atm_vcc
*vcc
, struct atm_qos
*qos
)
2243 if (test_bit(VCF_TX
, &vc
->flags
))
2246 switch (qos
->txtp
.traffic_class
) {
2248 vc
->class = SCHED_CBR
;
2252 vc
->class = SCHED_UBR
;
2258 return -EPROTONOSUPPORT
;
2261 vc
->scq
= alloc_scq(card
, vc
->class);
2263 printk("%s: can't get SCQ.\n", card
->name
);
2267 vc
->scq
->scd
= get_free_scd(card
, vc
);
2268 if (vc
->scq
->scd
== 0) {
2269 printk("%s: no SCD available.\n", card
->name
);
2270 free_scq(card
, vc
->scq
);
2274 fill_scd(card
, vc
->scq
, vc
->class);
2276 if (set_tct(card
, vc
)) {
2277 printk("%s: class %d not supported.\n",
2278 card
->name
, qos
->txtp
.traffic_class
);
2280 card
->scd2vc
[vc
->scd_index
] = NULL
;
2281 free_scq(card
, vc
->scq
);
2282 return -EPROTONOSUPPORT
;
2285 switch (vc
->class) {
2287 error
= idt77252_init_cbr(card
, vc
, vcc
, qos
);
2289 card
->scd2vc
[vc
->scd_index
] = NULL
;
2290 free_scq(card
, vc
->scq
);
2294 clear_bit(VCF_IDLE
, &vc
->flags
);
2295 writel(TCMDQ_START
| vc
->index
, SAR_REG_TCMDQ
);
2299 error
= idt77252_init_ubr(card
, vc
, vcc
, qos
);
2301 card
->scd2vc
[vc
->scd_index
] = NULL
;
2302 free_scq(card
, vc
->scq
);
2306 set_bit(VCF_IDLE
, &vc
->flags
);
2311 set_bit(VCF_TX
, &vc
->flags
);
2316 idt77252_init_rx(struct idt77252_dev
*card
, struct vc_map
*vc
,
2317 struct atm_vcc
*vcc
, struct atm_qos
*qos
)
2319 unsigned long flags
;
2323 if (test_bit(VCF_RX
, &vc
->flags
))
2327 set_bit(VCF_RX
, &vc
->flags
);
2329 if ((vcc
->vci
== 3) || (vcc
->vci
== 4))
2332 flush_rx_pool(card
, &vc
->rcv
.rx_pool
);
2334 rcte
|= SAR_RCTE_CONNECTOPEN
;
2335 rcte
|= SAR_RCTE_RAWCELLINTEN
;
2339 rcte
|= SAR_RCTE_RCQ
;
2342 rcte
|= SAR_RCTE_OAM
; /* Let SAR drop Video */
2345 rcte
|= SAR_RCTE_AAL34
;
2348 rcte
|= SAR_RCTE_AAL5
;
2351 rcte
|= SAR_RCTE_RCQ
;
2355 if (qos
->aal
!= ATM_AAL5
)
2356 rcte
|= SAR_RCTE_FBP_1
;
2357 else if (qos
->rxtp
.max_sdu
> SAR_FB_SIZE_2
)
2358 rcte
|= SAR_RCTE_FBP_3
;
2359 else if (qos
->rxtp
.max_sdu
> SAR_FB_SIZE_1
)
2360 rcte
|= SAR_RCTE_FBP_2
;
2361 else if (qos
->rxtp
.max_sdu
> SAR_FB_SIZE_0
)
2362 rcte
|= SAR_RCTE_FBP_1
;
2364 rcte
|= SAR_RCTE_FBP_01
;
2366 addr
= card
->rct_base
+ (vc
->index
<< 2);
2368 OPRINTK("%s: writing RCT at 0x%lx\n", card
->name
, addr
);
2369 write_sram(card
, addr
, rcte
);
2371 spin_lock_irqsave(&card
->cmd_lock
, flags
);
2372 writel(SAR_CMD_OPEN_CONNECTION
| (addr
<< 2), SAR_REG_CMD
);
2374 spin_unlock_irqrestore(&card
->cmd_lock
, flags
);
2380 idt77252_open(struct atm_vcc
*vcc
)
2382 struct atm_dev
*dev
= vcc
->dev
;
2383 struct idt77252_dev
*card
= dev
->dev_data
;
2389 short vpi
= vcc
->vpi
;
2391 if (vpi
== ATM_VPI_UNSPEC
|| vci
== ATM_VCI_UNSPEC
)
2394 if (vpi
>= (1 << card
->vpibits
)) {
2395 printk("%s: unsupported VPI: %d\n", card
->name
, vpi
);
2399 if (vci
>= (1 << card
->vcibits
)) {
2400 printk("%s: unsupported VCI: %d\n", card
->name
, vci
);
2404 set_bit(ATM_VF_ADDR
, &vcc
->flags
);
2406 mutex_lock(&card
->mutex
);
2408 OPRINTK("%s: opening vpi.vci: %d.%d\n", card
->name
, vpi
, vci
);
2410 switch (vcc
->qos
.aal
) {
2416 printk("%s: Unsupported AAL: %d\n", card
->name
, vcc
->qos
.aal
);
2417 mutex_unlock(&card
->mutex
);
2418 return -EPROTONOSUPPORT
;
2421 index
= VPCI2VC(card
, vpi
, vci
);
2422 if (!card
->vcs
[index
]) {
2423 card
->vcs
[index
] = kzalloc(sizeof(struct vc_map
), GFP_KERNEL
);
2424 if (!card
->vcs
[index
]) {
2425 printk("%s: can't alloc vc in open()\n", card
->name
);
2426 mutex_unlock(&card
->mutex
);
2429 card
->vcs
[index
]->card
= card
;
2430 card
->vcs
[index
]->index
= index
;
2432 spin_lock_init(&card
->vcs
[index
]->lock
);
2434 vc
= card
->vcs
[index
];
2438 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2439 card
->name
, vc
->index
, vcc
->vpi
, vcc
->vci
,
2440 vcc
->qos
.rxtp
.traffic_class
!= ATM_NONE
? "rx" : "--",
2441 vcc
->qos
.txtp
.traffic_class
!= ATM_NONE
? "tx" : "--",
2442 vcc
->qos
.rxtp
.max_sdu
);
2445 if (vcc
->qos
.txtp
.traffic_class
!= ATM_NONE
&&
2446 test_bit(VCF_TX
, &vc
->flags
))
2448 if (vcc
->qos
.rxtp
.traffic_class
!= ATM_NONE
&&
2449 test_bit(VCF_RX
, &vc
->flags
))
2453 printk("%s: %s vci already in use.\n", card
->name
,
2454 inuse
== 1 ? "tx" : inuse
== 2 ? "rx" : "tx and rx");
2455 mutex_unlock(&card
->mutex
);
2459 if (vcc
->qos
.txtp
.traffic_class
!= ATM_NONE
) {
2460 error
= idt77252_init_tx(card
, vc
, vcc
, &vcc
->qos
);
2462 mutex_unlock(&card
->mutex
);
2467 if (vcc
->qos
.rxtp
.traffic_class
!= ATM_NONE
) {
2468 error
= idt77252_init_rx(card
, vc
, vcc
, &vcc
->qos
);
2470 mutex_unlock(&card
->mutex
);
2475 set_bit(ATM_VF_READY
, &vcc
->flags
);
2477 mutex_unlock(&card
->mutex
);
2482 idt77252_close(struct atm_vcc
*vcc
)
2484 struct atm_dev
*dev
= vcc
->dev
;
2485 struct idt77252_dev
*card
= dev
->dev_data
;
2486 struct vc_map
*vc
= vcc
->dev_data
;
2487 unsigned long flags
;
2489 unsigned long timeout
;
2491 mutex_lock(&card
->mutex
);
2493 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2494 card
->name
, vc
->index
, vcc
->vpi
, vcc
->vci
);
2496 clear_bit(ATM_VF_READY
, &vcc
->flags
);
2498 if (vcc
->qos
.rxtp
.traffic_class
!= ATM_NONE
) {
2500 spin_lock_irqsave(&vc
->lock
, flags
);
2501 clear_bit(VCF_RX
, &vc
->flags
);
2503 spin_unlock_irqrestore(&vc
->lock
, flags
);
2505 if ((vcc
->vci
== 3) || (vcc
->vci
== 4))
2508 addr
= card
->rct_base
+ vc
->index
* SAR_SRAM_RCT_SIZE
;
2510 spin_lock_irqsave(&card
->cmd_lock
, flags
);
2511 writel(SAR_CMD_CLOSE_CONNECTION
| (addr
<< 2), SAR_REG_CMD
);
2513 spin_unlock_irqrestore(&card
->cmd_lock
, flags
);
2515 if (skb_queue_len(&vc
->rcv
.rx_pool
.queue
) != 0) {
2516 DPRINTK("%s: closing a VC with pending rx buffers.\n",
2519 recycle_rx_pool_skb(card
, &vc
->rcv
.rx_pool
);
2524 if (vcc
->qos
.txtp
.traffic_class
!= ATM_NONE
) {
2526 spin_lock_irqsave(&vc
->lock
, flags
);
2527 clear_bit(VCF_TX
, &vc
->flags
);
2528 clear_bit(VCF_IDLE
, &vc
->flags
);
2529 clear_bit(VCF_RSV
, &vc
->flags
);
2532 if (vc
->estimator
) {
2533 del_timer(&vc
->estimator
->timer
);
2534 kfree(vc
->estimator
);
2535 vc
->estimator
= NULL
;
2537 spin_unlock_irqrestore(&vc
->lock
, flags
);
2540 while (atomic_read(&vc
->scq
->used
) > 0) {
2541 timeout
= msleep_interruptible(timeout
);
2543 pr_warn("%s: SCQ drain timeout: %u used\n",
2544 card
->name
, atomic_read(&vc
->scq
->used
));
2549 writel(TCMDQ_HALT
| vc
->index
, SAR_REG_TCMDQ
);
2550 clear_scd(card
, vc
->scq
, vc
->class);
2552 if (vc
->class == SCHED_CBR
) {
2553 clear_tst(card
, vc
);
2554 card
->tst_free
+= vc
->ntste
;
2558 card
->scd2vc
[vc
->scd_index
] = NULL
;
2559 free_scq(card
, vc
->scq
);
2562 mutex_unlock(&card
->mutex
);
2566 idt77252_change_qos(struct atm_vcc
*vcc
, struct atm_qos
*qos
, int flags
)
2568 struct atm_dev
*dev
= vcc
->dev
;
2569 struct idt77252_dev
*card
= dev
->dev_data
;
2570 struct vc_map
*vc
= vcc
->dev_data
;
2573 mutex_lock(&card
->mutex
);
2575 if (qos
->txtp
.traffic_class
!= ATM_NONE
) {
2576 if (!test_bit(VCF_TX
, &vc
->flags
)) {
2577 error
= idt77252_init_tx(card
, vc
, vcc
, qos
);
2581 switch (qos
->txtp
.traffic_class
) {
2583 error
= idt77252_init_cbr(card
, vc
, vcc
, qos
);
2589 error
= idt77252_init_ubr(card
, vc
, vcc
, qos
);
2593 if (!test_bit(VCF_IDLE
, &vc
->flags
)) {
2594 writel(TCMDQ_LACR
| (vc
->lacr
<< 16) |
2595 vc
->index
, SAR_REG_TCMDQ
);
2601 error
= -EOPNOTSUPP
;
2607 if ((qos
->rxtp
.traffic_class
!= ATM_NONE
) &&
2608 !test_bit(VCF_RX
, &vc
->flags
)) {
2609 error
= idt77252_init_rx(card
, vc
, vcc
, qos
);
2614 memcpy(&vcc
->qos
, qos
, sizeof(struct atm_qos
));
2616 set_bit(ATM_VF_HASQOS
, &vcc
->flags
);
2619 mutex_unlock(&card
->mutex
);
2624 idt77252_proc_read(struct atm_dev
*dev
, loff_t
* pos
, char *page
)
2626 struct idt77252_dev
*card
= dev
->dev_data
;
2631 return sprintf(page
, "IDT77252 Interrupts:\n");
2633 return sprintf(page
, "TSIF: %lu\n", card
->irqstat
[15]);
2635 return sprintf(page
, "TXICP: %lu\n", card
->irqstat
[14]);
2637 return sprintf(page
, "TSQF: %lu\n", card
->irqstat
[12]);
2639 return sprintf(page
, "TMROF: %lu\n", card
->irqstat
[11]);
2641 return sprintf(page
, "PHYI: %lu\n", card
->irqstat
[10]);
2643 return sprintf(page
, "FBQ3A: %lu\n", card
->irqstat
[8]);
2645 return sprintf(page
, "FBQ2A: %lu\n", card
->irqstat
[7]);
2647 return sprintf(page
, "RSQF: %lu\n", card
->irqstat
[6]);
2649 return sprintf(page
, "EPDU: %lu\n", card
->irqstat
[5]);
2651 return sprintf(page
, "RAWCF: %lu\n", card
->irqstat
[4]);
2653 return sprintf(page
, "FBQ1A: %lu\n", card
->irqstat
[3]);
2655 return sprintf(page
, "FBQ0A: %lu\n", card
->irqstat
[2]);
2657 return sprintf(page
, "RSQAF: %lu\n", card
->irqstat
[1]);
2659 return sprintf(page
, "IDT77252 Transmit Connection Table:\n");
2661 for (i
= 0; i
< card
->tct_size
; i
++) {
2663 struct atm_vcc
*vcc
;
2680 p
+= sprintf(p
, " %4u: %u.%u: ", i
, vcc
->vpi
, vcc
->vci
);
2681 tct
= (unsigned long) (card
->tct_base
+ i
* SAR_SRAM_TCT_SIZE
);
2683 for (i
= 0; i
< 8; i
++)
2684 p
+= sprintf(p
, " %08x", read_sram(card
, tct
+ i
));
2685 p
+= sprintf(p
, "\n");
2691 /*****************************************************************************/
2693 /* Interrupt handler */
2695 /*****************************************************************************/
2698 idt77252_collect_stat(struct idt77252_dev
*card
)
2700 (void) readl(SAR_REG_CDC
);
2701 (void) readl(SAR_REG_VPEC
);
2702 (void) readl(SAR_REG_ICC
);
2707 idt77252_interrupt(int irq
, void *dev_id
)
2709 struct idt77252_dev
*card
= dev_id
;
2712 stat
= readl(SAR_REG_STAT
) & 0xffff;
2713 if (!stat
) /* no interrupt for us */
2716 if (test_and_set_bit(IDT77252_BIT_INTERRUPT
, &card
->flags
)) {
2717 printk("%s: Re-entering irq_handler()\n", card
->name
);
2721 writel(stat
, SAR_REG_STAT
); /* reset interrupt */
2723 if (stat
& SAR_STAT_TSIF
) { /* entry written to TSQ */
2724 INTPRINTK("%s: TSIF\n", card
->name
);
2725 card
->irqstat
[15]++;
2728 if (stat
& SAR_STAT_TXICP
) { /* Incomplete CS-PDU has */
2729 INTPRINTK("%s: TXICP\n", card
->name
);
2730 card
->irqstat
[14]++;
2731 #ifdef CONFIG_ATM_IDT77252_DEBUG
2732 idt77252_tx_dump(card
);
2735 if (stat
& SAR_STAT_TSQF
) { /* TSQ 7/8 full */
2736 INTPRINTK("%s: TSQF\n", card
->name
);
2737 card
->irqstat
[12]++;
2740 if (stat
& SAR_STAT_TMROF
) { /* Timer overflow */
2741 INTPRINTK("%s: TMROF\n", card
->name
);
2742 card
->irqstat
[11]++;
2743 idt77252_collect_stat(card
);
2746 if (stat
& SAR_STAT_EPDU
) { /* Got complete CS-PDU */
2747 INTPRINTK("%s: EPDU\n", card
->name
);
2751 if (stat
& SAR_STAT_RSQAF
) { /* RSQ is 7/8 full */
2752 INTPRINTK("%s: RSQAF\n", card
->name
);
2756 if (stat
& SAR_STAT_RSQF
) { /* RSQ is full */
2757 INTPRINTK("%s: RSQF\n", card
->name
);
2761 if (stat
& SAR_STAT_RAWCF
) { /* Raw cell received */
2762 INTPRINTK("%s: RAWCF\n", card
->name
);
2764 idt77252_rx_raw(card
);
2767 if (stat
& SAR_STAT_PHYI
) { /* PHY device interrupt */
2768 INTPRINTK("%s: PHYI", card
->name
);
2769 card
->irqstat
[10]++;
2770 if (card
->atmdev
->phy
&& card
->atmdev
->phy
->interrupt
)
2771 card
->atmdev
->phy
->interrupt(card
->atmdev
);
2774 if (stat
& (SAR_STAT_FBQ0A
| SAR_STAT_FBQ1A
|
2775 SAR_STAT_FBQ2A
| SAR_STAT_FBQ3A
)) {
2777 writel(readl(SAR_REG_CFG
) & ~(SAR_CFG_FBIE
), SAR_REG_CFG
);
2779 INTPRINTK("%s: FBQA: %04x\n", card
->name
, stat
);
2781 if (stat
& SAR_STAT_FBQ0A
)
2783 if (stat
& SAR_STAT_FBQ1A
)
2785 if (stat
& SAR_STAT_FBQ2A
)
2787 if (stat
& SAR_STAT_FBQ3A
)
2790 schedule_work(&card
->tqueue
);
2794 clear_bit(IDT77252_BIT_INTERRUPT
, &card
->flags
);
2799 idt77252_softint(struct work_struct
*work
)
2801 struct idt77252_dev
*card
=
2802 container_of(work
, struct idt77252_dev
, tqueue
);
2806 for (done
= 1; ; done
= 1) {
2807 stat
= readl(SAR_REG_STAT
) >> 16;
2809 if ((stat
& 0x0f) < SAR_FBQ0_HIGH
) {
2810 add_rx_skb(card
, 0, SAR_FB_SIZE_0
, 32);
2815 if ((stat
& 0x0f) < SAR_FBQ1_HIGH
) {
2816 add_rx_skb(card
, 1, SAR_FB_SIZE_1
, 32);
2821 if ((stat
& 0x0f) < SAR_FBQ2_HIGH
) {
2822 add_rx_skb(card
, 2, SAR_FB_SIZE_2
, 32);
2827 if ((stat
& 0x0f) < SAR_FBQ3_HIGH
) {
2828 add_rx_skb(card
, 3, SAR_FB_SIZE_3
, 32);
2836 writel(readl(SAR_REG_CFG
) | SAR_CFG_FBIE
, SAR_REG_CFG
);
2841 open_card_oam(struct idt77252_dev
*card
)
2843 unsigned long flags
;
2850 for (vpi
= 0; vpi
< (1 << card
->vpibits
); vpi
++) {
2851 for (vci
= 3; vci
< 5; vci
++) {
2852 index
= VPCI2VC(card
, vpi
, vci
);
2854 vc
= kzalloc(sizeof(struct vc_map
), GFP_KERNEL
);
2856 printk("%s: can't alloc vc\n", card
->name
);
2860 card
->vcs
[index
] = vc
;
2862 flush_rx_pool(card
, &vc
->rcv
.rx_pool
);
2864 rcte
= SAR_RCTE_CONNECTOPEN
|
2865 SAR_RCTE_RAWCELLINTEN
|
2869 addr
= card
->rct_base
+ (vc
->index
<< 2);
2870 write_sram(card
, addr
, rcte
);
2872 spin_lock_irqsave(&card
->cmd_lock
, flags
);
2873 writel(SAR_CMD_OPEN_CONNECTION
| (addr
<< 2),
2876 spin_unlock_irqrestore(&card
->cmd_lock
, flags
);
2884 close_card_oam(struct idt77252_dev
*card
)
2886 unsigned long flags
;
2892 for (vpi
= 0; vpi
< (1 << card
->vpibits
); vpi
++) {
2893 for (vci
= 3; vci
< 5; vci
++) {
2894 index
= VPCI2VC(card
, vpi
, vci
);
2895 vc
= card
->vcs
[index
];
2897 addr
= card
->rct_base
+ vc
->index
* SAR_SRAM_RCT_SIZE
;
2899 spin_lock_irqsave(&card
->cmd_lock
, flags
);
2900 writel(SAR_CMD_CLOSE_CONNECTION
| (addr
<< 2),
2903 spin_unlock_irqrestore(&card
->cmd_lock
, flags
);
2905 if (skb_queue_len(&vc
->rcv
.rx_pool
.queue
) != 0) {
2906 DPRINTK("%s: closing a VC "
2907 "with pending rx buffers.\n",
2910 recycle_rx_pool_skb(card
, &vc
->rcv
.rx_pool
);
2917 open_card_ubr0(struct idt77252_dev
*card
)
2921 vc
= kzalloc(sizeof(struct vc_map
), GFP_KERNEL
);
2923 printk("%s: can't alloc vc\n", card
->name
);
2927 vc
->class = SCHED_UBR0
;
2929 vc
->scq
= alloc_scq(card
, vc
->class);
2931 printk("%s: can't get SCQ.\n", card
->name
);
2935 card
->scd2vc
[0] = vc
;
2937 vc
->scq
->scd
= card
->scd_base
;
2939 fill_scd(card
, vc
->scq
, vc
->class);
2941 write_sram(card
, card
->tct_base
+ 0, TCT_UBR
| card
->scd_base
);
2942 write_sram(card
, card
->tct_base
+ 1, 0);
2943 write_sram(card
, card
->tct_base
+ 2, 0);
2944 write_sram(card
, card
->tct_base
+ 3, 0);
2945 write_sram(card
, card
->tct_base
+ 4, 0);
2946 write_sram(card
, card
->tct_base
+ 5, 0);
2947 write_sram(card
, card
->tct_base
+ 6, 0);
2948 write_sram(card
, card
->tct_base
+ 7, TCT_FLAG_UBR
);
2950 clear_bit(VCF_IDLE
, &vc
->flags
);
2951 writel(TCMDQ_START
| 0, SAR_REG_TCMDQ
);
2956 idt77252_dev_open(struct idt77252_dev
*card
)
2960 if (!test_bit(IDT77252_BIT_INIT
, &card
->flags
)) {
2961 printk("%s: SAR not yet initialized.\n", card
->name
);
2965 conf
= SAR_CFG_RXPTH
| /* enable receive path */
2966 SAR_RX_DELAY
| /* interrupt on complete PDU */
2967 SAR_CFG_RAWIE
| /* interrupt enable on raw cells */
2968 SAR_CFG_RQFIE
| /* interrupt on RSQ almost full */
2969 SAR_CFG_TMOIE
| /* interrupt on timer overflow */
2970 SAR_CFG_FBIE
| /* interrupt on low free buffers */
2971 SAR_CFG_TXEN
| /* transmit operation enable */
2972 SAR_CFG_TXINT
| /* interrupt on transmit status */
2973 SAR_CFG_TXUIE
| /* interrupt on transmit underrun */
2974 SAR_CFG_TXSFI
| /* interrupt on TSQ almost full */
2975 SAR_CFG_PHYIE
/* enable PHY interrupts */
2978 #ifdef CONFIG_ATM_IDT77252_RCV_ALL
2979 /* Test RAW cell receive. */
2980 conf
|= SAR_CFG_VPECA
;
2983 writel(readl(SAR_REG_CFG
) | conf
, SAR_REG_CFG
);
2985 if (open_card_oam(card
)) {
2986 printk("%s: Error initializing OAM.\n", card
->name
);
2990 if (open_card_ubr0(card
)) {
2991 printk("%s: Error initializing UBR0.\n", card
->name
);
2995 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card
->name
);
2999 static void idt77252_dev_close(struct atm_dev
*dev
)
3001 struct idt77252_dev
*card
= dev
->dev_data
;
3004 close_card_oam(card
);
3006 conf
= SAR_CFG_RXPTH
| /* enable receive path */
3007 SAR_RX_DELAY
| /* interrupt on complete PDU */
3008 SAR_CFG_RAWIE
| /* interrupt enable on raw cells */
3009 SAR_CFG_RQFIE
| /* interrupt on RSQ almost full */
3010 SAR_CFG_TMOIE
| /* interrupt on timer overflow */
3011 SAR_CFG_FBIE
| /* interrupt on low free buffers */
3012 SAR_CFG_TXEN
| /* transmit operation enable */
3013 SAR_CFG_TXINT
| /* interrupt on transmit status */
3014 SAR_CFG_TXUIE
| /* interrupt on xmit underrun */
3015 SAR_CFG_TXSFI
/* interrupt on TSQ almost full */
3018 writel(readl(SAR_REG_CFG
) & ~(conf
), SAR_REG_CFG
);
3020 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card
->name
);
3024 /*****************************************************************************/
3026 /* Initialisation and Deinitialization of IDT77252 */
3028 /*****************************************************************************/
3032 deinit_card(struct idt77252_dev
*card
)
3034 struct sk_buff
*skb
;
3037 if (!test_bit(IDT77252_BIT_INIT
, &card
->flags
)) {
3038 printk("%s: SAR not yet initialized.\n", card
->name
);
3041 DIPRINTK("idt77252: deinitialize card %u\n", card
->index
);
3043 writel(0, SAR_REG_CFG
);
3046 atm_dev_deregister(card
->atmdev
);
3048 for (i
= 0; i
< 4; i
++) {
3049 for (j
= 0; j
< FBQ_SIZE
; j
++) {
3050 skb
= card
->sbpool
[i
].skb
[j
];
3052 dma_unmap_single(&card
->pcidev
->dev
,
3053 IDT77252_PRV_PADDR(skb
),
3054 (skb_end_pointer(skb
) -
3057 card
->sbpool
[i
].skb
[j
] = NULL
;
3063 vfree(card
->soft_tst
);
3065 vfree(card
->scd2vc
);
3069 if (card
->raw_cell_hnd
) {
3070 dma_free_coherent(&card
->pcidev
->dev
, 2 * sizeof(u32
),
3071 card
->raw_cell_hnd
, card
->raw_cell_paddr
);
3074 if (card
->rsq
.base
) {
3075 DIPRINTK("%s: Release RSQ ...\n", card
->name
);
3079 if (card
->tsq
.base
) {
3080 DIPRINTK("%s: Release TSQ ...\n", card
->name
);
3084 DIPRINTK("idt77252: Release IRQ.\n");
3085 free_irq(card
->pcidev
->irq
, card
);
3087 for (i
= 0; i
< 4; i
++) {
3089 iounmap(card
->fbq
[i
]);
3093 iounmap(card
->membase
);
3095 clear_bit(IDT77252_BIT_INIT
, &card
->flags
);
3096 DIPRINTK("%s: Card deinitialized.\n", card
->name
);
3100 static void init_sram(struct idt77252_dev
*card
)
3104 for (i
= 0; i
< card
->sramsize
; i
+= 4)
3105 write_sram(card
, (i
>> 2), 0);
3107 /* set SRAM layout for THIS card */
3108 if (card
->sramsize
== (512 * 1024)) {
3109 card
->tct_base
= SAR_SRAM_TCT_128_BASE
;
3110 card
->tct_size
= (SAR_SRAM_TCT_128_TOP
- card
->tct_base
+ 1)
3111 / SAR_SRAM_TCT_SIZE
;
3112 card
->rct_base
= SAR_SRAM_RCT_128_BASE
;
3113 card
->rct_size
= (SAR_SRAM_RCT_128_TOP
- card
->rct_base
+ 1)
3114 / SAR_SRAM_RCT_SIZE
;
3115 card
->rt_base
= SAR_SRAM_RT_128_BASE
;
3116 card
->scd_base
= SAR_SRAM_SCD_128_BASE
;
3117 card
->scd_size
= (SAR_SRAM_SCD_128_TOP
- card
->scd_base
+ 1)
3118 / SAR_SRAM_SCD_SIZE
;
3119 card
->tst
[0] = SAR_SRAM_TST1_128_BASE
;
3120 card
->tst
[1] = SAR_SRAM_TST2_128_BASE
;
3121 card
->tst_size
= SAR_SRAM_TST1_128_TOP
- card
->tst
[0] + 1;
3122 card
->abrst_base
= SAR_SRAM_ABRSTD_128_BASE
;
3123 card
->abrst_size
= SAR_ABRSTD_SIZE_8K
;
3124 card
->fifo_base
= SAR_SRAM_FIFO_128_BASE
;
3125 card
->fifo_size
= SAR_RXFD_SIZE_32K
;
3127 card
->tct_base
= SAR_SRAM_TCT_32_BASE
;
3128 card
->tct_size
= (SAR_SRAM_TCT_32_TOP
- card
->tct_base
+ 1)
3129 / SAR_SRAM_TCT_SIZE
;
3130 card
->rct_base
= SAR_SRAM_RCT_32_BASE
;
3131 card
->rct_size
= (SAR_SRAM_RCT_32_TOP
- card
->rct_base
+ 1)
3132 / SAR_SRAM_RCT_SIZE
;
3133 card
->rt_base
= SAR_SRAM_RT_32_BASE
;
3134 card
->scd_base
= SAR_SRAM_SCD_32_BASE
;
3135 card
->scd_size
= (SAR_SRAM_SCD_32_TOP
- card
->scd_base
+ 1)
3136 / SAR_SRAM_SCD_SIZE
;
3137 card
->tst
[0] = SAR_SRAM_TST1_32_BASE
;
3138 card
->tst
[1] = SAR_SRAM_TST2_32_BASE
;
3139 card
->tst_size
= (SAR_SRAM_TST1_32_TOP
- card
->tst
[0] + 1);
3140 card
->abrst_base
= SAR_SRAM_ABRSTD_32_BASE
;
3141 card
->abrst_size
= SAR_ABRSTD_SIZE_1K
;
3142 card
->fifo_base
= SAR_SRAM_FIFO_32_BASE
;
3143 card
->fifo_size
= SAR_RXFD_SIZE_4K
;
3146 /* Initialize TCT */
3147 for (i
= 0; i
< card
->tct_size
; i
++) {
3148 write_sram(card
, i
* SAR_SRAM_TCT_SIZE
+ 0, 0);
3149 write_sram(card
, i
* SAR_SRAM_TCT_SIZE
+ 1, 0);
3150 write_sram(card
, i
* SAR_SRAM_TCT_SIZE
+ 2, 0);
3151 write_sram(card
, i
* SAR_SRAM_TCT_SIZE
+ 3, 0);
3152 write_sram(card
, i
* SAR_SRAM_TCT_SIZE
+ 4, 0);
3153 write_sram(card
, i
* SAR_SRAM_TCT_SIZE
+ 5, 0);
3154 write_sram(card
, i
* SAR_SRAM_TCT_SIZE
+ 6, 0);
3155 write_sram(card
, i
* SAR_SRAM_TCT_SIZE
+ 7, 0);
3158 /* Initialize RCT */
3159 for (i
= 0; i
< card
->rct_size
; i
++) {
3160 write_sram(card
, card
->rct_base
+ i
* SAR_SRAM_RCT_SIZE
,
3161 (u32
) SAR_RCTE_RAWCELLINTEN
);
3162 write_sram(card
, card
->rct_base
+ i
* SAR_SRAM_RCT_SIZE
+ 1,
3164 write_sram(card
, card
->rct_base
+ i
* SAR_SRAM_RCT_SIZE
+ 2,
3166 write_sram(card
, card
->rct_base
+ i
* SAR_SRAM_RCT_SIZE
+ 3,
3170 writel((SAR_FBQ0_LOW
<< 28) | (SAR_FB_SIZE_0
/ 48), SAR_REG_FBQS0
);
3171 writel((SAR_FBQ1_LOW
<< 28) | (SAR_FB_SIZE_1
/ 48), SAR_REG_FBQS1
);
3172 writel((SAR_FBQ2_LOW
<< 28) | (SAR_FB_SIZE_2
/ 48), SAR_REG_FBQS2
);
3173 writel((SAR_FBQ3_LOW
<< 28) | (SAR_FB_SIZE_3
/ 48), SAR_REG_FBQS3
);
3175 /* Initialize rate table */
3176 for (i
= 0; i
< 256; i
++) {
3177 write_sram(card
, card
->rt_base
+ i
, log_to_rate
[i
]);
3180 for (i
= 0; i
< 128; i
++) {
3183 tmp
= rate_to_log
[(i
<< 2) + 0] << 0;
3184 tmp
|= rate_to_log
[(i
<< 2) + 1] << 8;
3185 tmp
|= rate_to_log
[(i
<< 2) + 2] << 16;
3186 tmp
|= rate_to_log
[(i
<< 2) + 3] << 24;
3187 write_sram(card
, card
->rt_base
+ 256 + i
, tmp
);
3190 #if 0 /* Fill RDF and AIR tables. */
3191 for (i
= 0; i
< 128; i
++) {
3194 tmp
= RDF
[0][(i
<< 1) + 0] << 16;
3195 tmp
|= RDF
[0][(i
<< 1) + 1] << 0;
3196 write_sram(card
, card
->rt_base
+ 512 + i
, tmp
);
3199 for (i
= 0; i
< 128; i
++) {
3202 tmp
= AIR
[0][(i
<< 1) + 0] << 16;
3203 tmp
|= AIR
[0][(i
<< 1) + 1] << 0;
3204 write_sram(card
, card
->rt_base
+ 640 + i
, tmp
);
3208 IPRINTK("%s: initialize rate table ...\n", card
->name
);
3209 writel(card
->rt_base
<< 2, SAR_REG_RTBL
);
3211 /* Initialize TSTs */
3212 IPRINTK("%s: initialize TST ...\n", card
->name
);
3213 card
->tst_free
= card
->tst_size
- 2; /* last two are jumps */
3215 for (i
= card
->tst
[0]; i
< card
->tst
[0] + card
->tst_size
- 2; i
++)
3216 write_sram(card
, i
, TSTE_OPC_VAR
);
3217 write_sram(card
, i
++, TSTE_OPC_JMP
| (card
->tst
[0] << 2));
3218 idt77252_sram_write_errors
= 1;
3219 write_sram(card
, i
++, TSTE_OPC_JMP
| (card
->tst
[1] << 2));
3220 idt77252_sram_write_errors
= 0;
3221 for (i
= card
->tst
[1]; i
< card
->tst
[1] + card
->tst_size
- 2; i
++)
3222 write_sram(card
, i
, TSTE_OPC_VAR
);
3223 write_sram(card
, i
++, TSTE_OPC_JMP
| (card
->tst
[1] << 2));
3224 idt77252_sram_write_errors
= 1;
3225 write_sram(card
, i
++, TSTE_OPC_JMP
| (card
->tst
[0] << 2));
3226 idt77252_sram_write_errors
= 0;
3228 card
->tst_index
= 0;
3229 writel(card
->tst
[0] << 2, SAR_REG_TSTB
);
3231 /* Initialize ABRSTD and Receive FIFO */
3232 IPRINTK("%s: initialize ABRSTD ...\n", card
->name
);
3233 writel(card
->abrst_size
| (card
->abrst_base
<< 2),
3236 IPRINTK("%s: initialize receive fifo ...\n", card
->name
);
3237 writel(card
->fifo_size
| (card
->fifo_base
<< 2),
3240 IPRINTK("%s: SRAM initialization complete.\n", card
->name
);
3243 static int init_card(struct atm_dev
*dev
)
3245 struct idt77252_dev
*card
= dev
->dev_data
;
3246 struct pci_dev
*pcidev
= card
->pcidev
;
3247 unsigned long tmpl
, modl
;
3248 unsigned int linkrate
, rsvdcr
;
3249 unsigned int tst_entries
;
3250 struct net_device
*tmp
;
3258 if (test_bit(IDT77252_BIT_INIT
, &card
->flags
)) {
3259 printk("Error: SAR already initialized.\n");
3263 /*****************************************************************/
3264 /* P C I C O N F I G U R A T I O N */
3265 /*****************************************************************/
3267 /* Set PCI Retry-Timeout and TRDY timeout */
3268 IPRINTK("%s: Checking PCI retries.\n", card
->name
);
3269 if (pci_read_config_byte(pcidev
, 0x40, &pci_byte
) != 0) {
3270 printk("%s: can't read PCI retry timeout.\n", card
->name
);
3274 if (pci_byte
!= 0) {
3275 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3276 card
->name
, pci_byte
);
3277 if (pci_write_config_byte(pcidev
, 0x40, 0) != 0) {
3278 printk("%s: can't set PCI retry timeout.\n",
3284 IPRINTK("%s: Checking PCI TRDY.\n", card
->name
);
3285 if (pci_read_config_byte(pcidev
, 0x41, &pci_byte
) != 0) {
3286 printk("%s: can't read PCI TRDY timeout.\n", card
->name
);
3290 if (pci_byte
!= 0) {
3291 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3292 card
->name
, pci_byte
);
3293 if (pci_write_config_byte(pcidev
, 0x41, 0) != 0) {
3294 printk("%s: can't set PCI TRDY timeout.\n", card
->name
);
3299 /* Reset Timer register */
3300 if (readl(SAR_REG_STAT
) & SAR_STAT_TMROF
) {
3301 printk("%s: resetting timer overflow.\n", card
->name
);
3302 writel(SAR_STAT_TMROF
, SAR_REG_STAT
);
3304 IPRINTK("%s: Request IRQ ... ", card
->name
);
3305 if (request_irq(pcidev
->irq
, idt77252_interrupt
, IRQF_SHARED
,
3306 card
->name
, card
) != 0) {
3307 printk("%s: can't allocate IRQ.\n", card
->name
);
3311 IPRINTK("got %d.\n", pcidev
->irq
);
3313 /*****************************************************************/
3314 /* C H E C K A N D I N I T S R A M */
3315 /*****************************************************************/
3317 IPRINTK("%s: Initializing SRAM\n", card
->name
);
3319 /* preset size of connecton table, so that init_sram() knows about it */
3320 conf
= SAR_CFG_TX_FIFO_SIZE_9
| /* Use maximum fifo size */
3321 SAR_CFG_RXSTQ_SIZE_8k
| /* Receive Status Queue is 8k */
3322 SAR_CFG_IDLE_CLP
| /* Set CLP on idle cells */
3323 #ifndef ATM_IDT77252_SEND_IDLE
3324 SAR_CFG_NO_IDLE
| /* Do not send idle cells */
3328 if (card
->sramsize
== (512 * 1024))
3329 conf
|= SAR_CFG_CNTBL_1k
;
3331 conf
|= SAR_CFG_CNTBL_512
;
3335 conf
|= SAR_CFG_VPVCS_0
;
3339 conf
|= SAR_CFG_VPVCS_1
;
3342 conf
|= SAR_CFG_VPVCS_2
;
3345 conf
|= SAR_CFG_VPVCS_8
;
3349 writel(readl(SAR_REG_CFG
) | conf
, SAR_REG_CFG
);
3353 /********************************************************************/
3354 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */
3355 /********************************************************************/
3356 /* Initialize TSQ */
3357 if (0 != init_tsq(card
)) {
3361 /* Initialize RSQ */
3362 if (0 != init_rsq(card
)) {
3367 card
->vpibits
= vpibits
;
3368 if (card
->sramsize
== (512 * 1024)) {
3369 card
->vcibits
= 10 - card
->vpibits
;
3371 card
->vcibits
= 9 - card
->vpibits
;
3375 for (k
= 0, i
= 1; k
< card
->vcibits
; k
++) {
3380 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card
->name
);
3381 writel(0, SAR_REG_VPM
);
3383 /* Little Endian Order */
3384 writel(0, SAR_REG_GP
);
3386 /* Initialize RAW Cell Handle Register */
3387 card
->raw_cell_hnd
= dma_alloc_coherent(&card
->pcidev
->dev
,
3389 &card
->raw_cell_paddr
,
3391 if (!card
->raw_cell_hnd
) {
3392 printk("%s: memory allocation failure.\n", card
->name
);
3396 writel(card
->raw_cell_paddr
, SAR_REG_RAWHND
);
3397 IPRINTK("%s: raw cell handle is at 0x%p.\n", card
->name
,
3398 card
->raw_cell_hnd
);
3400 size
= sizeof(struct vc_map
*) * card
->tct_size
;
3401 IPRINTK("%s: allocate %d byte for VC map.\n", card
->name
, size
);
3402 card
->vcs
= vzalloc(size
);
3404 printk("%s: memory allocation failure.\n", card
->name
);
3409 size
= sizeof(struct vc_map
*) * card
->scd_size
;
3410 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3412 card
->scd2vc
= vzalloc(size
);
3413 if (!card
->scd2vc
) {
3414 printk("%s: memory allocation failure.\n", card
->name
);
3419 size
= sizeof(struct tst_info
) * (card
->tst_size
- 2);
3420 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3422 card
->soft_tst
= vmalloc(size
);
3423 if (!card
->soft_tst
) {
3424 printk("%s: memory allocation failure.\n", card
->name
);
3428 for (i
= 0; i
< card
->tst_size
- 2; i
++) {
3429 card
->soft_tst
[i
].tste
= TSTE_OPC_VAR
;
3430 card
->soft_tst
[i
].vc
= NULL
;
3433 if (dev
->phy
== NULL
) {
3434 printk("%s: No LT device defined.\n", card
->name
);
3438 if (dev
->phy
->ioctl
== NULL
) {
3439 printk("%s: LT had no IOCTL function defined.\n", card
->name
);
3444 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3446 * this is a jhs hack to get around special functionality in the
3447 * phy driver for the atecom hardware; the functionality doesn't
3448 * exist in the linux atm suni driver
3450 * it isn't the right way to do things, but as the guy from NIST
3451 * said, talking about their measurement of the fine structure
3452 * constant, "it's good enough for government work."
3454 linkrate
= 149760000;
3457 card
->link_pcr
= (linkrate
/ 8 / 53);
3458 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3459 card
->name
, linkrate
, card
->link_pcr
);
3461 #ifdef ATM_IDT77252_SEND_IDLE
3462 card
->utopia_pcr
= card
->link_pcr
;
3464 card
->utopia_pcr
= (160000000 / 8 / 54);
3468 if (card
->utopia_pcr
> card
->link_pcr
)
3469 rsvdcr
= card
->utopia_pcr
- card
->link_pcr
;
3471 tmpl
= (unsigned long) rsvdcr
* ((unsigned long) card
->tst_size
- 2);
3472 modl
= tmpl
% (unsigned long)card
->utopia_pcr
;
3473 tst_entries
= (int) (tmpl
/ (unsigned long)card
->utopia_pcr
);
3476 card
->tst_free
-= tst_entries
;
3477 fill_tst(card
, NULL
, tst_entries
, TSTE_OPC_NULL
);
3480 idt77252_eeprom_init(card
);
3481 printk("%s: EEPROM: %02x:", card
->name
,
3482 idt77252_eeprom_read_status(card
));
3484 for (i
= 0; i
< 0x80; i
++) {
3486 idt77252_eeprom_read_byte(card
, i
)
3490 #endif /* HAVE_EEPROM */
3495 sprintf(tname
, "eth%d", card
->index
);
3496 tmp
= dev_get_by_name(&init_net
, tname
); /* jhs: was "tmp = dev_get(tname);" */
3498 memcpy(card
->atmdev
->esi
, tmp
->dev_addr
, 6);
3500 printk("%s: ESI %pM\n", card
->name
, card
->atmdev
->esi
);
3506 /* Set Maximum Deficit Count for now. */
3507 writel(0xffff, SAR_REG_MDFCT
);
3509 set_bit(IDT77252_BIT_INIT
, &card
->flags
);
3511 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card
->name
);
3516 /*****************************************************************************/
3518 /* Probing of IDT77252 ABR SAR */
3520 /*****************************************************************************/
3523 static int idt77252_preset(struct idt77252_dev
*card
)
3527 /*****************************************************************/
3528 /* P C I C O N F I G U R A T I O N */
3529 /*****************************************************************/
3531 XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3533 if (pci_read_config_word(card
->pcidev
, PCI_COMMAND
, &pci_command
)) {
3534 printk("%s: can't read PCI_COMMAND.\n", card
->name
);
3538 if (!(pci_command
& PCI_COMMAND_IO
)) {
3539 printk("%s: PCI_COMMAND: %04x (?)\n",
3540 card
->name
, pci_command
);
3544 pci_command
|= (PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
3545 if (pci_write_config_word(card
->pcidev
, PCI_COMMAND
, pci_command
)) {
3546 printk("%s: can't write PCI_COMMAND.\n", card
->name
);
3550 /*****************************************************************/
3551 /* G E N E R I C R E S E T */
3552 /*****************************************************************/
3554 /* Software reset */
3555 writel(SAR_CFG_SWRST
, SAR_REG_CFG
);
3557 writel(0, SAR_REG_CFG
);
3559 IPRINTK("%s: Software resetted.\n", card
->name
);
3564 static unsigned long probe_sram(struct idt77252_dev
*card
)
3568 writel(0, SAR_REG_DR0
);
3569 writel(SAR_CMD_WRITE_SRAM
| (0 << 2), SAR_REG_CMD
);
3571 for (addr
= 0x4000; addr
< 0x80000; addr
+= 0x4000) {
3572 writel(ATM_POISON
, SAR_REG_DR0
);
3573 writel(SAR_CMD_WRITE_SRAM
| (addr
<< 2), SAR_REG_CMD
);
3575 writel(SAR_CMD_READ_SRAM
| (0 << 2), SAR_REG_CMD
);
3576 data
= readl(SAR_REG_DR0
);
3582 return addr
* sizeof(u32
);
3585 static int idt77252_init_one(struct pci_dev
*pcidev
,
3586 const struct pci_device_id
*id
)
3588 static struct idt77252_dev
**last
= &idt77252_chain
;
3589 static int index
= 0;
3591 unsigned long membase
, srambase
;
3592 struct idt77252_dev
*card
;
3593 struct atm_dev
*dev
;
3597 if ((err
= pci_enable_device(pcidev
))) {
3598 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev
));
3602 if ((err
= dma_set_mask_and_coherent(&pcidev
->dev
, DMA_BIT_MASK(32)))) {
3603 printk("idt77252: can't enable DMA for PCI device at %s\n", pci_name(pcidev
));
3604 goto err_out_disable_pdev
;
3607 card
= kzalloc(sizeof(struct idt77252_dev
), GFP_KERNEL
);
3609 printk("idt77252-%d: can't allocate private data\n", index
);
3611 goto err_out_disable_pdev
;
3613 card
->revision
= pcidev
->revision
;
3614 card
->index
= index
;
3615 card
->pcidev
= pcidev
;
3616 sprintf(card
->name
, "idt77252-%d", card
->index
);
3618 INIT_WORK(&card
->tqueue
, idt77252_softint
);
3620 membase
= pci_resource_start(pcidev
, 1);
3621 srambase
= pci_resource_start(pcidev
, 2);
3623 mutex_init(&card
->mutex
);
3624 spin_lock_init(&card
->cmd_lock
);
3625 spin_lock_init(&card
->tst_lock
);
3627 timer_setup(&card
->tst_timer
, tst_timer
, 0);
3629 /* Do the I/O remapping... */
3630 card
->membase
= ioremap(membase
, 1024);
3631 if (!card
->membase
) {
3632 printk("%s: can't ioremap() membase\n", card
->name
);
3634 goto err_out_free_card
;
3637 if (idt77252_preset(card
)) {
3638 printk("%s: preset failed\n", card
->name
);
3640 goto err_out_iounmap
;
3643 dev
= atm_dev_register("idt77252", &pcidev
->dev
, &idt77252_ops
, -1,
3646 printk("%s: can't register atm device\n", card
->name
);
3648 goto err_out_iounmap
;
3650 dev
->dev_data
= card
;
3653 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3656 printk("%s: can't init SUNI\n", card
->name
);
3658 goto err_out_deinit_card
;
3660 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
3662 card
->sramsize
= probe_sram(card
);
3664 for (i
= 0; i
< 4; i
++) {
3665 card
->fbq
[i
] = ioremap(srambase
| 0x200000 | (i
<< 18), 4);
3666 if (!card
->fbq
[i
]) {
3667 printk("%s: can't ioremap() FBQ%d\n", card
->name
, i
);
3669 goto err_out_deinit_card
;
3673 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3674 card
->name
, ((card
->revision
> 1) && (card
->revision
< 25)) ?
3675 'A' + card
->revision
- 1 : '?', membase
, srambase
,
3676 card
->sramsize
/ 1024);
3678 if (init_card(dev
)) {
3679 printk("%s: init_card failed\n", card
->name
);
3681 goto err_out_deinit_card
;
3684 dev
->ci_range
.vpi_bits
= card
->vpibits
;
3685 dev
->ci_range
.vci_bits
= card
->vcibits
;
3686 dev
->link_rate
= card
->link_pcr
;
3688 if (dev
->phy
->start
)
3689 dev
->phy
->start(dev
);
3691 if (idt77252_dev_open(card
)) {
3692 printk("%s: dev_open failed\n", card
->name
);
3705 dev
->phy
->stop(dev
);
3707 err_out_deinit_card
:
3711 iounmap(card
->membase
);
3716 err_out_disable_pdev
:
3717 pci_disable_device(pcidev
);
3721 static const struct pci_device_id idt77252_pci_tbl
[] =
3723 { PCI_VDEVICE(IDT
, PCI_DEVICE_ID_IDT_IDT77252
), 0 },
3727 MODULE_DEVICE_TABLE(pci
, idt77252_pci_tbl
);
3729 static struct pci_driver idt77252_driver
= {
3731 .id_table
= idt77252_pci_tbl
,
3732 .probe
= idt77252_init_one
,
3735 static int __init
idt77252_init(void)
3737 struct sk_buff
*skb
;
3739 printk("%s: at %p\n", __func__
, idt77252_init
);
3740 BUILD_BUG_ON(sizeof(skb
->cb
) < sizeof(struct idt77252_skb_prv
) + sizeof(struct atm_skb_data
));
3741 return pci_register_driver(&idt77252_driver
);
3744 static void __exit
idt77252_exit(void)
3746 struct idt77252_dev
*card
;
3747 struct atm_dev
*dev
;
3749 pci_unregister_driver(&idt77252_driver
);
3751 while (idt77252_chain
) {
3752 card
= idt77252_chain
;
3754 idt77252_chain
= card
->next
;
3757 dev
->phy
->stop(dev
);
3759 pci_disable_device(card
->pcidev
);
3763 DIPRINTK("idt77252: finished cleanup-module().\n");
3766 module_init(idt77252_init
);
3767 module_exit(idt77252_exit
);
3769 MODULE_LICENSE("GPL");
3771 module_param(vpibits
, uint
, 0);
3772 MODULE_PARM_DESC(vpibits
, "number of VPI bits supported (0, 1, or 2)");
3773 #ifdef CONFIG_ATM_IDT77252_DEBUG
3774 module_param(debug
, ulong
, 0644);
3775 MODULE_PARM_DESC(debug
, "debug bitmap, see drivers/atm/idt77252.h");
3778 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
3779 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");