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1 /* lanai.c -- Copyright 1999-2003 by Mitchell Blank Jr <mitch@sfgoth.com>
2 *
3 * This program is free software; you can redistribute it and/or
4 * modify it under the terms of the GNU General Public License
5 * as published by the Free Software Foundation; either version
6 * 2 of the License, or (at your option) any later version.
7 *
8 * This driver supports ATM cards based on the Efficient "Lanai"
9 * chipset such as the Speedstream 3010 and the ENI-25p. The
10 * Speedstream 3060 is currently not supported since we don't
11 * have the code to drive the on-board Alcatel DSL chipset (yet).
12 *
13 * Thanks to Efficient for supporting this project with hardware,
14 * documentation, and by answering my questions.
15 *
16 * Things not working yet:
17 *
18 * o We don't support the Speedstream 3060 yet - this card has
19 * an on-board DSL modem chip by Alcatel and the driver will
20 * need some extra code added to handle it
21 *
22 * o Note that due to limitations of the Lanai only one VCC can be
23 * in CBR at once
24 *
25 * o We don't currently parse the EEPROM at all. The code is all
26 * there as per the spec, but it doesn't actually work. I think
27 * there may be some issues with the docs. Anyway, do NOT
28 * enable it yet - bugs in that code may actually damage your
29 * hardware! Because of this you should hardware an ESI before
30 * trying to use this in a LANE or MPOA environment.
31 *
32 * o AAL0 is stubbed in but the actual rx/tx path isn't written yet:
33 * vcc_tx_aal0() needs to send or queue a SKB
34 * vcc_tx_unqueue_aal0() needs to attempt to send queued SKBs
35 * vcc_rx_aal0() needs to handle AAL0 interrupts
36 * This isn't too much work - I just wanted to get other things
37 * done first.
38 *
39 * o lanai_change_qos() isn't written yet
40 *
41 * o There aren't any ioctl's yet -- I'd like to eventually support
42 * setting loopback and LED modes that way.
43 *
44 * o If the segmentation engine or DMA gets shut down we should restart
45 * card as per section 17.0i. (see lanai_reset)
46 *
47 * o setsockopt(SO_CIRANGE) isn't done (although despite what the
48 * API says it isn't exactly commonly implemented)
49 */
50
51 /* Version history:
52 * v.1.00 -- 26-JUL-2003 -- PCI/DMA updates
53 * v.0.02 -- 11-JAN-2000 -- Endian fixes
54 * v.0.01 -- 30-NOV-1999 -- Initial release
55 */
56
57 #include <linux/module.h>
58 #include <linux/slab.h>
59 #include <linux/mm.h>
60 #include <linux/atmdev.h>
61 #include <asm/io.h>
62 #include <asm/byteorder.h>
63 #include <linux/spinlock.h>
64 #include <linux/pci.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/init.h>
67 #include <linux/delay.h>
68 #include <linux/interrupt.h>
69
70 /* -------------------- TUNABLE PARAMATERS: */
71
72 /*
73 * Maximum number of VCIs per card. Setting it lower could theoretically
74 * save some memory, but since we allocate our vcc list with get_free_pages,
75 * it's not really likely for most architectures
76 */
77 #define NUM_VCI (1024)
78
79 /*
80 * Enable extra debugging
81 */
82 #define DEBUG
83 /*
84 * Debug _all_ register operations with card, except the memory test.
85 * Also disables the timed poll to prevent extra chattiness. This
86 * isn't for normal use
87 */
88 #undef DEBUG_RW
89
90 /*
91 * The programming guide specifies a full test of the on-board SRAM
92 * at initialization time. Undefine to remove this
93 */
94 #define FULL_MEMORY_TEST
95
96 /*
97 * This is the number of (4 byte) service entries that we will
98 * try to allocate at startup. Note that we will end up with
99 * one PAGE_SIZE's worth regardless of what this is set to
100 */
101 #define SERVICE_ENTRIES (1024)
102 /* TODO: make above a module load-time option */
103
104 /*
105 * We normally read the onboard EEPROM in order to discover our MAC
106 * address. Undefine to _not_ do this
107 */
108 /* #define READ_EEPROM */ /* ***DONT ENABLE YET*** */
109 /* TODO: make above a module load-time option (also) */
110
111 /*
112 * Depth of TX fifo (in 128 byte units; range 2-31)
113 * Smaller numbers are better for network latency
114 * Larger numbers are better for PCI latency
115 * I'm really sure where the best tradeoff is, but the BSD driver uses
116 * 7 and it seems to work ok.
117 */
118 #define TX_FIFO_DEPTH (7)
119 /* TODO: make above a module load-time option */
120
121 /*
122 * How often (in jiffies) we will try to unstick stuck connections -
123 * shouldn't need to happen much
124 */
125 #define LANAI_POLL_PERIOD (10*HZ)
126 /* TODO: make above a module load-time option */
127
128 /*
129 * When allocating an AAL5 receiving buffer, try to make it at least
130 * large enough to hold this many max_sdu sized PDUs
131 */
132 #define AAL5_RX_MULTIPLIER (3)
133 /* TODO: make above a module load-time option */
134
135 /*
136 * Same for transmitting buffer
137 */
138 #define AAL5_TX_MULTIPLIER (3)
139 /* TODO: make above a module load-time option */
140
141 /*
142 * When allocating an AAL0 transmiting buffer, how many cells should fit.
143 * Remember we'll end up with a PAGE_SIZE of them anyway, so this isn't
144 * really critical
145 */
146 #define AAL0_TX_MULTIPLIER (40)
147 /* TODO: make above a module load-time option */
148
149 /*
150 * How large should we make the AAL0 receiving buffer. Remember that this
151 * is shared between all AAL0 VC's
152 */
153 #define AAL0_RX_BUFFER_SIZE (PAGE_SIZE)
154 /* TODO: make above a module load-time option */
155
156 /*
157 * Should we use Lanai's "powerdown" feature when no vcc's are bound?
158 */
159 /* #define USE_POWERDOWN */
160 /* TODO: make above a module load-time option (also) */
161
162 /* -------------------- DEBUGGING AIDS: */
163
164 #define DEV_LABEL "lanai"
165
166 #ifdef DEBUG
167
168 #define DPRINTK(format, args...) \
169 printk(KERN_DEBUG DEV_LABEL ": " format, ##args)
170 #define APRINTK(truth, format, args...) \
171 do { \
172 if (unlikely(!(truth))) \
173 printk(KERN_ERR DEV_LABEL ": " format, ##args); \
174 } while (0)
175
176 #else /* !DEBUG */
177
178 #define DPRINTK(format, args...)
179 #define APRINTK(truth, format, args...)
180
181 #endif /* DEBUG */
182
183 #ifdef DEBUG_RW
184 #define RWDEBUG(format, args...) \
185 printk(KERN_DEBUG DEV_LABEL ": " format, ##args)
186 #else /* !DEBUG_RW */
187 #define RWDEBUG(format, args...)
188 #endif
189
190 /* -------------------- DATA DEFINITIONS: */
191
192 #define LANAI_MAPPING_SIZE (0x40000)
193 #define LANAI_EEPROM_SIZE (128)
194
195 typedef int vci_t;
196 typedef void __iomem *bus_addr_t;
197
198 /* DMA buffer in host memory for TX, RX, or service list. */
199 struct lanai_buffer {
200 u32 *start; /* From get_free_pages */
201 u32 *end; /* One past last byte */
202 u32 *ptr; /* Pointer to current host location */
203 dma_addr_t dmaaddr;
204 };
205
206 struct lanai_vcc_stats {
207 unsigned rx_nomem;
208 union {
209 struct {
210 unsigned rx_badlen;
211 unsigned service_trash;
212 unsigned service_stream;
213 unsigned service_rxcrc;
214 } aal5;
215 struct {
216 } aal0;
217 } x;
218 };
219
220 struct lanai_dev; /* Forward declaration */
221
222 /*
223 * This is the card-specific per-vcc data. Note that unlike some other
224 * drivers there is NOT a 1-to-1 correspondance between these and
225 * atm_vcc's - each one of these represents an actual 2-way vcc, but
226 * an atm_vcc can be 1-way and share with a 1-way vcc in the other
227 * direction. To make it weirder, there can even be 0-way vccs
228 * bound to us, waiting to do a change_qos
229 */
230 struct lanai_vcc {
231 bus_addr_t vbase; /* Base of VCC's registers */
232 struct lanai_vcc_stats stats;
233 int nref; /* # of atm_vcc's who reference us */
234 vci_t vci;
235 struct {
236 struct lanai_buffer buf;
237 struct atm_vcc *atmvcc; /* atm_vcc who is receiver */
238 } rx;
239 struct {
240 struct lanai_buffer buf;
241 struct atm_vcc *atmvcc; /* atm_vcc who is transmitter */
242 int endptr; /* last endptr from service entry */
243 struct sk_buff_head backlog;
244 void (*unqueue)(struct lanai_dev *, struct lanai_vcc *, int);
245 } tx;
246 };
247
248 enum lanai_type {
249 lanai2 = PCI_DEVICE_ID_EF_ATM_LANAI2,
250 lanaihb = PCI_DEVICE_ID_EF_ATM_LANAIHB
251 };
252
253 struct lanai_dev_stats {
254 unsigned ovfl_trash; /* # of cells dropped - buffer overflow */
255 unsigned vci_trash; /* # of cells dropped - closed vci */
256 unsigned hec_err; /* # of cells dropped - bad HEC */
257 unsigned atm_ovfl; /* # of cells dropped - rx fifo overflow */
258 unsigned pcierr_parity_detect;
259 unsigned pcierr_serr_set;
260 unsigned pcierr_master_abort;
261 unsigned pcierr_m_target_abort;
262 unsigned pcierr_s_target_abort;
263 unsigned pcierr_master_parity;
264 unsigned service_notx;
265 unsigned service_norx;
266 unsigned service_rxnotaal5;
267 unsigned dma_reenable;
268 unsigned card_reset;
269 };
270
271 struct lanai_dev {
272 bus_addr_t base;
273 struct lanai_dev_stats stats;
274 struct lanai_buffer service;
275 struct lanai_vcc **vccs;
276 #ifdef USE_POWERDOWN
277 int nbound; /* number of bound vccs */
278 #endif
279 enum lanai_type type;
280 vci_t num_vci; /* Currently just NUM_VCI */
281 u8 eeprom[LANAI_EEPROM_SIZE];
282 u32 serialno, magicno;
283 struct pci_dev *pci;
284 DECLARE_BITMAP(backlog_vccs, NUM_VCI); /* VCCs with tx backlog */
285 DECLARE_BITMAP(transmit_ready, NUM_VCI); /* VCCs with transmit space */
286 struct timer_list timer;
287 int naal0;
288 struct lanai_buffer aal0buf; /* AAL0 RX buffers */
289 u32 conf1, conf2; /* CONFIG[12] registers */
290 u32 status; /* STATUS register */
291 spinlock_t endtxlock;
292 spinlock_t servicelock;
293 struct atm_vcc *cbrvcc;
294 int number;
295 int board_rev;
296 /* TODO - look at race conditions with maintence of conf1/conf2 */
297 /* TODO - transmit locking: should we use _irq not _irqsave? */
298 /* TODO - organize above in some rational fashion (see <asm/cache.h>) */
299 };
300
301 /*
302 * Each device has two bitmaps for each VCC (baclog_vccs and transmit_ready)
303 * This function iterates one of these, calling a given function for each
304 * vci with their bit set
305 */
306 static void vci_bitfield_iterate(struct lanai_dev *lanai,
307 const unsigned long *lp,
308 void (*func)(struct lanai_dev *,vci_t vci))
309 {
310 vci_t vci;
311
312 for_each_set_bit(vci, lp, NUM_VCI)
313 func(lanai, vci);
314 }
315
316 /* -------------------- BUFFER UTILITIES: */
317
318 /*
319 * Lanai needs DMA buffers aligned to 256 bytes of at least 1024 bytes -
320 * usually any page allocation will do. Just to be safe in case
321 * PAGE_SIZE is insanely tiny, though...
322 */
323 #define LANAI_PAGE_SIZE ((PAGE_SIZE >= 1024) ? PAGE_SIZE : 1024)
324
325 /*
326 * Allocate a buffer in host RAM for service list, RX, or TX
327 * Returns buf->start==NULL if no memory
328 * Note that the size will be rounded up 2^n bytes, and
329 * if we can't allocate that we'll settle for something smaller
330 * until minbytes
331 */
332 static void lanai_buf_allocate(struct lanai_buffer *buf,
333 size_t bytes, size_t minbytes, struct pci_dev *pci)
334 {
335 int size;
336
337 if (bytes > (128 * 1024)) /* max lanai buffer size */
338 bytes = 128 * 1024;
339 for (size = LANAI_PAGE_SIZE; size < bytes; size *= 2)
340 ;
341 if (minbytes < LANAI_PAGE_SIZE)
342 minbytes = LANAI_PAGE_SIZE;
343 do {
344 /*
345 * Technically we could use non-consistent mappings for
346 * everything, but the way the lanai uses DMA memory would
347 * make that a terrific pain. This is much simpler.
348 */
349 buf->start = pci_alloc_consistent(pci, size, &buf->dmaaddr);
350 if (buf->start != NULL) { /* Success */
351 /* Lanai requires 256-byte alignment of DMA bufs */
352 APRINTK((buf->dmaaddr & ~0xFFFFFF00) == 0,
353 "bad dmaaddr: 0x%lx\n",
354 (unsigned long) buf->dmaaddr);
355 buf->ptr = buf->start;
356 buf->end = (u32 *)
357 (&((unsigned char *) buf->start)[size]);
358 memset(buf->start, 0, size);
359 break;
360 }
361 size /= 2;
362 } while (size >= minbytes);
363 }
364
365 /* size of buffer in bytes */
366 static inline size_t lanai_buf_size(const struct lanai_buffer *buf)
367 {
368 return ((unsigned long) buf->end) - ((unsigned long) buf->start);
369 }
370
371 static void lanai_buf_deallocate(struct lanai_buffer *buf,
372 struct pci_dev *pci)
373 {
374 if (buf->start != NULL) {
375 pci_free_consistent(pci, lanai_buf_size(buf),
376 buf->start, buf->dmaaddr);
377 buf->start = buf->end = buf->ptr = NULL;
378 }
379 }
380
381 /* size of buffer as "card order" (0=1k .. 7=128k) */
382 static int lanai_buf_size_cardorder(const struct lanai_buffer *buf)
383 {
384 int order = get_order(lanai_buf_size(buf)) + (PAGE_SHIFT - 10);
385
386 /* This can only happen if PAGE_SIZE is gigantic, but just in case */
387 if (order > 7)
388 order = 7;
389 return order;
390 }
391
392 /* -------------------- PORT I/O UTILITIES: */
393
394 /* Registers (and their bit-fields) */
395 enum lanai_register {
396 Reset_Reg = 0x00, /* Reset; read for chip type; bits: */
397 #define RESET_GET_BOARD_REV(x) (((x)>> 0)&0x03) /* Board revision */
398 #define RESET_GET_BOARD_ID(x) (((x)>> 2)&0x03) /* Board ID */
399 #define BOARD_ID_LANAI256 (0) /* 25.6M adapter card */
400 Endian_Reg = 0x04, /* Endian setting */
401 IntStatus_Reg = 0x08, /* Interrupt status */
402 IntStatusMasked_Reg = 0x0C, /* Interrupt status (masked) */
403 IntAck_Reg = 0x10, /* Interrupt acknowledge */
404 IntAckMasked_Reg = 0x14, /* Interrupt acknowledge (masked) */
405 IntStatusSet_Reg = 0x18, /* Get status + enable/disable */
406 IntStatusSetMasked_Reg = 0x1C, /* Get status + en/di (masked) */
407 IntControlEna_Reg = 0x20, /* Interrupt control enable */
408 IntControlDis_Reg = 0x24, /* Interrupt control disable */
409 Status_Reg = 0x28, /* Status */
410 #define STATUS_PROMDATA (0x00000001) /* PROM_DATA pin */
411 #define STATUS_WAITING (0x00000002) /* Interrupt being delayed */
412 #define STATUS_SOOL (0x00000004) /* SOOL alarm */
413 #define STATUS_LOCD (0x00000008) /* LOCD alarm */
414 #define STATUS_LED (0x00000010) /* LED (HAPPI) output */
415 #define STATUS_GPIN (0x00000020) /* GPIN pin */
416 #define STATUS_BUTTBUSY (0x00000040) /* Butt register is pending */
417 Config1_Reg = 0x2C, /* Config word 1; bits: */
418 #define CONFIG1_PROMDATA (0x00000001) /* PROM_DATA pin */
419 #define CONFIG1_PROMCLK (0x00000002) /* PROM_CLK pin */
420 #define CONFIG1_SET_READMODE(x) ((x)*0x004) /* PCI BM reads; values: */
421 #define READMODE_PLAIN (0) /* Plain memory read */
422 #define READMODE_LINE (2) /* Memory read line */
423 #define READMODE_MULTIPLE (3) /* Memory read multiple */
424 #define CONFIG1_DMA_ENABLE (0x00000010) /* Turn on DMA */
425 #define CONFIG1_POWERDOWN (0x00000020) /* Turn off clocks */
426 #define CONFIG1_SET_LOOPMODE(x) ((x)*0x080) /* Clock&loop mode; values: */
427 #define LOOPMODE_NORMAL (0) /* Normal - no loop */
428 #define LOOPMODE_TIME (1)
429 #define LOOPMODE_DIAG (2)
430 #define LOOPMODE_LINE (3)
431 #define CONFIG1_MASK_LOOPMODE (0x00000180)
432 #define CONFIG1_SET_LEDMODE(x) ((x)*0x0200) /* Mode of LED; values: */
433 #define LEDMODE_NOT_SOOL (0) /* !SOOL */
434 #define LEDMODE_OFF (1) /* 0 */
435 #define LEDMODE_ON (2) /* 1 */
436 #define LEDMODE_NOT_LOCD (3) /* !LOCD */
437 #define LEDMORE_GPIN (4) /* GPIN */
438 #define LEDMODE_NOT_GPIN (7) /* !GPIN */
439 #define CONFIG1_MASK_LEDMODE (0x00000E00)
440 #define CONFIG1_GPOUT1 (0x00001000) /* Toggle for reset */
441 #define CONFIG1_GPOUT2 (0x00002000) /* Loopback PHY */
442 #define CONFIG1_GPOUT3 (0x00004000) /* Loopback lanai */
443 Config2_Reg = 0x30, /* Config word 2; bits: */
444 #define CONFIG2_HOWMANY (0x00000001) /* >512 VCIs? */
445 #define CONFIG2_PTI7_MODE (0x00000002) /* Make PTI=7 RM, not OAM */
446 #define CONFIG2_VPI_CHK_DIS (0x00000004) /* Ignore RX VPI value */
447 #define CONFIG2_HEC_DROP (0x00000008) /* Drop cells w/ HEC errors */
448 #define CONFIG2_VCI0_NORMAL (0x00000010) /* Treat VCI=0 normally */
449 #define CONFIG2_CBR_ENABLE (0x00000020) /* Deal with CBR traffic */
450 #define CONFIG2_TRASH_ALL (0x00000040) /* Trashing incoming cells */
451 #define CONFIG2_TX_DISABLE (0x00000080) /* Trashing outgoing cells */
452 #define CONFIG2_SET_TRASH (0x00000100) /* Turn trashing on */
453 Statistics_Reg = 0x34, /* Statistics; bits: */
454 #define STATS_GET_FIFO_OVFL(x) (((x)>> 0)&0xFF) /* FIFO overflowed */
455 #define STATS_GET_HEC_ERR(x) (((x)>> 8)&0xFF) /* HEC was bad */
456 #define STATS_GET_BAD_VCI(x) (((x)>>16)&0xFF) /* VCI not open */
457 #define STATS_GET_BUF_OVFL(x) (((x)>>24)&0xFF) /* VCC buffer full */
458 ServiceStuff_Reg = 0x38, /* Service stuff; bits: */
459 #define SSTUFF_SET_SIZE(x) ((x)*0x20000000) /* size of service buffer */
460 #define SSTUFF_SET_ADDR(x) ((x)>>8) /* set address of buffer */
461 ServWrite_Reg = 0x3C, /* ServWrite Pointer */
462 ServRead_Reg = 0x40, /* ServRead Pointer */
463 TxDepth_Reg = 0x44, /* FIFO Transmit Depth */
464 Butt_Reg = 0x48, /* Butt register */
465 CBR_ICG_Reg = 0x50,
466 CBR_PTR_Reg = 0x54,
467 PingCount_Reg = 0x58, /* Ping count */
468 DMA_Addr_Reg = 0x5C /* DMA address */
469 };
470
471 static inline bus_addr_t reg_addr(const struct lanai_dev *lanai,
472 enum lanai_register reg)
473 {
474 return lanai->base + reg;
475 }
476
477 static inline u32 reg_read(const struct lanai_dev *lanai,
478 enum lanai_register reg)
479 {
480 u32 t;
481 t = readl(reg_addr(lanai, reg));
482 RWDEBUG("R [0x%08X] 0x%02X = 0x%08X\n", (unsigned int) lanai->base,
483 (int) reg, t);
484 return t;
485 }
486
487 static inline void reg_write(const struct lanai_dev *lanai, u32 val,
488 enum lanai_register reg)
489 {
490 RWDEBUG("W [0x%08X] 0x%02X < 0x%08X\n", (unsigned int) lanai->base,
491 (int) reg, val);
492 writel(val, reg_addr(lanai, reg));
493 }
494
495 static inline void conf1_write(const struct lanai_dev *lanai)
496 {
497 reg_write(lanai, lanai->conf1, Config1_Reg);
498 }
499
500 static inline void conf2_write(const struct lanai_dev *lanai)
501 {
502 reg_write(lanai, lanai->conf2, Config2_Reg);
503 }
504
505 /* Same as conf2_write(), but defers I/O if we're powered down */
506 static inline void conf2_write_if_powerup(const struct lanai_dev *lanai)
507 {
508 #ifdef USE_POWERDOWN
509 if (unlikely((lanai->conf1 & CONFIG1_POWERDOWN) != 0))
510 return;
511 #endif /* USE_POWERDOWN */
512 conf2_write(lanai);
513 }
514
515 static inline void reset_board(const struct lanai_dev *lanai)
516 {
517 DPRINTK("about to reset board\n");
518 reg_write(lanai, 0, Reset_Reg);
519 /*
520 * If we don't delay a little while here then we can end up
521 * leaving the card in a VERY weird state and lock up the
522 * PCI bus. This isn't documented anywhere but I've convinced
523 * myself after a lot of painful experimentation
524 */
525 udelay(5);
526 }
527
528 /* -------------------- CARD SRAM UTILITIES: */
529
530 /* The SRAM is mapped into normal PCI memory space - the only catch is
531 * that it is only 16-bits wide but must be accessed as 32-bit. The
532 * 16 high bits will be zero. We don't hide this, since they get
533 * programmed mostly like discrete registers anyway
534 */
535 #define SRAM_START (0x20000)
536 #define SRAM_BYTES (0x20000) /* Again, half don't really exist */
537
538 static inline bus_addr_t sram_addr(const struct lanai_dev *lanai, int offset)
539 {
540 return lanai->base + SRAM_START + offset;
541 }
542
543 static inline u32 sram_read(const struct lanai_dev *lanai, int offset)
544 {
545 return readl(sram_addr(lanai, offset));
546 }
547
548 static inline void sram_write(const struct lanai_dev *lanai,
549 u32 val, int offset)
550 {
551 writel(val, sram_addr(lanai, offset));
552 }
553
554 static int sram_test_word(const struct lanai_dev *lanai, int offset,
555 u32 pattern)
556 {
557 u32 readback;
558 sram_write(lanai, pattern, offset);
559 readback = sram_read(lanai, offset);
560 if (likely(readback == pattern))
561 return 0;
562 printk(KERN_ERR DEV_LABEL
563 "(itf %d): SRAM word at %d bad: wrote 0x%X, read 0x%X\n",
564 lanai->number, offset,
565 (unsigned int) pattern, (unsigned int) readback);
566 return -EIO;
567 }
568
569 static int sram_test_pass(const struct lanai_dev *lanai, u32 pattern)
570 {
571 int offset, result = 0;
572 for (offset = 0; offset < SRAM_BYTES && result == 0; offset += 4)
573 result = sram_test_word(lanai, offset, pattern);
574 return result;
575 }
576
577 static int sram_test_and_clear(const struct lanai_dev *lanai)
578 {
579 #ifdef FULL_MEMORY_TEST
580 int result;
581 DPRINTK("testing SRAM\n");
582 if ((result = sram_test_pass(lanai, 0x5555)) != 0)
583 return result;
584 if ((result = sram_test_pass(lanai, 0xAAAA)) != 0)
585 return result;
586 #endif
587 DPRINTK("clearing SRAM\n");
588 return sram_test_pass(lanai, 0x0000);
589 }
590
591 /* -------------------- CARD-BASED VCC TABLE UTILITIES: */
592
593 /* vcc table */
594 enum lanai_vcc_offset {
595 vcc_rxaddr1 = 0x00, /* Location1, plus bits: */
596 #define RXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of RX buffer */
597 #define RXADDR1_SET_RMMODE(x) ((x)*0x00800) /* RM cell action; values: */
598 #define RMMODE_TRASH (0) /* discard */
599 #define RMMODE_PRESERVE (1) /* input as AAL0 */
600 #define RMMODE_PIPE (2) /* pipe to coscheduler */
601 #define RMMODE_PIPEALL (3) /* pipe non-RM too */
602 #define RXADDR1_OAM_PRESERVE (0x00002000) /* Input OAM cells as AAL0 */
603 #define RXADDR1_SET_MODE(x) ((x)*0x0004000) /* Reassembly mode */
604 #define RXMODE_TRASH (0) /* discard */
605 #define RXMODE_AAL0 (1) /* non-AAL5 mode */
606 #define RXMODE_AAL5 (2) /* AAL5, intr. each PDU */
607 #define RXMODE_AAL5_STREAM (3) /* AAL5 w/o per-PDU intr */
608 vcc_rxaddr2 = 0x04, /* Location2 */
609 vcc_rxcrc1 = 0x08, /* RX CRC claculation space */
610 vcc_rxcrc2 = 0x0C,
611 vcc_rxwriteptr = 0x10, /* RX writeptr, plus bits: */
612 #define RXWRITEPTR_LASTEFCI (0x00002000) /* Last PDU had EFCI bit */
613 #define RXWRITEPTR_DROPPING (0x00004000) /* Had error, dropping */
614 #define RXWRITEPTR_TRASHING (0x00008000) /* Trashing */
615 vcc_rxbufstart = 0x14, /* RX bufstart, plus bits: */
616 #define RXBUFSTART_CLP (0x00004000)
617 #define RXBUFSTART_CI (0x00008000)
618 vcc_rxreadptr = 0x18, /* RX readptr */
619 vcc_txicg = 0x1C, /* TX ICG */
620 vcc_txaddr1 = 0x20, /* Location1, plus bits: */
621 #define TXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of TX buffer */
622 #define TXADDR1_ABR (0x00008000) /* use ABR (doesn't work) */
623 vcc_txaddr2 = 0x24, /* Location2 */
624 vcc_txcrc1 = 0x28, /* TX CRC claculation space */
625 vcc_txcrc2 = 0x2C,
626 vcc_txreadptr = 0x30, /* TX Readptr, plus bits: */
627 #define TXREADPTR_GET_PTR(x) ((x)&0x01FFF)
628 #define TXREADPTR_MASK_DELTA (0x0000E000) /* ? */
629 vcc_txendptr = 0x34, /* TX Endptr, plus bits: */
630 #define TXENDPTR_CLP (0x00002000)
631 #define TXENDPTR_MASK_PDUMODE (0x0000C000) /* PDU mode; values: */
632 #define PDUMODE_AAL0 (0*0x04000)
633 #define PDUMODE_AAL5 (2*0x04000)
634 #define PDUMODE_AAL5STREAM (3*0x04000)
635 vcc_txwriteptr = 0x38, /* TX Writeptr */
636 #define TXWRITEPTR_GET_PTR(x) ((x)&0x1FFF)
637 vcc_txcbr_next = 0x3C /* # of next CBR VCI in ring */
638 #define TXCBR_NEXT_BOZO (0x00008000) /* "bozo bit" */
639 };
640
641 #define CARDVCC_SIZE (0x40)
642
643 static inline bus_addr_t cardvcc_addr(const struct lanai_dev *lanai,
644 vci_t vci)
645 {
646 return sram_addr(lanai, vci * CARDVCC_SIZE);
647 }
648
649 static inline u32 cardvcc_read(const struct lanai_vcc *lvcc,
650 enum lanai_vcc_offset offset)
651 {
652 u32 val;
653 APRINTK(lvcc->vbase != NULL, "cardvcc_read: unbound vcc!\n");
654 val= readl(lvcc->vbase + offset);
655 RWDEBUG("VR vci=%04d 0x%02X = 0x%08X\n",
656 lvcc->vci, (int) offset, val);
657 return val;
658 }
659
660 static inline void cardvcc_write(const struct lanai_vcc *lvcc,
661 u32 val, enum lanai_vcc_offset offset)
662 {
663 APRINTK(lvcc->vbase != NULL, "cardvcc_write: unbound vcc!\n");
664 APRINTK((val & ~0xFFFF) == 0,
665 "cardvcc_write: bad val 0x%X (vci=%d, addr=0x%02X)\n",
666 (unsigned int) val, lvcc->vci, (unsigned int) offset);
667 RWDEBUG("VW vci=%04d 0x%02X > 0x%08X\n",
668 lvcc->vci, (unsigned int) offset, (unsigned int) val);
669 writel(val, lvcc->vbase + offset);
670 }
671
672 /* -------------------- COMPUTE SIZE OF AN AAL5 PDU: */
673
674 /* How many bytes will an AAL5 PDU take to transmit - remember that:
675 * o we need to add 8 bytes for length, CPI, UU, and CRC
676 * o we need to round up to 48 bytes for cells
677 */
678 static inline int aal5_size(int size)
679 {
680 int cells = (size + 8 + 47) / 48;
681 return cells * 48;
682 }
683
684 /* -------------------- FREE AN ATM SKB: */
685
686 static inline void lanai_free_skb(struct atm_vcc *atmvcc, struct sk_buff *skb)
687 {
688 if (atmvcc->pop != NULL)
689 atmvcc->pop(atmvcc, skb);
690 else
691 dev_kfree_skb_any(skb);
692 }
693
694 /* -------------------- TURN VCCS ON AND OFF: */
695
696 static void host_vcc_start_rx(const struct lanai_vcc *lvcc)
697 {
698 u32 addr1;
699 if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5) {
700 dma_addr_t dmaaddr = lvcc->rx.buf.dmaaddr;
701 cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc1);
702 cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc2);
703 cardvcc_write(lvcc, 0, vcc_rxwriteptr);
704 cardvcc_write(lvcc, 0, vcc_rxbufstart);
705 cardvcc_write(lvcc, 0, vcc_rxreadptr);
706 cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_rxaddr2);
707 addr1 = ((dmaaddr >> 8) & 0xFF) |
708 RXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->rx.buf))|
709 RXADDR1_SET_RMMODE(RMMODE_TRASH) | /* ??? */
710 /* RXADDR1_OAM_PRESERVE | --- no OAM support yet */
711 RXADDR1_SET_MODE(RXMODE_AAL5);
712 } else
713 addr1 = RXADDR1_SET_RMMODE(RMMODE_PRESERVE) | /* ??? */
714 RXADDR1_OAM_PRESERVE | /* ??? */
715 RXADDR1_SET_MODE(RXMODE_AAL0);
716 /* This one must be last! */
717 cardvcc_write(lvcc, addr1, vcc_rxaddr1);
718 }
719
720 static void host_vcc_start_tx(const struct lanai_vcc *lvcc)
721 {
722 dma_addr_t dmaaddr = lvcc->tx.buf.dmaaddr;
723 cardvcc_write(lvcc, 0, vcc_txicg);
724 cardvcc_write(lvcc, 0xFFFF, vcc_txcrc1);
725 cardvcc_write(lvcc, 0xFFFF, vcc_txcrc2);
726 cardvcc_write(lvcc, 0, vcc_txreadptr);
727 cardvcc_write(lvcc, 0, vcc_txendptr);
728 cardvcc_write(lvcc, 0, vcc_txwriteptr);
729 cardvcc_write(lvcc,
730 (lvcc->tx.atmvcc->qos.txtp.traffic_class == ATM_CBR) ?
731 TXCBR_NEXT_BOZO | lvcc->vci : 0, vcc_txcbr_next);
732 cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_txaddr2);
733 cardvcc_write(lvcc,
734 ((dmaaddr >> 8) & 0xFF) |
735 TXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->tx.buf)),
736 vcc_txaddr1);
737 }
738
739 /* Shutdown receiving on card */
740 static void lanai_shutdown_rx_vci(const struct lanai_vcc *lvcc)
741 {
742 if (lvcc->vbase == NULL) /* We were never bound to a VCI */
743 return;
744 /* 15.1.1 - set to trashing, wait one cell time (15us) */
745 cardvcc_write(lvcc,
746 RXADDR1_SET_RMMODE(RMMODE_TRASH) |
747 RXADDR1_SET_MODE(RXMODE_TRASH), vcc_rxaddr1);
748 udelay(15);
749 /* 15.1.2 - clear rest of entries */
750 cardvcc_write(lvcc, 0, vcc_rxaddr2);
751 cardvcc_write(lvcc, 0, vcc_rxcrc1);
752 cardvcc_write(lvcc, 0, vcc_rxcrc2);
753 cardvcc_write(lvcc, 0, vcc_rxwriteptr);
754 cardvcc_write(lvcc, 0, vcc_rxbufstart);
755 cardvcc_write(lvcc, 0, vcc_rxreadptr);
756 }
757
758 /* Shutdown transmitting on card.
759 * Unfortunately the lanai needs us to wait until all the data
760 * drains out of the buffer before we can dealloc it, so this
761 * can take awhile -- up to 370ms for a full 128KB buffer
762 * assuming everone else is quiet. In theory the time is
763 * boundless if there's a CBR VCC holding things up.
764 */
765 static void lanai_shutdown_tx_vci(struct lanai_dev *lanai,
766 struct lanai_vcc *lvcc)
767 {
768 struct sk_buff *skb;
769 unsigned long flags, timeout;
770 int read, write, lastread = -1;
771 APRINTK(!in_interrupt(),
772 "lanai_shutdown_tx_vci called w/o process context!\n");
773 if (lvcc->vbase == NULL) /* We were never bound to a VCI */
774 return;
775 /* 15.2.1 - wait for queue to drain */
776 while ((skb = skb_dequeue(&lvcc->tx.backlog)) != NULL)
777 lanai_free_skb(lvcc->tx.atmvcc, skb);
778 read_lock_irqsave(&vcc_sklist_lock, flags);
779 __clear_bit(lvcc->vci, lanai->backlog_vccs);
780 read_unlock_irqrestore(&vcc_sklist_lock, flags);
781 /*
782 * We need to wait for the VCC to drain but don't wait forever. We
783 * give each 1K of buffer size 1/128th of a second to clear out.
784 * TODO: maybe disable CBR if we're about to timeout?
785 */
786 timeout = jiffies +
787 (((lanai_buf_size(&lvcc->tx.buf) / 1024) * HZ) >> 7);
788 write = TXWRITEPTR_GET_PTR(cardvcc_read(lvcc, vcc_txwriteptr));
789 for (;;) {
790 read = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
791 if (read == write && /* Is TX buffer empty? */
792 (lvcc->tx.atmvcc->qos.txtp.traffic_class != ATM_CBR ||
793 (cardvcc_read(lvcc, vcc_txcbr_next) &
794 TXCBR_NEXT_BOZO) == 0))
795 break;
796 if (read != lastread) { /* Has there been any progress? */
797 lastread = read;
798 timeout += HZ / 10;
799 }
800 if (unlikely(time_after(jiffies, timeout))) {
801 printk(KERN_ERR DEV_LABEL "(itf %d): Timed out on "
802 "backlog closing vci %d\n",
803 lvcc->tx.atmvcc->dev->number, lvcc->vci);
804 DPRINTK("read, write = %d, %d\n", read, write);
805 break;
806 }
807 msleep(40);
808 }
809 /* 15.2.2 - clear out all tx registers */
810 cardvcc_write(lvcc, 0, vcc_txreadptr);
811 cardvcc_write(lvcc, 0, vcc_txwriteptr);
812 cardvcc_write(lvcc, 0, vcc_txendptr);
813 cardvcc_write(lvcc, 0, vcc_txcrc1);
814 cardvcc_write(lvcc, 0, vcc_txcrc2);
815 cardvcc_write(lvcc, 0, vcc_txaddr2);
816 cardvcc_write(lvcc, 0, vcc_txaddr1);
817 }
818
819 /* -------------------- MANAGING AAL0 RX BUFFER: */
820
821 static inline int aal0_buffer_allocate(struct lanai_dev *lanai)
822 {
823 DPRINTK("aal0_buffer_allocate: allocating AAL0 RX buffer\n");
824 lanai_buf_allocate(&lanai->aal0buf, AAL0_RX_BUFFER_SIZE, 80,
825 lanai->pci);
826 return (lanai->aal0buf.start == NULL) ? -ENOMEM : 0;
827 }
828
829 static inline void aal0_buffer_free(struct lanai_dev *lanai)
830 {
831 DPRINTK("aal0_buffer_allocate: freeing AAL0 RX buffer\n");
832 lanai_buf_deallocate(&lanai->aal0buf, lanai->pci);
833 }
834
835 /* -------------------- EEPROM UTILITIES: */
836
837 /* Offsets of data in the EEPROM */
838 #define EEPROM_COPYRIGHT (0)
839 #define EEPROM_COPYRIGHT_LEN (44)
840 #define EEPROM_CHECKSUM (62)
841 #define EEPROM_CHECKSUM_REV (63)
842 #define EEPROM_MAC (64)
843 #define EEPROM_MAC_REV (70)
844 #define EEPROM_SERIAL (112)
845 #define EEPROM_SERIAL_REV (116)
846 #define EEPROM_MAGIC (120)
847 #define EEPROM_MAGIC_REV (124)
848
849 #define EEPROM_MAGIC_VALUE (0x5AB478D2)
850
851 #ifndef READ_EEPROM
852
853 /* Stub functions to use if EEPROM reading is disabled */
854 static int eeprom_read(struct lanai_dev *lanai)
855 {
856 printk(KERN_INFO DEV_LABEL "(itf %d): *NOT* reading EEPROM\n",
857 lanai->number);
858 memset(&lanai->eeprom[EEPROM_MAC], 0, 6);
859 return 0;
860 }
861
862 static int eeprom_validate(struct lanai_dev *lanai)
863 {
864 lanai->serialno = 0;
865 lanai->magicno = EEPROM_MAGIC_VALUE;
866 return 0;
867 }
868
869 #else /* READ_EEPROM */
870
871 static int eeprom_read(struct lanai_dev *lanai)
872 {
873 int i, address;
874 u8 data;
875 u32 tmp;
876 #define set_config1(x) do { lanai->conf1 = x; conf1_write(lanai); \
877 } while (0)
878 #define clock_h() set_config1(lanai->conf1 | CONFIG1_PROMCLK)
879 #define clock_l() set_config1(lanai->conf1 &~ CONFIG1_PROMCLK)
880 #define data_h() set_config1(lanai->conf1 | CONFIG1_PROMDATA)
881 #define data_l() set_config1(lanai->conf1 &~ CONFIG1_PROMDATA)
882 #define pre_read() do { data_h(); clock_h(); udelay(5); } while (0)
883 #define read_pin() (reg_read(lanai, Status_Reg) & STATUS_PROMDATA)
884 #define send_stop() do { data_l(); udelay(5); clock_h(); udelay(5); \
885 data_h(); udelay(5); } while (0)
886 /* start with both clock and data high */
887 data_h(); clock_h(); udelay(5);
888 for (address = 0; address < LANAI_EEPROM_SIZE; address++) {
889 data = (address << 1) | 1; /* Command=read + address */
890 /* send start bit */
891 data_l(); udelay(5);
892 clock_l(); udelay(5);
893 for (i = 128; i != 0; i >>= 1) { /* write command out */
894 tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) |
895 ((data & i) ? CONFIG1_PROMDATA : 0);
896 if (lanai->conf1 != tmp) {
897 set_config1(tmp);
898 udelay(5); /* Let new data settle */
899 }
900 clock_h(); udelay(5); clock_l(); udelay(5);
901 }
902 /* look for ack */
903 data_h(); clock_h(); udelay(5);
904 if (read_pin() != 0)
905 goto error; /* No ack seen */
906 clock_l(); udelay(5);
907 /* read back result */
908 for (data = 0, i = 7; i >= 0; i--) {
909 data_h(); clock_h(); udelay(5);
910 data = (data << 1) | !!read_pin();
911 clock_l(); udelay(5);
912 }
913 /* look again for ack */
914 data_h(); clock_h(); udelay(5);
915 if (read_pin() == 0)
916 goto error; /* Spurious ack */
917 clock_l(); udelay(5);
918 send_stop();
919 lanai->eeprom[address] = data;
920 DPRINTK("EEPROM 0x%04X %02X\n",
921 (unsigned int) address, (unsigned int) data);
922 }
923 return 0;
924 error:
925 clock_l(); udelay(5); /* finish read */
926 send_stop();
927 printk(KERN_ERR DEV_LABEL "(itf %d): error reading EEPROM byte %d\n",
928 lanai->number, address);
929 return -EIO;
930 #undef set_config1
931 #undef clock_h
932 #undef clock_l
933 #undef data_h
934 #undef data_l
935 #undef pre_read
936 #undef read_pin
937 #undef send_stop
938 }
939
940 /* read a big-endian 4-byte value out of eeprom */
941 static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address)
942 {
943 return be32_to_cpup((const u32 *) &lanai->eeprom[address]);
944 }
945
946 /* Checksum/validate EEPROM contents */
947 static int eeprom_validate(struct lanai_dev *lanai)
948 {
949 int i, s;
950 u32 v;
951 const u8 *e = lanai->eeprom;
952 #ifdef DEBUG
953 /* First, see if we can get an ASCIIZ string out of the copyright */
954 for (i = EEPROM_COPYRIGHT;
955 i < (EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN); i++)
956 if (e[i] < 0x20 || e[i] > 0x7E)
957 break;
958 if ( i != EEPROM_COPYRIGHT &&
959 i != EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN && e[i] == '\0')
960 DPRINTK("eeprom: copyright = \"%s\"\n",
961 (char *) &e[EEPROM_COPYRIGHT]);
962 else
963 DPRINTK("eeprom: copyright not found\n");
964 #endif
965 /* Validate checksum */
966 for (i = s = 0; i < EEPROM_CHECKSUM; i++)
967 s += e[i];
968 s &= 0xFF;
969 if (s != e[EEPROM_CHECKSUM]) {
970 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM checksum bad "
971 "(wanted 0x%02X, got 0x%02X)\n", lanai->number,
972 (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM]);
973 return -EIO;
974 }
975 s ^= 0xFF;
976 if (s != e[EEPROM_CHECKSUM_REV]) {
977 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM inverse checksum "
978 "bad (wanted 0x%02X, got 0x%02X)\n", lanai->number,
979 (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM_REV]);
980 return -EIO;
981 }
982 /* Verify MAC address */
983 for (i = 0; i < 6; i++)
984 if ((e[EEPROM_MAC + i] ^ e[EEPROM_MAC_REV + i]) != 0xFF) {
985 printk(KERN_ERR DEV_LABEL
986 "(itf %d) : EEPROM MAC addresses don't match "
987 "(0x%02X, inverse 0x%02X)\n", lanai->number,
988 (unsigned int) e[EEPROM_MAC + i],
989 (unsigned int) e[EEPROM_MAC_REV + i]);
990 return -EIO;
991 }
992 DPRINTK("eeprom: MAC address = %pM\n", &e[EEPROM_MAC]);
993 /* Verify serial number */
994 lanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL);
995 v = eeprom_be4(lanai, EEPROM_SERIAL_REV);
996 if ((lanai->serialno ^ v) != 0xFFFFFFFF) {
997 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM serial numbers "
998 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
999 (unsigned int) lanai->serialno, (unsigned int) v);
1000 return -EIO;
1001 }
1002 DPRINTK("eeprom: Serial number = %d\n", (unsigned int) lanai->serialno);
1003 /* Verify magic number */
1004 lanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC);
1005 v = eeprom_be4(lanai, EEPROM_MAGIC_REV);
1006 if ((lanai->magicno ^ v) != 0xFFFFFFFF) {
1007 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM magic numbers "
1008 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
1009 lanai->magicno, v);
1010 return -EIO;
1011 }
1012 DPRINTK("eeprom: Magic number = 0x%08X\n", lanai->magicno);
1013 if (lanai->magicno != EEPROM_MAGIC_VALUE)
1014 printk(KERN_WARNING DEV_LABEL "(itf %d): warning - EEPROM "
1015 "magic not what expected (got 0x%08X, not 0x%08X)\n",
1016 lanai->number, (unsigned int) lanai->magicno,
1017 (unsigned int) EEPROM_MAGIC_VALUE);
1018 return 0;
1019 }
1020
1021 #endif /* READ_EEPROM */
1022
1023 static inline const u8 *eeprom_mac(const struct lanai_dev *lanai)
1024 {
1025 return &lanai->eeprom[EEPROM_MAC];
1026 }
1027
1028 /* -------------------- INTERRUPT HANDLING UTILITIES: */
1029
1030 /* Interrupt types */
1031 #define INT_STATS (0x00000002) /* Statistics counter overflow */
1032 #define INT_SOOL (0x00000004) /* SOOL changed state */
1033 #define INT_LOCD (0x00000008) /* LOCD changed state */
1034 #define INT_LED (0x00000010) /* LED (HAPPI) changed state */
1035 #define INT_GPIN (0x00000020) /* GPIN changed state */
1036 #define INT_PING (0x00000040) /* PING_COUNT fulfilled */
1037 #define INT_WAKE (0x00000080) /* Lanai wants bus */
1038 #define INT_CBR0 (0x00000100) /* CBR sched hit VCI 0 */
1039 #define INT_LOCK (0x00000200) /* Service list overflow */
1040 #define INT_MISMATCH (0x00000400) /* TX magic list mismatch */
1041 #define INT_AAL0_STR (0x00000800) /* Non-AAL5 buffer half filled */
1042 #define INT_AAL0 (0x00001000) /* Non-AAL5 data available */
1043 #define INT_SERVICE (0x00002000) /* Service list entries available */
1044 #define INT_TABORTSENT (0x00004000) /* Target abort sent by lanai */
1045 #define INT_TABORTBM (0x00008000) /* Abort rcv'd as bus master */
1046 #define INT_TIMEOUTBM (0x00010000) /* No response to bus master */
1047 #define INT_PCIPARITY (0x00020000) /* Parity error on PCI */
1048
1049 /* Sets of the above */
1050 #define INT_ALL (0x0003FFFE) /* All interrupts */
1051 #define INT_STATUS (0x0000003C) /* Some status pin changed */
1052 #define INT_DMASHUT (0x00038000) /* DMA engine got shut down */
1053 #define INT_SEGSHUT (0x00000700) /* Segmentation got shut down */
1054
1055 static inline u32 intr_pending(const struct lanai_dev *lanai)
1056 {
1057 return reg_read(lanai, IntStatusMasked_Reg);
1058 }
1059
1060 static inline void intr_enable(const struct lanai_dev *lanai, u32 i)
1061 {
1062 reg_write(lanai, i, IntControlEna_Reg);
1063 }
1064
1065 static inline void intr_disable(const struct lanai_dev *lanai, u32 i)
1066 {
1067 reg_write(lanai, i, IntControlDis_Reg);
1068 }
1069
1070 /* -------------------- CARD/PCI STATUS: */
1071
1072 static void status_message(int itf, const char *name, int status)
1073 {
1074 static const char *onoff[2] = { "off to on", "on to off" };
1075 printk(KERN_INFO DEV_LABEL "(itf %d): %s changed from %s\n",
1076 itf, name, onoff[!status]);
1077 }
1078
1079 static void lanai_check_status(struct lanai_dev *lanai)
1080 {
1081 u32 new = reg_read(lanai, Status_Reg);
1082 u32 changes = new ^ lanai->status;
1083 lanai->status = new;
1084 #define e(flag, name) \
1085 if (changes & flag) \
1086 status_message(lanai->number, name, new & flag)
1087 e(STATUS_SOOL, "SOOL");
1088 e(STATUS_LOCD, "LOCD");
1089 e(STATUS_LED, "LED");
1090 e(STATUS_GPIN, "GPIN");
1091 #undef e
1092 }
1093
1094 static void pcistatus_got(int itf, const char *name)
1095 {
1096 printk(KERN_INFO DEV_LABEL "(itf %d): PCI got %s error\n", itf, name);
1097 }
1098
1099 static void pcistatus_check(struct lanai_dev *lanai, int clearonly)
1100 {
1101 u16 s;
1102 int result;
1103 result = pci_read_config_word(lanai->pci, PCI_STATUS, &s);
1104 if (result != PCIBIOS_SUCCESSFUL) {
1105 printk(KERN_ERR DEV_LABEL "(itf %d): can't read PCI_STATUS: "
1106 "%d\n", lanai->number, result);
1107 return;
1108 }
1109 s &= PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR |
1110 PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT |
1111 PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_PARITY;
1112 if (s == 0)
1113 return;
1114 result = pci_write_config_word(lanai->pci, PCI_STATUS, s);
1115 if (result != PCIBIOS_SUCCESSFUL)
1116 printk(KERN_ERR DEV_LABEL "(itf %d): can't write PCI_STATUS: "
1117 "%d\n", lanai->number, result);
1118 if (clearonly)
1119 return;
1120 #define e(flag, name, stat) \
1121 if (s & flag) { \
1122 pcistatus_got(lanai->number, name); \
1123 ++lanai->stats.pcierr_##stat; \
1124 }
1125 e(PCI_STATUS_DETECTED_PARITY, "parity", parity_detect);
1126 e(PCI_STATUS_SIG_SYSTEM_ERROR, "signalled system", serr_set);
1127 e(PCI_STATUS_REC_MASTER_ABORT, "master", master_abort);
1128 e(PCI_STATUS_REC_TARGET_ABORT, "master target", m_target_abort);
1129 e(PCI_STATUS_SIG_TARGET_ABORT, "slave", s_target_abort);
1130 e(PCI_STATUS_PARITY, "master parity", master_parity);
1131 #undef e
1132 }
1133
1134 /* -------------------- VCC TX BUFFER UTILITIES: */
1135
1136 /* space left in tx buffer in bytes */
1137 static inline int vcc_tx_space(const struct lanai_vcc *lvcc, int endptr)
1138 {
1139 int r;
1140 r = endptr * 16;
1141 r -= ((unsigned long) lvcc->tx.buf.ptr) -
1142 ((unsigned long) lvcc->tx.buf.start);
1143 r -= 16; /* Leave "bubble" - if start==end it looks empty */
1144 if (r < 0)
1145 r += lanai_buf_size(&lvcc->tx.buf);
1146 return r;
1147 }
1148
1149 /* test if VCC is currently backlogged */
1150 static inline int vcc_is_backlogged(const struct lanai_vcc *lvcc)
1151 {
1152 return !skb_queue_empty(&lvcc->tx.backlog);
1153 }
1154
1155 /* Bit fields in the segmentation buffer descriptor */
1156 #define DESCRIPTOR_MAGIC (0xD0000000)
1157 #define DESCRIPTOR_AAL5 (0x00008000)
1158 #define DESCRIPTOR_AAL5_STREAM (0x00004000)
1159 #define DESCRIPTOR_CLP (0x00002000)
1160
1161 /* Add 32-bit descriptor with its padding */
1162 static inline void vcc_tx_add_aal5_descriptor(struct lanai_vcc *lvcc,
1163 u32 flags, int len)
1164 {
1165 int pos;
1166 APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 0,
1167 "vcc_tx_add_aal5_descriptor: bad ptr=%p\n", lvcc->tx.buf.ptr);
1168 lvcc->tx.buf.ptr += 4; /* Hope the values REALLY don't matter */
1169 pos = ((unsigned char *) lvcc->tx.buf.ptr) -
1170 (unsigned char *) lvcc->tx.buf.start;
1171 APRINTK((pos & ~0x0001FFF0) == 0,
1172 "vcc_tx_add_aal5_descriptor: bad pos (%d) before, vci=%d, "
1173 "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci,
1174 lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);
1175 pos = (pos + len) & (lanai_buf_size(&lvcc->tx.buf) - 1);
1176 APRINTK((pos & ~0x0001FFF0) == 0,
1177 "vcc_tx_add_aal5_descriptor: bad pos (%d) after, vci=%d, "
1178 "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci,
1179 lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);
1180 lvcc->tx.buf.ptr[-1] =
1181 cpu_to_le32(DESCRIPTOR_MAGIC | DESCRIPTOR_AAL5 |
1182 ((lvcc->tx.atmvcc->atm_options & ATM_ATMOPT_CLP) ?
1183 DESCRIPTOR_CLP : 0) | flags | pos >> 4);
1184 if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)
1185 lvcc->tx.buf.ptr = lvcc->tx.buf.start;
1186 }
1187
1188 /* Add 32-bit AAL5 trailer and leave room for its CRC */
1189 static inline void vcc_tx_add_aal5_trailer(struct lanai_vcc *lvcc,
1190 int len, int cpi, int uu)
1191 {
1192 APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 8,
1193 "vcc_tx_add_aal5_trailer: bad ptr=%p\n", lvcc->tx.buf.ptr);
1194 lvcc->tx.buf.ptr += 2;
1195 lvcc->tx.buf.ptr[-2] = cpu_to_be32((uu << 24) | (cpi << 16) | len);
1196 if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)
1197 lvcc->tx.buf.ptr = lvcc->tx.buf.start;
1198 }
1199
1200 static inline void vcc_tx_memcpy(struct lanai_vcc *lvcc,
1201 const unsigned char *src, int n)
1202 {
1203 unsigned char *e;
1204 int m;
1205 e = ((unsigned char *) lvcc->tx.buf.ptr) + n;
1206 m = e - (unsigned char *) lvcc->tx.buf.end;
1207 if (m < 0)
1208 m = 0;
1209 memcpy(lvcc->tx.buf.ptr, src, n - m);
1210 if (m != 0) {
1211 memcpy(lvcc->tx.buf.start, src + n - m, m);
1212 e = ((unsigned char *) lvcc->tx.buf.start) + m;
1213 }
1214 lvcc->tx.buf.ptr = (u32 *) e;
1215 }
1216
1217 static inline void vcc_tx_memzero(struct lanai_vcc *lvcc, int n)
1218 {
1219 unsigned char *e;
1220 int m;
1221 if (n == 0)
1222 return;
1223 e = ((unsigned char *) lvcc->tx.buf.ptr) + n;
1224 m = e - (unsigned char *) lvcc->tx.buf.end;
1225 if (m < 0)
1226 m = 0;
1227 memset(lvcc->tx.buf.ptr, 0, n - m);
1228 if (m != 0) {
1229 memset(lvcc->tx.buf.start, 0, m);
1230 e = ((unsigned char *) lvcc->tx.buf.start) + m;
1231 }
1232 lvcc->tx.buf.ptr = (u32 *) e;
1233 }
1234
1235 /* Update "butt" register to specify new WritePtr */
1236 static inline void lanai_endtx(struct lanai_dev *lanai,
1237 const struct lanai_vcc *lvcc)
1238 {
1239 int i, ptr = ((unsigned char *) lvcc->tx.buf.ptr) -
1240 (unsigned char *) lvcc->tx.buf.start;
1241 APRINTK((ptr & ~0x0001FFF0) == 0,
1242 "lanai_endtx: bad ptr (%d), vci=%d, start,ptr,end=%p,%p,%p\n",
1243 ptr, lvcc->vci, lvcc->tx.buf.start, lvcc->tx.buf.ptr,
1244 lvcc->tx.buf.end);
1245
1246 /*
1247 * Since the "butt register" is a shared resounce on the card we
1248 * serialize all accesses to it through this spinlock. This is
1249 * mostly just paranoia since the register is rarely "busy" anyway
1250 * but is needed for correctness.
1251 */
1252 spin_lock(&lanai->endtxlock);
1253 /*
1254 * We need to check if the "butt busy" bit is set before
1255 * updating the butt register. In theory this should
1256 * never happen because the ATM card is plenty fast at
1257 * updating the register. Still, we should make sure
1258 */
1259 for (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) {
1260 if (unlikely(i > 50)) {
1261 printk(KERN_ERR DEV_LABEL "(itf %d): butt register "
1262 "always busy!\n", lanai->number);
1263 break;
1264 }
1265 udelay(5);
1266 }
1267 /*
1268 * Before we tall the card to start work we need to be sure 100% of
1269 * the info in the service buffer has been written before we tell
1270 * the card about it
1271 */
1272 wmb();
1273 reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg);
1274 spin_unlock(&lanai->endtxlock);
1275 }
1276
1277 /*
1278 * Add one AAL5 PDU to lvcc's transmit buffer. Caller garauntees there's
1279 * space available. "pdusize" is the number of bytes the PDU will take
1280 */
1281 static void lanai_send_one_aal5(struct lanai_dev *lanai,
1282 struct lanai_vcc *lvcc, struct sk_buff *skb, int pdusize)
1283 {
1284 int pad;
1285 APRINTK(pdusize == aal5_size(skb->len),
1286 "lanai_send_one_aal5: wrong size packet (%d != %d)\n",
1287 pdusize, aal5_size(skb->len));
1288 vcc_tx_add_aal5_descriptor(lvcc, 0, pdusize);
1289 pad = pdusize - skb->len - 8;
1290 APRINTK(pad >= 0, "pad is negative (%d)\n", pad);
1291 APRINTK(pad < 48, "pad is too big (%d)\n", pad);
1292 vcc_tx_memcpy(lvcc, skb->data, skb->len);
1293 vcc_tx_memzero(lvcc, pad);
1294 vcc_tx_add_aal5_trailer(lvcc, skb->len, 0, 0);
1295 lanai_endtx(lanai, lvcc);
1296 lanai_free_skb(lvcc->tx.atmvcc, skb);
1297 atomic_inc(&lvcc->tx.atmvcc->stats->tx);
1298 }
1299
1300 /* Try to fill the buffer - don't call unless there is backlog */
1301 static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai,
1302 struct lanai_vcc *lvcc, int endptr)
1303 {
1304 int n;
1305 struct sk_buff *skb;
1306 int space = vcc_tx_space(lvcc, endptr);
1307 APRINTK(vcc_is_backlogged(lvcc),
1308 "vcc_tx_unqueue() called with empty backlog (vci=%d)\n",
1309 lvcc->vci);
1310 while (space >= 64) {
1311 skb = skb_dequeue(&lvcc->tx.backlog);
1312 if (skb == NULL)
1313 goto no_backlog;
1314 n = aal5_size(skb->len);
1315 if (n + 16 > space) {
1316 /* No room for this packet - put it back on queue */
1317 skb_queue_head(&lvcc->tx.backlog, skb);
1318 return;
1319 }
1320 lanai_send_one_aal5(lanai, lvcc, skb, n);
1321 space -= n + 16;
1322 }
1323 if (!vcc_is_backlogged(lvcc)) {
1324 no_backlog:
1325 __clear_bit(lvcc->vci, lanai->backlog_vccs);
1326 }
1327 }
1328
1329 /* Given an skb that we want to transmit either send it now or queue */
1330 static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1331 struct sk_buff *skb)
1332 {
1333 int space, n;
1334 if (vcc_is_backlogged(lvcc)) /* Already backlogged */
1335 goto queue_it;
1336 space = vcc_tx_space(lvcc,
1337 TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)));
1338 n = aal5_size(skb->len);
1339 APRINTK(n + 16 >= 64, "vcc_tx_aal5: n too small (%d)\n", n);
1340 if (space < n + 16) { /* No space for this PDU */
1341 __set_bit(lvcc->vci, lanai->backlog_vccs);
1342 queue_it:
1343 skb_queue_tail(&lvcc->tx.backlog, skb);
1344 return;
1345 }
1346 lanai_send_one_aal5(lanai, lvcc, skb, n);
1347 }
1348
1349 static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai,
1350 struct lanai_vcc *lvcc, int endptr)
1351 {
1352 printk(KERN_INFO DEV_LABEL
1353 ": vcc_tx_unqueue_aal0: not implemented\n");
1354 }
1355
1356 static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1357 struct sk_buff *skb)
1358 {
1359 printk(KERN_INFO DEV_LABEL ": vcc_tx_aal0: not implemented\n");
1360 /* Remember to increment lvcc->tx.atmvcc->stats->tx */
1361 lanai_free_skb(lvcc->tx.atmvcc, skb);
1362 }
1363
1364 /* -------------------- VCC RX BUFFER UTILITIES: */
1365
1366 /* unlike the _tx_ cousins, this doesn't update ptr */
1367 static inline void vcc_rx_memcpy(unsigned char *dest,
1368 const struct lanai_vcc *lvcc, int n)
1369 {
1370 int m = ((const unsigned char *) lvcc->rx.buf.ptr) + n -
1371 ((const unsigned char *) (lvcc->rx.buf.end));
1372 if (m < 0)
1373 m = 0;
1374 memcpy(dest, lvcc->rx.buf.ptr, n - m);
1375 memcpy(dest + n - m, lvcc->rx.buf.start, m);
1376 /* Make sure that these copies don't get reordered */
1377 barrier();
1378 }
1379
1380 /* Receive AAL5 data on a VCC with a particular endptr */
1381 static void vcc_rx_aal5(struct lanai_vcc *lvcc, int endptr)
1382 {
1383 int size;
1384 struct sk_buff *skb;
1385 const u32 *x;
1386 u32 *end = &lvcc->rx.buf.start[endptr * 4];
1387 int n = ((unsigned long) end) - ((unsigned long) lvcc->rx.buf.ptr);
1388 if (n < 0)
1389 n += lanai_buf_size(&lvcc->rx.buf);
1390 APRINTK(n >= 0 && n < lanai_buf_size(&lvcc->rx.buf) && !(n & 15),
1391 "vcc_rx_aal5: n out of range (%d/%Zu)\n",
1392 n, lanai_buf_size(&lvcc->rx.buf));
1393 /* Recover the second-to-last word to get true pdu length */
1394 if ((x = &end[-2]) < lvcc->rx.buf.start)
1395 x = &lvcc->rx.buf.end[-2];
1396 /*
1397 * Before we actually read from the buffer, make sure the memory
1398 * changes have arrived
1399 */
1400 rmb();
1401 size = be32_to_cpup(x) & 0xffff;
1402 if (unlikely(n != aal5_size(size))) {
1403 /* Make sure size matches padding */
1404 printk(KERN_INFO DEV_LABEL "(itf %d): Got bad AAL5 length "
1405 "on vci=%d - size=%d n=%d\n",
1406 lvcc->rx.atmvcc->dev->number, lvcc->vci, size, n);
1407 lvcc->stats.x.aal5.rx_badlen++;
1408 goto out;
1409 }
1410 skb = atm_alloc_charge(lvcc->rx.atmvcc, size, GFP_ATOMIC);
1411 if (unlikely(skb == NULL)) {
1412 lvcc->stats.rx_nomem++;
1413 goto out;
1414 }
1415 skb_put(skb, size);
1416 vcc_rx_memcpy(skb->data, lvcc, size);
1417 ATM_SKB(skb)->vcc = lvcc->rx.atmvcc;
1418 __net_timestamp(skb);
1419 lvcc->rx.atmvcc->push(lvcc->rx.atmvcc, skb);
1420 atomic_inc(&lvcc->rx.atmvcc->stats->rx);
1421 out:
1422 lvcc->rx.buf.ptr = end;
1423 cardvcc_write(lvcc, endptr, vcc_rxreadptr);
1424 }
1425
1426 static void vcc_rx_aal0(struct lanai_dev *lanai)
1427 {
1428 printk(KERN_INFO DEV_LABEL ": vcc_rx_aal0: not implemented\n");
1429 /* Remember to get read_lock(&vcc_sklist_lock) while looking up VC */
1430 /* Remember to increment lvcc->rx.atmvcc->stats->rx */
1431 }
1432
1433 /* -------------------- MANAGING HOST-BASED VCC TABLE: */
1434
1435 /* Decide whether to use vmalloc or get_zeroed_page for VCC table */
1436 #if (NUM_VCI * BITS_PER_LONG) <= PAGE_SIZE
1437 #define VCCTABLE_GETFREEPAGE
1438 #else
1439 #include <linux/vmalloc.h>
1440 #endif
1441
1442 static int vcc_table_allocate(struct lanai_dev *lanai)
1443 {
1444 #ifdef VCCTABLE_GETFREEPAGE
1445 APRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE,
1446 "vcc table > PAGE_SIZE!");
1447 lanai->vccs = (struct lanai_vcc **) get_zeroed_page(GFP_KERNEL);
1448 return (lanai->vccs == NULL) ? -ENOMEM : 0;
1449 #else
1450 int bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *);
1451 lanai->vccs = vzalloc(bytes);
1452 if (unlikely(lanai->vccs == NULL))
1453 return -ENOMEM;
1454 return 0;
1455 #endif
1456 }
1457
1458 static inline void vcc_table_deallocate(const struct lanai_dev *lanai)
1459 {
1460 #ifdef VCCTABLE_GETFREEPAGE
1461 free_page((unsigned long) lanai->vccs);
1462 #else
1463 vfree(lanai->vccs);
1464 #endif
1465 }
1466
1467 /* Allocate a fresh lanai_vcc, with the appropriate things cleared */
1468 static inline struct lanai_vcc *new_lanai_vcc(void)
1469 {
1470 struct lanai_vcc *lvcc;
1471 lvcc = kzalloc(sizeof(*lvcc), GFP_KERNEL);
1472 if (likely(lvcc != NULL)) {
1473 skb_queue_head_init(&lvcc->tx.backlog);
1474 #ifdef DEBUG
1475 lvcc->vci = -1;
1476 #endif
1477 }
1478 return lvcc;
1479 }
1480
1481 static int lanai_get_sized_buffer(struct lanai_dev *lanai,
1482 struct lanai_buffer *buf, int max_sdu, int multiplier,
1483 const char *name)
1484 {
1485 int size;
1486 if (unlikely(max_sdu < 1))
1487 max_sdu = 1;
1488 max_sdu = aal5_size(max_sdu);
1489 size = (max_sdu + 16) * multiplier + 16;
1490 lanai_buf_allocate(buf, size, max_sdu + 32, lanai->pci);
1491 if (unlikely(buf->start == NULL))
1492 return -ENOMEM;
1493 if (unlikely(lanai_buf_size(buf) < size))
1494 printk(KERN_WARNING DEV_LABEL "(itf %d): wanted %d bytes "
1495 "for %s buffer, got only %Zu\n", lanai->number, size,
1496 name, lanai_buf_size(buf));
1497 DPRINTK("Allocated %Zu byte %s buffer\n", lanai_buf_size(buf), name);
1498 return 0;
1499 }
1500
1501 /* Setup a RX buffer for a currently unbound AAL5 vci */
1502 static inline int lanai_setup_rx_vci_aal5(struct lanai_dev *lanai,
1503 struct lanai_vcc *lvcc, const struct atm_qos *qos)
1504 {
1505 return lanai_get_sized_buffer(lanai, &lvcc->rx.buf,
1506 qos->rxtp.max_sdu, AAL5_RX_MULTIPLIER, "RX");
1507 }
1508
1509 /* Setup a TX buffer for a currently unbound AAL5 vci */
1510 static int lanai_setup_tx_vci(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1511 const struct atm_qos *qos)
1512 {
1513 int max_sdu, multiplier;
1514 if (qos->aal == ATM_AAL0) {
1515 lvcc->tx.unqueue = vcc_tx_unqueue_aal0;
1516 max_sdu = ATM_CELL_SIZE - 1;
1517 multiplier = AAL0_TX_MULTIPLIER;
1518 } else {
1519 lvcc->tx.unqueue = vcc_tx_unqueue_aal5;
1520 max_sdu = qos->txtp.max_sdu;
1521 multiplier = AAL5_TX_MULTIPLIER;
1522 }
1523 return lanai_get_sized_buffer(lanai, &lvcc->tx.buf, max_sdu,
1524 multiplier, "TX");
1525 }
1526
1527 static inline void host_vcc_bind(struct lanai_dev *lanai,
1528 struct lanai_vcc *lvcc, vci_t vci)
1529 {
1530 if (lvcc->vbase != NULL)
1531 return; /* We already were bound in the other direction */
1532 DPRINTK("Binding vci %d\n", vci);
1533 #ifdef USE_POWERDOWN
1534 if (lanai->nbound++ == 0) {
1535 DPRINTK("Coming out of powerdown\n");
1536 lanai->conf1 &= ~CONFIG1_POWERDOWN;
1537 conf1_write(lanai);
1538 conf2_write(lanai);
1539 }
1540 #endif
1541 lvcc->vbase = cardvcc_addr(lanai, vci);
1542 lanai->vccs[lvcc->vci = vci] = lvcc;
1543 }
1544
1545 static inline void host_vcc_unbind(struct lanai_dev *lanai,
1546 struct lanai_vcc *lvcc)
1547 {
1548 if (lvcc->vbase == NULL)
1549 return; /* This vcc was never bound */
1550 DPRINTK("Unbinding vci %d\n", lvcc->vci);
1551 lvcc->vbase = NULL;
1552 lanai->vccs[lvcc->vci] = NULL;
1553 #ifdef USE_POWERDOWN
1554 if (--lanai->nbound == 0) {
1555 DPRINTK("Going into powerdown\n");
1556 lanai->conf1 |= CONFIG1_POWERDOWN;
1557 conf1_write(lanai);
1558 }
1559 #endif
1560 }
1561
1562 /* -------------------- RESET CARD: */
1563
1564 static void lanai_reset(struct lanai_dev *lanai)
1565 {
1566 printk(KERN_CRIT DEV_LABEL "(itf %d): *NOT* resetting - not "
1567 "implemented\n", lanai->number);
1568 /* TODO */
1569 /* The following is just a hack until we write the real
1570 * resetter - at least ack whatever interrupt sent us
1571 * here
1572 */
1573 reg_write(lanai, INT_ALL, IntAck_Reg);
1574 lanai->stats.card_reset++;
1575 }
1576
1577 /* -------------------- SERVICE LIST UTILITIES: */
1578
1579 /*
1580 * Allocate service buffer and tell card about it
1581 */
1582 static int service_buffer_allocate(struct lanai_dev *lanai)
1583 {
1584 lanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 8,
1585 lanai->pci);
1586 if (unlikely(lanai->service.start == NULL))
1587 return -ENOMEM;
1588 DPRINTK("allocated service buffer at 0x%08lX, size %Zu(%d)\n",
1589 (unsigned long) lanai->service.start,
1590 lanai_buf_size(&lanai->service),
1591 lanai_buf_size_cardorder(&lanai->service));
1592 /* Clear ServWrite register to be safe */
1593 reg_write(lanai, 0, ServWrite_Reg);
1594 /* ServiceStuff register contains size and address of buffer */
1595 reg_write(lanai,
1596 SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) |
1597 SSTUFF_SET_ADDR(lanai->service.dmaaddr),
1598 ServiceStuff_Reg);
1599 return 0;
1600 }
1601
1602 static inline void service_buffer_deallocate(struct lanai_dev *lanai)
1603 {
1604 lanai_buf_deallocate(&lanai->service, lanai->pci);
1605 }
1606
1607 /* Bitfields in service list */
1608 #define SERVICE_TX (0x80000000) /* Was from transmission */
1609 #define SERVICE_TRASH (0x40000000) /* RXed PDU was trashed */
1610 #define SERVICE_CRCERR (0x20000000) /* RXed PDU had CRC error */
1611 #define SERVICE_CI (0x10000000) /* RXed PDU had CI set */
1612 #define SERVICE_CLP (0x08000000) /* RXed PDU had CLP set */
1613 #define SERVICE_STREAM (0x04000000) /* RX Stream mode */
1614 #define SERVICE_GET_VCI(x) (((x)>>16)&0x3FF)
1615 #define SERVICE_GET_END(x) ((x)&0x1FFF)
1616
1617 /* Handle one thing from the service list - returns true if it marked a
1618 * VCC ready for xmit
1619 */
1620 static int handle_service(struct lanai_dev *lanai, u32 s)
1621 {
1622 vci_t vci = SERVICE_GET_VCI(s);
1623 struct lanai_vcc *lvcc;
1624 read_lock(&vcc_sklist_lock);
1625 lvcc = lanai->vccs[vci];
1626 if (unlikely(lvcc == NULL)) {
1627 read_unlock(&vcc_sklist_lock);
1628 DPRINTK("(itf %d) got service entry 0x%X for nonexistent "
1629 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1630 if (s & SERVICE_TX)
1631 lanai->stats.service_notx++;
1632 else
1633 lanai->stats.service_norx++;
1634 return 0;
1635 }
1636 if (s & SERVICE_TX) { /* segmentation interrupt */
1637 if (unlikely(lvcc->tx.atmvcc == NULL)) {
1638 read_unlock(&vcc_sklist_lock);
1639 DPRINTK("(itf %d) got service entry 0x%X for non-TX "
1640 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1641 lanai->stats.service_notx++;
1642 return 0;
1643 }
1644 __set_bit(vci, lanai->transmit_ready);
1645 lvcc->tx.endptr = SERVICE_GET_END(s);
1646 read_unlock(&vcc_sklist_lock);
1647 return 1;
1648 }
1649 if (unlikely(lvcc->rx.atmvcc == NULL)) {
1650 read_unlock(&vcc_sklist_lock);
1651 DPRINTK("(itf %d) got service entry 0x%X for non-RX "
1652 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1653 lanai->stats.service_norx++;
1654 return 0;
1655 }
1656 if (unlikely(lvcc->rx.atmvcc->qos.aal != ATM_AAL5)) {
1657 read_unlock(&vcc_sklist_lock);
1658 DPRINTK("(itf %d) got RX service entry 0x%X for non-AAL5 "
1659 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1660 lanai->stats.service_rxnotaal5++;
1661 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1662 return 0;
1663 }
1664 if (likely(!(s & (SERVICE_TRASH | SERVICE_STREAM | SERVICE_CRCERR)))) {
1665 vcc_rx_aal5(lvcc, SERVICE_GET_END(s));
1666 read_unlock(&vcc_sklist_lock);
1667 return 0;
1668 }
1669 if (s & SERVICE_TRASH) {
1670 int bytes;
1671 read_unlock(&vcc_sklist_lock);
1672 DPRINTK("got trashed rx pdu on vci %d\n", vci);
1673 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1674 lvcc->stats.x.aal5.service_trash++;
1675 bytes = (SERVICE_GET_END(s) * 16) -
1676 (((unsigned long) lvcc->rx.buf.ptr) -
1677 ((unsigned long) lvcc->rx.buf.start)) + 47;
1678 if (bytes < 0)
1679 bytes += lanai_buf_size(&lvcc->rx.buf);
1680 lanai->stats.ovfl_trash += (bytes / 48);
1681 return 0;
1682 }
1683 if (s & SERVICE_STREAM) {
1684 read_unlock(&vcc_sklist_lock);
1685 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1686 lvcc->stats.x.aal5.service_stream++;
1687 printk(KERN_ERR DEV_LABEL "(itf %d): Got AAL5 stream "
1688 "PDU on VCI %d!\n", lanai->number, vci);
1689 lanai_reset(lanai);
1690 return 0;
1691 }
1692 DPRINTK("got rx crc error on vci %d\n", vci);
1693 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1694 lvcc->stats.x.aal5.service_rxcrc++;
1695 lvcc->rx.buf.ptr = &lvcc->rx.buf.start[SERVICE_GET_END(s) * 4];
1696 cardvcc_write(lvcc, SERVICE_GET_END(s), vcc_rxreadptr);
1697 read_unlock(&vcc_sklist_lock);
1698 return 0;
1699 }
1700
1701 /* Try transmitting on all VCIs that we marked ready to serve */
1702 static void iter_transmit(struct lanai_dev *lanai, vci_t vci)
1703 {
1704 struct lanai_vcc *lvcc = lanai->vccs[vci];
1705 if (vcc_is_backlogged(lvcc))
1706 lvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr);
1707 }
1708
1709 /* Run service queue -- called from interrupt context or with
1710 * interrupts otherwise disabled and with the lanai->servicelock
1711 * lock held
1712 */
1713 static void run_service(struct lanai_dev *lanai)
1714 {
1715 int ntx = 0;
1716 u32 wreg = reg_read(lanai, ServWrite_Reg);
1717 const u32 *end = lanai->service.start + wreg;
1718 while (lanai->service.ptr != end) {
1719 ntx += handle_service(lanai,
1720 le32_to_cpup(lanai->service.ptr++));
1721 if (lanai->service.ptr >= lanai->service.end)
1722 lanai->service.ptr = lanai->service.start;
1723 }
1724 reg_write(lanai, wreg, ServRead_Reg);
1725 if (ntx != 0) {
1726 read_lock(&vcc_sklist_lock);
1727 vci_bitfield_iterate(lanai, lanai->transmit_ready,
1728 iter_transmit);
1729 bitmap_zero(lanai->transmit_ready, NUM_VCI);
1730 read_unlock(&vcc_sklist_lock);
1731 }
1732 }
1733
1734 /* -------------------- GATHER STATISTICS: */
1735
1736 static void get_statistics(struct lanai_dev *lanai)
1737 {
1738 u32 statreg = reg_read(lanai, Statistics_Reg);
1739 lanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg);
1740 lanai->stats.hec_err += STATS_GET_HEC_ERR(statreg);
1741 lanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg);
1742 lanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg);
1743 }
1744
1745 /* -------------------- POLLING TIMER: */
1746
1747 #ifndef DEBUG_RW
1748 /* Try to undequeue 1 backlogged vcc */
1749 static void iter_dequeue(struct lanai_dev *lanai, vci_t vci)
1750 {
1751 struct lanai_vcc *lvcc = lanai->vccs[vci];
1752 int endptr;
1753 if (lvcc == NULL || lvcc->tx.atmvcc == NULL ||
1754 !vcc_is_backlogged(lvcc)) {
1755 __clear_bit(vci, lanai->backlog_vccs);
1756 return;
1757 }
1758 endptr = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
1759 lvcc->tx.unqueue(lanai, lvcc, endptr);
1760 }
1761 #endif /* !DEBUG_RW */
1762
1763 static void lanai_timed_poll(unsigned long arg)
1764 {
1765 struct lanai_dev *lanai = (struct lanai_dev *) arg;
1766 #ifndef DEBUG_RW
1767 unsigned long flags;
1768 #ifdef USE_POWERDOWN
1769 if (lanai->conf1 & CONFIG1_POWERDOWN)
1770 return;
1771 #endif /* USE_POWERDOWN */
1772 local_irq_save(flags);
1773 /* If we can grab the spinlock, check if any services need to be run */
1774 if (spin_trylock(&lanai->servicelock)) {
1775 run_service(lanai);
1776 spin_unlock(&lanai->servicelock);
1777 }
1778 /* ...and see if any backlogged VCs can make progress */
1779 /* unfortunately linux has no read_trylock() currently */
1780 read_lock(&vcc_sklist_lock);
1781 vci_bitfield_iterate(lanai, lanai->backlog_vccs, iter_dequeue);
1782 read_unlock(&vcc_sklist_lock);
1783 local_irq_restore(flags);
1784
1785 get_statistics(lanai);
1786 #endif /* !DEBUG_RW */
1787 mod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD);
1788 }
1789
1790 static inline void lanai_timed_poll_start(struct lanai_dev *lanai)
1791 {
1792 init_timer(&lanai->timer);
1793 lanai->timer.expires = jiffies + LANAI_POLL_PERIOD;
1794 lanai->timer.data = (unsigned long) lanai;
1795 lanai->timer.function = lanai_timed_poll;
1796 add_timer(&lanai->timer);
1797 }
1798
1799 static inline void lanai_timed_poll_stop(struct lanai_dev *lanai)
1800 {
1801 del_timer_sync(&lanai->timer);
1802 }
1803
1804 /* -------------------- INTERRUPT SERVICE: */
1805
1806 static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason)
1807 {
1808 u32 ack = 0;
1809 if (reason & INT_SERVICE) {
1810 ack = INT_SERVICE;
1811 spin_lock(&lanai->servicelock);
1812 run_service(lanai);
1813 spin_unlock(&lanai->servicelock);
1814 }
1815 if (reason & (INT_AAL0_STR | INT_AAL0)) {
1816 ack |= reason & (INT_AAL0_STR | INT_AAL0);
1817 vcc_rx_aal0(lanai);
1818 }
1819 /* The rest of the interrupts are pretty rare */
1820 if (ack == reason)
1821 goto done;
1822 if (reason & INT_STATS) {
1823 reason &= ~INT_STATS; /* No need to ack */
1824 get_statistics(lanai);
1825 }
1826 if (reason & INT_STATUS) {
1827 ack |= reason & INT_STATUS;
1828 lanai_check_status(lanai);
1829 }
1830 if (unlikely(reason & INT_DMASHUT)) {
1831 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - DMA "
1832 "shutdown, reason=0x%08X, address=0x%08X\n",
1833 lanai->number, (unsigned int) (reason & INT_DMASHUT),
1834 (unsigned int) reg_read(lanai, DMA_Addr_Reg));
1835 if (reason & INT_TABORTBM) {
1836 lanai_reset(lanai);
1837 return;
1838 }
1839 ack |= (reason & INT_DMASHUT);
1840 printk(KERN_ERR DEV_LABEL "(itf %d): re-enabling DMA\n",
1841 lanai->number);
1842 conf1_write(lanai);
1843 lanai->stats.dma_reenable++;
1844 pcistatus_check(lanai, 0);
1845 }
1846 if (unlikely(reason & INT_TABORTSENT)) {
1847 ack |= (reason & INT_TABORTSENT);
1848 printk(KERN_ERR DEV_LABEL "(itf %d): sent PCI target abort\n",
1849 lanai->number);
1850 pcistatus_check(lanai, 0);
1851 }
1852 if (unlikely(reason & INT_SEGSHUT)) {
1853 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - "
1854 "segmentation shutdown, reason=0x%08X\n", lanai->number,
1855 (unsigned int) (reason & INT_SEGSHUT));
1856 lanai_reset(lanai);
1857 return;
1858 }
1859 if (unlikely(reason & (INT_PING | INT_WAKE))) {
1860 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - "
1861 "unexpected interrupt 0x%08X, resetting\n",
1862 lanai->number,
1863 (unsigned int) (reason & (INT_PING | INT_WAKE)));
1864 lanai_reset(lanai);
1865 return;
1866 }
1867 #ifdef DEBUG
1868 if (unlikely(ack != reason)) {
1869 DPRINTK("unacked ints: 0x%08X\n",
1870 (unsigned int) (reason & ~ack));
1871 ack = reason;
1872 }
1873 #endif
1874 done:
1875 if (ack != 0)
1876 reg_write(lanai, ack, IntAck_Reg);
1877 }
1878
1879 static irqreturn_t lanai_int(int irq, void *devid)
1880 {
1881 struct lanai_dev *lanai = devid;
1882 u32 reason;
1883
1884 #ifdef USE_POWERDOWN
1885 /*
1886 * If we're powered down we shouldn't be generating any interrupts -
1887 * so assume that this is a shared interrupt line and it's for someone
1888 * else
1889 */
1890 if (unlikely(lanai->conf1 & CONFIG1_POWERDOWN))
1891 return IRQ_NONE;
1892 #endif
1893
1894 reason = intr_pending(lanai);
1895 if (reason == 0)
1896 return IRQ_NONE; /* Must be for someone else */
1897
1898 do {
1899 if (unlikely(reason == 0xFFFFFFFF))
1900 break; /* Maybe we've been unplugged? */
1901 lanai_int_1(lanai, reason);
1902 reason = intr_pending(lanai);
1903 } while (reason != 0);
1904
1905 return IRQ_HANDLED;
1906 }
1907
1908 /* TODO - it would be nice if we could use the "delayed interrupt" system
1909 * to some advantage
1910 */
1911
1912 /* -------------------- CHECK BOARD ID/REV: */
1913
1914 /*
1915 * The board id and revision are stored both in the reset register and
1916 * in the PCI configuration space - the documentation says to check
1917 * each of them. If revp!=NULL we store the revision there
1918 */
1919 static int check_board_id_and_rev(const char *name, u32 val, int *revp)
1920 {
1921 DPRINTK("%s says board_id=%d, board_rev=%d\n", name,
1922 (int) RESET_GET_BOARD_ID(val),
1923 (int) RESET_GET_BOARD_REV(val));
1924 if (RESET_GET_BOARD_ID(val) != BOARD_ID_LANAI256) {
1925 printk(KERN_ERR DEV_LABEL ": Found %s board-id %d -- not a "
1926 "Lanai 25.6\n", name, (int) RESET_GET_BOARD_ID(val));
1927 return -ENODEV;
1928 }
1929 if (revp != NULL)
1930 *revp = RESET_GET_BOARD_REV(val);
1931 return 0;
1932 }
1933
1934 /* -------------------- PCI INITIALIZATION/SHUTDOWN: */
1935
1936 static int lanai_pci_start(struct lanai_dev *lanai)
1937 {
1938 struct pci_dev *pci = lanai->pci;
1939 int result;
1940
1941 if (pci_enable_device(pci) != 0) {
1942 printk(KERN_ERR DEV_LABEL "(itf %d): can't enable "
1943 "PCI device", lanai->number);
1944 return -ENXIO;
1945 }
1946 pci_set_master(pci);
1947 if (pci_set_dma_mask(pci, DMA_BIT_MASK(32)) != 0) {
1948 printk(KERN_WARNING DEV_LABEL
1949 "(itf %d): No suitable DMA available.\n", lanai->number);
1950 return -EBUSY;
1951 }
1952 if (pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)) != 0) {
1953 printk(KERN_WARNING DEV_LABEL
1954 "(itf %d): No suitable DMA available.\n", lanai->number);
1955 return -EBUSY;
1956 }
1957 result = check_board_id_and_rev("PCI", pci->subsystem_device, NULL);
1958 if (result != 0)
1959 return result;
1960 /* Set latency timer to zero as per lanai docs */
1961 result = pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0);
1962 if (result != PCIBIOS_SUCCESSFUL) {
1963 printk(KERN_ERR DEV_LABEL "(itf %d): can't write "
1964 "PCI_LATENCY_TIMER: %d\n", lanai->number, result);
1965 return -EINVAL;
1966 }
1967 pcistatus_check(lanai, 1);
1968 pcistatus_check(lanai, 0);
1969 return 0;
1970 }
1971
1972 /* -------------------- VPI/VCI ALLOCATION: */
1973
1974 /*
1975 * We _can_ use VCI==0 for normal traffic, but only for UBR (or we'll
1976 * get a CBRZERO interrupt), and we can use it only if no one is receiving
1977 * AAL0 traffic (since they will use the same queue) - according to the
1978 * docs we shouldn't even use it for AAL0 traffic
1979 */
1980 static inline int vci0_is_ok(struct lanai_dev *lanai,
1981 const struct atm_qos *qos)
1982 {
1983 if (qos->txtp.traffic_class == ATM_CBR || qos->aal == ATM_AAL0)
1984 return 0;
1985 if (qos->rxtp.traffic_class != ATM_NONE) {
1986 if (lanai->naal0 != 0)
1987 return 0;
1988 lanai->conf2 |= CONFIG2_VCI0_NORMAL;
1989 conf2_write_if_powerup(lanai);
1990 }
1991 return 1;
1992 }
1993
1994 /* return true if vci is currently unused, or if requested qos is
1995 * compatible
1996 */
1997 static int vci_is_ok(struct lanai_dev *lanai, vci_t vci,
1998 const struct atm_vcc *atmvcc)
1999 {
2000 const struct atm_qos *qos = &atmvcc->qos;
2001 const struct lanai_vcc *lvcc = lanai->vccs[vci];
2002 if (vci == 0 && !vci0_is_ok(lanai, qos))
2003 return 0;
2004 if (unlikely(lvcc != NULL)) {
2005 if (qos->rxtp.traffic_class != ATM_NONE &&
2006 lvcc->rx.atmvcc != NULL && lvcc->rx.atmvcc != atmvcc)
2007 return 0;
2008 if (qos->txtp.traffic_class != ATM_NONE &&
2009 lvcc->tx.atmvcc != NULL && lvcc->tx.atmvcc != atmvcc)
2010 return 0;
2011 if (qos->txtp.traffic_class == ATM_CBR &&
2012 lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc)
2013 return 0;
2014 }
2015 if (qos->aal == ATM_AAL0 && lanai->naal0 == 0 &&
2016 qos->rxtp.traffic_class != ATM_NONE) {
2017 const struct lanai_vcc *vci0 = lanai->vccs[0];
2018 if (vci0 != NULL && vci0->rx.atmvcc != NULL)
2019 return 0;
2020 lanai->conf2 &= ~CONFIG2_VCI0_NORMAL;
2021 conf2_write_if_powerup(lanai);
2022 }
2023 return 1;
2024 }
2025
2026 static int lanai_normalize_ci(struct lanai_dev *lanai,
2027 const struct atm_vcc *atmvcc, short *vpip, vci_t *vcip)
2028 {
2029 switch (*vpip) {
2030 case ATM_VPI_ANY:
2031 *vpip = 0;
2032 /* FALLTHROUGH */
2033 case 0:
2034 break;
2035 default:
2036 return -EADDRINUSE;
2037 }
2038 switch (*vcip) {
2039 case ATM_VCI_ANY:
2040 for (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci;
2041 (*vcip)++)
2042 if (vci_is_ok(lanai, *vcip, atmvcc))
2043 return 0;
2044 return -EADDRINUSE;
2045 default:
2046 if (*vcip >= lanai->num_vci || *vcip < 0 ||
2047 !vci_is_ok(lanai, *vcip, atmvcc))
2048 return -EADDRINUSE;
2049 }
2050 return 0;
2051 }
2052
2053 /* -------------------- MANAGE CBR: */
2054
2055 /*
2056 * CBR ICG is stored as a fixed-point number with 4 fractional bits.
2057 * Note that storing a number greater than 2046.0 will result in
2058 * incorrect shaping
2059 */
2060 #define CBRICG_FRAC_BITS (4)
2061 #define CBRICG_MAX (2046 << CBRICG_FRAC_BITS)
2062
2063 /*
2064 * ICG is related to PCR with the formula PCR = MAXPCR / (ICG + 1)
2065 * where MAXPCR is (according to the docs) 25600000/(54*8),
2066 * which is equal to (3125<<9)/27.
2067 *
2068 * Solving for ICG, we get:
2069 * ICG = MAXPCR/PCR - 1
2070 * ICG = (3125<<9)/(27*PCR) - 1
2071 * ICG = ((3125<<9) - (27*PCR)) / (27*PCR)
2072 *
2073 * The end result is supposed to be a fixed-point number with FRAC_BITS
2074 * bits of a fractional part, so we keep everything in the numerator
2075 * shifted by that much as we compute
2076 *
2077 */
2078 static int pcr_to_cbricg(const struct atm_qos *qos)
2079 {
2080 int rounddown = 0; /* 1 = Round PCR down, i.e. round ICG _up_ */
2081 int x, icg, pcr = atm_pcr_goal(&qos->txtp);
2082 if (pcr == 0) /* Use maximum bandwidth */
2083 return 0;
2084 if (pcr < 0) {
2085 rounddown = 1;
2086 pcr = -pcr;
2087 }
2088 x = pcr * 27;
2089 icg = (3125 << (9 + CBRICG_FRAC_BITS)) - (x << CBRICG_FRAC_BITS);
2090 if (rounddown)
2091 icg += x - 1;
2092 icg /= x;
2093 if (icg > CBRICG_MAX)
2094 icg = CBRICG_MAX;
2095 DPRINTK("pcr_to_cbricg: pcr=%d rounddown=%c icg=%d\n",
2096 pcr, rounddown ? 'Y' : 'N', icg);
2097 return icg;
2098 }
2099
2100 static inline void lanai_cbr_setup(struct lanai_dev *lanai)
2101 {
2102 reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg);
2103 reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg);
2104 lanai->conf2 |= CONFIG2_CBR_ENABLE;
2105 conf2_write(lanai);
2106 }
2107
2108 static inline void lanai_cbr_shutdown(struct lanai_dev *lanai)
2109 {
2110 lanai->conf2 &= ~CONFIG2_CBR_ENABLE;
2111 conf2_write(lanai);
2112 }
2113
2114 /* -------------------- OPERATIONS: */
2115
2116 /* setup a newly detected device */
2117 static int lanai_dev_open(struct atm_dev *atmdev)
2118 {
2119 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2120 unsigned long raw_base;
2121 int result;
2122
2123 DPRINTK("In lanai_dev_open()\n");
2124 /* Basic device fields */
2125 lanai->number = atmdev->number;
2126 lanai->num_vci = NUM_VCI;
2127 bitmap_zero(lanai->backlog_vccs, NUM_VCI);
2128 bitmap_zero(lanai->transmit_ready, NUM_VCI);
2129 lanai->naal0 = 0;
2130 #ifdef USE_POWERDOWN
2131 lanai->nbound = 0;
2132 #endif
2133 lanai->cbrvcc = NULL;
2134 memset(&lanai->stats, 0, sizeof lanai->stats);
2135 spin_lock_init(&lanai->endtxlock);
2136 spin_lock_init(&lanai->servicelock);
2137 atmdev->ci_range.vpi_bits = 0;
2138 atmdev->ci_range.vci_bits = 0;
2139 while (1 << atmdev->ci_range.vci_bits < lanai->num_vci)
2140 atmdev->ci_range.vci_bits++;
2141 atmdev->link_rate = ATM_25_PCR;
2142
2143 /* 3.2: PCI initialization */
2144 if ((result = lanai_pci_start(lanai)) != 0)
2145 goto error;
2146 raw_base = lanai->pci->resource[0].start;
2147 lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE);
2148 if (lanai->base == NULL) {
2149 printk(KERN_ERR DEV_LABEL ": couldn't remap I/O space\n");
2150 goto error_pci;
2151 }
2152 /* 3.3: Reset lanai and PHY */
2153 reset_board(lanai);
2154 lanai->conf1 = reg_read(lanai, Config1_Reg);
2155 lanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN |
2156 CONFIG1_MASK_LEDMODE);
2157 lanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL);
2158 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2159 udelay(1000);
2160 conf1_write(lanai);
2161
2162 /*
2163 * 3.4: Turn on endian mode for big-endian hardware
2164 * We don't actually want to do this - the actual bit fields
2165 * in the endian register are not documented anywhere.
2166 * Instead we do the bit-flipping ourselves on big-endian
2167 * hardware.
2168 *
2169 * 3.5: get the board ID/rev by reading the reset register
2170 */
2171 result = check_board_id_and_rev("register",
2172 reg_read(lanai, Reset_Reg), &lanai->board_rev);
2173 if (result != 0)
2174 goto error_unmap;
2175
2176 /* 3.6: read EEPROM */
2177 if ((result = eeprom_read(lanai)) != 0)
2178 goto error_unmap;
2179 if ((result = eeprom_validate(lanai)) != 0)
2180 goto error_unmap;
2181
2182 /* 3.7: re-reset PHY, do loopback tests, setup PHY */
2183 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2184 udelay(1000);
2185 conf1_write(lanai);
2186 /* TODO - loopback tests */
2187 lanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE);
2188 conf1_write(lanai);
2189
2190 /* 3.8/3.9: test and initialize card SRAM */
2191 if ((result = sram_test_and_clear(lanai)) != 0)
2192 goto error_unmap;
2193
2194 /* 3.10: initialize lanai registers */
2195 lanai->conf1 |= CONFIG1_DMA_ENABLE;
2196 conf1_write(lanai);
2197 if ((result = service_buffer_allocate(lanai)) != 0)
2198 goto error_unmap;
2199 if ((result = vcc_table_allocate(lanai)) != 0)
2200 goto error_service;
2201 lanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) |
2202 CONFIG2_HEC_DROP | /* ??? */ CONFIG2_PTI7_MODE;
2203 conf2_write(lanai);
2204 reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg);
2205 reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */
2206 if ((result = request_irq(lanai->pci->irq, lanai_int, IRQF_SHARED,
2207 DEV_LABEL, lanai)) != 0) {
2208 printk(KERN_ERR DEV_LABEL ": can't allocate interrupt\n");
2209 goto error_vcctable;
2210 }
2211 mb(); /* Make sure that all that made it */
2212 intr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE));
2213 /* 3.11: initialize loop mode (i.e. turn looping off) */
2214 lanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) |
2215 CONFIG1_SET_LOOPMODE(LOOPMODE_NORMAL) |
2216 CONFIG1_GPOUT2 | CONFIG1_GPOUT3;
2217 conf1_write(lanai);
2218 lanai->status = reg_read(lanai, Status_Reg);
2219 /* We're now done initializing this card */
2220 #ifdef USE_POWERDOWN
2221 lanai->conf1 |= CONFIG1_POWERDOWN;
2222 conf1_write(lanai);
2223 #endif
2224 memcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN);
2225 lanai_timed_poll_start(lanai);
2226 printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d, base=0x%lx, irq=%u "
2227 "(%pMF)\n", lanai->number, (int) lanai->pci->revision,
2228 (unsigned long) lanai->base, lanai->pci->irq, atmdev->esi);
2229 printk(KERN_NOTICE DEV_LABEL "(itf %d): LANAI%s, serialno=%u(0x%X), "
2230 "board_rev=%d\n", lanai->number,
2231 lanai->type==lanai2 ? "2" : "HB", (unsigned int) lanai->serialno,
2232 (unsigned int) lanai->serialno, lanai->board_rev);
2233 return 0;
2234
2235 error_vcctable:
2236 vcc_table_deallocate(lanai);
2237 error_service:
2238 service_buffer_deallocate(lanai);
2239 error_unmap:
2240 reset_board(lanai);
2241 #ifdef USE_POWERDOWN
2242 lanai->conf1 = reg_read(lanai, Config1_Reg) | CONFIG1_POWERDOWN;
2243 conf1_write(lanai);
2244 #endif
2245 iounmap(lanai->base);
2246 error_pci:
2247 pci_disable_device(lanai->pci);
2248 error:
2249 return result;
2250 }
2251
2252 /* called when device is being shutdown, and all vcc's are gone - higher
2253 * levels will deallocate the atm device for us
2254 */
2255 static void lanai_dev_close(struct atm_dev *atmdev)
2256 {
2257 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2258 printk(KERN_INFO DEV_LABEL "(itf %d): shutting down interface\n",
2259 lanai->number);
2260 lanai_timed_poll_stop(lanai);
2261 #ifdef USE_POWERDOWN
2262 lanai->conf1 = reg_read(lanai, Config1_Reg) & ~CONFIG1_POWERDOWN;
2263 conf1_write(lanai);
2264 #endif
2265 intr_disable(lanai, INT_ALL);
2266 free_irq(lanai->pci->irq, lanai);
2267 reset_board(lanai);
2268 #ifdef USE_POWERDOWN
2269 lanai->conf1 |= CONFIG1_POWERDOWN;
2270 conf1_write(lanai);
2271 #endif
2272 pci_disable_device(lanai->pci);
2273 vcc_table_deallocate(lanai);
2274 service_buffer_deallocate(lanai);
2275 iounmap(lanai->base);
2276 kfree(lanai);
2277 }
2278
2279 /* close a vcc */
2280 static void lanai_close(struct atm_vcc *atmvcc)
2281 {
2282 struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;
2283 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2284 if (lvcc == NULL)
2285 return;
2286 clear_bit(ATM_VF_READY, &atmvcc->flags);
2287 clear_bit(ATM_VF_PARTIAL, &atmvcc->flags);
2288 if (lvcc->rx.atmvcc == atmvcc) {
2289 lanai_shutdown_rx_vci(lvcc);
2290 if (atmvcc->qos.aal == ATM_AAL0) {
2291 if (--lanai->naal0 <= 0)
2292 aal0_buffer_free(lanai);
2293 } else
2294 lanai_buf_deallocate(&lvcc->rx.buf, lanai->pci);
2295 lvcc->rx.atmvcc = NULL;
2296 }
2297 if (lvcc->tx.atmvcc == atmvcc) {
2298 if (atmvcc == lanai->cbrvcc) {
2299 if (lvcc->vbase != NULL)
2300 lanai_cbr_shutdown(lanai);
2301 lanai->cbrvcc = NULL;
2302 }
2303 lanai_shutdown_tx_vci(lanai, lvcc);
2304 lanai_buf_deallocate(&lvcc->tx.buf, lanai->pci);
2305 lvcc->tx.atmvcc = NULL;
2306 }
2307 if (--lvcc->nref == 0) {
2308 host_vcc_unbind(lanai, lvcc);
2309 kfree(lvcc);
2310 }
2311 atmvcc->dev_data = NULL;
2312 clear_bit(ATM_VF_ADDR, &atmvcc->flags);
2313 }
2314
2315 /* open a vcc on the card to vpi/vci */
2316 static int lanai_open(struct atm_vcc *atmvcc)
2317 {
2318 struct lanai_dev *lanai;
2319 struct lanai_vcc *lvcc;
2320 int result = 0;
2321 int vci = atmvcc->vci;
2322 short vpi = atmvcc->vpi;
2323 /* we don't support partial open - it's not really useful anyway */
2324 if ((test_bit(ATM_VF_PARTIAL, &atmvcc->flags)) ||
2325 (vpi == ATM_VPI_UNSPEC) || (vci == ATM_VCI_UNSPEC))
2326 return -EINVAL;
2327 lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2328 result = lanai_normalize_ci(lanai, atmvcc, &vpi, &vci);
2329 if (unlikely(result != 0))
2330 goto out;
2331 set_bit(ATM_VF_ADDR, &atmvcc->flags);
2332 if (atmvcc->qos.aal != ATM_AAL0 && atmvcc->qos.aal != ATM_AAL5)
2333 return -EINVAL;
2334 DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n", lanai->number,
2335 (int) vpi, vci);
2336 lvcc = lanai->vccs[vci];
2337 if (lvcc == NULL) {
2338 lvcc = new_lanai_vcc();
2339 if (unlikely(lvcc == NULL))
2340 return -ENOMEM;
2341 atmvcc->dev_data = lvcc;
2342 }
2343 lvcc->nref++;
2344 if (atmvcc->qos.rxtp.traffic_class != ATM_NONE) {
2345 APRINTK(lvcc->rx.atmvcc == NULL, "rx.atmvcc!=NULL, vci=%d\n",
2346 vci);
2347 if (atmvcc->qos.aal == ATM_AAL0) {
2348 if (lanai->naal0 == 0)
2349 result = aal0_buffer_allocate(lanai);
2350 } else
2351 result = lanai_setup_rx_vci_aal5(
2352 lanai, lvcc, &atmvcc->qos);
2353 if (unlikely(result != 0))
2354 goto out_free;
2355 lvcc->rx.atmvcc = atmvcc;
2356 lvcc->stats.rx_nomem = 0;
2357 lvcc->stats.x.aal5.rx_badlen = 0;
2358 lvcc->stats.x.aal5.service_trash = 0;
2359 lvcc->stats.x.aal5.service_stream = 0;
2360 lvcc->stats.x.aal5.service_rxcrc = 0;
2361 if (atmvcc->qos.aal == ATM_AAL0)
2362 lanai->naal0++;
2363 }
2364 if (atmvcc->qos.txtp.traffic_class != ATM_NONE) {
2365 APRINTK(lvcc->tx.atmvcc == NULL, "tx.atmvcc!=NULL, vci=%d\n",
2366 vci);
2367 result = lanai_setup_tx_vci(lanai, lvcc, &atmvcc->qos);
2368 if (unlikely(result != 0))
2369 goto out_free;
2370 lvcc->tx.atmvcc = atmvcc;
2371 if (atmvcc->qos.txtp.traffic_class == ATM_CBR) {
2372 APRINTK(lanai->cbrvcc == NULL,
2373 "cbrvcc!=NULL, vci=%d\n", vci);
2374 lanai->cbrvcc = atmvcc;
2375 }
2376 }
2377 host_vcc_bind(lanai, lvcc, vci);
2378 /*
2379 * Make sure everything made it to RAM before we tell the card about
2380 * the VCC
2381 */
2382 wmb();
2383 if (atmvcc == lvcc->rx.atmvcc)
2384 host_vcc_start_rx(lvcc);
2385 if (atmvcc == lvcc->tx.atmvcc) {
2386 host_vcc_start_tx(lvcc);
2387 if (lanai->cbrvcc == atmvcc)
2388 lanai_cbr_setup(lanai);
2389 }
2390 set_bit(ATM_VF_READY, &atmvcc->flags);
2391 return 0;
2392 out_free:
2393 lanai_close(atmvcc);
2394 out:
2395 return result;
2396 }
2397
2398 static int lanai_send(struct atm_vcc *atmvcc, struct sk_buff *skb)
2399 {
2400 struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;
2401 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2402 unsigned long flags;
2403 if (unlikely(lvcc == NULL || lvcc->vbase == NULL ||
2404 lvcc->tx.atmvcc != atmvcc))
2405 goto einval;
2406 #ifdef DEBUG
2407 if (unlikely(skb == NULL)) {
2408 DPRINTK("lanai_send: skb==NULL for vci=%d\n", atmvcc->vci);
2409 goto einval;
2410 }
2411 if (unlikely(lanai == NULL)) {
2412 DPRINTK("lanai_send: lanai==NULL for vci=%d\n", atmvcc->vci);
2413 goto einval;
2414 }
2415 #endif
2416 ATM_SKB(skb)->vcc = atmvcc;
2417 switch (atmvcc->qos.aal) {
2418 case ATM_AAL5:
2419 read_lock_irqsave(&vcc_sklist_lock, flags);
2420 vcc_tx_aal5(lanai, lvcc, skb);
2421 read_unlock_irqrestore(&vcc_sklist_lock, flags);
2422 return 0;
2423 case ATM_AAL0:
2424 if (unlikely(skb->len != ATM_CELL_SIZE-1))
2425 goto einval;
2426 /* NOTE - this next line is technically invalid - we haven't unshared skb */
2427 cpu_to_be32s((u32 *) skb->data);
2428 read_lock_irqsave(&vcc_sklist_lock, flags);
2429 vcc_tx_aal0(lanai, lvcc, skb);
2430 read_unlock_irqrestore(&vcc_sklist_lock, flags);
2431 return 0;
2432 }
2433 DPRINTK("lanai_send: bad aal=%d on vci=%d\n", (int) atmvcc->qos.aal,
2434 atmvcc->vci);
2435 einval:
2436 lanai_free_skb(atmvcc, skb);
2437 return -EINVAL;
2438 }
2439
2440 static int lanai_change_qos(struct atm_vcc *atmvcc,
2441 /*const*/ struct atm_qos *qos, int flags)
2442 {
2443 return -EBUSY; /* TODO: need to write this */
2444 }
2445
2446 #ifndef CONFIG_PROC_FS
2447 #define lanai_proc_read NULL
2448 #else
2449 static int lanai_proc_read(struct atm_dev *atmdev, loff_t *pos, char *page)
2450 {
2451 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2452 loff_t left = *pos;
2453 struct lanai_vcc *lvcc;
2454 if (left-- == 0)
2455 return sprintf(page, DEV_LABEL "(itf %d): chip=LANAI%s, "
2456 "serial=%u, magic=0x%08X, num_vci=%d\n",
2457 atmdev->number, lanai->type==lanai2 ? "2" : "HB",
2458 (unsigned int) lanai->serialno,
2459 (unsigned int) lanai->magicno, lanai->num_vci);
2460 if (left-- == 0)
2461 return sprintf(page, "revision: board=%d, pci_if=%d\n",
2462 lanai->board_rev, (int) lanai->pci->revision);
2463 if (left-- == 0)
2464 return sprintf(page, "EEPROM ESI: %pM\n",
2465 &lanai->eeprom[EEPROM_MAC]);
2466 if (left-- == 0)
2467 return sprintf(page, "status: SOOL=%d, LOCD=%d, LED=%d, "
2468 "GPIN=%d\n", (lanai->status & STATUS_SOOL) ? 1 : 0,
2469 (lanai->status & STATUS_LOCD) ? 1 : 0,
2470 (lanai->status & STATUS_LED) ? 1 : 0,
2471 (lanai->status & STATUS_GPIN) ? 1 : 0);
2472 if (left-- == 0)
2473 return sprintf(page, "global buffer sizes: service=%Zu, "
2474 "aal0_rx=%Zu\n", lanai_buf_size(&lanai->service),
2475 lanai->naal0 ? lanai_buf_size(&lanai->aal0buf) : 0);
2476 if (left-- == 0) {
2477 get_statistics(lanai);
2478 return sprintf(page, "cells in error: overflow=%u, "
2479 "closed_vci=%u, bad_HEC=%u, rx_fifo=%u\n",
2480 lanai->stats.ovfl_trash, lanai->stats.vci_trash,
2481 lanai->stats.hec_err, lanai->stats.atm_ovfl);
2482 }
2483 if (left-- == 0)
2484 return sprintf(page, "PCI errors: parity_detect=%u, "
2485 "master_abort=%u, master_target_abort=%u,\n",
2486 lanai->stats.pcierr_parity_detect,
2487 lanai->stats.pcierr_serr_set,
2488 lanai->stats.pcierr_m_target_abort);
2489 if (left-- == 0)
2490 return sprintf(page, " slave_target_abort=%u, "
2491 "master_parity=%u\n", lanai->stats.pcierr_s_target_abort,
2492 lanai->stats.pcierr_master_parity);
2493 if (left-- == 0)
2494 return sprintf(page, " no_tx=%u, "
2495 "no_rx=%u, bad_rx_aal=%u\n", lanai->stats.service_norx,
2496 lanai->stats.service_notx,
2497 lanai->stats.service_rxnotaal5);
2498 if (left-- == 0)
2499 return sprintf(page, "resets: dma=%u, card=%u\n",
2500 lanai->stats.dma_reenable, lanai->stats.card_reset);
2501 /* At this point, "left" should be the VCI we're looking for */
2502 read_lock(&vcc_sklist_lock);
2503 for (; ; left++) {
2504 if (left >= NUM_VCI) {
2505 left = 0;
2506 goto out;
2507 }
2508 if ((lvcc = lanai->vccs[left]) != NULL)
2509 break;
2510 (*pos)++;
2511 }
2512 /* Note that we re-use "left" here since we're done with it */
2513 left = sprintf(page, "VCI %4d: nref=%d, rx_nomem=%u", (vci_t) left,
2514 lvcc->nref, lvcc->stats.rx_nomem);
2515 if (lvcc->rx.atmvcc != NULL) {
2516 left += sprintf(&page[left], ",\n rx_AAL=%d",
2517 lvcc->rx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0);
2518 if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5)
2519 left += sprintf(&page[left], ", rx_buf_size=%Zu, "
2520 "rx_bad_len=%u,\n rx_service_trash=%u, "
2521 "rx_service_stream=%u, rx_bad_crc=%u",
2522 lanai_buf_size(&lvcc->rx.buf),
2523 lvcc->stats.x.aal5.rx_badlen,
2524 lvcc->stats.x.aal5.service_trash,
2525 lvcc->stats.x.aal5.service_stream,
2526 lvcc->stats.x.aal5.service_rxcrc);
2527 }
2528 if (lvcc->tx.atmvcc != NULL)
2529 left += sprintf(&page[left], ",\n tx_AAL=%d, "
2530 "tx_buf_size=%Zu, tx_qos=%cBR, tx_backlogged=%c",
2531 lvcc->tx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0,
2532 lanai_buf_size(&lvcc->tx.buf),
2533 lvcc->tx.atmvcc == lanai->cbrvcc ? 'C' : 'U',
2534 vcc_is_backlogged(lvcc) ? 'Y' : 'N');
2535 page[left++] = '\n';
2536 page[left] = '\0';
2537 out:
2538 read_unlock(&vcc_sklist_lock);
2539 return left;
2540 }
2541 #endif /* CONFIG_PROC_FS */
2542
2543 /* -------------------- HOOKS: */
2544
2545 static const struct atmdev_ops ops = {
2546 .dev_close = lanai_dev_close,
2547 .open = lanai_open,
2548 .close = lanai_close,
2549 .getsockopt = NULL,
2550 .setsockopt = NULL,
2551 .send = lanai_send,
2552 .phy_put = NULL,
2553 .phy_get = NULL,
2554 .change_qos = lanai_change_qos,
2555 .proc_read = lanai_proc_read,
2556 .owner = THIS_MODULE
2557 };
2558
2559 /* initialize one probed card */
2560 static int lanai_init_one(struct pci_dev *pci,
2561 const struct pci_device_id *ident)
2562 {
2563 struct lanai_dev *lanai;
2564 struct atm_dev *atmdev;
2565 int result;
2566
2567 lanai = kmalloc(sizeof(*lanai), GFP_KERNEL);
2568 if (lanai == NULL) {
2569 printk(KERN_ERR DEV_LABEL
2570 ": couldn't allocate dev_data structure!\n");
2571 return -ENOMEM;
2572 }
2573
2574 atmdev = atm_dev_register(DEV_LABEL, &pci->dev, &ops, -1, NULL);
2575 if (atmdev == NULL) {
2576 printk(KERN_ERR DEV_LABEL
2577 ": couldn't register atm device!\n");
2578 kfree(lanai);
2579 return -EBUSY;
2580 }
2581
2582 atmdev->dev_data = lanai;
2583 lanai->pci = pci;
2584 lanai->type = (enum lanai_type) ident->device;
2585
2586 result = lanai_dev_open(atmdev);
2587 if (result != 0) {
2588 DPRINTK("lanai_start() failed, err=%d\n", -result);
2589 atm_dev_deregister(atmdev);
2590 kfree(lanai);
2591 }
2592 return result;
2593 }
2594
2595 static struct pci_device_id lanai_pci_tbl[] = {
2596 { PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAI2) },
2597 { PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAIHB) },
2598 { 0, } /* terminal entry */
2599 };
2600 MODULE_DEVICE_TABLE(pci, lanai_pci_tbl);
2601
2602 static struct pci_driver lanai_driver = {
2603 .name = DEV_LABEL,
2604 .id_table = lanai_pci_tbl,
2605 .probe = lanai_init_one,
2606 };
2607
2608 module_pci_driver(lanai_driver);
2609
2610 MODULE_AUTHOR("Mitchell Blank Jr <mitch@sfgoth.com>");
2611 MODULE_DESCRIPTION("Efficient Networks Speedstream 3010 driver");
2612 MODULE_LICENSE("GPL");
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