drivers/base/regmap/regcache.c

   1 /*
   2  * Register cache access API
   3  *
   4  * Copyright 2011 Wolfson Microelectronics plc
   5  *
   6  * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/bsearch.h>
  14 #include <linux/device.h>
  15 #include <linux/export.h>
  16 #include <linux/slab.h>
  17 #include <linux/sort.h>
  18
  19 #include "trace.h"
  20 #include "internal.h"
  21
  22 static const struct regcache_ops *cache_types[] = {
  23         &regcache_rbtree_ops,
  24         &regcache_lzo_ops,
  25         &regcache_flat_ops,
  26 };
  27
  28 static int regcache_hw_init(struct regmap *map)
  29 {
  30         int i, j;
  31         int ret;
  32         int count;
  33         unsigned int val;
  34         void *tmp_buf;
  35
  36         if (!map->num_reg_defaults_raw)
  37                 return -EINVAL;
  38
  39         /* calculate the size of reg_defaults */
  40         for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)
  41                 if (!regmap_volatile(map, i * map->reg_stride))
  42                         count++;
  43
  44         /* all registers are volatile, so just bypass */
  45         if (!count) {
  46                 map->cache_bypass = true;
  47                 return 0;
  48         }
  49
  50         map->num_reg_defaults = count;
  51         map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),
  52                                           GFP_KERNEL);
  53         if (!map->reg_defaults)
  54                 return -ENOMEM;
  55
  56         if (!map->reg_defaults_raw) {
  57                 bool cache_bypass = map->cache_bypass;
  58                 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
  59
  60                 /* Bypass the cache access till data read from HW */
  61                 map->cache_bypass = true;
  62                 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
  63                 if (!tmp_buf) {
  64                         ret = -ENOMEM;
  65                         goto err_free;
  66                 }
  67                 ret = regmap_raw_read(map, 0, tmp_buf,
  68                                       map->cache_size_raw);
  69                 map->cache_bypass = cache_bypass;
  70                 if (ret < 0)
  71                         goto err_cache_free;
  72
  73                 map->reg_defaults_raw = tmp_buf;
  74                 map->cache_free = 1;
  75         }
  76
  77         /* fill the reg_defaults */
  78         for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
  79                 if (regmap_volatile(map, i * map->reg_stride))
  80                         continue;
  81                 val = regcache_get_val(map, map->reg_defaults_raw, i);
  82                 map->reg_defaults[j].reg = i * map->reg_stride;
  83                 map->reg_defaults[j].def = val;
  84                 j++;
  85         }
  86
  87         return 0;
  88
  89 err_cache_free:
  90         kfree(tmp_buf);
  91 err_free:
  92         kfree(map->reg_defaults);
  93
  94         return ret;
  95 }
  96
  97 int regcache_init(struct regmap *map, const struct regmap_config *config)
  98 {
  99         int ret;
 100         int i;
 101         void *tmp_buf;
 102
 103         if (map->cache_type == REGCACHE_NONE) {
 104                 if (config->reg_defaults || config->num_reg_defaults_raw)
 105                         dev_warn(map->dev,
 106                                  "No cache used with register defaults set!\n");
 107
 108                 map->cache_bypass = true;
 109                 return 0;
 110         }
 111
 112         if (config->reg_defaults && !config->num_reg_defaults) {
 113                 dev_err(map->dev,
 114                          "Register defaults are set without the number!\n");
 115                 return -EINVAL;
 116         }
 117
 118         for (i = 0; i < config->num_reg_defaults; i++)
 119                 if (config->reg_defaults[i].reg % map->reg_stride)
 120                         return -EINVAL;
 121
 122         for (i = 0; i < ARRAY_SIZE(cache_types); i++)
 123                 if (cache_types[i]->type == map->cache_type)
 124                         break;
 125
 126         if (i == ARRAY_SIZE(cache_types)) {
 127                 dev_err(map->dev, "Could not match compress type: %d\n",
 128                         map->cache_type);
 129                 return -EINVAL;
 130         }
 131
 132         map->num_reg_defaults = config->num_reg_defaults;
 133         map->num_reg_defaults_raw = config->num_reg_defaults_raw;
 134         map->reg_defaults_raw = config->reg_defaults_raw;
 135         map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8);
 136         map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
 137
 138         map->cache = NULL;
 139         map->cache_ops = cache_types[i];
 140
 141         if (!map->cache_ops->read ||
 142             !map->cache_ops->write ||
 143             !map->cache_ops->name)
 144                 return -EINVAL;
 145
 146         /* We still need to ensure that the reg_defaults
 147          * won't vanish from under us.  We'll need to make
 148          * a copy of it.
 149          */
 150         if (config->reg_defaults) {
 151                 tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults *
 152                                   sizeof(struct reg_default), GFP_KERNEL);
 153                 if (!tmp_buf)
 154                         return -ENOMEM;
 155                 map->reg_defaults = tmp_buf;
 156         } else if (map->num_reg_defaults_raw) {
 157                 /* Some devices such as PMICs don't have cache defaults,
 158                  * we cope with this by reading back the HW registers and
 159                  * crafting the cache defaults by hand.
 160                  */
 161                 ret = regcache_hw_init(map);
 162                 if (ret < 0)
 163                         return ret;
 164                 if (map->cache_bypass)
 165                         return 0;
 166         }
 167
 168         if (!map->max_register)
 169                 map->max_register = map->num_reg_defaults_raw;
 170
 171         if (map->cache_ops->init) {
 172                 dev_dbg(map->dev, "Initializing %s cache\n",
 173                         map->cache_ops->name);
 174                 ret = map->cache_ops->init(map);
 175                 if (ret)
 176                         goto err_free;
 177         }
 178         return 0;
 179
 180 err_free:
 181         kfree(map->reg_defaults);
 182         if (map->cache_free)
 183                 kfree(map->reg_defaults_raw);
 184
 185         return ret;
 186 }
 187
 188 void regcache_exit(struct regmap *map)
 189 {
 190         if (map->cache_type == REGCACHE_NONE)
 191                 return;
 192
 193         BUG_ON(!map->cache_ops);
 194
 195         kfree(map->reg_defaults);
 196         if (map->cache_free)
 197                 kfree(map->reg_defaults_raw);
 198
 199         if (map->cache_ops->exit) {
 200                 dev_dbg(map->dev, "Destroying %s cache\n",
 201                         map->cache_ops->name);
 202                 map->cache_ops->exit(map);
 203         }
 204 }
 205
 206 /**
 207  * regcache_read: Fetch the value of a given register from the cache.
 208  *
 209  * @map: map to configure.
 210  * @reg: The register index.
 211  * @value: The value to be returned.
 212  *
 213  * Return a negative value on failure, 0 on success.
 214  */
 215 int regcache_read(struct regmap *map,
 216                   unsigned int reg, unsigned int *value)
 217 {
 218         int ret;
 219
 220         if (map->cache_type == REGCACHE_NONE)
 221                 return -ENOSYS;
 222
 223         BUG_ON(!map->cache_ops);
 224
 225         if (!regmap_volatile(map, reg)) {
 226                 ret = map->cache_ops->read(map, reg, value);
 227
 228                 if (ret == 0)
 229                         trace_regmap_reg_read_cache(map, reg, *value);
 230
 231                 return ret;
 232         }
 233
 234         return -EINVAL;
 235 }
 236
 237 /**
 238  * regcache_write: Set the value of a given register in the cache.
 239  *
 240  * @map: map to configure.
 241  * @reg: The register index.
 242  * @value: The new register value.
 243  *
 244  * Return a negative value on failure, 0 on success.
 245  */
 246 int regcache_write(struct regmap *map,
 247                    unsigned int reg, unsigned int value)
 248 {
 249         if (map->cache_type == REGCACHE_NONE)
 250                 return 0;
 251
 252         BUG_ON(!map->cache_ops);
 253
 254         if (!regmap_volatile(map, reg))
 255                 return map->cache_ops->write(map, reg, value);
 256
 257         return 0;
 258 }
 259
 260 static bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
 261                                     unsigned int val)
 262 {
 263         int ret;
 264
 265         /* If we don't know the chip just got reset, then sync everything. */
 266         if (!map->no_sync_defaults)
 267                 return true;
 268
 269         /* Is this the hardware default?  If so skip. */
 270         ret = regcache_lookup_reg(map, reg);
 271         if (ret >= 0 && val == map->reg_defaults[ret].def)
 272                 return false;
 273         return true;
 274 }
 275
 276 static int regcache_default_sync(struct regmap *map, unsigned int min,
 277                                  unsigned int max)
 278 {
 279         unsigned int reg;
 280
 281         for (reg = min; reg <= max; reg += map->reg_stride) {
 282                 unsigned int val;
 283                 int ret;
 284
 285                 if (regmap_volatile(map, reg) ||
 286                     !regmap_writeable(map, reg))
 287                         continue;
 288
 289                 ret = regcache_read(map, reg, &val);
 290                 if (ret)
 291                         return ret;
 292
 293                 if (!regcache_reg_needs_sync(map, reg, val))
 294                         continue;
 295
 296                 map->cache_bypass = true;
 297                 ret = _regmap_write(map, reg, val);
 298                 map->cache_bypass = false;
 299                 if (ret) {
 300                         dev_err(map->dev, "Unable to sync register %#x. %d\n",
 301                                 reg, ret);
 302                         return ret;
 303                 }
 304                 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
 305         }
 306
 307         return 0;
 308 }
 309
 310 /**
 311  * regcache_sync: Sync the register cache with the hardware.
 312  *
 313  * @map: map to configure.
 314  *
 315  * Any registers that should not be synced should be marked as
 316  * volatile.  In general drivers can choose not to use the provided
 317  * syncing functionality if they so require.
 318  *
 319  * Return a negative value on failure, 0 on success.
 320  */
 321 int regcache_sync(struct regmap *map)
 322 {
 323         int ret = 0;
 324         unsigned int i;
 325         const char *name;
 326         bool bypass;
 327
 328         BUG_ON(!map->cache_ops);
 329
 330         map->lock(map->lock_arg);
 331         /* Remember the initial bypass state */
 332         bypass = map->cache_bypass;
 333         dev_dbg(map->dev, "Syncing %s cache\n",
 334                 map->cache_ops->name);
 335         name = map->cache_ops->name;
 336         trace_regcache_sync(map, name, "start");
 337
 338         if (!map->cache_dirty)
 339                 goto out;
 340
 341         map->async = true;
 342
 343         /* Apply any patch first */
 344         map->cache_bypass = true;
 345         for (i = 0; i < map->patch_regs; i++) {
 346                 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
 347                 if (ret != 0) {
 348                         dev_err(map->dev, "Failed to write %x = %x: %d\n",
 349                                 map->patch[i].reg, map->patch[i].def, ret);
 350                         goto out;
 351                 }
 352         }
 353         map->cache_bypass = false;
 354
 355         if (map->cache_ops->sync)
 356                 ret = map->cache_ops->sync(map, 0, map->max_register);
 357         else
 358                 ret = regcache_default_sync(map, 0, map->max_register);
 359
 360         if (ret == 0)
 361                 map->cache_dirty = false;
 362
 363 out:
 364         /* Restore the bypass state */
 365         map->async = false;
 366         map->cache_bypass = bypass;
 367         map->no_sync_defaults = false;
 368         map->unlock(map->lock_arg);
 369
 370         regmap_async_complete(map);
 371
 372         trace_regcache_sync(map, name, "stop");
 373
 374         return ret;
 375 }
 376 EXPORT_SYMBOL_GPL(regcache_sync);
 377
 378 /**
 379  * regcache_sync_region: Sync part  of the register cache with the hardware.
 380  *
 381  * @map: map to sync.
 382  * @min: first register to sync
 383  * @max: last register to sync
 384  *
 385  * Write all non-default register values in the specified region to
 386  * the hardware.
 387  *
 388  * Return a negative value on failure, 0 on success.
 389  */
 390 int regcache_sync_region(struct regmap *map, unsigned int min,
 391                          unsigned int max)
 392 {
 393         int ret = 0;
 394         const char *name;
 395         bool bypass;
 396
 397         BUG_ON(!map->cache_ops);
 398
 399         map->lock(map->lock_arg);
 400
 401         /* Remember the initial bypass state */
 402         bypass = map->cache_bypass;
 403
 404         name = map->cache_ops->name;
 405         dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
 406
 407         trace_regcache_sync(map, name, "start region");
 408
 409         if (!map->cache_dirty)
 410                 goto out;
 411
 412         map->async = true;
 413
 414         if (map->cache_ops->sync)
 415                 ret = map->cache_ops->sync(map, min, max);
 416         else
 417                 ret = regcache_default_sync(map, min, max);
 418
 419 out:
 420         /* Restore the bypass state */
 421         map->cache_bypass = bypass;
 422         map->async = false;
 423         map->no_sync_defaults = false;
 424         map->unlock(map->lock_arg);
 425
 426         regmap_async_complete(map);
 427
 428         trace_regcache_sync(map, name, "stop region");
 429
 430         return ret;
 431 }
 432 EXPORT_SYMBOL_GPL(regcache_sync_region);
 433
 434 /**
 435  * regcache_drop_region: Discard part of the register cache
 436  *
 437  * @map: map to operate on
 438  * @min: first register to discard
 439  * @max: last register to discard
 440  *
 441  * Discard part of the register cache.
 442  *
 443  * Return a negative value on failure, 0 on success.
 444  */
 445 int regcache_drop_region(struct regmap *map, unsigned int min,
 446                          unsigned int max)
 447 {
 448         int ret = 0;
 449
 450         if (!map->cache_ops || !map->cache_ops->drop)
 451                 return -EINVAL;
 452
 453         map->lock(map->lock_arg);
 454
 455         trace_regcache_drop_region(map, min, max);
 456
 457         ret = map->cache_ops->drop(map, min, max);
 458
 459         map->unlock(map->lock_arg);
 460
 461         return ret;
 462 }
 463 EXPORT_SYMBOL_GPL(regcache_drop_region);
 464
 465 /**
 466  * regcache_cache_only: Put a register map into cache only mode
 467  *
 468  * @map: map to configure
 469  * @cache_only: flag if changes should be written to the hardware
 470  *
 471  * When a register map is marked as cache only writes to the register
 472  * map API will only update the register cache, they will not cause
 473  * any hardware changes.  This is useful for allowing portions of
 474  * drivers to act as though the device were functioning as normal when
 475  * it is disabled for power saving reasons.
 476  */
 477 void regcache_cache_only(struct regmap *map, bool enable)
 478 {
 479         map->lock(map->lock_arg);
 480         WARN_ON(map->cache_bypass && enable);
 481         map->cache_only = enable;
 482         trace_regmap_cache_only(map, enable);
 483         map->unlock(map->lock_arg);
 484 }
 485 EXPORT_SYMBOL_GPL(regcache_cache_only);
 486
 487 /**
 488  * regcache_mark_dirty: Indicate that HW registers were reset to default values
 489  *
 490  * @map: map to mark
 491  *
 492  * Inform regcache that the device has been powered down or reset, so that
 493  * on resume, regcache_sync() knows to write out all non-default values
 494  * stored in the cache.
 495  *
 496  * If this function is not called, regcache_sync() will assume that
 497  * the hardware state still matches the cache state, modulo any writes that
 498  * happened when cache_only was true.
 499  */
 500 void regcache_mark_dirty(struct regmap *map)
 501 {
 502         map->lock(map->lock_arg);
 503         map->cache_dirty = true;
 504         map->no_sync_defaults = true;
 505         map->unlock(map->lock_arg);
 506 }
 507 EXPORT_SYMBOL_GPL(regcache_mark_dirty);
 508
 509 /**
 510  * regcache_cache_bypass: Put a register map into cache bypass mode
 511  *
 512  * @map: map to configure
 513  * @cache_bypass: flag if changes should not be written to the hardware
 514  *
 515  * When a register map is marked with the cache bypass option, writes
 516  * to the register map API will only update the hardware and not the
 517  * the cache directly.  This is useful when syncing the cache back to
 518  * the hardware.
 519  */
 520 void regcache_cache_bypass(struct regmap *map, bool enable)
 521 {
 522         map->lock(map->lock_arg);
 523         WARN_ON(map->cache_only && enable);
 524         map->cache_bypass = enable;
 525         trace_regmap_cache_bypass(map, enable);
 526         map->unlock(map->lock_arg);
 527 }
 528 EXPORT_SYMBOL_GPL(regcache_cache_bypass);
 529
 530 bool regcache_set_val(struct regmap *map, void *base, unsigned int idx,
 531                       unsigned int val)
 532 {
 533         if (regcache_get_val(map, base, idx) == val)
 534                 return true;
 535
 536         /* Use device native format if possible */
 537         if (map->format.format_val) {
 538                 map->format.format_val(base + (map->cache_word_size * idx),
 539                                        val, 0);
 540                 return false;
 541         }
 542
 543         switch (map->cache_word_size) {
 544         case 1: {
 545                 u8 *cache = base;
 546
 547                 cache[idx] = val;
 548                 break;
 549         }
 550         case 2: {
 551                 u16 *cache = base;
 552
 553                 cache[idx] = val;
 554                 break;
 555         }
 556         case 4: {
 557                 u32 *cache = base;
 558
 559                 cache[idx] = val;
 560                 break;
 561         }
 562 #ifdef CONFIG_64BIT
 563         case 8: {
 564                 u64 *cache = base;
 565
 566                 cache[idx] = val;
 567                 break;
 568         }
 569 #endif
 570         default:
 571                 BUG();
 572         }
 573         return false;
 574 }
 575
 576 unsigned int regcache_get_val(struct regmap *map, const void *base,
 577                               unsigned int idx)
 578 {
 579         if (!base)
 580                 return -EINVAL;
 581
 582         /* Use device native format if possible */
 583         if (map->format.parse_val)
 584                 return map->format.parse_val(regcache_get_val_addr(map, base,
 585                                                                    idx));
 586
 587         switch (map->cache_word_size) {
 588         case 1: {
 589                 const u8 *cache = base;
 590
 591                 return cache[idx];
 592         }
 593         case 2: {
 594                 const u16 *cache = base;
 595
 596                 return cache[idx];
 597         }
 598         case 4: {
 599                 const u32 *cache = base;
 600
 601                 return cache[idx];
 602         }
 603 #ifdef CONFIG_64BIT
 604         case 8: {
 605                 const u64 *cache = base;
 606
 607                 return cache[idx];
 608         }
 609 #endif
 610         default:
 611                 BUG();
 612         }
 613         /* unreachable */
 614         return -1;
 615 }
 616
 617 static int regcache_default_cmp(const void *a, const void *b)
 618 {
 619         const struct reg_default *_a = a;
 620         const struct reg_default *_b = b;
 621
 622         return _a->reg - _b->reg;
 623 }
 624
 625 int regcache_lookup_reg(struct regmap *map, unsigned int reg)
 626 {
 627         struct reg_default key;
 628         struct reg_default *r;
 629
 630         key.reg = reg;
 631         key.def = 0;
 632
 633         r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
 634                     sizeof(struct reg_default), regcache_default_cmp);
 635
 636         if (r)
 637                 return r - map->reg_defaults;
 638         else
 639                 return -ENOENT;
 640 }
 641
 642 static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx)
 643 {
 644         if (!cache_present)
 645                 return true;
 646
 647         return test_bit(idx, cache_present);
 648 }
 649
 650 static int regcache_sync_block_single(struct regmap *map, void *block,
 651                                       unsigned long *cache_present,
 652                                       unsigned int block_base,
 653                                       unsigned int start, unsigned int end)
 654 {
 655         unsigned int i, regtmp, val;
 656         int ret;
 657
 658         for (i = start; i < end; i++) {
 659                 regtmp = block_base + (i * map->reg_stride);
 660
 661                 if (!regcache_reg_present(cache_present, i) ||
 662                     !regmap_writeable(map, regtmp))
 663                         continue;
 664
 665                 val = regcache_get_val(map, block, i);
 666                 if (!regcache_reg_needs_sync(map, regtmp, val))
 667                         continue;
 668
 669                 map->cache_bypass = true;
 670
 671                 ret = _regmap_write(map, regtmp, val);
 672
 673                 map->cache_bypass = false;
 674                 if (ret != 0) {
 675                         dev_err(map->dev, "Unable to sync register %#x. %d\n",
 676                                 regtmp, ret);
 677                         return ret;
 678                 }
 679                 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
 680                         regtmp, val);
 681         }
 682
 683         return 0;
 684 }
 685
 686 static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
 687                                          unsigned int base, unsigned int cur)
 688 {
 689         size_t val_bytes = map->format.val_bytes;
 690         int ret, count;
 691
 692         if (*data == NULL)
 693                 return 0;
 694
 695         count = (cur - base) / map->reg_stride;
 696
 697         dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
 698                 count * val_bytes, count, base, cur - map->reg_stride);
 699
 700         map->cache_bypass = true;
 701
 702         ret = _regmap_raw_write(map, base, *data, count * val_bytes);
 703         if (ret)
 704                 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
 705                         base, cur - map->reg_stride, ret);
 706
 707         map->cache_bypass = false;
 708
 709         *data = NULL;
 710
 711         return ret;
 712 }
 713
 714 static int regcache_sync_block_raw(struct regmap *map, void *block,
 715                             unsigned long *cache_present,
 716                             unsigned int block_base, unsigned int start,
 717                             unsigned int end)
 718 {
 719         unsigned int i, val;
 720         unsigned int regtmp = 0;
 721         unsigned int base = 0;
 722         const void *data = NULL;
 723         int ret;
 724
 725         for (i = start; i < end; i++) {
 726                 regtmp = block_base + (i * map->reg_stride);
 727
 728                 if (!regcache_reg_present(cache_present, i) ||
 729                     !regmap_writeable(map, regtmp)) {
 730                         ret = regcache_sync_block_raw_flush(map, &data,
 731                                                             base, regtmp);
 732                         if (ret != 0)
 733                                 return ret;
 734                         continue;
 735                 }
 736
 737                 val = regcache_get_val(map, block, i);
 738                 if (!regcache_reg_needs_sync(map, regtmp, val)) {
 739                         ret = regcache_sync_block_raw_flush(map, &data,
 740                                                             base, regtmp);
 741                         if (ret != 0)
 742                                 return ret;
 743                         continue;
 744                 }
 745
 746                 if (!data) {
 747                         data = regcache_get_val_addr(map, block, i);
 748                         base = regtmp;
 749                 }
 750         }
 751
 752         return regcache_sync_block_raw_flush(map, &data, base, regtmp +
 753                         map->reg_stride);
 754 }
 755
 756 int regcache_sync_block(struct regmap *map, void *block,
 757                         unsigned long *cache_present,
 758                         unsigned int block_base, unsigned int start,
 759                         unsigned int end)
 760 {
 761         if (regmap_can_raw_write(map) && !map->use_single_write)
 762                 return regcache_sync_block_raw(map, block, cache_present,
 763                                                block_base, start, end);
 764         else
 765                 return regcache_sync_block_single(map, block, cache_present,
 766                                                   block_base, start, end);
 767 }