]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/block/cciss.c
block: fold cmd_type into the REQ_OP_ space
[mirror_ubuntu-bionic-kernel.git] / drivers / block / cciss.c
1 /*
2 * Disk Array driver for HP Smart Array controllers.
3 * (C) Copyright 2000, 2007 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
17 * 02111-1307, USA.
18 *
19 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
20 *
21 */
22
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/types.h>
26 #include <linux/pci.h>
27 #include <linux/pci-aspm.h>
28 #include <linux/kernel.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
31 #include <linux/major.h>
32 #include <linux/fs.h>
33 #include <linux/bio.h>
34 #include <linux/blkpg.h>
35 #include <linux/timer.h>
36 #include <linux/proc_fs.h>
37 #include <linux/seq_file.h>
38 #include <linux/init.h>
39 #include <linux/jiffies.h>
40 #include <linux/hdreg.h>
41 #include <linux/spinlock.h>
42 #include <linux/compat.h>
43 #include <linux/mutex.h>
44 #include <linux/bitmap.h>
45 #include <linux/io.h>
46 #include <linux/uaccess.h>
47
48 #include <linux/dma-mapping.h>
49 #include <linux/blkdev.h>
50 #include <linux/genhd.h>
51 #include <linux/completion.h>
52 #include <scsi/scsi.h>
53 #include <scsi/sg.h>
54 #include <scsi/scsi_ioctl.h>
55 #include <scsi/scsi_request.h>
56 #include <linux/cdrom.h>
57 #include <linux/scatterlist.h>
58 #include <linux/kthread.h>
59
60 #define CCISS_DRIVER_VERSION(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
61 #define DRIVER_NAME "HP CISS Driver (v 3.6.26)"
62 #define DRIVER_VERSION CCISS_DRIVER_VERSION(3, 6, 26)
63
64 /* Embedded module documentation macros - see modules.h */
65 MODULE_AUTHOR("Hewlett-Packard Company");
66 MODULE_DESCRIPTION("Driver for HP Smart Array Controllers");
67 MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
68 MODULE_VERSION("3.6.26");
69 MODULE_LICENSE("GPL");
70 static int cciss_tape_cmds = 6;
71 module_param(cciss_tape_cmds, int, 0644);
72 MODULE_PARM_DESC(cciss_tape_cmds,
73 "number of commands to allocate for tape devices (default: 6)");
74 static int cciss_simple_mode;
75 module_param(cciss_simple_mode, int, S_IRUGO|S_IWUSR);
76 MODULE_PARM_DESC(cciss_simple_mode,
77 "Use 'simple mode' rather than 'performant mode'");
78
79 static int cciss_allow_hpsa;
80 module_param(cciss_allow_hpsa, int, S_IRUGO|S_IWUSR);
81 MODULE_PARM_DESC(cciss_allow_hpsa,
82 "Prevent cciss driver from accessing hardware known to be "
83 " supported by the hpsa driver");
84
85 static DEFINE_MUTEX(cciss_mutex);
86 static struct proc_dir_entry *proc_cciss;
87
88 #include "cciss_cmd.h"
89 #include "cciss.h"
90 #include <linux/cciss_ioctl.h>
91
92 /* define the PCI info for the cards we can control */
93 static const struct pci_device_id cciss_pci_device_id[] = {
94 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISS, 0x0E11, 0x4070},
95 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4080},
96 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4082},
97 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4083},
98 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x4091},
99 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409A},
100 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409B},
101 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409C},
102 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409D},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSA, 0x103C, 0x3225},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3223},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3234},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3235},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3211},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3212},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3213},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3214},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3215},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3237},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x323D},
114 {0,}
115 };
116
117 MODULE_DEVICE_TABLE(pci, cciss_pci_device_id);
118
119 /* board_id = Subsystem Device ID & Vendor ID
120 * product = Marketing Name for the board
121 * access = Address of the struct of function pointers
122 */
123 static struct board_type products[] = {
124 {0x40700E11, "Smart Array 5300", &SA5_access},
125 {0x40800E11, "Smart Array 5i", &SA5B_access},
126 {0x40820E11, "Smart Array 532", &SA5B_access},
127 {0x40830E11, "Smart Array 5312", &SA5B_access},
128 {0x409A0E11, "Smart Array 641", &SA5_access},
129 {0x409B0E11, "Smart Array 642", &SA5_access},
130 {0x409C0E11, "Smart Array 6400", &SA5_access},
131 {0x409D0E11, "Smart Array 6400 EM", &SA5_access},
132 {0x40910E11, "Smart Array 6i", &SA5_access},
133 {0x3225103C, "Smart Array P600", &SA5_access},
134 {0x3223103C, "Smart Array P800", &SA5_access},
135 {0x3234103C, "Smart Array P400", &SA5_access},
136 {0x3235103C, "Smart Array P400i", &SA5_access},
137 {0x3211103C, "Smart Array E200i", &SA5_access},
138 {0x3212103C, "Smart Array E200", &SA5_access},
139 {0x3213103C, "Smart Array E200i", &SA5_access},
140 {0x3214103C, "Smart Array E200i", &SA5_access},
141 {0x3215103C, "Smart Array E200i", &SA5_access},
142 {0x3237103C, "Smart Array E500", &SA5_access},
143 {0x323D103C, "Smart Array P700m", &SA5_access},
144 };
145
146 /* How long to wait (in milliseconds) for board to go into simple mode */
147 #define MAX_CONFIG_WAIT 30000
148 #define MAX_IOCTL_CONFIG_WAIT 1000
149
150 /*define how many times we will try a command because of bus resets */
151 #define MAX_CMD_RETRIES 3
152
153 #define MAX_CTLR 32
154
155 /* Originally cciss driver only supports 8 major numbers */
156 #define MAX_CTLR_ORIG 8
157
158 static ctlr_info_t *hba[MAX_CTLR];
159
160 static struct task_struct *cciss_scan_thread;
161 static DEFINE_MUTEX(scan_mutex);
162 static LIST_HEAD(scan_q);
163
164 static void do_cciss_request(struct request_queue *q);
165 static irqreturn_t do_cciss_intx(int irq, void *dev_id);
166 static irqreturn_t do_cciss_msix_intr(int irq, void *dev_id);
167 static int cciss_open(struct block_device *bdev, fmode_t mode);
168 static int cciss_unlocked_open(struct block_device *bdev, fmode_t mode);
169 static void cciss_release(struct gendisk *disk, fmode_t mode);
170 static int cciss_ioctl(struct block_device *bdev, fmode_t mode,
171 unsigned int cmd, unsigned long arg);
172 static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo);
173
174 static int cciss_revalidate(struct gendisk *disk);
175 static int rebuild_lun_table(ctlr_info_t *h, int first_time, int via_ioctl);
176 static int deregister_disk(ctlr_info_t *h, int drv_index,
177 int clear_all, int via_ioctl);
178
179 static void cciss_read_capacity(ctlr_info_t *h, int logvol,
180 sector_t *total_size, unsigned int *block_size);
181 static void cciss_read_capacity_16(ctlr_info_t *h, int logvol,
182 sector_t *total_size, unsigned int *block_size);
183 static void cciss_geometry_inquiry(ctlr_info_t *h, int logvol,
184 sector_t total_size,
185 unsigned int block_size, InquiryData_struct *inq_buff,
186 drive_info_struct *drv);
187 static void cciss_interrupt_mode(ctlr_info_t *);
188 static int cciss_enter_simple_mode(struct ctlr_info *h);
189 static void start_io(ctlr_info_t *h);
190 static int sendcmd_withirq(ctlr_info_t *h, __u8 cmd, void *buff, size_t size,
191 __u8 page_code, unsigned char scsi3addr[],
192 int cmd_type);
193 static int sendcmd_withirq_core(ctlr_info_t *h, CommandList_struct *c,
194 int attempt_retry);
195 static int process_sendcmd_error(ctlr_info_t *h, CommandList_struct *c);
196
197 static int add_to_scan_list(struct ctlr_info *h);
198 static int scan_thread(void *data);
199 static int check_for_unit_attention(ctlr_info_t *h, CommandList_struct *c);
200 static void cciss_hba_release(struct device *dev);
201 static void cciss_device_release(struct device *dev);
202 static void cciss_free_gendisk(ctlr_info_t *h, int drv_index);
203 static void cciss_free_drive_info(ctlr_info_t *h, int drv_index);
204 static inline u32 next_command(ctlr_info_t *h);
205 static int cciss_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
206 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
207 u64 *cfg_offset);
208 static int cciss_pci_find_memory_BAR(struct pci_dev *pdev,
209 unsigned long *memory_bar);
210 static inline u32 cciss_tag_discard_error_bits(ctlr_info_t *h, u32 tag);
211 static int write_driver_ver_to_cfgtable(CfgTable_struct __iomem *cfgtable);
212
213 /* performant mode helper functions */
214 static void calc_bucket_map(int *bucket, int num_buckets, int nsgs,
215 int *bucket_map);
216 static void cciss_put_controller_into_performant_mode(ctlr_info_t *h);
217
218 #ifdef CONFIG_PROC_FS
219 static void cciss_procinit(ctlr_info_t *h);
220 #else
221 static void cciss_procinit(ctlr_info_t *h)
222 {
223 }
224 #endif /* CONFIG_PROC_FS */
225
226 #ifdef CONFIG_COMPAT
227 static int cciss_compat_ioctl(struct block_device *, fmode_t,
228 unsigned, unsigned long);
229 #endif
230
231 static const struct block_device_operations cciss_fops = {
232 .owner = THIS_MODULE,
233 .open = cciss_unlocked_open,
234 .release = cciss_release,
235 .ioctl = cciss_ioctl,
236 .getgeo = cciss_getgeo,
237 #ifdef CONFIG_COMPAT
238 .compat_ioctl = cciss_compat_ioctl,
239 #endif
240 .revalidate_disk = cciss_revalidate,
241 };
242
243 /* set_performant_mode: Modify the tag for cciss performant
244 * set bit 0 for pull model, bits 3-1 for block fetch
245 * register number
246 */
247 static void set_performant_mode(ctlr_info_t *h, CommandList_struct *c)
248 {
249 if (likely(h->transMethod & CFGTBL_Trans_Performant))
250 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
251 }
252
253 /*
254 * Enqueuing and dequeuing functions for cmdlists.
255 */
256 static inline void addQ(struct list_head *list, CommandList_struct *c)
257 {
258 list_add_tail(&c->list, list);
259 }
260
261 static inline void removeQ(CommandList_struct *c)
262 {
263 /*
264 * After kexec/dump some commands might still
265 * be in flight, which the firmware will try
266 * to complete. Resetting the firmware doesn't work
267 * with old fw revisions, so we have to mark
268 * them off as 'stale' to prevent the driver from
269 * falling over.
270 */
271 if (WARN_ON(list_empty(&c->list))) {
272 c->cmd_type = CMD_MSG_STALE;
273 return;
274 }
275
276 list_del_init(&c->list);
277 }
278
279 static void enqueue_cmd_and_start_io(ctlr_info_t *h,
280 CommandList_struct *c)
281 {
282 unsigned long flags;
283 set_performant_mode(h, c);
284 spin_lock_irqsave(&h->lock, flags);
285 addQ(&h->reqQ, c);
286 h->Qdepth++;
287 if (h->Qdepth > h->maxQsinceinit)
288 h->maxQsinceinit = h->Qdepth;
289 start_io(h);
290 spin_unlock_irqrestore(&h->lock, flags);
291 }
292
293 static void cciss_free_sg_chain_blocks(SGDescriptor_struct **cmd_sg_list,
294 int nr_cmds)
295 {
296 int i;
297
298 if (!cmd_sg_list)
299 return;
300 for (i = 0; i < nr_cmds; i++) {
301 kfree(cmd_sg_list[i]);
302 cmd_sg_list[i] = NULL;
303 }
304 kfree(cmd_sg_list);
305 }
306
307 static SGDescriptor_struct **cciss_allocate_sg_chain_blocks(
308 ctlr_info_t *h, int chainsize, int nr_cmds)
309 {
310 int j;
311 SGDescriptor_struct **cmd_sg_list;
312
313 if (chainsize <= 0)
314 return NULL;
315
316 cmd_sg_list = kmalloc(sizeof(*cmd_sg_list) * nr_cmds, GFP_KERNEL);
317 if (!cmd_sg_list)
318 return NULL;
319
320 /* Build up chain blocks for each command */
321 for (j = 0; j < nr_cmds; j++) {
322 /* Need a block of chainsized s/g elements. */
323 cmd_sg_list[j] = kmalloc((chainsize *
324 sizeof(*cmd_sg_list[j])), GFP_KERNEL);
325 if (!cmd_sg_list[j]) {
326 dev_err(&h->pdev->dev, "Cannot get memory "
327 "for s/g chains.\n");
328 goto clean;
329 }
330 }
331 return cmd_sg_list;
332 clean:
333 cciss_free_sg_chain_blocks(cmd_sg_list, nr_cmds);
334 return NULL;
335 }
336
337 static void cciss_unmap_sg_chain_block(ctlr_info_t *h, CommandList_struct *c)
338 {
339 SGDescriptor_struct *chain_sg;
340 u64bit temp64;
341
342 if (c->Header.SGTotal <= h->max_cmd_sgentries)
343 return;
344
345 chain_sg = &c->SG[h->max_cmd_sgentries - 1];
346 temp64.val32.lower = chain_sg->Addr.lower;
347 temp64.val32.upper = chain_sg->Addr.upper;
348 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
349 }
350
351 static void cciss_map_sg_chain_block(ctlr_info_t *h, CommandList_struct *c,
352 SGDescriptor_struct *chain_block, int len)
353 {
354 SGDescriptor_struct *chain_sg;
355 u64bit temp64;
356
357 chain_sg = &c->SG[h->max_cmd_sgentries - 1];
358 chain_sg->Ext = CCISS_SG_CHAIN;
359 chain_sg->Len = len;
360 temp64.val = pci_map_single(h->pdev, chain_block, len,
361 PCI_DMA_TODEVICE);
362 chain_sg->Addr.lower = temp64.val32.lower;
363 chain_sg->Addr.upper = temp64.val32.upper;
364 }
365
366 #include "cciss_scsi.c" /* For SCSI tape support */
367
368 static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
369 "UNKNOWN"
370 };
371 #define RAID_UNKNOWN (ARRAY_SIZE(raid_label)-1)
372
373 #ifdef CONFIG_PROC_FS
374
375 /*
376 * Report information about this controller.
377 */
378 #define ENG_GIG 1000000000
379 #define ENG_GIG_FACTOR (ENG_GIG/512)
380 #define ENGAGE_SCSI "engage scsi"
381
382 static void cciss_seq_show_header(struct seq_file *seq)
383 {
384 ctlr_info_t *h = seq->private;
385
386 seq_printf(seq, "%s: HP %s Controller\n"
387 "Board ID: 0x%08lx\n"
388 "Firmware Version: %c%c%c%c\n"
389 "IRQ: %d\n"
390 "Logical drives: %d\n"
391 "Current Q depth: %d\n"
392 "Current # commands on controller: %d\n"
393 "Max Q depth since init: %d\n"
394 "Max # commands on controller since init: %d\n"
395 "Max SG entries since init: %d\n",
396 h->devname,
397 h->product_name,
398 (unsigned long)h->board_id,
399 h->firm_ver[0], h->firm_ver[1], h->firm_ver[2],
400 h->firm_ver[3], (unsigned int)h->intr[h->intr_mode],
401 h->num_luns,
402 h->Qdepth, h->commands_outstanding,
403 h->maxQsinceinit, h->max_outstanding, h->maxSG);
404
405 #ifdef CONFIG_CISS_SCSI_TAPE
406 cciss_seq_tape_report(seq, h);
407 #endif /* CONFIG_CISS_SCSI_TAPE */
408 }
409
410 static void *cciss_seq_start(struct seq_file *seq, loff_t *pos)
411 {
412 ctlr_info_t *h = seq->private;
413 unsigned long flags;
414
415 /* prevent displaying bogus info during configuration
416 * or deconfiguration of a logical volume
417 */
418 spin_lock_irqsave(&h->lock, flags);
419 if (h->busy_configuring) {
420 spin_unlock_irqrestore(&h->lock, flags);
421 return ERR_PTR(-EBUSY);
422 }
423 h->busy_configuring = 1;
424 spin_unlock_irqrestore(&h->lock, flags);
425
426 if (*pos == 0)
427 cciss_seq_show_header(seq);
428
429 return pos;
430 }
431
432 static int cciss_seq_show(struct seq_file *seq, void *v)
433 {
434 sector_t vol_sz, vol_sz_frac;
435 ctlr_info_t *h = seq->private;
436 unsigned ctlr = h->ctlr;
437 loff_t *pos = v;
438 drive_info_struct *drv = h->drv[*pos];
439
440 if (*pos > h->highest_lun)
441 return 0;
442
443 if (drv == NULL) /* it's possible for h->drv[] to have holes. */
444 return 0;
445
446 if (drv->heads == 0)
447 return 0;
448
449 vol_sz = drv->nr_blocks;
450 vol_sz_frac = sector_div(vol_sz, ENG_GIG_FACTOR);
451 vol_sz_frac *= 100;
452 sector_div(vol_sz_frac, ENG_GIG_FACTOR);
453
454 if (drv->raid_level < 0 || drv->raid_level > RAID_UNKNOWN)
455 drv->raid_level = RAID_UNKNOWN;
456 seq_printf(seq, "cciss/c%dd%d:"
457 "\t%4u.%02uGB\tRAID %s\n",
458 ctlr, (int) *pos, (int)vol_sz, (int)vol_sz_frac,
459 raid_label[drv->raid_level]);
460 return 0;
461 }
462
463 static void *cciss_seq_next(struct seq_file *seq, void *v, loff_t *pos)
464 {
465 ctlr_info_t *h = seq->private;
466
467 if (*pos > h->highest_lun)
468 return NULL;
469 *pos += 1;
470
471 return pos;
472 }
473
474 static void cciss_seq_stop(struct seq_file *seq, void *v)
475 {
476 ctlr_info_t *h = seq->private;
477
478 /* Only reset h->busy_configuring if we succeeded in setting
479 * it during cciss_seq_start. */
480 if (v == ERR_PTR(-EBUSY))
481 return;
482
483 h->busy_configuring = 0;
484 }
485
486 static const struct seq_operations cciss_seq_ops = {
487 .start = cciss_seq_start,
488 .show = cciss_seq_show,
489 .next = cciss_seq_next,
490 .stop = cciss_seq_stop,
491 };
492
493 static int cciss_seq_open(struct inode *inode, struct file *file)
494 {
495 int ret = seq_open(file, &cciss_seq_ops);
496 struct seq_file *seq = file->private_data;
497
498 if (!ret)
499 seq->private = PDE_DATA(inode);
500
501 return ret;
502 }
503
504 static ssize_t
505 cciss_proc_write(struct file *file, const char __user *buf,
506 size_t length, loff_t *ppos)
507 {
508 int err;
509 char *buffer;
510
511 #ifndef CONFIG_CISS_SCSI_TAPE
512 return -EINVAL;
513 #endif
514
515 if (!buf || length > PAGE_SIZE - 1)
516 return -EINVAL;
517
518 buffer = memdup_user_nul(buf, length);
519 if (IS_ERR(buffer))
520 return PTR_ERR(buffer);
521
522 #ifdef CONFIG_CISS_SCSI_TAPE
523 if (strncmp(ENGAGE_SCSI, buffer, sizeof ENGAGE_SCSI - 1) == 0) {
524 struct seq_file *seq = file->private_data;
525 ctlr_info_t *h = seq->private;
526
527 err = cciss_engage_scsi(h);
528 if (err == 0)
529 err = length;
530 } else
531 #endif /* CONFIG_CISS_SCSI_TAPE */
532 err = -EINVAL;
533 /* might be nice to have "disengage" too, but it's not
534 safely possible. (only 1 module use count, lock issues.) */
535
536 kfree(buffer);
537 return err;
538 }
539
540 static const struct file_operations cciss_proc_fops = {
541 .owner = THIS_MODULE,
542 .open = cciss_seq_open,
543 .read = seq_read,
544 .llseek = seq_lseek,
545 .release = seq_release,
546 .write = cciss_proc_write,
547 };
548
549 static void cciss_procinit(ctlr_info_t *h)
550 {
551 struct proc_dir_entry *pde;
552
553 if (proc_cciss == NULL)
554 proc_cciss = proc_mkdir("driver/cciss", NULL);
555 if (!proc_cciss)
556 return;
557 pde = proc_create_data(h->devname, S_IWUSR | S_IRUSR | S_IRGRP |
558 S_IROTH, proc_cciss,
559 &cciss_proc_fops, h);
560 }
561 #endif /* CONFIG_PROC_FS */
562
563 #define MAX_PRODUCT_NAME_LEN 19
564
565 #define to_hba(n) container_of(n, struct ctlr_info, dev)
566 #define to_drv(n) container_of(n, drive_info_struct, dev)
567
568 /* List of controllers which cannot be hard reset on kexec with reset_devices */
569 static u32 unresettable_controller[] = {
570 0x3223103C, /* Smart Array P800 */
571 0x3234103C, /* Smart Array P400 */
572 0x3235103C, /* Smart Array P400i */
573 0x3211103C, /* Smart Array E200i */
574 0x3212103C, /* Smart Array E200 */
575 0x3213103C, /* Smart Array E200i */
576 0x3214103C, /* Smart Array E200i */
577 0x3215103C, /* Smart Array E200i */
578 0x3237103C, /* Smart Array E500 */
579 0x323D103C, /* Smart Array P700m */
580 0x40800E11, /* Smart Array 5i */
581 0x409C0E11, /* Smart Array 6400 */
582 0x409D0E11, /* Smart Array 6400 EM */
583 0x40700E11, /* Smart Array 5300 */
584 0x40820E11, /* Smart Array 532 */
585 0x40830E11, /* Smart Array 5312 */
586 0x409A0E11, /* Smart Array 641 */
587 0x409B0E11, /* Smart Array 642 */
588 0x40910E11, /* Smart Array 6i */
589 };
590
591 /* List of controllers which cannot even be soft reset */
592 static u32 soft_unresettable_controller[] = {
593 0x40800E11, /* Smart Array 5i */
594 0x40700E11, /* Smart Array 5300 */
595 0x40820E11, /* Smart Array 532 */
596 0x40830E11, /* Smart Array 5312 */
597 0x409A0E11, /* Smart Array 641 */
598 0x409B0E11, /* Smart Array 642 */
599 0x40910E11, /* Smart Array 6i */
600 /* Exclude 640x boards. These are two pci devices in one slot
601 * which share a battery backed cache module. One controls the
602 * cache, the other accesses the cache through the one that controls
603 * it. If we reset the one controlling the cache, the other will
604 * likely not be happy. Just forbid resetting this conjoined mess.
605 */
606 0x409C0E11, /* Smart Array 6400 */
607 0x409D0E11, /* Smart Array 6400 EM */
608 };
609
610 static int ctlr_is_hard_resettable(u32 board_id)
611 {
612 int i;
613
614 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
615 if (unresettable_controller[i] == board_id)
616 return 0;
617 return 1;
618 }
619
620 static int ctlr_is_soft_resettable(u32 board_id)
621 {
622 int i;
623
624 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
625 if (soft_unresettable_controller[i] == board_id)
626 return 0;
627 return 1;
628 }
629
630 static int ctlr_is_resettable(u32 board_id)
631 {
632 return ctlr_is_hard_resettable(board_id) ||
633 ctlr_is_soft_resettable(board_id);
634 }
635
636 static ssize_t host_show_resettable(struct device *dev,
637 struct device_attribute *attr,
638 char *buf)
639 {
640 struct ctlr_info *h = to_hba(dev);
641
642 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
643 }
644 static DEVICE_ATTR(resettable, S_IRUGO, host_show_resettable, NULL);
645
646 static ssize_t host_store_rescan(struct device *dev,
647 struct device_attribute *attr,
648 const char *buf, size_t count)
649 {
650 struct ctlr_info *h = to_hba(dev);
651
652 add_to_scan_list(h);
653 wake_up_process(cciss_scan_thread);
654 wait_for_completion_interruptible(&h->scan_wait);
655
656 return count;
657 }
658 static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
659
660 static ssize_t host_show_transport_mode(struct device *dev,
661 struct device_attribute *attr,
662 char *buf)
663 {
664 struct ctlr_info *h = to_hba(dev);
665
666 return snprintf(buf, 20, "%s\n",
667 h->transMethod & CFGTBL_Trans_Performant ?
668 "performant" : "simple");
669 }
670 static DEVICE_ATTR(transport_mode, S_IRUGO, host_show_transport_mode, NULL);
671
672 static ssize_t dev_show_unique_id(struct device *dev,
673 struct device_attribute *attr,
674 char *buf)
675 {
676 drive_info_struct *drv = to_drv(dev);
677 struct ctlr_info *h = to_hba(drv->dev.parent);
678 __u8 sn[16];
679 unsigned long flags;
680 int ret = 0;
681
682 spin_lock_irqsave(&h->lock, flags);
683 if (h->busy_configuring)
684 ret = -EBUSY;
685 else
686 memcpy(sn, drv->serial_no, sizeof(sn));
687 spin_unlock_irqrestore(&h->lock, flags);
688
689 if (ret)
690 return ret;
691 else
692 return snprintf(buf, 16 * 2 + 2,
693 "%02X%02X%02X%02X%02X%02X%02X%02X"
694 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
695 sn[0], sn[1], sn[2], sn[3],
696 sn[4], sn[5], sn[6], sn[7],
697 sn[8], sn[9], sn[10], sn[11],
698 sn[12], sn[13], sn[14], sn[15]);
699 }
700 static DEVICE_ATTR(unique_id, S_IRUGO, dev_show_unique_id, NULL);
701
702 static ssize_t dev_show_vendor(struct device *dev,
703 struct device_attribute *attr,
704 char *buf)
705 {
706 drive_info_struct *drv = to_drv(dev);
707 struct ctlr_info *h = to_hba(drv->dev.parent);
708 char vendor[VENDOR_LEN + 1];
709 unsigned long flags;
710 int ret = 0;
711
712 spin_lock_irqsave(&h->lock, flags);
713 if (h->busy_configuring)
714 ret = -EBUSY;
715 else
716 memcpy(vendor, drv->vendor, VENDOR_LEN + 1);
717 spin_unlock_irqrestore(&h->lock, flags);
718
719 if (ret)
720 return ret;
721 else
722 return snprintf(buf, sizeof(vendor) + 1, "%s\n", drv->vendor);
723 }
724 static DEVICE_ATTR(vendor, S_IRUGO, dev_show_vendor, NULL);
725
726 static ssize_t dev_show_model(struct device *dev,
727 struct device_attribute *attr,
728 char *buf)
729 {
730 drive_info_struct *drv = to_drv(dev);
731 struct ctlr_info *h = to_hba(drv->dev.parent);
732 char model[MODEL_LEN + 1];
733 unsigned long flags;
734 int ret = 0;
735
736 spin_lock_irqsave(&h->lock, flags);
737 if (h->busy_configuring)
738 ret = -EBUSY;
739 else
740 memcpy(model, drv->model, MODEL_LEN + 1);
741 spin_unlock_irqrestore(&h->lock, flags);
742
743 if (ret)
744 return ret;
745 else
746 return snprintf(buf, sizeof(model) + 1, "%s\n", drv->model);
747 }
748 static DEVICE_ATTR(model, S_IRUGO, dev_show_model, NULL);
749
750 static ssize_t dev_show_rev(struct device *dev,
751 struct device_attribute *attr,
752 char *buf)
753 {
754 drive_info_struct *drv = to_drv(dev);
755 struct ctlr_info *h = to_hba(drv->dev.parent);
756 char rev[REV_LEN + 1];
757 unsigned long flags;
758 int ret = 0;
759
760 spin_lock_irqsave(&h->lock, flags);
761 if (h->busy_configuring)
762 ret = -EBUSY;
763 else
764 memcpy(rev, drv->rev, REV_LEN + 1);
765 spin_unlock_irqrestore(&h->lock, flags);
766
767 if (ret)
768 return ret;
769 else
770 return snprintf(buf, sizeof(rev) + 1, "%s\n", drv->rev);
771 }
772 static DEVICE_ATTR(rev, S_IRUGO, dev_show_rev, NULL);
773
774 static ssize_t cciss_show_lunid(struct device *dev,
775 struct device_attribute *attr, char *buf)
776 {
777 drive_info_struct *drv = to_drv(dev);
778 struct ctlr_info *h = to_hba(drv->dev.parent);
779 unsigned long flags;
780 unsigned char lunid[8];
781
782 spin_lock_irqsave(&h->lock, flags);
783 if (h->busy_configuring) {
784 spin_unlock_irqrestore(&h->lock, flags);
785 return -EBUSY;
786 }
787 if (!drv->heads) {
788 spin_unlock_irqrestore(&h->lock, flags);
789 return -ENOTTY;
790 }
791 memcpy(lunid, drv->LunID, sizeof(lunid));
792 spin_unlock_irqrestore(&h->lock, flags);
793 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
794 lunid[0], lunid[1], lunid[2], lunid[3],
795 lunid[4], lunid[5], lunid[6], lunid[7]);
796 }
797 static DEVICE_ATTR(lunid, S_IRUGO, cciss_show_lunid, NULL);
798
799 static ssize_t cciss_show_raid_level(struct device *dev,
800 struct device_attribute *attr, char *buf)
801 {
802 drive_info_struct *drv = to_drv(dev);
803 struct ctlr_info *h = to_hba(drv->dev.parent);
804 int raid;
805 unsigned long flags;
806
807 spin_lock_irqsave(&h->lock, flags);
808 if (h->busy_configuring) {
809 spin_unlock_irqrestore(&h->lock, flags);
810 return -EBUSY;
811 }
812 raid = drv->raid_level;
813 spin_unlock_irqrestore(&h->lock, flags);
814 if (raid < 0 || raid > RAID_UNKNOWN)
815 raid = RAID_UNKNOWN;
816
817 return snprintf(buf, strlen(raid_label[raid]) + 7, "RAID %s\n",
818 raid_label[raid]);
819 }
820 static DEVICE_ATTR(raid_level, S_IRUGO, cciss_show_raid_level, NULL);
821
822 static ssize_t cciss_show_usage_count(struct device *dev,
823 struct device_attribute *attr, char *buf)
824 {
825 drive_info_struct *drv = to_drv(dev);
826 struct ctlr_info *h = to_hba(drv->dev.parent);
827 unsigned long flags;
828 int count;
829
830 spin_lock_irqsave(&h->lock, flags);
831 if (h->busy_configuring) {
832 spin_unlock_irqrestore(&h->lock, flags);
833 return -EBUSY;
834 }
835 count = drv->usage_count;
836 spin_unlock_irqrestore(&h->lock, flags);
837 return snprintf(buf, 20, "%d\n", count);
838 }
839 static DEVICE_ATTR(usage_count, S_IRUGO, cciss_show_usage_count, NULL);
840
841 static struct attribute *cciss_host_attrs[] = {
842 &dev_attr_rescan.attr,
843 &dev_attr_resettable.attr,
844 &dev_attr_transport_mode.attr,
845 NULL
846 };
847
848 static struct attribute_group cciss_host_attr_group = {
849 .attrs = cciss_host_attrs,
850 };
851
852 static const struct attribute_group *cciss_host_attr_groups[] = {
853 &cciss_host_attr_group,
854 NULL
855 };
856
857 static struct device_type cciss_host_type = {
858 .name = "cciss_host",
859 .groups = cciss_host_attr_groups,
860 .release = cciss_hba_release,
861 };
862
863 static struct attribute *cciss_dev_attrs[] = {
864 &dev_attr_unique_id.attr,
865 &dev_attr_model.attr,
866 &dev_attr_vendor.attr,
867 &dev_attr_rev.attr,
868 &dev_attr_lunid.attr,
869 &dev_attr_raid_level.attr,
870 &dev_attr_usage_count.attr,
871 NULL
872 };
873
874 static struct attribute_group cciss_dev_attr_group = {
875 .attrs = cciss_dev_attrs,
876 };
877
878 static const struct attribute_group *cciss_dev_attr_groups[] = {
879 &cciss_dev_attr_group,
880 NULL
881 };
882
883 static struct device_type cciss_dev_type = {
884 .name = "cciss_device",
885 .groups = cciss_dev_attr_groups,
886 .release = cciss_device_release,
887 };
888
889 static struct bus_type cciss_bus_type = {
890 .name = "cciss",
891 };
892
893 /*
894 * cciss_hba_release is called when the reference count
895 * of h->dev goes to zero.
896 */
897 static void cciss_hba_release(struct device *dev)
898 {
899 /*
900 * nothing to do, but need this to avoid a warning
901 * about not having a release handler from lib/kref.c.
902 */
903 }
904
905 /*
906 * Initialize sysfs entry for each controller. This sets up and registers
907 * the 'cciss#' directory for each individual controller under
908 * /sys/bus/pci/devices/<dev>/.
909 */
910 static int cciss_create_hba_sysfs_entry(struct ctlr_info *h)
911 {
912 device_initialize(&h->dev);
913 h->dev.type = &cciss_host_type;
914 h->dev.bus = &cciss_bus_type;
915 dev_set_name(&h->dev, "%s", h->devname);
916 h->dev.parent = &h->pdev->dev;
917
918 return device_add(&h->dev);
919 }
920
921 /*
922 * Remove sysfs entries for an hba.
923 */
924 static void cciss_destroy_hba_sysfs_entry(struct ctlr_info *h)
925 {
926 device_del(&h->dev);
927 put_device(&h->dev); /* final put. */
928 }
929
930 /* cciss_device_release is called when the reference count
931 * of h->drv[x]dev goes to zero.
932 */
933 static void cciss_device_release(struct device *dev)
934 {
935 drive_info_struct *drv = to_drv(dev);
936 kfree(drv);
937 }
938
939 /*
940 * Initialize sysfs for each logical drive. This sets up and registers
941 * the 'c#d#' directory for each individual logical drive under
942 * /sys/bus/pci/devices/<dev/ccis#/. We also create a link from
943 * /sys/block/cciss!c#d# to this entry.
944 */
945 static long cciss_create_ld_sysfs_entry(struct ctlr_info *h,
946 int drv_index)
947 {
948 struct device *dev;
949
950 if (h->drv[drv_index]->device_initialized)
951 return 0;
952
953 dev = &h->drv[drv_index]->dev;
954 device_initialize(dev);
955 dev->type = &cciss_dev_type;
956 dev->bus = &cciss_bus_type;
957 dev_set_name(dev, "c%dd%d", h->ctlr, drv_index);
958 dev->parent = &h->dev;
959 h->drv[drv_index]->device_initialized = 1;
960 return device_add(dev);
961 }
962
963 /*
964 * Remove sysfs entries for a logical drive.
965 */
966 static void cciss_destroy_ld_sysfs_entry(struct ctlr_info *h, int drv_index,
967 int ctlr_exiting)
968 {
969 struct device *dev = &h->drv[drv_index]->dev;
970
971 /* special case for c*d0, we only destroy it on controller exit */
972 if (drv_index == 0 && !ctlr_exiting)
973 return;
974
975 device_del(dev);
976 put_device(dev); /* the "final" put. */
977 h->drv[drv_index] = NULL;
978 }
979
980 /*
981 * For operations that cannot sleep, a command block is allocated at init,
982 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
983 * which ones are free or in use.
984 */
985 static CommandList_struct *cmd_alloc(ctlr_info_t *h)
986 {
987 CommandList_struct *c;
988 int i;
989 u64bit temp64;
990 dma_addr_t cmd_dma_handle, err_dma_handle;
991
992 do {
993 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
994 if (i == h->nr_cmds)
995 return NULL;
996 } while (test_and_set_bit(i, h->cmd_pool_bits) != 0);
997 c = h->cmd_pool + i;
998 memset(c, 0, sizeof(CommandList_struct));
999 cmd_dma_handle = h->cmd_pool_dhandle + i * sizeof(CommandList_struct);
1000 c->err_info = h->errinfo_pool + i;
1001 memset(c->err_info, 0, sizeof(ErrorInfo_struct));
1002 err_dma_handle = h->errinfo_pool_dhandle
1003 + i * sizeof(ErrorInfo_struct);
1004 h->nr_allocs++;
1005
1006 c->cmdindex = i;
1007
1008 INIT_LIST_HEAD(&c->list);
1009 c->busaddr = (__u32) cmd_dma_handle;
1010 temp64.val = (__u64) err_dma_handle;
1011 c->ErrDesc.Addr.lower = temp64.val32.lower;
1012 c->ErrDesc.Addr.upper = temp64.val32.upper;
1013 c->ErrDesc.Len = sizeof(ErrorInfo_struct);
1014
1015 c->ctlr = h->ctlr;
1016 return c;
1017 }
1018
1019 /* allocate a command using pci_alloc_consistent, used for ioctls,
1020 * etc., not for the main i/o path.
1021 */
1022 static CommandList_struct *cmd_special_alloc(ctlr_info_t *h)
1023 {
1024 CommandList_struct *c;
1025 u64bit temp64;
1026 dma_addr_t cmd_dma_handle, err_dma_handle;
1027
1028 c = pci_zalloc_consistent(h->pdev, sizeof(CommandList_struct),
1029 &cmd_dma_handle);
1030 if (c == NULL)
1031 return NULL;
1032
1033 c->cmdindex = -1;
1034
1035 c->err_info = pci_zalloc_consistent(h->pdev, sizeof(ErrorInfo_struct),
1036 &err_dma_handle);
1037
1038 if (c->err_info == NULL) {
1039 pci_free_consistent(h->pdev,
1040 sizeof(CommandList_struct), c, cmd_dma_handle);
1041 return NULL;
1042 }
1043
1044 INIT_LIST_HEAD(&c->list);
1045 c->busaddr = (__u32) cmd_dma_handle;
1046 temp64.val = (__u64) err_dma_handle;
1047 c->ErrDesc.Addr.lower = temp64.val32.lower;
1048 c->ErrDesc.Addr.upper = temp64.val32.upper;
1049 c->ErrDesc.Len = sizeof(ErrorInfo_struct);
1050
1051 c->ctlr = h->ctlr;
1052 return c;
1053 }
1054
1055 static void cmd_free(ctlr_info_t *h, CommandList_struct *c)
1056 {
1057 int i;
1058
1059 i = c - h->cmd_pool;
1060 clear_bit(i, h->cmd_pool_bits);
1061 h->nr_frees++;
1062 }
1063
1064 static void cmd_special_free(ctlr_info_t *h, CommandList_struct *c)
1065 {
1066 u64bit temp64;
1067
1068 temp64.val32.lower = c->ErrDesc.Addr.lower;
1069 temp64.val32.upper = c->ErrDesc.Addr.upper;
1070 pci_free_consistent(h->pdev, sizeof(ErrorInfo_struct),
1071 c->err_info, (dma_addr_t) temp64.val);
1072 pci_free_consistent(h->pdev, sizeof(CommandList_struct), c,
1073 (dma_addr_t) cciss_tag_discard_error_bits(h, (u32) c->busaddr));
1074 }
1075
1076 static inline ctlr_info_t *get_host(struct gendisk *disk)
1077 {
1078 return disk->queue->queuedata;
1079 }
1080
1081 static inline drive_info_struct *get_drv(struct gendisk *disk)
1082 {
1083 return disk->private_data;
1084 }
1085
1086 /*
1087 * Open. Make sure the device is really there.
1088 */
1089 static int cciss_open(struct block_device *bdev, fmode_t mode)
1090 {
1091 ctlr_info_t *h = get_host(bdev->bd_disk);
1092 drive_info_struct *drv = get_drv(bdev->bd_disk);
1093
1094 dev_dbg(&h->pdev->dev, "cciss_open %s\n", bdev->bd_disk->disk_name);
1095 if (drv->busy_configuring)
1096 return -EBUSY;
1097 /*
1098 * Root is allowed to open raw volume zero even if it's not configured
1099 * so array config can still work. Root is also allowed to open any
1100 * volume that has a LUN ID, so it can issue IOCTL to reread the
1101 * disk information. I don't think I really like this
1102 * but I'm already using way to many device nodes to claim another one
1103 * for "raw controller".
1104 */
1105 if (drv->heads == 0) {
1106 if (MINOR(bdev->bd_dev) != 0) { /* not node 0? */
1107 /* if not node 0 make sure it is a partition = 0 */
1108 if (MINOR(bdev->bd_dev) & 0x0f) {
1109 return -ENXIO;
1110 /* if it is, make sure we have a LUN ID */
1111 } else if (memcmp(drv->LunID, CTLR_LUNID,
1112 sizeof(drv->LunID))) {
1113 return -ENXIO;
1114 }
1115 }
1116 if (!capable(CAP_SYS_ADMIN))
1117 return -EPERM;
1118 }
1119 drv->usage_count++;
1120 h->usage_count++;
1121 return 0;
1122 }
1123
1124 static int cciss_unlocked_open(struct block_device *bdev, fmode_t mode)
1125 {
1126 int ret;
1127
1128 mutex_lock(&cciss_mutex);
1129 ret = cciss_open(bdev, mode);
1130 mutex_unlock(&cciss_mutex);
1131
1132 return ret;
1133 }
1134
1135 /*
1136 * Close. Sync first.
1137 */
1138 static void cciss_release(struct gendisk *disk, fmode_t mode)
1139 {
1140 ctlr_info_t *h;
1141 drive_info_struct *drv;
1142
1143 mutex_lock(&cciss_mutex);
1144 h = get_host(disk);
1145 drv = get_drv(disk);
1146 dev_dbg(&h->pdev->dev, "cciss_release %s\n", disk->disk_name);
1147 drv->usage_count--;
1148 h->usage_count--;
1149 mutex_unlock(&cciss_mutex);
1150 }
1151
1152 #ifdef CONFIG_COMPAT
1153
1154 static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
1155 unsigned cmd, unsigned long arg);
1156 static int cciss_ioctl32_big_passthru(struct block_device *bdev, fmode_t mode,
1157 unsigned cmd, unsigned long arg);
1158
1159 static int cciss_compat_ioctl(struct block_device *bdev, fmode_t mode,
1160 unsigned cmd, unsigned long arg)
1161 {
1162 switch (cmd) {
1163 case CCISS_GETPCIINFO:
1164 case CCISS_GETINTINFO:
1165 case CCISS_SETINTINFO:
1166 case CCISS_GETNODENAME:
1167 case CCISS_SETNODENAME:
1168 case CCISS_GETHEARTBEAT:
1169 case CCISS_GETBUSTYPES:
1170 case CCISS_GETFIRMVER:
1171 case CCISS_GETDRIVVER:
1172 case CCISS_REVALIDVOLS:
1173 case CCISS_DEREGDISK:
1174 case CCISS_REGNEWDISK:
1175 case CCISS_REGNEWD:
1176 case CCISS_RESCANDISK:
1177 case CCISS_GETLUNINFO:
1178 return cciss_ioctl(bdev, mode, cmd, arg);
1179
1180 case CCISS_PASSTHRU32:
1181 return cciss_ioctl32_passthru(bdev, mode, cmd, arg);
1182 case CCISS_BIG_PASSTHRU32:
1183 return cciss_ioctl32_big_passthru(bdev, mode, cmd, arg);
1184
1185 default:
1186 return -ENOIOCTLCMD;
1187 }
1188 }
1189
1190 static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
1191 unsigned cmd, unsigned long arg)
1192 {
1193 IOCTL32_Command_struct __user *arg32 =
1194 (IOCTL32_Command_struct __user *) arg;
1195 IOCTL_Command_struct arg64;
1196 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
1197 int err;
1198 u32 cp;
1199
1200 memset(&arg64, 0, sizeof(arg64));
1201 err = 0;
1202 err |=
1203 copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
1204 sizeof(arg64.LUN_info));
1205 err |=
1206 copy_from_user(&arg64.Request, &arg32->Request,
1207 sizeof(arg64.Request));
1208 err |=
1209 copy_from_user(&arg64.error_info, &arg32->error_info,
1210 sizeof(arg64.error_info));
1211 err |= get_user(arg64.buf_size, &arg32->buf_size);
1212 err |= get_user(cp, &arg32->buf);
1213 arg64.buf = compat_ptr(cp);
1214 err |= copy_to_user(p, &arg64, sizeof(arg64));
1215
1216 if (err)
1217 return -EFAULT;
1218
1219 err = cciss_ioctl(bdev, mode, CCISS_PASSTHRU, (unsigned long)p);
1220 if (err)
1221 return err;
1222 err |=
1223 copy_in_user(&arg32->error_info, &p->error_info,
1224 sizeof(arg32->error_info));
1225 if (err)
1226 return -EFAULT;
1227 return err;
1228 }
1229
1230 static int cciss_ioctl32_big_passthru(struct block_device *bdev, fmode_t mode,
1231 unsigned cmd, unsigned long arg)
1232 {
1233 BIG_IOCTL32_Command_struct __user *arg32 =
1234 (BIG_IOCTL32_Command_struct __user *) arg;
1235 BIG_IOCTL_Command_struct arg64;
1236 BIG_IOCTL_Command_struct __user *p =
1237 compat_alloc_user_space(sizeof(arg64));
1238 int err;
1239 u32 cp;
1240
1241 memset(&arg64, 0, sizeof(arg64));
1242 err = 0;
1243 err |=
1244 copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
1245 sizeof(arg64.LUN_info));
1246 err |=
1247 copy_from_user(&arg64.Request, &arg32->Request,
1248 sizeof(arg64.Request));
1249 err |=
1250 copy_from_user(&arg64.error_info, &arg32->error_info,
1251 sizeof(arg64.error_info));
1252 err |= get_user(arg64.buf_size, &arg32->buf_size);
1253 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
1254 err |= get_user(cp, &arg32->buf);
1255 arg64.buf = compat_ptr(cp);
1256 err |= copy_to_user(p, &arg64, sizeof(arg64));
1257
1258 if (err)
1259 return -EFAULT;
1260
1261 err = cciss_ioctl(bdev, mode, CCISS_BIG_PASSTHRU, (unsigned long)p);
1262 if (err)
1263 return err;
1264 err |=
1265 copy_in_user(&arg32->error_info, &p->error_info,
1266 sizeof(arg32->error_info));
1267 if (err)
1268 return -EFAULT;
1269 return err;
1270 }
1271 #endif
1272
1273 static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1274 {
1275 drive_info_struct *drv = get_drv(bdev->bd_disk);
1276
1277 if (!drv->cylinders)
1278 return -ENXIO;
1279
1280 geo->heads = drv->heads;
1281 geo->sectors = drv->sectors;
1282 geo->cylinders = drv->cylinders;
1283 return 0;
1284 }
1285
1286 static void check_ioctl_unit_attention(ctlr_info_t *h, CommandList_struct *c)
1287 {
1288 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
1289 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
1290 (void)check_for_unit_attention(h, c);
1291 }
1292
1293 static int cciss_getpciinfo(ctlr_info_t *h, void __user *argp)
1294 {
1295 cciss_pci_info_struct pciinfo;
1296
1297 if (!argp)
1298 return -EINVAL;
1299 pciinfo.domain = pci_domain_nr(h->pdev->bus);
1300 pciinfo.bus = h->pdev->bus->number;
1301 pciinfo.dev_fn = h->pdev->devfn;
1302 pciinfo.board_id = h->board_id;
1303 if (copy_to_user(argp, &pciinfo, sizeof(cciss_pci_info_struct)))
1304 return -EFAULT;
1305 return 0;
1306 }
1307
1308 static int cciss_getintinfo(ctlr_info_t *h, void __user *argp)
1309 {
1310 cciss_coalint_struct intinfo;
1311 unsigned long flags;
1312
1313 if (!argp)
1314 return -EINVAL;
1315 spin_lock_irqsave(&h->lock, flags);
1316 intinfo.delay = readl(&h->cfgtable->HostWrite.CoalIntDelay);
1317 intinfo.count = readl(&h->cfgtable->HostWrite.CoalIntCount);
1318 spin_unlock_irqrestore(&h->lock, flags);
1319 if (copy_to_user
1320 (argp, &intinfo, sizeof(cciss_coalint_struct)))
1321 return -EFAULT;
1322 return 0;
1323 }
1324
1325 static int cciss_setintinfo(ctlr_info_t *h, void __user *argp)
1326 {
1327 cciss_coalint_struct intinfo;
1328 unsigned long flags;
1329 int i;
1330
1331 if (!argp)
1332 return -EINVAL;
1333 if (!capable(CAP_SYS_ADMIN))
1334 return -EPERM;
1335 if (copy_from_user(&intinfo, argp, sizeof(intinfo)))
1336 return -EFAULT;
1337 if ((intinfo.delay == 0) && (intinfo.count == 0))
1338 return -EINVAL;
1339 spin_lock_irqsave(&h->lock, flags);
1340 /* Update the field, and then ring the doorbell */
1341 writel(intinfo.delay, &(h->cfgtable->HostWrite.CoalIntDelay));
1342 writel(intinfo.count, &(h->cfgtable->HostWrite.CoalIntCount));
1343 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
1344
1345 for (i = 0; i < MAX_IOCTL_CONFIG_WAIT; i++) {
1346 if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
1347 break;
1348 udelay(1000); /* delay and try again */
1349 }
1350 spin_unlock_irqrestore(&h->lock, flags);
1351 if (i >= MAX_IOCTL_CONFIG_WAIT)
1352 return -EAGAIN;
1353 return 0;
1354 }
1355
1356 static int cciss_getnodename(ctlr_info_t *h, void __user *argp)
1357 {
1358 NodeName_type NodeName;
1359 unsigned long flags;
1360 int i;
1361
1362 if (!argp)
1363 return -EINVAL;
1364 spin_lock_irqsave(&h->lock, flags);
1365 for (i = 0; i < 16; i++)
1366 NodeName[i] = readb(&h->cfgtable->ServerName[i]);
1367 spin_unlock_irqrestore(&h->lock, flags);
1368 if (copy_to_user(argp, NodeName, sizeof(NodeName_type)))
1369 return -EFAULT;
1370 return 0;
1371 }
1372
1373 static int cciss_setnodename(ctlr_info_t *h, void __user *argp)
1374 {
1375 NodeName_type NodeName;
1376 unsigned long flags;
1377 int i;
1378
1379 if (!argp)
1380 return -EINVAL;
1381 if (!capable(CAP_SYS_ADMIN))
1382 return -EPERM;
1383 if (copy_from_user(NodeName, argp, sizeof(NodeName_type)))
1384 return -EFAULT;
1385 spin_lock_irqsave(&h->lock, flags);
1386 /* Update the field, and then ring the doorbell */
1387 for (i = 0; i < 16; i++)
1388 writeb(NodeName[i], &h->cfgtable->ServerName[i]);
1389 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
1390 for (i = 0; i < MAX_IOCTL_CONFIG_WAIT; i++) {
1391 if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
1392 break;
1393 udelay(1000); /* delay and try again */
1394 }
1395 spin_unlock_irqrestore(&h->lock, flags);
1396 if (i >= MAX_IOCTL_CONFIG_WAIT)
1397 return -EAGAIN;
1398 return 0;
1399 }
1400
1401 static int cciss_getheartbeat(ctlr_info_t *h, void __user *argp)
1402 {
1403 Heartbeat_type heartbeat;
1404 unsigned long flags;
1405
1406 if (!argp)
1407 return -EINVAL;
1408 spin_lock_irqsave(&h->lock, flags);
1409 heartbeat = readl(&h->cfgtable->HeartBeat);
1410 spin_unlock_irqrestore(&h->lock, flags);
1411 if (copy_to_user(argp, &heartbeat, sizeof(Heartbeat_type)))
1412 return -EFAULT;
1413 return 0;
1414 }
1415
1416 static int cciss_getbustypes(ctlr_info_t *h, void __user *argp)
1417 {
1418 BusTypes_type BusTypes;
1419 unsigned long flags;
1420
1421 if (!argp)
1422 return -EINVAL;
1423 spin_lock_irqsave(&h->lock, flags);
1424 BusTypes = readl(&h->cfgtable->BusTypes);
1425 spin_unlock_irqrestore(&h->lock, flags);
1426 if (copy_to_user(argp, &BusTypes, sizeof(BusTypes_type)))
1427 return -EFAULT;
1428 return 0;
1429 }
1430
1431 static int cciss_getfirmver(ctlr_info_t *h, void __user *argp)
1432 {
1433 FirmwareVer_type firmware;
1434
1435 if (!argp)
1436 return -EINVAL;
1437 memcpy(firmware, h->firm_ver, 4);
1438
1439 if (copy_to_user
1440 (argp, firmware, sizeof(FirmwareVer_type)))
1441 return -EFAULT;
1442 return 0;
1443 }
1444
1445 static int cciss_getdrivver(ctlr_info_t *h, void __user *argp)
1446 {
1447 DriverVer_type DriverVer = DRIVER_VERSION;
1448
1449 if (!argp)
1450 return -EINVAL;
1451 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
1452 return -EFAULT;
1453 return 0;
1454 }
1455
1456 static int cciss_getluninfo(ctlr_info_t *h,
1457 struct gendisk *disk, void __user *argp)
1458 {
1459 LogvolInfo_struct luninfo;
1460 drive_info_struct *drv = get_drv(disk);
1461
1462 if (!argp)
1463 return -EINVAL;
1464 memcpy(&luninfo.LunID, drv->LunID, sizeof(luninfo.LunID));
1465 luninfo.num_opens = drv->usage_count;
1466 luninfo.num_parts = 0;
1467 if (copy_to_user(argp, &luninfo, sizeof(LogvolInfo_struct)))
1468 return -EFAULT;
1469 return 0;
1470 }
1471
1472 static int cciss_passthru(ctlr_info_t *h, void __user *argp)
1473 {
1474 IOCTL_Command_struct iocommand;
1475 CommandList_struct *c;
1476 char *buff = NULL;
1477 u64bit temp64;
1478 DECLARE_COMPLETION_ONSTACK(wait);
1479
1480 if (!argp)
1481 return -EINVAL;
1482
1483 if (!capable(CAP_SYS_RAWIO))
1484 return -EPERM;
1485
1486 if (copy_from_user
1487 (&iocommand, argp, sizeof(IOCTL_Command_struct)))
1488 return -EFAULT;
1489 if ((iocommand.buf_size < 1) &&
1490 (iocommand.Request.Type.Direction != XFER_NONE)) {
1491 return -EINVAL;
1492 }
1493 if (iocommand.buf_size > 0) {
1494 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
1495 if (buff == NULL)
1496 return -EFAULT;
1497 }
1498 if (iocommand.Request.Type.Direction == XFER_WRITE) {
1499 /* Copy the data into the buffer we created */
1500 if (copy_from_user(buff, iocommand.buf, iocommand.buf_size)) {
1501 kfree(buff);
1502 return -EFAULT;
1503 }
1504 } else {
1505 memset(buff, 0, iocommand.buf_size);
1506 }
1507 c = cmd_special_alloc(h);
1508 if (!c) {
1509 kfree(buff);
1510 return -ENOMEM;
1511 }
1512 /* Fill in the command type */
1513 c->cmd_type = CMD_IOCTL_PEND;
1514 /* Fill in Command Header */
1515 c->Header.ReplyQueue = 0; /* unused in simple mode */
1516 if (iocommand.buf_size > 0) { /* buffer to fill */
1517 c->Header.SGList = 1;
1518 c->Header.SGTotal = 1;
1519 } else { /* no buffers to fill */
1520 c->Header.SGList = 0;
1521 c->Header.SGTotal = 0;
1522 }
1523 c->Header.LUN = iocommand.LUN_info;
1524 /* use the kernel address the cmd block for tag */
1525 c->Header.Tag.lower = c->busaddr;
1526
1527 /* Fill in Request block */
1528 c->Request = iocommand.Request;
1529
1530 /* Fill in the scatter gather information */
1531 if (iocommand.buf_size > 0) {
1532 temp64.val = pci_map_single(h->pdev, buff,
1533 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
1534 c->SG[0].Addr.lower = temp64.val32.lower;
1535 c->SG[0].Addr.upper = temp64.val32.upper;
1536 c->SG[0].Len = iocommand.buf_size;
1537 c->SG[0].Ext = 0; /* we are not chaining */
1538 }
1539 c->waiting = &wait;
1540
1541 enqueue_cmd_and_start_io(h, c);
1542 wait_for_completion(&wait);
1543
1544 /* unlock the buffers from DMA */
1545 temp64.val32.lower = c->SG[0].Addr.lower;
1546 temp64.val32.upper = c->SG[0].Addr.upper;
1547 pci_unmap_single(h->pdev, (dma_addr_t) temp64.val, iocommand.buf_size,
1548 PCI_DMA_BIDIRECTIONAL);
1549 check_ioctl_unit_attention(h, c);
1550
1551 /* Copy the error information out */
1552 iocommand.error_info = *(c->err_info);
1553 if (copy_to_user(argp, &iocommand, sizeof(IOCTL_Command_struct))) {
1554 kfree(buff);
1555 cmd_special_free(h, c);
1556 return -EFAULT;
1557 }
1558
1559 if (iocommand.Request.Type.Direction == XFER_READ) {
1560 /* Copy the data out of the buffer we created */
1561 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
1562 kfree(buff);
1563 cmd_special_free(h, c);
1564 return -EFAULT;
1565 }
1566 }
1567 kfree(buff);
1568 cmd_special_free(h, c);
1569 return 0;
1570 }
1571
1572 static int cciss_bigpassthru(ctlr_info_t *h, void __user *argp)
1573 {
1574 BIG_IOCTL_Command_struct *ioc;
1575 CommandList_struct *c;
1576 unsigned char **buff = NULL;
1577 int *buff_size = NULL;
1578 u64bit temp64;
1579 BYTE sg_used = 0;
1580 int status = 0;
1581 int i;
1582 DECLARE_COMPLETION_ONSTACK(wait);
1583 __u32 left;
1584 __u32 sz;
1585 BYTE __user *data_ptr;
1586
1587 if (!argp)
1588 return -EINVAL;
1589 if (!capable(CAP_SYS_RAWIO))
1590 return -EPERM;
1591 ioc = kmalloc(sizeof(*ioc), GFP_KERNEL);
1592 if (!ioc) {
1593 status = -ENOMEM;
1594 goto cleanup1;
1595 }
1596 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
1597 status = -EFAULT;
1598 goto cleanup1;
1599 }
1600 if ((ioc->buf_size < 1) &&
1601 (ioc->Request.Type.Direction != XFER_NONE)) {
1602 status = -EINVAL;
1603 goto cleanup1;
1604 }
1605 /* Check kmalloc limits using all SGs */
1606 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
1607 status = -EINVAL;
1608 goto cleanup1;
1609 }
1610 if (ioc->buf_size > ioc->malloc_size * MAXSGENTRIES) {
1611 status = -EINVAL;
1612 goto cleanup1;
1613 }
1614 buff = kzalloc(MAXSGENTRIES * sizeof(char *), GFP_KERNEL);
1615 if (!buff) {
1616 status = -ENOMEM;
1617 goto cleanup1;
1618 }
1619 buff_size = kmalloc(MAXSGENTRIES * sizeof(int), GFP_KERNEL);
1620 if (!buff_size) {
1621 status = -ENOMEM;
1622 goto cleanup1;
1623 }
1624 left = ioc->buf_size;
1625 data_ptr = ioc->buf;
1626 while (left) {
1627 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
1628 buff_size[sg_used] = sz;
1629 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
1630 if (buff[sg_used] == NULL) {
1631 status = -ENOMEM;
1632 goto cleanup1;
1633 }
1634 if (ioc->Request.Type.Direction == XFER_WRITE) {
1635 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
1636 status = -EFAULT;
1637 goto cleanup1;
1638 }
1639 } else {
1640 memset(buff[sg_used], 0, sz);
1641 }
1642 left -= sz;
1643 data_ptr += sz;
1644 sg_used++;
1645 }
1646 c = cmd_special_alloc(h);
1647 if (!c) {
1648 status = -ENOMEM;
1649 goto cleanup1;
1650 }
1651 c->cmd_type = CMD_IOCTL_PEND;
1652 c->Header.ReplyQueue = 0;
1653 c->Header.SGList = sg_used;
1654 c->Header.SGTotal = sg_used;
1655 c->Header.LUN = ioc->LUN_info;
1656 c->Header.Tag.lower = c->busaddr;
1657
1658 c->Request = ioc->Request;
1659 for (i = 0; i < sg_used; i++) {
1660 temp64.val = pci_map_single(h->pdev, buff[i], buff_size[i],
1661 PCI_DMA_BIDIRECTIONAL);
1662 c->SG[i].Addr.lower = temp64.val32.lower;
1663 c->SG[i].Addr.upper = temp64.val32.upper;
1664 c->SG[i].Len = buff_size[i];
1665 c->SG[i].Ext = 0; /* we are not chaining */
1666 }
1667 c->waiting = &wait;
1668 enqueue_cmd_and_start_io(h, c);
1669 wait_for_completion(&wait);
1670 /* unlock the buffers from DMA */
1671 for (i = 0; i < sg_used; i++) {
1672 temp64.val32.lower = c->SG[i].Addr.lower;
1673 temp64.val32.upper = c->SG[i].Addr.upper;
1674 pci_unmap_single(h->pdev,
1675 (dma_addr_t) temp64.val, buff_size[i],
1676 PCI_DMA_BIDIRECTIONAL);
1677 }
1678 check_ioctl_unit_attention(h, c);
1679 /* Copy the error information out */
1680 ioc->error_info = *(c->err_info);
1681 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
1682 cmd_special_free(h, c);
1683 status = -EFAULT;
1684 goto cleanup1;
1685 }
1686 if (ioc->Request.Type.Direction == XFER_READ) {
1687 /* Copy the data out of the buffer we created */
1688 BYTE __user *ptr = ioc->buf;
1689 for (i = 0; i < sg_used; i++) {
1690 if (copy_to_user(ptr, buff[i], buff_size[i])) {
1691 cmd_special_free(h, c);
1692 status = -EFAULT;
1693 goto cleanup1;
1694 }
1695 ptr += buff_size[i];
1696 }
1697 }
1698 cmd_special_free(h, c);
1699 status = 0;
1700 cleanup1:
1701 if (buff) {
1702 for (i = 0; i < sg_used; i++)
1703 kfree(buff[i]);
1704 kfree(buff);
1705 }
1706 kfree(buff_size);
1707 kfree(ioc);
1708 return status;
1709 }
1710
1711 static int cciss_ioctl(struct block_device *bdev, fmode_t mode,
1712 unsigned int cmd, unsigned long arg)
1713 {
1714 struct gendisk *disk = bdev->bd_disk;
1715 ctlr_info_t *h = get_host(disk);
1716 void __user *argp = (void __user *)arg;
1717
1718 dev_dbg(&h->pdev->dev, "cciss_ioctl: Called with cmd=%x %lx\n",
1719 cmd, arg);
1720 switch (cmd) {
1721 case CCISS_GETPCIINFO:
1722 return cciss_getpciinfo(h, argp);
1723 case CCISS_GETINTINFO:
1724 return cciss_getintinfo(h, argp);
1725 case CCISS_SETINTINFO:
1726 return cciss_setintinfo(h, argp);
1727 case CCISS_GETNODENAME:
1728 return cciss_getnodename(h, argp);
1729 case CCISS_SETNODENAME:
1730 return cciss_setnodename(h, argp);
1731 case CCISS_GETHEARTBEAT:
1732 return cciss_getheartbeat(h, argp);
1733 case CCISS_GETBUSTYPES:
1734 return cciss_getbustypes(h, argp);
1735 case CCISS_GETFIRMVER:
1736 return cciss_getfirmver(h, argp);
1737 case CCISS_GETDRIVVER:
1738 return cciss_getdrivver(h, argp);
1739 case CCISS_DEREGDISK:
1740 case CCISS_REGNEWD:
1741 case CCISS_REVALIDVOLS:
1742 return rebuild_lun_table(h, 0, 1);
1743 case CCISS_GETLUNINFO:
1744 return cciss_getluninfo(h, disk, argp);
1745 case CCISS_PASSTHRU:
1746 return cciss_passthru(h, argp);
1747 case CCISS_BIG_PASSTHRU:
1748 return cciss_bigpassthru(h, argp);
1749
1750 /* scsi_cmd_blk_ioctl handles these, below, though some are not */
1751 /* very meaningful for cciss. SG_IO is the main one people want. */
1752
1753 case SG_GET_VERSION_NUM:
1754 case SG_SET_TIMEOUT:
1755 case SG_GET_TIMEOUT:
1756 case SG_GET_RESERVED_SIZE:
1757 case SG_SET_RESERVED_SIZE:
1758 case SG_EMULATED_HOST:
1759 case SG_IO:
1760 case SCSI_IOCTL_SEND_COMMAND:
1761 return scsi_cmd_blk_ioctl(bdev, mode, cmd, argp);
1762
1763 /* scsi_cmd_blk_ioctl would normally handle these, below, but */
1764 /* they aren't a good fit for cciss, as CD-ROMs are */
1765 /* not supported, and we don't have any bus/target/lun */
1766 /* which we present to the kernel. */
1767
1768 case CDROM_SEND_PACKET:
1769 case CDROMCLOSETRAY:
1770 case CDROMEJECT:
1771 case SCSI_IOCTL_GET_IDLUN:
1772 case SCSI_IOCTL_GET_BUS_NUMBER:
1773 default:
1774 return -ENOTTY;
1775 }
1776 }
1777
1778 static void cciss_check_queues(ctlr_info_t *h)
1779 {
1780 int start_queue = h->next_to_run;
1781 int i;
1782
1783 /* check to see if we have maxed out the number of commands that can
1784 * be placed on the queue. If so then exit. We do this check here
1785 * in case the interrupt we serviced was from an ioctl and did not
1786 * free any new commands.
1787 */
1788 if ((find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds)) == h->nr_cmds)
1789 return;
1790
1791 /* We have room on the queue for more commands. Now we need to queue
1792 * them up. We will also keep track of the next queue to run so
1793 * that every queue gets a chance to be started first.
1794 */
1795 for (i = 0; i < h->highest_lun + 1; i++) {
1796 int curr_queue = (start_queue + i) % (h->highest_lun + 1);
1797 /* make sure the disk has been added and the drive is real
1798 * because this can be called from the middle of init_one.
1799 */
1800 if (!h->drv[curr_queue])
1801 continue;
1802 if (!(h->drv[curr_queue]->queue) ||
1803 !(h->drv[curr_queue]->heads))
1804 continue;
1805 blk_start_queue(h->gendisk[curr_queue]->queue);
1806
1807 /* check to see if we have maxed out the number of commands
1808 * that can be placed on the queue.
1809 */
1810 if ((find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds)) == h->nr_cmds) {
1811 if (curr_queue == start_queue) {
1812 h->next_to_run =
1813 (start_queue + 1) % (h->highest_lun + 1);
1814 break;
1815 } else {
1816 h->next_to_run = curr_queue;
1817 break;
1818 }
1819 }
1820 }
1821 }
1822
1823 static void cciss_softirq_done(struct request *rq)
1824 {
1825 CommandList_struct *c = rq->completion_data;
1826 ctlr_info_t *h = hba[c->ctlr];
1827 SGDescriptor_struct *curr_sg = c->SG;
1828 u64bit temp64;
1829 unsigned long flags;
1830 int i, ddir;
1831 int sg_index = 0;
1832
1833 if (c->Request.Type.Direction == XFER_READ)
1834 ddir = PCI_DMA_FROMDEVICE;
1835 else
1836 ddir = PCI_DMA_TODEVICE;
1837
1838 /* command did not need to be retried */
1839 /* unmap the DMA mapping for all the scatter gather elements */
1840 for (i = 0; i < c->Header.SGList; i++) {
1841 if (curr_sg[sg_index].Ext == CCISS_SG_CHAIN) {
1842 cciss_unmap_sg_chain_block(h, c);
1843 /* Point to the next block */
1844 curr_sg = h->cmd_sg_list[c->cmdindex];
1845 sg_index = 0;
1846 }
1847 temp64.val32.lower = curr_sg[sg_index].Addr.lower;
1848 temp64.val32.upper = curr_sg[sg_index].Addr.upper;
1849 pci_unmap_page(h->pdev, temp64.val, curr_sg[sg_index].Len,
1850 ddir);
1851 ++sg_index;
1852 }
1853
1854 dev_dbg(&h->pdev->dev, "Done with %p\n", rq);
1855
1856 /* set the residual count for pc requests */
1857 if (blk_rq_is_passthrough(rq))
1858 scsi_req(rq)->resid_len = c->err_info->ResidualCnt;
1859
1860 blk_end_request_all(rq, (rq->errors == 0) ? 0 : -EIO);
1861
1862 spin_lock_irqsave(&h->lock, flags);
1863 cmd_free(h, c);
1864 cciss_check_queues(h);
1865 spin_unlock_irqrestore(&h->lock, flags);
1866 }
1867
1868 static inline void log_unit_to_scsi3addr(ctlr_info_t *h,
1869 unsigned char scsi3addr[], uint32_t log_unit)
1870 {
1871 memcpy(scsi3addr, h->drv[log_unit]->LunID,
1872 sizeof(h->drv[log_unit]->LunID));
1873 }
1874
1875 /* This function gets the SCSI vendor, model, and revision of a logical drive
1876 * via the inquiry page 0. Model, vendor, and rev are set to empty strings if
1877 * they cannot be read.
1878 */
1879 static void cciss_get_device_descr(ctlr_info_t *h, int logvol,
1880 char *vendor, char *model, char *rev)
1881 {
1882 int rc;
1883 InquiryData_struct *inq_buf;
1884 unsigned char scsi3addr[8];
1885
1886 *vendor = '\0';
1887 *model = '\0';
1888 *rev = '\0';
1889
1890 inq_buf = kzalloc(sizeof(InquiryData_struct), GFP_KERNEL);
1891 if (!inq_buf)
1892 return;
1893
1894 log_unit_to_scsi3addr(h, scsi3addr, logvol);
1895 rc = sendcmd_withirq(h, CISS_INQUIRY, inq_buf, sizeof(*inq_buf), 0,
1896 scsi3addr, TYPE_CMD);
1897 if (rc == IO_OK) {
1898 memcpy(vendor, &inq_buf->data_byte[8], VENDOR_LEN);
1899 vendor[VENDOR_LEN] = '\0';
1900 memcpy(model, &inq_buf->data_byte[16], MODEL_LEN);
1901 model[MODEL_LEN] = '\0';
1902 memcpy(rev, &inq_buf->data_byte[32], REV_LEN);
1903 rev[REV_LEN] = '\0';
1904 }
1905
1906 kfree(inq_buf);
1907 return;
1908 }
1909
1910 /* This function gets the serial number of a logical drive via
1911 * inquiry page 0x83. Serial no. is 16 bytes. If the serial
1912 * number cannot be had, for whatever reason, 16 bytes of 0xff
1913 * are returned instead.
1914 */
1915 static void cciss_get_serial_no(ctlr_info_t *h, int logvol,
1916 unsigned char *serial_no, int buflen)
1917 {
1918 #define PAGE_83_INQ_BYTES 64
1919 int rc;
1920 unsigned char *buf;
1921 unsigned char scsi3addr[8];
1922
1923 if (buflen > 16)
1924 buflen = 16;
1925 memset(serial_no, 0xff, buflen);
1926 buf = kzalloc(PAGE_83_INQ_BYTES, GFP_KERNEL);
1927 if (!buf)
1928 return;
1929 memset(serial_no, 0, buflen);
1930 log_unit_to_scsi3addr(h, scsi3addr, logvol);
1931 rc = sendcmd_withirq(h, CISS_INQUIRY, buf,
1932 PAGE_83_INQ_BYTES, 0x83, scsi3addr, TYPE_CMD);
1933 if (rc == IO_OK)
1934 memcpy(serial_no, &buf[8], buflen);
1935 kfree(buf);
1936 return;
1937 }
1938
1939 /*
1940 * cciss_add_disk sets up the block device queue for a logical drive
1941 */
1942 static int cciss_add_disk(ctlr_info_t *h, struct gendisk *disk,
1943 int drv_index)
1944 {
1945 disk->queue = blk_alloc_queue(GFP_KERNEL);
1946 if (!disk->queue)
1947 goto init_queue_failure;
1948
1949 disk->queue->cmd_size = sizeof(struct scsi_request);
1950 disk->queue->request_fn = do_cciss_request;
1951 disk->queue->queue_lock = &h->lock;
1952 if (blk_init_allocated_queue(disk->queue) < 0)
1953 goto cleanup_queue;
1954
1955 sprintf(disk->disk_name, "cciss/c%dd%d", h->ctlr, drv_index);
1956 disk->major = h->major;
1957 disk->first_minor = drv_index << NWD_SHIFT;
1958 disk->fops = &cciss_fops;
1959 if (cciss_create_ld_sysfs_entry(h, drv_index))
1960 goto cleanup_queue;
1961 disk->private_data = h->drv[drv_index];
1962
1963 /* Set up queue information */
1964 blk_queue_bounce_limit(disk->queue, h->pdev->dma_mask);
1965
1966 /* This is a hardware imposed limit. */
1967 blk_queue_max_segments(disk->queue, h->maxsgentries);
1968
1969 blk_queue_max_hw_sectors(disk->queue, h->cciss_max_sectors);
1970
1971 blk_queue_softirq_done(disk->queue, cciss_softirq_done);
1972
1973 disk->queue->queuedata = h;
1974
1975 blk_queue_logical_block_size(disk->queue,
1976 h->drv[drv_index]->block_size);
1977
1978 /* Make sure all queue data is written out before */
1979 /* setting h->drv[drv_index]->queue, as setting this */
1980 /* allows the interrupt handler to start the queue */
1981 wmb();
1982 h->drv[drv_index]->queue = disk->queue;
1983 device_add_disk(&h->drv[drv_index]->dev, disk);
1984 return 0;
1985
1986 cleanup_queue:
1987 blk_cleanup_queue(disk->queue);
1988 disk->queue = NULL;
1989 init_queue_failure:
1990 return -1;
1991 }
1992
1993 /* This function will check the usage_count of the drive to be updated/added.
1994 * If the usage_count is zero and it is a heretofore unknown drive, or,
1995 * the drive's capacity, geometry, or serial number has changed,
1996 * then the drive information will be updated and the disk will be
1997 * re-registered with the kernel. If these conditions don't hold,
1998 * then it will be left alone for the next reboot. The exception to this
1999 * is disk 0 which will always be left registered with the kernel since it
2000 * is also the controller node. Any changes to disk 0 will show up on
2001 * the next reboot.
2002 */
2003 static void cciss_update_drive_info(ctlr_info_t *h, int drv_index,
2004 int first_time, int via_ioctl)
2005 {
2006 struct gendisk *disk;
2007 InquiryData_struct *inq_buff = NULL;
2008 unsigned int block_size;
2009 sector_t total_size;
2010 unsigned long flags = 0;
2011 int ret = 0;
2012 drive_info_struct *drvinfo;
2013
2014 /* Get information about the disk and modify the driver structure */
2015 inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL);
2016 drvinfo = kzalloc(sizeof(*drvinfo), GFP_KERNEL);
2017 if (inq_buff == NULL || drvinfo == NULL)
2018 goto mem_msg;
2019
2020 /* testing to see if 16-byte CDBs are already being used */
2021 if (h->cciss_read == CCISS_READ_16) {
2022 cciss_read_capacity_16(h, drv_index,
2023 &total_size, &block_size);
2024
2025 } else {
2026 cciss_read_capacity(h, drv_index, &total_size, &block_size);
2027 /* if read_capacity returns all F's this volume is >2TB */
2028 /* in size so we switch to 16-byte CDB's for all */
2029 /* read/write ops */
2030 if (total_size == 0xFFFFFFFFULL) {
2031 cciss_read_capacity_16(h, drv_index,
2032 &total_size, &block_size);
2033 h->cciss_read = CCISS_READ_16;
2034 h->cciss_write = CCISS_WRITE_16;
2035 } else {
2036 h->cciss_read = CCISS_READ_10;
2037 h->cciss_write = CCISS_WRITE_10;
2038 }
2039 }
2040
2041 cciss_geometry_inquiry(h, drv_index, total_size, block_size,
2042 inq_buff, drvinfo);
2043 drvinfo->block_size = block_size;
2044 drvinfo->nr_blocks = total_size + 1;
2045
2046 cciss_get_device_descr(h, drv_index, drvinfo->vendor,
2047 drvinfo->model, drvinfo->rev);
2048 cciss_get_serial_no(h, drv_index, drvinfo->serial_no,
2049 sizeof(drvinfo->serial_no));
2050 /* Save the lunid in case we deregister the disk, below. */
2051 memcpy(drvinfo->LunID, h->drv[drv_index]->LunID,
2052 sizeof(drvinfo->LunID));
2053
2054 /* Is it the same disk we already know, and nothing's changed? */
2055 if (h->drv[drv_index]->raid_level != -1 &&
2056 ((memcmp(drvinfo->serial_no,
2057 h->drv[drv_index]->serial_no, 16) == 0) &&
2058 drvinfo->block_size == h->drv[drv_index]->block_size &&
2059 drvinfo->nr_blocks == h->drv[drv_index]->nr_blocks &&
2060 drvinfo->heads == h->drv[drv_index]->heads &&
2061 drvinfo->sectors == h->drv[drv_index]->sectors &&
2062 drvinfo->cylinders == h->drv[drv_index]->cylinders))
2063 /* The disk is unchanged, nothing to update */
2064 goto freeret;
2065
2066 /* If we get here it's not the same disk, or something's changed,
2067 * so we need to * deregister it, and re-register it, if it's not
2068 * in use.
2069 * If the disk already exists then deregister it before proceeding
2070 * (unless it's the first disk (for the controller node).
2071 */
2072 if (h->drv[drv_index]->raid_level != -1 && drv_index != 0) {
2073 dev_warn(&h->pdev->dev, "disk %d has changed.\n", drv_index);
2074 spin_lock_irqsave(&h->lock, flags);
2075 h->drv[drv_index]->busy_configuring = 1;
2076 spin_unlock_irqrestore(&h->lock, flags);
2077
2078 /* deregister_disk sets h->drv[drv_index]->queue = NULL
2079 * which keeps the interrupt handler from starting
2080 * the queue.
2081 */
2082 ret = deregister_disk(h, drv_index, 0, via_ioctl);
2083 }
2084
2085 /* If the disk is in use return */
2086 if (ret)
2087 goto freeret;
2088
2089 /* Save the new information from cciss_geometry_inquiry
2090 * and serial number inquiry. If the disk was deregistered
2091 * above, then h->drv[drv_index] will be NULL.
2092 */
2093 if (h->drv[drv_index] == NULL) {
2094 drvinfo->device_initialized = 0;
2095 h->drv[drv_index] = drvinfo;
2096 drvinfo = NULL; /* so it won't be freed below. */
2097 } else {
2098 /* special case for cxd0 */
2099 h->drv[drv_index]->block_size = drvinfo->block_size;
2100 h->drv[drv_index]->nr_blocks = drvinfo->nr_blocks;
2101 h->drv[drv_index]->heads = drvinfo->heads;
2102 h->drv[drv_index]->sectors = drvinfo->sectors;
2103 h->drv[drv_index]->cylinders = drvinfo->cylinders;
2104 h->drv[drv_index]->raid_level = drvinfo->raid_level;
2105 memcpy(h->drv[drv_index]->serial_no, drvinfo->serial_no, 16);
2106 memcpy(h->drv[drv_index]->vendor, drvinfo->vendor,
2107 VENDOR_LEN + 1);
2108 memcpy(h->drv[drv_index]->model, drvinfo->model, MODEL_LEN + 1);
2109 memcpy(h->drv[drv_index]->rev, drvinfo->rev, REV_LEN + 1);
2110 }
2111
2112 ++h->num_luns;
2113 disk = h->gendisk[drv_index];
2114 set_capacity(disk, h->drv[drv_index]->nr_blocks);
2115
2116 /* If it's not disk 0 (drv_index != 0)
2117 * or if it was disk 0, but there was previously
2118 * no actual corresponding configured logical drive
2119 * (raid_leve == -1) then we want to update the
2120 * logical drive's information.
2121 */
2122 if (drv_index || first_time) {
2123 if (cciss_add_disk(h, disk, drv_index) != 0) {
2124 cciss_free_gendisk(h, drv_index);
2125 cciss_free_drive_info(h, drv_index);
2126 dev_warn(&h->pdev->dev, "could not update disk %d\n",
2127 drv_index);
2128 --h->num_luns;
2129 }
2130 }
2131
2132 freeret:
2133 kfree(inq_buff);
2134 kfree(drvinfo);
2135 return;
2136 mem_msg:
2137 dev_err(&h->pdev->dev, "out of memory\n");
2138 goto freeret;
2139 }
2140
2141 /* This function will find the first index of the controllers drive array
2142 * that has a null drv pointer and allocate the drive info struct and
2143 * will return that index This is where new drives will be added.
2144 * If the index to be returned is greater than the highest_lun index for
2145 * the controller then highest_lun is set * to this new index.
2146 * If there are no available indexes or if tha allocation fails, then -1
2147 * is returned. * "controller_node" is used to know if this is a real
2148 * logical drive, or just the controller node, which determines if this
2149 * counts towards highest_lun.
2150 */
2151 static int cciss_alloc_drive_info(ctlr_info_t *h, int controller_node)
2152 {
2153 int i;
2154 drive_info_struct *drv;
2155
2156 /* Search for an empty slot for our drive info */
2157 for (i = 0; i < CISS_MAX_LUN; i++) {
2158
2159 /* if not cxd0 case, and it's occupied, skip it. */
2160 if (h->drv[i] && i != 0)
2161 continue;
2162 /*
2163 * If it's cxd0 case, and drv is alloc'ed already, and a
2164 * disk is configured there, skip it.
2165 */
2166 if (i == 0 && h->drv[i] && h->drv[i]->raid_level != -1)
2167 continue;
2168
2169 /*
2170 * We've found an empty slot. Update highest_lun
2171 * provided this isn't just the fake cxd0 controller node.
2172 */
2173 if (i > h->highest_lun && !controller_node)
2174 h->highest_lun = i;
2175
2176 /* If adding a real disk at cxd0, and it's already alloc'ed */
2177 if (i == 0 && h->drv[i] != NULL)
2178 return i;
2179
2180 /*
2181 * Found an empty slot, not already alloc'ed. Allocate it.
2182 * Mark it with raid_level == -1, so we know it's new later on.
2183 */
2184 drv = kzalloc(sizeof(*drv), GFP_KERNEL);
2185 if (!drv)
2186 return -1;
2187 drv->raid_level = -1; /* so we know it's new */
2188 h->drv[i] = drv;
2189 return i;
2190 }
2191 return -1;
2192 }
2193
2194 static void cciss_free_drive_info(ctlr_info_t *h, int drv_index)
2195 {
2196 kfree(h->drv[drv_index]);
2197 h->drv[drv_index] = NULL;
2198 }
2199
2200 static void cciss_free_gendisk(ctlr_info_t *h, int drv_index)
2201 {
2202 put_disk(h->gendisk[drv_index]);
2203 h->gendisk[drv_index] = NULL;
2204 }
2205
2206 /* cciss_add_gendisk finds a free hba[]->drv structure
2207 * and allocates a gendisk if needed, and sets the lunid
2208 * in the drvinfo structure. It returns the index into
2209 * the ->drv[] array, or -1 if none are free.
2210 * is_controller_node indicates whether highest_lun should
2211 * count this disk, or if it's only being added to provide
2212 * a means to talk to the controller in case no logical
2213 * drives have yet been configured.
2214 */
2215 static int cciss_add_gendisk(ctlr_info_t *h, unsigned char lunid[],
2216 int controller_node)
2217 {
2218 int drv_index;
2219
2220 drv_index = cciss_alloc_drive_info(h, controller_node);
2221 if (drv_index == -1)
2222 return -1;
2223
2224 /*Check if the gendisk needs to be allocated */
2225 if (!h->gendisk[drv_index]) {
2226 h->gendisk[drv_index] =
2227 alloc_disk(1 << NWD_SHIFT);
2228 if (!h->gendisk[drv_index]) {
2229 dev_err(&h->pdev->dev,
2230 "could not allocate a new disk %d\n",
2231 drv_index);
2232 goto err_free_drive_info;
2233 }
2234 }
2235 memcpy(h->drv[drv_index]->LunID, lunid,
2236 sizeof(h->drv[drv_index]->LunID));
2237 if (cciss_create_ld_sysfs_entry(h, drv_index))
2238 goto err_free_disk;
2239 /* Don't need to mark this busy because nobody */
2240 /* else knows about this disk yet to contend */
2241 /* for access to it. */
2242 h->drv[drv_index]->busy_configuring = 0;
2243 wmb();
2244 return drv_index;
2245
2246 err_free_disk:
2247 cciss_free_gendisk(h, drv_index);
2248 err_free_drive_info:
2249 cciss_free_drive_info(h, drv_index);
2250 return -1;
2251 }
2252
2253 /* This is for the special case of a controller which
2254 * has no logical drives. In this case, we still need
2255 * to register a disk so the controller can be accessed
2256 * by the Array Config Utility.
2257 */
2258 static void cciss_add_controller_node(ctlr_info_t *h)
2259 {
2260 struct gendisk *disk;
2261 int drv_index;
2262
2263 if (h->gendisk[0] != NULL) /* already did this? Then bail. */
2264 return;
2265
2266 drv_index = cciss_add_gendisk(h, CTLR_LUNID, 1);
2267 if (drv_index == -1)
2268 goto error;
2269 h->drv[drv_index]->block_size = 512;
2270 h->drv[drv_index]->nr_blocks = 0;
2271 h->drv[drv_index]->heads = 0;
2272 h->drv[drv_index]->sectors = 0;
2273 h->drv[drv_index]->cylinders = 0;
2274 h->drv[drv_index]->raid_level = -1;
2275 memset(h->drv[drv_index]->serial_no, 0, 16);
2276 disk = h->gendisk[drv_index];
2277 if (cciss_add_disk(h, disk, drv_index) == 0)
2278 return;
2279 cciss_free_gendisk(h, drv_index);
2280 cciss_free_drive_info(h, drv_index);
2281 error:
2282 dev_warn(&h->pdev->dev, "could not add disk 0.\n");
2283 return;
2284 }
2285
2286 /* This function will add and remove logical drives from the Logical
2287 * drive array of the controller and maintain persistency of ordering
2288 * so that mount points are preserved until the next reboot. This allows
2289 * for the removal of logical drives in the middle of the drive array
2290 * without a re-ordering of those drives.
2291 * INPUT
2292 * h = The controller to perform the operations on
2293 */
2294 static int rebuild_lun_table(ctlr_info_t *h, int first_time,
2295 int via_ioctl)
2296 {
2297 int num_luns;
2298 ReportLunData_struct *ld_buff = NULL;
2299 int return_code;
2300 int listlength = 0;
2301 int i;
2302 int drv_found;
2303 int drv_index = 0;
2304 unsigned char lunid[8] = CTLR_LUNID;
2305 unsigned long flags;
2306
2307 if (!capable(CAP_SYS_RAWIO))
2308 return -EPERM;
2309
2310 /* Set busy_configuring flag for this operation */
2311 spin_lock_irqsave(&h->lock, flags);
2312 if (h->busy_configuring) {
2313 spin_unlock_irqrestore(&h->lock, flags);
2314 return -EBUSY;
2315 }
2316 h->busy_configuring = 1;
2317 spin_unlock_irqrestore(&h->lock, flags);
2318
2319 ld_buff = kzalloc(sizeof(ReportLunData_struct), GFP_KERNEL);
2320 if (ld_buff == NULL)
2321 goto mem_msg;
2322
2323 return_code = sendcmd_withirq(h, CISS_REPORT_LOG, ld_buff,
2324 sizeof(ReportLunData_struct),
2325 0, CTLR_LUNID, TYPE_CMD);
2326
2327 if (return_code == IO_OK)
2328 listlength = be32_to_cpu(*(__be32 *) ld_buff->LUNListLength);
2329 else { /* reading number of logical volumes failed */
2330 dev_warn(&h->pdev->dev,
2331 "report logical volume command failed\n");
2332 listlength = 0;
2333 goto freeret;
2334 }
2335
2336 num_luns = listlength / 8; /* 8 bytes per entry */
2337 if (num_luns > CISS_MAX_LUN) {
2338 num_luns = CISS_MAX_LUN;
2339 dev_warn(&h->pdev->dev, "more luns configured"
2340 " on controller than can be handled by"
2341 " this driver.\n");
2342 }
2343
2344 if (num_luns == 0)
2345 cciss_add_controller_node(h);
2346
2347 /* Compare controller drive array to driver's drive array
2348 * to see if any drives are missing on the controller due
2349 * to action of Array Config Utility (user deletes drive)
2350 * and deregister logical drives which have disappeared.
2351 */
2352 for (i = 0; i <= h->highest_lun; i++) {
2353 int j;
2354 drv_found = 0;
2355
2356 /* skip holes in the array from already deleted drives */
2357 if (h->drv[i] == NULL)
2358 continue;
2359
2360 for (j = 0; j < num_luns; j++) {
2361 memcpy(lunid, &ld_buff->LUN[j][0], sizeof(lunid));
2362 if (memcmp(h->drv[i]->LunID, lunid,
2363 sizeof(lunid)) == 0) {
2364 drv_found = 1;
2365 break;
2366 }
2367 }
2368 if (!drv_found) {
2369 /* Deregister it from the OS, it's gone. */
2370 spin_lock_irqsave(&h->lock, flags);
2371 h->drv[i]->busy_configuring = 1;
2372 spin_unlock_irqrestore(&h->lock, flags);
2373 return_code = deregister_disk(h, i, 1, via_ioctl);
2374 if (h->drv[i] != NULL)
2375 h->drv[i]->busy_configuring = 0;
2376 }
2377 }
2378
2379 /* Compare controller drive array to driver's drive array.
2380 * Check for updates in the drive information and any new drives
2381 * on the controller due to ACU adding logical drives, or changing
2382 * a logical drive's size, etc. Reregister any new/changed drives
2383 */
2384 for (i = 0; i < num_luns; i++) {
2385 int j;
2386
2387 drv_found = 0;
2388
2389 memcpy(lunid, &ld_buff->LUN[i][0], sizeof(lunid));
2390 /* Find if the LUN is already in the drive array
2391 * of the driver. If so then update its info
2392 * if not in use. If it does not exist then find
2393 * the first free index and add it.
2394 */
2395 for (j = 0; j <= h->highest_lun; j++) {
2396 if (h->drv[j] != NULL &&
2397 memcmp(h->drv[j]->LunID, lunid,
2398 sizeof(h->drv[j]->LunID)) == 0) {
2399 drv_index = j;
2400 drv_found = 1;
2401 break;
2402 }
2403 }
2404
2405 /* check if the drive was found already in the array */
2406 if (!drv_found) {
2407 drv_index = cciss_add_gendisk(h, lunid, 0);
2408 if (drv_index == -1)
2409 goto freeret;
2410 }
2411 cciss_update_drive_info(h, drv_index, first_time, via_ioctl);
2412 } /* end for */
2413
2414 freeret:
2415 kfree(ld_buff);
2416 h->busy_configuring = 0;
2417 /* We return -1 here to tell the ACU that we have registered/updated
2418 * all of the drives that we can and to keep it from calling us
2419 * additional times.
2420 */
2421 return -1;
2422 mem_msg:
2423 dev_err(&h->pdev->dev, "out of memory\n");
2424 h->busy_configuring = 0;
2425 goto freeret;
2426 }
2427
2428 static void cciss_clear_drive_info(drive_info_struct *drive_info)
2429 {
2430 /* zero out the disk size info */
2431 drive_info->nr_blocks = 0;
2432 drive_info->block_size = 0;
2433 drive_info->heads = 0;
2434 drive_info->sectors = 0;
2435 drive_info->cylinders = 0;
2436 drive_info->raid_level = -1;
2437 memset(drive_info->serial_no, 0, sizeof(drive_info->serial_no));
2438 memset(drive_info->model, 0, sizeof(drive_info->model));
2439 memset(drive_info->rev, 0, sizeof(drive_info->rev));
2440 memset(drive_info->vendor, 0, sizeof(drive_info->vendor));
2441 /*
2442 * don't clear the LUNID though, we need to remember which
2443 * one this one is.
2444 */
2445 }
2446
2447 /* This function will deregister the disk and it's queue from the
2448 * kernel. It must be called with the controller lock held and the
2449 * drv structures busy_configuring flag set. It's parameters are:
2450 *
2451 * disk = This is the disk to be deregistered
2452 * drv = This is the drive_info_struct associated with the disk to be
2453 * deregistered. It contains information about the disk used
2454 * by the driver.
2455 * clear_all = This flag determines whether or not the disk information
2456 * is going to be completely cleared out and the highest_lun
2457 * reset. Sometimes we want to clear out information about
2458 * the disk in preparation for re-adding it. In this case
2459 * the highest_lun should be left unchanged and the LunID
2460 * should not be cleared.
2461 * via_ioctl
2462 * This indicates whether we've reached this path via ioctl.
2463 * This affects the maximum usage count allowed for c0d0 to be messed with.
2464 * If this path is reached via ioctl(), then the max_usage_count will
2465 * be 1, as the process calling ioctl() has got to have the device open.
2466 * If we get here via sysfs, then the max usage count will be zero.
2467 */
2468 static int deregister_disk(ctlr_info_t *h, int drv_index,
2469 int clear_all, int via_ioctl)
2470 {
2471 int i;
2472 struct gendisk *disk;
2473 drive_info_struct *drv;
2474 int recalculate_highest_lun;
2475
2476 if (!capable(CAP_SYS_RAWIO))
2477 return -EPERM;
2478
2479 drv = h->drv[drv_index];
2480 disk = h->gendisk[drv_index];
2481
2482 /* make sure logical volume is NOT is use */
2483 if (clear_all || (h->gendisk[0] == disk)) {
2484 if (drv->usage_count > via_ioctl)
2485 return -EBUSY;
2486 } else if (drv->usage_count > 0)
2487 return -EBUSY;
2488
2489 recalculate_highest_lun = (drv == h->drv[h->highest_lun]);
2490
2491 /* invalidate the devices and deregister the disk. If it is disk
2492 * zero do not deregister it but just zero out it's values. This
2493 * allows us to delete disk zero but keep the controller registered.
2494 */
2495 if (h->gendisk[0] != disk) {
2496 struct request_queue *q = disk->queue;
2497 if (disk->flags & GENHD_FL_UP) {
2498 cciss_destroy_ld_sysfs_entry(h, drv_index, 0);
2499 del_gendisk(disk);
2500 }
2501 if (q)
2502 blk_cleanup_queue(q);
2503 /* If clear_all is set then we are deleting the logical
2504 * drive, not just refreshing its info. For drives
2505 * other than disk 0 we will call put_disk. We do not
2506 * do this for disk 0 as we need it to be able to
2507 * configure the controller.
2508 */
2509 if (clear_all){
2510 /* This isn't pretty, but we need to find the
2511 * disk in our array and NULL our the pointer.
2512 * This is so that we will call alloc_disk if
2513 * this index is used again later.
2514 */
2515 for (i=0; i < CISS_MAX_LUN; i++){
2516 if (h->gendisk[i] == disk) {
2517 h->gendisk[i] = NULL;
2518 break;
2519 }
2520 }
2521 put_disk(disk);
2522 }
2523 } else {
2524 set_capacity(disk, 0);
2525 cciss_clear_drive_info(drv);
2526 }
2527
2528 --h->num_luns;
2529
2530 /* if it was the last disk, find the new hightest lun */
2531 if (clear_all && recalculate_highest_lun) {
2532 int newhighest = -1;
2533 for (i = 0; i <= h->highest_lun; i++) {
2534 /* if the disk has size > 0, it is available */
2535 if (h->drv[i] && h->drv[i]->heads)
2536 newhighest = i;
2537 }
2538 h->highest_lun = newhighest;
2539 }
2540 return 0;
2541 }
2542
2543 static int fill_cmd(ctlr_info_t *h, CommandList_struct *c, __u8 cmd, void *buff,
2544 size_t size, __u8 page_code, unsigned char *scsi3addr,
2545 int cmd_type)
2546 {
2547 u64bit buff_dma_handle;
2548 int status = IO_OK;
2549
2550 c->cmd_type = CMD_IOCTL_PEND;
2551 c->Header.ReplyQueue = 0;
2552 if (buff != NULL) {
2553 c->Header.SGList = 1;
2554 c->Header.SGTotal = 1;
2555 } else {
2556 c->Header.SGList = 0;
2557 c->Header.SGTotal = 0;
2558 }
2559 c->Header.Tag.lower = c->busaddr;
2560 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
2561
2562 c->Request.Type.Type = cmd_type;
2563 if (cmd_type == TYPE_CMD) {
2564 switch (cmd) {
2565 case CISS_INQUIRY:
2566 /* are we trying to read a vital product page */
2567 if (page_code != 0) {
2568 c->Request.CDB[1] = 0x01;
2569 c->Request.CDB[2] = page_code;
2570 }
2571 c->Request.CDBLen = 6;
2572 c->Request.Type.Attribute = ATTR_SIMPLE;
2573 c->Request.Type.Direction = XFER_READ;
2574 c->Request.Timeout = 0;
2575 c->Request.CDB[0] = CISS_INQUIRY;
2576 c->Request.CDB[4] = size & 0xFF;
2577 break;
2578 case CISS_REPORT_LOG:
2579 case CISS_REPORT_PHYS:
2580 /* Talking to controller so It's a physical command
2581 mode = 00 target = 0. Nothing to write.
2582 */
2583 c->Request.CDBLen = 12;
2584 c->Request.Type.Attribute = ATTR_SIMPLE;
2585 c->Request.Type.Direction = XFER_READ;
2586 c->Request.Timeout = 0;
2587 c->Request.CDB[0] = cmd;
2588 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
2589 c->Request.CDB[7] = (size >> 16) & 0xFF;
2590 c->Request.CDB[8] = (size >> 8) & 0xFF;
2591 c->Request.CDB[9] = size & 0xFF;
2592 break;
2593
2594 case CCISS_READ_CAPACITY:
2595 c->Request.CDBLen = 10;
2596 c->Request.Type.Attribute = ATTR_SIMPLE;
2597 c->Request.Type.Direction = XFER_READ;
2598 c->Request.Timeout = 0;
2599 c->Request.CDB[0] = cmd;
2600 break;
2601 case CCISS_READ_CAPACITY_16:
2602 c->Request.CDBLen = 16;
2603 c->Request.Type.Attribute = ATTR_SIMPLE;
2604 c->Request.Type.Direction = XFER_READ;
2605 c->Request.Timeout = 0;
2606 c->Request.CDB[0] = cmd;
2607 c->Request.CDB[1] = 0x10;
2608 c->Request.CDB[10] = (size >> 24) & 0xFF;
2609 c->Request.CDB[11] = (size >> 16) & 0xFF;
2610 c->Request.CDB[12] = (size >> 8) & 0xFF;
2611 c->Request.CDB[13] = size & 0xFF;
2612 c->Request.Timeout = 0;
2613 c->Request.CDB[0] = cmd;
2614 break;
2615 case CCISS_CACHE_FLUSH:
2616 c->Request.CDBLen = 12;
2617 c->Request.Type.Attribute = ATTR_SIMPLE;
2618 c->Request.Type.Direction = XFER_WRITE;
2619 c->Request.Timeout = 0;
2620 c->Request.CDB[0] = BMIC_WRITE;
2621 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
2622 c->Request.CDB[7] = (size >> 8) & 0xFF;
2623 c->Request.CDB[8] = size & 0xFF;
2624 break;
2625 case TEST_UNIT_READY:
2626 c->Request.CDBLen = 6;
2627 c->Request.Type.Attribute = ATTR_SIMPLE;
2628 c->Request.Type.Direction = XFER_NONE;
2629 c->Request.Timeout = 0;
2630 break;
2631 default:
2632 dev_warn(&h->pdev->dev, "Unknown Command 0x%c\n", cmd);
2633 return IO_ERROR;
2634 }
2635 } else if (cmd_type == TYPE_MSG) {
2636 switch (cmd) {
2637 case CCISS_ABORT_MSG:
2638 c->Request.CDBLen = 12;
2639 c->Request.Type.Attribute = ATTR_SIMPLE;
2640 c->Request.Type.Direction = XFER_WRITE;
2641 c->Request.Timeout = 0;
2642 c->Request.CDB[0] = cmd; /* abort */
2643 c->Request.CDB[1] = 0; /* abort a command */
2644 /* buff contains the tag of the command to abort */
2645 memcpy(&c->Request.CDB[4], buff, 8);
2646 break;
2647 case CCISS_RESET_MSG:
2648 c->Request.CDBLen = 16;
2649 c->Request.Type.Attribute = ATTR_SIMPLE;
2650 c->Request.Type.Direction = XFER_NONE;
2651 c->Request.Timeout = 0;
2652 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
2653 c->Request.CDB[0] = cmd; /* reset */
2654 c->Request.CDB[1] = CCISS_RESET_TYPE_TARGET;
2655 break;
2656 case CCISS_NOOP_MSG:
2657 c->Request.CDBLen = 1;
2658 c->Request.Type.Attribute = ATTR_SIMPLE;
2659 c->Request.Type.Direction = XFER_WRITE;
2660 c->Request.Timeout = 0;
2661 c->Request.CDB[0] = cmd;
2662 break;
2663 default:
2664 dev_warn(&h->pdev->dev,
2665 "unknown message type %d\n", cmd);
2666 return IO_ERROR;
2667 }
2668 } else {
2669 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
2670 return IO_ERROR;
2671 }
2672 /* Fill in the scatter gather information */
2673 if (size > 0) {
2674 buff_dma_handle.val = (__u64) pci_map_single(h->pdev,
2675 buff, size,
2676 PCI_DMA_BIDIRECTIONAL);
2677 c->SG[0].Addr.lower = buff_dma_handle.val32.lower;
2678 c->SG[0].Addr.upper = buff_dma_handle.val32.upper;
2679 c->SG[0].Len = size;
2680 c->SG[0].Ext = 0; /* we are not chaining */
2681 }
2682 return status;
2683 }
2684
2685 static int cciss_send_reset(ctlr_info_t *h, unsigned char *scsi3addr,
2686 u8 reset_type)
2687 {
2688 CommandList_struct *c;
2689 int return_status;
2690
2691 c = cmd_alloc(h);
2692 if (!c)
2693 return -ENOMEM;
2694 return_status = fill_cmd(h, c, CCISS_RESET_MSG, NULL, 0, 0,
2695 CTLR_LUNID, TYPE_MSG);
2696 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
2697 if (return_status != IO_OK) {
2698 cmd_special_free(h, c);
2699 return return_status;
2700 }
2701 c->waiting = NULL;
2702 enqueue_cmd_and_start_io(h, c);
2703 /* Don't wait for completion, the reset won't complete. Don't free
2704 * the command either. This is the last command we will send before
2705 * re-initializing everything, so it doesn't matter and won't leak.
2706 */
2707 return 0;
2708 }
2709
2710 static int check_target_status(ctlr_info_t *h, CommandList_struct *c)
2711 {
2712 switch (c->err_info->ScsiStatus) {
2713 case SAM_STAT_GOOD:
2714 return IO_OK;
2715 case SAM_STAT_CHECK_CONDITION:
2716 switch (0xf & c->err_info->SenseInfo[2]) {
2717 case 0: return IO_OK; /* no sense */
2718 case 1: return IO_OK; /* recovered error */
2719 default:
2720 if (check_for_unit_attention(h, c))
2721 return IO_NEEDS_RETRY;
2722 dev_warn(&h->pdev->dev, "cmd 0x%02x "
2723 "check condition, sense key = 0x%02x\n",
2724 c->Request.CDB[0], c->err_info->SenseInfo[2]);
2725 }
2726 break;
2727 default:
2728 dev_warn(&h->pdev->dev, "cmd 0x%02x"
2729 "scsi status = 0x%02x\n",
2730 c->Request.CDB[0], c->err_info->ScsiStatus);
2731 break;
2732 }
2733 return IO_ERROR;
2734 }
2735
2736 static int process_sendcmd_error(ctlr_info_t *h, CommandList_struct *c)
2737 {
2738 int return_status = IO_OK;
2739
2740 if (c->err_info->CommandStatus == CMD_SUCCESS)
2741 return IO_OK;
2742
2743 switch (c->err_info->CommandStatus) {
2744 case CMD_TARGET_STATUS:
2745 return_status = check_target_status(h, c);
2746 break;
2747 case CMD_DATA_UNDERRUN:
2748 case CMD_DATA_OVERRUN:
2749 /* expected for inquiry and report lun commands */
2750 break;
2751 case CMD_INVALID:
2752 dev_warn(&h->pdev->dev, "cmd 0x%02x is "
2753 "reported invalid\n", c->Request.CDB[0]);
2754 return_status = IO_ERROR;
2755 break;
2756 case CMD_PROTOCOL_ERR:
2757 dev_warn(&h->pdev->dev, "cmd 0x%02x has "
2758 "protocol error\n", c->Request.CDB[0]);
2759 return_status = IO_ERROR;
2760 break;
2761 case CMD_HARDWARE_ERR:
2762 dev_warn(&h->pdev->dev, "cmd 0x%02x had "
2763 " hardware error\n", c->Request.CDB[0]);
2764 return_status = IO_ERROR;
2765 break;
2766 case CMD_CONNECTION_LOST:
2767 dev_warn(&h->pdev->dev, "cmd 0x%02x had "
2768 "connection lost\n", c->Request.CDB[0]);
2769 return_status = IO_ERROR;
2770 break;
2771 case CMD_ABORTED:
2772 dev_warn(&h->pdev->dev, "cmd 0x%02x was "
2773 "aborted\n", c->Request.CDB[0]);
2774 return_status = IO_ERROR;
2775 break;
2776 case CMD_ABORT_FAILED:
2777 dev_warn(&h->pdev->dev, "cmd 0x%02x reports "
2778 "abort failed\n", c->Request.CDB[0]);
2779 return_status = IO_ERROR;
2780 break;
2781 case CMD_UNSOLICITED_ABORT:
2782 dev_warn(&h->pdev->dev, "unsolicited abort 0x%02x\n",
2783 c->Request.CDB[0]);
2784 return_status = IO_NEEDS_RETRY;
2785 break;
2786 case CMD_UNABORTABLE:
2787 dev_warn(&h->pdev->dev, "cmd unabortable\n");
2788 return_status = IO_ERROR;
2789 break;
2790 default:
2791 dev_warn(&h->pdev->dev, "cmd 0x%02x returned "
2792 "unknown status %x\n", c->Request.CDB[0],
2793 c->err_info->CommandStatus);
2794 return_status = IO_ERROR;
2795 }
2796 return return_status;
2797 }
2798
2799 static int sendcmd_withirq_core(ctlr_info_t *h, CommandList_struct *c,
2800 int attempt_retry)
2801 {
2802 DECLARE_COMPLETION_ONSTACK(wait);
2803 u64bit buff_dma_handle;
2804 int return_status = IO_OK;
2805
2806 resend_cmd2:
2807 c->waiting = &wait;
2808 enqueue_cmd_and_start_io(h, c);
2809
2810 wait_for_completion(&wait);
2811
2812 if (c->err_info->CommandStatus == 0 || !attempt_retry)
2813 goto command_done;
2814
2815 return_status = process_sendcmd_error(h, c);
2816
2817 if (return_status == IO_NEEDS_RETRY &&
2818 c->retry_count < MAX_CMD_RETRIES) {
2819 dev_warn(&h->pdev->dev, "retrying 0x%02x\n",
2820 c->Request.CDB[0]);
2821 c->retry_count++;
2822 /* erase the old error information */
2823 memset(c->err_info, 0, sizeof(ErrorInfo_struct));
2824 return_status = IO_OK;
2825 reinit_completion(&wait);
2826 goto resend_cmd2;
2827 }
2828
2829 command_done:
2830 /* unlock the buffers from DMA */
2831 buff_dma_handle.val32.lower = c->SG[0].Addr.lower;
2832 buff_dma_handle.val32.upper = c->SG[0].Addr.upper;
2833 pci_unmap_single(h->pdev, (dma_addr_t) buff_dma_handle.val,
2834 c->SG[0].Len, PCI_DMA_BIDIRECTIONAL);
2835 return return_status;
2836 }
2837
2838 static int sendcmd_withirq(ctlr_info_t *h, __u8 cmd, void *buff, size_t size,
2839 __u8 page_code, unsigned char scsi3addr[],
2840 int cmd_type)
2841 {
2842 CommandList_struct *c;
2843 int return_status;
2844
2845 c = cmd_special_alloc(h);
2846 if (!c)
2847 return -ENOMEM;
2848 return_status = fill_cmd(h, c, cmd, buff, size, page_code,
2849 scsi3addr, cmd_type);
2850 if (return_status == IO_OK)
2851 return_status = sendcmd_withirq_core(h, c, 1);
2852
2853 cmd_special_free(h, c);
2854 return return_status;
2855 }
2856
2857 static void cciss_geometry_inquiry(ctlr_info_t *h, int logvol,
2858 sector_t total_size,
2859 unsigned int block_size,
2860 InquiryData_struct *inq_buff,
2861 drive_info_struct *drv)
2862 {
2863 int return_code;
2864 unsigned long t;
2865 unsigned char scsi3addr[8];
2866
2867 memset(inq_buff, 0, sizeof(InquiryData_struct));
2868 log_unit_to_scsi3addr(h, scsi3addr, logvol);
2869 return_code = sendcmd_withirq(h, CISS_INQUIRY, inq_buff,
2870 sizeof(*inq_buff), 0xC1, scsi3addr, TYPE_CMD);
2871 if (return_code == IO_OK) {
2872 if (inq_buff->data_byte[8] == 0xFF) {
2873 dev_warn(&h->pdev->dev,
2874 "reading geometry failed, volume "
2875 "does not support reading geometry\n");
2876 drv->heads = 255;
2877 drv->sectors = 32; /* Sectors per track */
2878 drv->cylinders = total_size + 1;
2879 drv->raid_level = RAID_UNKNOWN;
2880 } else {
2881 drv->heads = inq_buff->data_byte[6];
2882 drv->sectors = inq_buff->data_byte[7];
2883 drv->cylinders = (inq_buff->data_byte[4] & 0xff) << 8;
2884 drv->cylinders += inq_buff->data_byte[5];
2885 drv->raid_level = inq_buff->data_byte[8];
2886 }
2887 drv->block_size = block_size;
2888 drv->nr_blocks = total_size + 1;
2889 t = drv->heads * drv->sectors;
2890 if (t > 1) {
2891 sector_t real_size = total_size + 1;
2892 unsigned long rem = sector_div(real_size, t);
2893 if (rem)
2894 real_size++;
2895 drv->cylinders = real_size;
2896 }
2897 } else { /* Get geometry failed */
2898 dev_warn(&h->pdev->dev, "reading geometry failed\n");
2899 }
2900 }
2901
2902 static void
2903 cciss_read_capacity(ctlr_info_t *h, int logvol, sector_t *total_size,
2904 unsigned int *block_size)
2905 {
2906 ReadCapdata_struct *buf;
2907 int return_code;
2908 unsigned char scsi3addr[8];
2909
2910 buf = kzalloc(sizeof(ReadCapdata_struct), GFP_KERNEL);
2911 if (!buf) {
2912 dev_warn(&h->pdev->dev, "out of memory\n");
2913 return;
2914 }
2915
2916 log_unit_to_scsi3addr(h, scsi3addr, logvol);
2917 return_code = sendcmd_withirq(h, CCISS_READ_CAPACITY, buf,
2918 sizeof(ReadCapdata_struct), 0, scsi3addr, TYPE_CMD);
2919 if (return_code == IO_OK) {
2920 *total_size = be32_to_cpu(*(__be32 *) buf->total_size);
2921 *block_size = be32_to_cpu(*(__be32 *) buf->block_size);
2922 } else { /* read capacity command failed */
2923 dev_warn(&h->pdev->dev, "read capacity failed\n");
2924 *total_size = 0;
2925 *block_size = BLOCK_SIZE;
2926 }
2927 kfree(buf);
2928 }
2929
2930 static void cciss_read_capacity_16(ctlr_info_t *h, int logvol,
2931 sector_t *total_size, unsigned int *block_size)
2932 {
2933 ReadCapdata_struct_16 *buf;
2934 int return_code;
2935 unsigned char scsi3addr[8];
2936
2937 buf = kzalloc(sizeof(ReadCapdata_struct_16), GFP_KERNEL);
2938 if (!buf) {
2939 dev_warn(&h->pdev->dev, "out of memory\n");
2940 return;
2941 }
2942
2943 log_unit_to_scsi3addr(h, scsi3addr, logvol);
2944 return_code = sendcmd_withirq(h, CCISS_READ_CAPACITY_16,
2945 buf, sizeof(ReadCapdata_struct_16),
2946 0, scsi3addr, TYPE_CMD);
2947 if (return_code == IO_OK) {
2948 *total_size = be64_to_cpu(*(__be64 *) buf->total_size);
2949 *block_size = be32_to_cpu(*(__be32 *) buf->block_size);
2950 } else { /* read capacity command failed */
2951 dev_warn(&h->pdev->dev, "read capacity failed\n");
2952 *total_size = 0;
2953 *block_size = BLOCK_SIZE;
2954 }
2955 dev_info(&h->pdev->dev, " blocks= %llu block_size= %d\n",
2956 (unsigned long long)*total_size+1, *block_size);
2957 kfree(buf);
2958 }
2959
2960 static int cciss_revalidate(struct gendisk *disk)
2961 {
2962 ctlr_info_t *h = get_host(disk);
2963 drive_info_struct *drv = get_drv(disk);
2964 int logvol;
2965 int FOUND = 0;
2966 unsigned int block_size;
2967 sector_t total_size;
2968 InquiryData_struct *inq_buff = NULL;
2969
2970 for (logvol = 0; logvol <= h->highest_lun; logvol++) {
2971 if (!h->drv[logvol])
2972 continue;
2973 if (memcmp(h->drv[logvol]->LunID, drv->LunID,
2974 sizeof(drv->LunID)) == 0) {
2975 FOUND = 1;
2976 break;
2977 }
2978 }
2979
2980 if (!FOUND)
2981 return 1;
2982
2983 inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL);
2984 if (inq_buff == NULL) {
2985 dev_warn(&h->pdev->dev, "out of memory\n");
2986 return 1;
2987 }
2988 if (h->cciss_read == CCISS_READ_10) {
2989 cciss_read_capacity(h, logvol,
2990 &total_size, &block_size);
2991 } else {
2992 cciss_read_capacity_16(h, logvol,
2993 &total_size, &block_size);
2994 }
2995 cciss_geometry_inquiry(h, logvol, total_size, block_size,
2996 inq_buff, drv);
2997
2998 blk_queue_logical_block_size(drv->queue, drv->block_size);
2999 set_capacity(disk, drv->nr_blocks);
3000
3001 kfree(inq_buff);
3002 return 0;
3003 }
3004
3005 /*
3006 * Map (physical) PCI mem into (virtual) kernel space
3007 */
3008 static void __iomem *remap_pci_mem(ulong base, ulong size)
3009 {
3010 ulong page_base = ((ulong) base) & PAGE_MASK;
3011 ulong page_offs = ((ulong) base) - page_base;
3012 void __iomem *page_remapped = ioremap(page_base, page_offs + size);
3013
3014 return page_remapped ? (page_remapped + page_offs) : NULL;
3015 }
3016
3017 /*
3018 * Takes jobs of the Q and sends them to the hardware, then puts it on
3019 * the Q to wait for completion.
3020 */
3021 static void start_io(ctlr_info_t *h)
3022 {
3023 CommandList_struct *c;
3024
3025 while (!list_empty(&h->reqQ)) {
3026 c = list_entry(h->reqQ.next, CommandList_struct, list);
3027 /* can't do anything if fifo is full */
3028 if ((h->access.fifo_full(h))) {
3029 dev_warn(&h->pdev->dev, "fifo full\n");
3030 break;
3031 }
3032
3033 /* Get the first entry from the Request Q */
3034 removeQ(c);
3035 h->Qdepth--;
3036
3037 /* Tell the controller execute command */
3038 h->access.submit_command(h, c);
3039
3040 /* Put job onto the completed Q */
3041 addQ(&h->cmpQ, c);
3042 }
3043 }
3044
3045 /* Assumes that h->lock is held. */
3046 /* Zeros out the error record and then resends the command back */
3047 /* to the controller */
3048 static inline void resend_cciss_cmd(ctlr_info_t *h, CommandList_struct *c)
3049 {
3050 /* erase the old error information */
3051 memset(c->err_info, 0, sizeof(ErrorInfo_struct));
3052
3053 /* add it to software queue and then send it to the controller */
3054 addQ(&h->reqQ, c);
3055 h->Qdepth++;
3056 if (h->Qdepth > h->maxQsinceinit)
3057 h->maxQsinceinit = h->Qdepth;
3058
3059 start_io(h);
3060 }
3061
3062 static inline unsigned int make_status_bytes(unsigned int scsi_status_byte,
3063 unsigned int msg_byte, unsigned int host_byte,
3064 unsigned int driver_byte)
3065 {
3066 /* inverse of macros in scsi.h */
3067 return (scsi_status_byte & 0xff) |
3068 ((msg_byte & 0xff) << 8) |
3069 ((host_byte & 0xff) << 16) |
3070 ((driver_byte & 0xff) << 24);
3071 }
3072
3073 static inline int evaluate_target_status(ctlr_info_t *h,
3074 CommandList_struct *cmd, int *retry_cmd)
3075 {
3076 unsigned char sense_key;
3077 unsigned char status_byte, msg_byte, host_byte, driver_byte;
3078 int error_value;
3079
3080 *retry_cmd = 0;
3081 /* If we get in here, it means we got "target status", that is, scsi status */
3082 status_byte = cmd->err_info->ScsiStatus;
3083 driver_byte = DRIVER_OK;
3084 msg_byte = cmd->err_info->CommandStatus; /* correct? seems too device specific */
3085
3086 if (blk_rq_is_passthrough(cmd->rq))
3087 host_byte = DID_PASSTHROUGH;
3088 else
3089 host_byte = DID_OK;
3090
3091 error_value = make_status_bytes(status_byte, msg_byte,
3092 host_byte, driver_byte);
3093
3094 if (cmd->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION) {
3095 if (!blk_rq_is_passthrough(cmd->rq))
3096 dev_warn(&h->pdev->dev, "cmd %p "
3097 "has SCSI Status 0x%x\n",
3098 cmd, cmd->err_info->ScsiStatus);
3099 return error_value;
3100 }
3101
3102 /* check the sense key */
3103 sense_key = 0xf & cmd->err_info->SenseInfo[2];
3104 /* no status or recovered error */
3105 if (((sense_key == 0x0) || (sense_key == 0x1)) &&
3106 !blk_rq_is_passthrough(cmd->rq))
3107 error_value = 0;
3108
3109 if (check_for_unit_attention(h, cmd)) {
3110 *retry_cmd = !blk_rq_is_passthrough(cmd->rq);
3111 return 0;
3112 }
3113
3114 /* Not SG_IO or similar? */
3115 if (!blk_rq_is_passthrough(cmd->rq)) {
3116 if (error_value != 0)
3117 dev_warn(&h->pdev->dev, "cmd %p has CHECK CONDITION"
3118 " sense key = 0x%x\n", cmd, sense_key);
3119 return error_value;
3120 }
3121
3122 scsi_req(cmd->rq)->sense_len = cmd->err_info->SenseLen;
3123 return error_value;
3124 }
3125
3126 /* checks the status of the job and calls complete buffers to mark all
3127 * buffers for the completed job. Note that this function does not need
3128 * to hold the hba/queue lock.
3129 */
3130 static inline void complete_command(ctlr_info_t *h, CommandList_struct *cmd,
3131 int timeout)
3132 {
3133 int retry_cmd = 0;
3134 struct request *rq = cmd->rq;
3135
3136 rq->errors = 0;
3137
3138 if (timeout)
3139 rq->errors = make_status_bytes(0, 0, 0, DRIVER_TIMEOUT);
3140
3141 if (cmd->err_info->CommandStatus == 0) /* no error has occurred */
3142 goto after_error_processing;
3143
3144 switch (cmd->err_info->CommandStatus) {
3145 case CMD_TARGET_STATUS:
3146 rq->errors = evaluate_target_status(h, cmd, &retry_cmd);
3147 break;
3148 case CMD_DATA_UNDERRUN:
3149 if (!blk_rq_is_passthrough(cmd->rq)) {
3150 dev_warn(&h->pdev->dev, "cmd %p has"
3151 " completed with data underrun "
3152 "reported\n", cmd);
3153 }
3154 break;
3155 case CMD_DATA_OVERRUN:
3156 if (!blk_rq_is_passthrough(cmd->rq))
3157 dev_warn(&h->pdev->dev, "cciss: cmd %p has"
3158 " completed with data overrun "
3159 "reported\n", cmd);
3160 break;
3161 case CMD_INVALID:
3162 dev_warn(&h->pdev->dev, "cciss: cmd %p is "
3163 "reported invalid\n", cmd);
3164 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3165 cmd->err_info->CommandStatus, DRIVER_OK,
3166 blk_rq_is_passthrough(cmd->rq) ?
3167 DID_PASSTHROUGH : DID_ERROR);
3168 break;
3169 case CMD_PROTOCOL_ERR:
3170 dev_warn(&h->pdev->dev, "cciss: cmd %p has "
3171 "protocol error\n", cmd);
3172 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3173 cmd->err_info->CommandStatus, DRIVER_OK,
3174 blk_rq_is_passthrough(cmd->rq) ?
3175 DID_PASSTHROUGH : DID_ERROR);
3176 break;
3177 case CMD_HARDWARE_ERR:
3178 dev_warn(&h->pdev->dev, "cciss: cmd %p had "
3179 " hardware error\n", cmd);
3180 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3181 cmd->err_info->CommandStatus, DRIVER_OK,
3182 blk_rq_is_passthrough(cmd->rq) ?
3183 DID_PASSTHROUGH : DID_ERROR);
3184 break;
3185 case CMD_CONNECTION_LOST:
3186 dev_warn(&h->pdev->dev, "cciss: cmd %p had "
3187 "connection lost\n", cmd);
3188 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3189 cmd->err_info->CommandStatus, DRIVER_OK,
3190 blk_rq_is_passthrough(cmd->rq) ?
3191 DID_PASSTHROUGH : DID_ERROR);
3192 break;
3193 case CMD_ABORTED:
3194 dev_warn(&h->pdev->dev, "cciss: cmd %p was "
3195 "aborted\n", cmd);
3196 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3197 cmd->err_info->CommandStatus, DRIVER_OK,
3198 blk_rq_is_passthrough(cmd->rq) ?
3199 DID_PASSTHROUGH : DID_ABORT);
3200 break;
3201 case CMD_ABORT_FAILED:
3202 dev_warn(&h->pdev->dev, "cciss: cmd %p reports "
3203 "abort failed\n", cmd);
3204 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3205 cmd->err_info->CommandStatus, DRIVER_OK,
3206 blk_rq_is_passthrough(cmd->rq) ?
3207 DID_PASSTHROUGH : DID_ERROR);
3208 break;
3209 case CMD_UNSOLICITED_ABORT:
3210 dev_warn(&h->pdev->dev, "cciss%d: unsolicited "
3211 "abort %p\n", h->ctlr, cmd);
3212 if (cmd->retry_count < MAX_CMD_RETRIES) {
3213 retry_cmd = 1;
3214 dev_warn(&h->pdev->dev, "retrying %p\n", cmd);
3215 cmd->retry_count++;
3216 } else
3217 dev_warn(&h->pdev->dev,
3218 "%p retried too many times\n", cmd);
3219 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3220 cmd->err_info->CommandStatus, DRIVER_OK,
3221 blk_rq_is_passthrough(cmd->rq) ?
3222 DID_PASSTHROUGH : DID_ABORT);
3223 break;
3224 case CMD_TIMEOUT:
3225 dev_warn(&h->pdev->dev, "cmd %p timedout\n", cmd);
3226 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3227 cmd->err_info->CommandStatus, DRIVER_OK,
3228 blk_rq_is_passthrough(cmd->rq) ?
3229 DID_PASSTHROUGH : DID_ERROR);
3230 break;
3231 case CMD_UNABORTABLE:
3232 dev_warn(&h->pdev->dev, "cmd %p unabortable\n", cmd);
3233 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3234 cmd->err_info->CommandStatus, DRIVER_OK,
3235 blk_rq_is_passthrough(cmd->rq) ?
3236 DID_PASSTHROUGH : DID_ERROR);
3237 break;
3238 default:
3239 dev_warn(&h->pdev->dev, "cmd %p returned "
3240 "unknown status %x\n", cmd,
3241 cmd->err_info->CommandStatus);
3242 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3243 cmd->err_info->CommandStatus, DRIVER_OK,
3244 blk_rq_is_passthrough(cmd->rq) ?
3245 DID_PASSTHROUGH : DID_ERROR);
3246 }
3247
3248 after_error_processing:
3249
3250 /* We need to return this command */
3251 if (retry_cmd) {
3252 resend_cciss_cmd(h, cmd);
3253 return;
3254 }
3255 cmd->rq->completion_data = cmd;
3256 blk_complete_request(cmd->rq);
3257 }
3258
3259 static inline u32 cciss_tag_contains_index(u32 tag)
3260 {
3261 #define DIRECT_LOOKUP_BIT 0x10
3262 return tag & DIRECT_LOOKUP_BIT;
3263 }
3264
3265 static inline u32 cciss_tag_to_index(u32 tag)
3266 {
3267 #define DIRECT_LOOKUP_SHIFT 5
3268 return tag >> DIRECT_LOOKUP_SHIFT;
3269 }
3270
3271 static inline u32 cciss_tag_discard_error_bits(ctlr_info_t *h, u32 tag)
3272 {
3273 #define CCISS_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
3274 #define CCISS_SIMPLE_ERROR_BITS 0x03
3275 if (likely(h->transMethod & CFGTBL_Trans_Performant))
3276 return tag & ~CCISS_PERF_ERROR_BITS;
3277 return tag & ~CCISS_SIMPLE_ERROR_BITS;
3278 }
3279
3280 static inline void cciss_mark_tag_indexed(u32 *tag)
3281 {
3282 *tag |= DIRECT_LOOKUP_BIT;
3283 }
3284
3285 static inline void cciss_set_tag_index(u32 *tag, u32 index)
3286 {
3287 *tag |= (index << DIRECT_LOOKUP_SHIFT);
3288 }
3289
3290 /*
3291 * Get a request and submit it to the controller.
3292 */
3293 static void do_cciss_request(struct request_queue *q)
3294 {
3295 ctlr_info_t *h = q->queuedata;
3296 CommandList_struct *c;
3297 sector_t start_blk;
3298 int seg;
3299 struct request *creq;
3300 u64bit temp64;
3301 struct scatterlist *tmp_sg;
3302 SGDescriptor_struct *curr_sg;
3303 drive_info_struct *drv;
3304 int i, dir;
3305 int sg_index = 0;
3306 int chained = 0;
3307
3308 queue:
3309 creq = blk_peek_request(q);
3310 if (!creq)
3311 goto startio;
3312
3313 BUG_ON(creq->nr_phys_segments > h->maxsgentries);
3314
3315 c = cmd_alloc(h);
3316 if (!c)
3317 goto full;
3318
3319 blk_start_request(creq);
3320
3321 tmp_sg = h->scatter_list[c->cmdindex];
3322 spin_unlock_irq(q->queue_lock);
3323
3324 c->cmd_type = CMD_RWREQ;
3325 c->rq = creq;
3326
3327 /* fill in the request */
3328 drv = creq->rq_disk->private_data;
3329 c->Header.ReplyQueue = 0; /* unused in simple mode */
3330 /* got command from pool, so use the command block index instead */
3331 /* for direct lookups. */
3332 /* The first 2 bits are reserved for controller error reporting. */
3333 cciss_set_tag_index(&c->Header.Tag.lower, c->cmdindex);
3334 cciss_mark_tag_indexed(&c->Header.Tag.lower);
3335 memcpy(&c->Header.LUN, drv->LunID, sizeof(drv->LunID));
3336 c->Request.CDBLen = 10; /* 12 byte commands not in FW yet; */
3337 c->Request.Type.Type = TYPE_CMD; /* It is a command. */
3338 c->Request.Type.Attribute = ATTR_SIMPLE;
3339 c->Request.Type.Direction =
3340 (rq_data_dir(creq) == READ) ? XFER_READ : XFER_WRITE;
3341 c->Request.Timeout = 0; /* Don't time out */
3342 c->Request.CDB[0] =
3343 (rq_data_dir(creq) == READ) ? h->cciss_read : h->cciss_write;
3344 start_blk = blk_rq_pos(creq);
3345 dev_dbg(&h->pdev->dev, "sector =%d nr_sectors=%d\n",
3346 (int)blk_rq_pos(creq), (int)blk_rq_sectors(creq));
3347 sg_init_table(tmp_sg, h->maxsgentries);
3348 seg = blk_rq_map_sg(q, creq, tmp_sg);
3349
3350 /* get the DMA records for the setup */
3351 if (c->Request.Type.Direction == XFER_READ)
3352 dir = PCI_DMA_FROMDEVICE;
3353 else
3354 dir = PCI_DMA_TODEVICE;
3355
3356 curr_sg = c->SG;
3357 sg_index = 0;
3358 chained = 0;
3359
3360 for (i = 0; i < seg; i++) {
3361 if (((sg_index+1) == (h->max_cmd_sgentries)) &&
3362 !chained && ((seg - i) > 1)) {
3363 /* Point to next chain block. */
3364 curr_sg = h->cmd_sg_list[c->cmdindex];
3365 sg_index = 0;
3366 chained = 1;
3367 }
3368 curr_sg[sg_index].Len = tmp_sg[i].length;
3369 temp64.val = (__u64) pci_map_page(h->pdev, sg_page(&tmp_sg[i]),
3370 tmp_sg[i].offset,
3371 tmp_sg[i].length, dir);
3372 curr_sg[sg_index].Addr.lower = temp64.val32.lower;
3373 curr_sg[sg_index].Addr.upper = temp64.val32.upper;
3374 curr_sg[sg_index].Ext = 0; /* we are not chaining */
3375 ++sg_index;
3376 }
3377 if (chained)
3378 cciss_map_sg_chain_block(h, c, h->cmd_sg_list[c->cmdindex],
3379 (seg - (h->max_cmd_sgentries - 1)) *
3380 sizeof(SGDescriptor_struct));
3381
3382 /* track how many SG entries we are using */
3383 if (seg > h->maxSG)
3384 h->maxSG = seg;
3385
3386 dev_dbg(&h->pdev->dev, "Submitting %u sectors in %d segments "
3387 "chained[%d]\n",
3388 blk_rq_sectors(creq), seg, chained);
3389
3390 c->Header.SGTotal = seg + chained;
3391 if (seg <= h->max_cmd_sgentries)
3392 c->Header.SGList = c->Header.SGTotal;
3393 else
3394 c->Header.SGList = h->max_cmd_sgentries;
3395 set_performant_mode(h, c);
3396
3397 switch (req_op(creq)) {
3398 case REQ_OP_READ:
3399 case REQ_OP_WRITE:
3400 if(h->cciss_read == CCISS_READ_10) {
3401 c->Request.CDB[1] = 0;
3402 c->Request.CDB[2] = (start_blk >> 24) & 0xff; /* MSB */
3403 c->Request.CDB[3] = (start_blk >> 16) & 0xff;
3404 c->Request.CDB[4] = (start_blk >> 8) & 0xff;
3405 c->Request.CDB[5] = start_blk & 0xff;
3406 c->Request.CDB[6] = 0; /* (sect >> 24) & 0xff; MSB */
3407 c->Request.CDB[7] = (blk_rq_sectors(creq) >> 8) & 0xff;
3408 c->Request.CDB[8] = blk_rq_sectors(creq) & 0xff;
3409 c->Request.CDB[9] = c->Request.CDB[11] = c->Request.CDB[12] = 0;
3410 } else {
3411 u32 upper32 = upper_32_bits(start_blk);
3412
3413 c->Request.CDBLen = 16;
3414 c->Request.CDB[1]= 0;
3415 c->Request.CDB[2]= (upper32 >> 24) & 0xff; /* MSB */
3416 c->Request.CDB[3]= (upper32 >> 16) & 0xff;
3417 c->Request.CDB[4]= (upper32 >> 8) & 0xff;
3418 c->Request.CDB[5]= upper32 & 0xff;
3419 c->Request.CDB[6]= (start_blk >> 24) & 0xff;
3420 c->Request.CDB[7]= (start_blk >> 16) & 0xff;
3421 c->Request.CDB[8]= (start_blk >> 8) & 0xff;
3422 c->Request.CDB[9]= start_blk & 0xff;
3423 c->Request.CDB[10]= (blk_rq_sectors(creq) >> 24) & 0xff;
3424 c->Request.CDB[11]= (blk_rq_sectors(creq) >> 16) & 0xff;
3425 c->Request.CDB[12]= (blk_rq_sectors(creq) >> 8) & 0xff;
3426 c->Request.CDB[13]= blk_rq_sectors(creq) & 0xff;
3427 c->Request.CDB[14] = c->Request.CDB[15] = 0;
3428 }
3429 break;
3430 case REQ_OP_SCSI_IN:
3431 case REQ_OP_SCSI_OUT:
3432 c->Request.CDBLen = scsi_req(creq)->cmd_len;
3433 memcpy(c->Request.CDB, scsi_req(creq)->cmd, BLK_MAX_CDB);
3434 scsi_req(creq)->sense = c->err_info->SenseInfo;
3435 break;
3436 default:
3437 dev_warn(&h->pdev->dev, "bad request type %d\n",
3438 creq->cmd_flags);
3439 BUG();
3440 }
3441
3442 spin_lock_irq(q->queue_lock);
3443
3444 addQ(&h->reqQ, c);
3445 h->Qdepth++;
3446 if (h->Qdepth > h->maxQsinceinit)
3447 h->maxQsinceinit = h->Qdepth;
3448
3449 goto queue;
3450 full:
3451 blk_stop_queue(q);
3452 startio:
3453 /* We will already have the driver lock here so not need
3454 * to lock it.
3455 */
3456 start_io(h);
3457 }
3458
3459 static inline unsigned long get_next_completion(ctlr_info_t *h)
3460 {
3461 return h->access.command_completed(h);
3462 }
3463
3464 static inline int interrupt_pending(ctlr_info_t *h)
3465 {
3466 return h->access.intr_pending(h);
3467 }
3468
3469 static inline long interrupt_not_for_us(ctlr_info_t *h)
3470 {
3471 return ((h->access.intr_pending(h) == 0) ||
3472 (h->interrupts_enabled == 0));
3473 }
3474
3475 static inline int bad_tag(ctlr_info_t *h, u32 tag_index,
3476 u32 raw_tag)
3477 {
3478 if (unlikely(tag_index >= h->nr_cmds)) {
3479 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
3480 return 1;
3481 }
3482 return 0;
3483 }
3484
3485 static inline void finish_cmd(ctlr_info_t *h, CommandList_struct *c,
3486 u32 raw_tag)
3487 {
3488 removeQ(c);
3489 if (likely(c->cmd_type == CMD_RWREQ))
3490 complete_command(h, c, 0);
3491 else if (c->cmd_type == CMD_IOCTL_PEND)
3492 complete(c->waiting);
3493 #ifdef CONFIG_CISS_SCSI_TAPE
3494 else if (c->cmd_type == CMD_SCSI)
3495 complete_scsi_command(c, 0, raw_tag);
3496 #endif
3497 }
3498
3499 static inline u32 next_command(ctlr_info_t *h)
3500 {
3501 u32 a;
3502
3503 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
3504 return h->access.command_completed(h);
3505
3506 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
3507 a = *(h->reply_pool_head); /* Next cmd in ring buffer */
3508 (h->reply_pool_head)++;
3509 h->commands_outstanding--;
3510 } else {
3511 a = FIFO_EMPTY;
3512 }
3513 /* Check for wraparound */
3514 if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
3515 h->reply_pool_head = h->reply_pool;
3516 h->reply_pool_wraparound ^= 1;
3517 }
3518 return a;
3519 }
3520
3521 /* process completion of an indexed ("direct lookup") command */
3522 static inline u32 process_indexed_cmd(ctlr_info_t *h, u32 raw_tag)
3523 {
3524 u32 tag_index;
3525 CommandList_struct *c;
3526
3527 tag_index = cciss_tag_to_index(raw_tag);
3528 if (bad_tag(h, tag_index, raw_tag))
3529 return next_command(h);
3530 c = h->cmd_pool + tag_index;
3531 finish_cmd(h, c, raw_tag);
3532 return next_command(h);
3533 }
3534
3535 /* process completion of a non-indexed command */
3536 static inline u32 process_nonindexed_cmd(ctlr_info_t *h, u32 raw_tag)
3537 {
3538 CommandList_struct *c = NULL;
3539 __u32 busaddr_masked, tag_masked;
3540
3541 tag_masked = cciss_tag_discard_error_bits(h, raw_tag);
3542 list_for_each_entry(c, &h->cmpQ, list) {
3543 busaddr_masked = cciss_tag_discard_error_bits(h, c->busaddr);
3544 if (busaddr_masked == tag_masked) {
3545 finish_cmd(h, c, raw_tag);
3546 return next_command(h);
3547 }
3548 }
3549 bad_tag(h, h->nr_cmds + 1, raw_tag);
3550 return next_command(h);
3551 }
3552
3553 /* Some controllers, like p400, will give us one interrupt
3554 * after a soft reset, even if we turned interrupts off.
3555 * Only need to check for this in the cciss_xxx_discard_completions
3556 * functions.
3557 */
3558 static int ignore_bogus_interrupt(ctlr_info_t *h)
3559 {
3560 if (likely(!reset_devices))
3561 return 0;
3562
3563 if (likely(h->interrupts_enabled))
3564 return 0;
3565
3566 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
3567 "(known firmware bug.) Ignoring.\n");
3568
3569 return 1;
3570 }
3571
3572 static irqreturn_t cciss_intx_discard_completions(int irq, void *dev_id)
3573 {
3574 ctlr_info_t *h = dev_id;
3575 unsigned long flags;
3576 u32 raw_tag;
3577
3578 if (ignore_bogus_interrupt(h))
3579 return IRQ_NONE;
3580
3581 if (interrupt_not_for_us(h))
3582 return IRQ_NONE;
3583 spin_lock_irqsave(&h->lock, flags);
3584 while (interrupt_pending(h)) {
3585 raw_tag = get_next_completion(h);
3586 while (raw_tag != FIFO_EMPTY)
3587 raw_tag = next_command(h);
3588 }
3589 spin_unlock_irqrestore(&h->lock, flags);
3590 return IRQ_HANDLED;
3591 }
3592
3593 static irqreturn_t cciss_msix_discard_completions(int irq, void *dev_id)
3594 {
3595 ctlr_info_t *h = dev_id;
3596 unsigned long flags;
3597 u32 raw_tag;
3598
3599 if (ignore_bogus_interrupt(h))
3600 return IRQ_NONE;
3601
3602 spin_lock_irqsave(&h->lock, flags);
3603 raw_tag = get_next_completion(h);
3604 while (raw_tag != FIFO_EMPTY)
3605 raw_tag = next_command(h);
3606 spin_unlock_irqrestore(&h->lock, flags);
3607 return IRQ_HANDLED;
3608 }
3609
3610 static irqreturn_t do_cciss_intx(int irq, void *dev_id)
3611 {
3612 ctlr_info_t *h = dev_id;
3613 unsigned long flags;
3614 u32 raw_tag;
3615
3616 if (interrupt_not_for_us(h))
3617 return IRQ_NONE;
3618 spin_lock_irqsave(&h->lock, flags);
3619 while (interrupt_pending(h)) {
3620 raw_tag = get_next_completion(h);
3621 while (raw_tag != FIFO_EMPTY) {
3622 if (cciss_tag_contains_index(raw_tag))
3623 raw_tag = process_indexed_cmd(h, raw_tag);
3624 else
3625 raw_tag = process_nonindexed_cmd(h, raw_tag);
3626 }
3627 }
3628 spin_unlock_irqrestore(&h->lock, flags);
3629 return IRQ_HANDLED;
3630 }
3631
3632 /* Add a second interrupt handler for MSI/MSI-X mode. In this mode we never
3633 * check the interrupt pending register because it is not set.
3634 */
3635 static irqreturn_t do_cciss_msix_intr(int irq, void *dev_id)
3636 {
3637 ctlr_info_t *h = dev_id;
3638 unsigned long flags;
3639 u32 raw_tag;
3640
3641 spin_lock_irqsave(&h->lock, flags);
3642 raw_tag = get_next_completion(h);
3643 while (raw_tag != FIFO_EMPTY) {
3644 if (cciss_tag_contains_index(raw_tag))
3645 raw_tag = process_indexed_cmd(h, raw_tag);
3646 else
3647 raw_tag = process_nonindexed_cmd(h, raw_tag);
3648 }
3649 spin_unlock_irqrestore(&h->lock, flags);
3650 return IRQ_HANDLED;
3651 }
3652
3653 /**
3654 * add_to_scan_list() - add controller to rescan queue
3655 * @h: Pointer to the controller.
3656 *
3657 * Adds the controller to the rescan queue if not already on the queue.
3658 *
3659 * returns 1 if added to the queue, 0 if skipped (could be on the
3660 * queue already, or the controller could be initializing or shutting
3661 * down).
3662 **/
3663 static int add_to_scan_list(struct ctlr_info *h)
3664 {
3665 struct ctlr_info *test_h;
3666 int found = 0;
3667 int ret = 0;
3668
3669 if (h->busy_initializing)
3670 return 0;
3671
3672 if (!mutex_trylock(&h->busy_shutting_down))
3673 return 0;
3674
3675 mutex_lock(&scan_mutex);
3676 list_for_each_entry(test_h, &scan_q, scan_list) {
3677 if (test_h == h) {
3678 found = 1;
3679 break;
3680 }
3681 }
3682 if (!found && !h->busy_scanning) {
3683 reinit_completion(&h->scan_wait);
3684 list_add_tail(&h->scan_list, &scan_q);
3685 ret = 1;
3686 }
3687 mutex_unlock(&scan_mutex);
3688 mutex_unlock(&h->busy_shutting_down);
3689
3690 return ret;
3691 }
3692
3693 /**
3694 * remove_from_scan_list() - remove controller from rescan queue
3695 * @h: Pointer to the controller.
3696 *
3697 * Removes the controller from the rescan queue if present. Blocks if
3698 * the controller is currently conducting a rescan. The controller
3699 * can be in one of three states:
3700 * 1. Doesn't need a scan
3701 * 2. On the scan list, but not scanning yet (we remove it)
3702 * 3. Busy scanning (and not on the list). In this case we want to wait for
3703 * the scan to complete to make sure the scanning thread for this
3704 * controller is completely idle.
3705 **/
3706 static void remove_from_scan_list(struct ctlr_info *h)
3707 {
3708 struct ctlr_info *test_h, *tmp_h;
3709
3710 mutex_lock(&scan_mutex);
3711 list_for_each_entry_safe(test_h, tmp_h, &scan_q, scan_list) {
3712 if (test_h == h) { /* state 2. */
3713 list_del(&h->scan_list);
3714 complete_all(&h->scan_wait);
3715 mutex_unlock(&scan_mutex);
3716 return;
3717 }
3718 }
3719 if (h->busy_scanning) { /* state 3. */
3720 mutex_unlock(&scan_mutex);
3721 wait_for_completion(&h->scan_wait);
3722 } else { /* state 1, nothing to do. */
3723 mutex_unlock(&scan_mutex);
3724 }
3725 }
3726
3727 /**
3728 * scan_thread() - kernel thread used to rescan controllers
3729 * @data: Ignored.
3730 *
3731 * A kernel thread used scan for drive topology changes on
3732 * controllers. The thread processes only one controller at a time
3733 * using a queue. Controllers are added to the queue using
3734 * add_to_scan_list() and removed from the queue either after done
3735 * processing or using remove_from_scan_list().
3736 *
3737 * returns 0.
3738 **/
3739 static int scan_thread(void *data)
3740 {
3741 struct ctlr_info *h;
3742
3743 while (1) {
3744 set_current_state(TASK_INTERRUPTIBLE);
3745 schedule();
3746 if (kthread_should_stop())
3747 break;
3748
3749 while (1) {
3750 mutex_lock(&scan_mutex);
3751 if (list_empty(&scan_q)) {
3752 mutex_unlock(&scan_mutex);
3753 break;
3754 }
3755
3756 h = list_entry(scan_q.next,
3757 struct ctlr_info,
3758 scan_list);
3759 list_del(&h->scan_list);
3760 h->busy_scanning = 1;
3761 mutex_unlock(&scan_mutex);
3762
3763 rebuild_lun_table(h, 0, 0);
3764 complete_all(&h->scan_wait);
3765 mutex_lock(&scan_mutex);
3766 h->busy_scanning = 0;
3767 mutex_unlock(&scan_mutex);
3768 }
3769 }
3770
3771 return 0;
3772 }
3773
3774 static int check_for_unit_attention(ctlr_info_t *h, CommandList_struct *c)
3775 {
3776 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
3777 return 0;
3778
3779 switch (c->err_info->SenseInfo[12]) {
3780 case STATE_CHANGED:
3781 dev_warn(&h->pdev->dev, "a state change "
3782 "detected, command retried\n");
3783 return 1;
3784 break;
3785 case LUN_FAILED:
3786 dev_warn(&h->pdev->dev, "LUN failure "
3787 "detected, action required\n");
3788 return 1;
3789 break;
3790 case REPORT_LUNS_CHANGED:
3791 dev_warn(&h->pdev->dev, "report LUN data changed\n");
3792 /*
3793 * Here, we could call add_to_scan_list and wake up the scan thread,
3794 * except that it's quite likely that we will get more than one
3795 * REPORT_LUNS_CHANGED condition in quick succession, which means
3796 * that those which occur after the first one will likely happen
3797 * *during* the scan_thread's rescan. And the rescan code is not
3798 * robust enough to restart in the middle, undoing what it has already
3799 * done, and it's not clear that it's even possible to do this, since
3800 * part of what it does is notify the block layer, which starts
3801 * doing it's own i/o to read partition tables and so on, and the
3802 * driver doesn't have visibility to know what might need undoing.
3803 * In any event, if possible, it is horribly complicated to get right
3804 * so we just don't do it for now.
3805 *
3806 * Note: this REPORT_LUNS_CHANGED condition only occurs on the MSA2012.
3807 */
3808 return 1;
3809 break;
3810 case POWER_OR_RESET:
3811 dev_warn(&h->pdev->dev,
3812 "a power on or device reset detected\n");
3813 return 1;
3814 break;
3815 case UNIT_ATTENTION_CLEARED:
3816 dev_warn(&h->pdev->dev,
3817 "unit attention cleared by another initiator\n");
3818 return 1;
3819 break;
3820 default:
3821 dev_warn(&h->pdev->dev, "unknown unit attention detected\n");
3822 return 1;
3823 }
3824 }
3825
3826 /*
3827 * We cannot read the structure directly, for portability we must use
3828 * the io functions.
3829 * This is for debug only.
3830 */
3831 static void print_cfg_table(ctlr_info_t *h)
3832 {
3833 int i;
3834 char temp_name[17];
3835 CfgTable_struct *tb = h->cfgtable;
3836
3837 dev_dbg(&h->pdev->dev, "Controller Configuration information\n");
3838 dev_dbg(&h->pdev->dev, "------------------------------------\n");
3839 for (i = 0; i < 4; i++)
3840 temp_name[i] = readb(&(tb->Signature[i]));
3841 temp_name[4] = '\0';
3842 dev_dbg(&h->pdev->dev, " Signature = %s\n", temp_name);
3843 dev_dbg(&h->pdev->dev, " Spec Number = %d\n",
3844 readl(&(tb->SpecValence)));
3845 dev_dbg(&h->pdev->dev, " Transport methods supported = 0x%x\n",
3846 readl(&(tb->TransportSupport)));
3847 dev_dbg(&h->pdev->dev, " Transport methods active = 0x%x\n",
3848 readl(&(tb->TransportActive)));
3849 dev_dbg(&h->pdev->dev, " Requested transport Method = 0x%x\n",
3850 readl(&(tb->HostWrite.TransportRequest)));
3851 dev_dbg(&h->pdev->dev, " Coalesce Interrupt Delay = 0x%x\n",
3852 readl(&(tb->HostWrite.CoalIntDelay)));
3853 dev_dbg(&h->pdev->dev, " Coalesce Interrupt Count = 0x%x\n",
3854 readl(&(tb->HostWrite.CoalIntCount)));
3855 dev_dbg(&h->pdev->dev, " Max outstanding commands = 0x%x\n",
3856 readl(&(tb->CmdsOutMax)));
3857 dev_dbg(&h->pdev->dev, " Bus Types = 0x%x\n",
3858 readl(&(tb->BusTypes)));
3859 for (i = 0; i < 16; i++)
3860 temp_name[i] = readb(&(tb->ServerName[i]));
3861 temp_name[16] = '\0';
3862 dev_dbg(&h->pdev->dev, " Server Name = %s\n", temp_name);
3863 dev_dbg(&h->pdev->dev, " Heartbeat Counter = 0x%x\n\n\n",
3864 readl(&(tb->HeartBeat)));
3865 }
3866
3867 static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
3868 {
3869 int i, offset, mem_type, bar_type;
3870 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
3871 return 0;
3872 offset = 0;
3873 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
3874 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
3875 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
3876 offset += 4;
3877 else {
3878 mem_type = pci_resource_flags(pdev, i) &
3879 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
3880 switch (mem_type) {
3881 case PCI_BASE_ADDRESS_MEM_TYPE_32:
3882 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
3883 offset += 4; /* 32 bit */
3884 break;
3885 case PCI_BASE_ADDRESS_MEM_TYPE_64:
3886 offset += 8;
3887 break;
3888 default: /* reserved in PCI 2.2 */
3889 dev_warn(&pdev->dev,
3890 "Base address is invalid\n");
3891 return -1;
3892 break;
3893 }
3894 }
3895 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
3896 return i + 1;
3897 }
3898 return -1;
3899 }
3900
3901 /* Fill in bucket_map[], given nsgs (the max number of
3902 * scatter gather elements supported) and bucket[],
3903 * which is an array of 8 integers. The bucket[] array
3904 * contains 8 different DMA transfer sizes (in 16
3905 * byte increments) which the controller uses to fetch
3906 * commands. This function fills in bucket_map[], which
3907 * maps a given number of scatter gather elements to one of
3908 * the 8 DMA transfer sizes. The point of it is to allow the
3909 * controller to only do as much DMA as needed to fetch the
3910 * command, with the DMA transfer size encoded in the lower
3911 * bits of the command address.
3912 */
3913 static void calc_bucket_map(int bucket[], int num_buckets,
3914 int nsgs, int *bucket_map)
3915 {
3916 int i, j, b, size;
3917
3918 /* even a command with 0 SGs requires 4 blocks */
3919 #define MINIMUM_TRANSFER_BLOCKS 4
3920 #define NUM_BUCKETS 8
3921 /* Note, bucket_map must have nsgs+1 entries. */
3922 for (i = 0; i <= nsgs; i++) {
3923 /* Compute size of a command with i SG entries */
3924 size = i + MINIMUM_TRANSFER_BLOCKS;
3925 b = num_buckets; /* Assume the biggest bucket */
3926 /* Find the bucket that is just big enough */
3927 for (j = 0; j < 8; j++) {
3928 if (bucket[j] >= size) {
3929 b = j;
3930 break;
3931 }
3932 }
3933 /* for a command with i SG entries, use bucket b. */
3934 bucket_map[i] = b;
3935 }
3936 }
3937
3938 static void cciss_wait_for_mode_change_ack(ctlr_info_t *h)
3939 {
3940 int i;
3941
3942 /* under certain very rare conditions, this can take awhile.
3943 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
3944 * as we enter this code.) */
3945 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
3946 if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
3947 break;
3948 usleep_range(10000, 20000);
3949 }
3950 }
3951
3952 static void cciss_enter_performant_mode(ctlr_info_t *h, u32 use_short_tags)
3953 {
3954 /* This is a bit complicated. There are 8 registers on
3955 * the controller which we write to to tell it 8 different
3956 * sizes of commands which there may be. It's a way of
3957 * reducing the DMA done to fetch each command. Encoded into
3958 * each command's tag are 3 bits which communicate to the controller
3959 * which of the eight sizes that command fits within. The size of
3960 * each command depends on how many scatter gather entries there are.
3961 * Each SG entry requires 16 bytes. The eight registers are programmed
3962 * with the number of 16-byte blocks a command of that size requires.
3963 * The smallest command possible requires 5 such 16 byte blocks.
3964 * the largest command possible requires MAXSGENTRIES + 4 16-byte
3965 * blocks. Note, this only extends to the SG entries contained
3966 * within the command block, and does not extend to chained blocks
3967 * of SG elements. bft[] contains the eight values we write to
3968 * the registers. They are not evenly distributed, but have more
3969 * sizes for small commands, and fewer sizes for larger commands.
3970 */
3971 __u32 trans_offset;
3972 int bft[8] = { 5, 6, 8, 10, 12, 20, 28, MAXSGENTRIES + 4};
3973 /*
3974 * 5 = 1 s/g entry or 4k
3975 * 6 = 2 s/g entry or 8k
3976 * 8 = 4 s/g entry or 16k
3977 * 10 = 6 s/g entry or 24k
3978 */
3979 unsigned long register_value;
3980 BUILD_BUG_ON(28 > MAXSGENTRIES + 4);
3981
3982 h->reply_pool_wraparound = 1; /* spec: init to 1 */
3983
3984 /* Controller spec: zero out this buffer. */
3985 memset(h->reply_pool, 0, h->max_commands * sizeof(__u64));
3986 h->reply_pool_head = h->reply_pool;
3987
3988 trans_offset = readl(&(h->cfgtable->TransMethodOffset));
3989 calc_bucket_map(bft, ARRAY_SIZE(bft), h->maxsgentries,
3990 h->blockFetchTable);
3991 writel(bft[0], &h->transtable->BlockFetch0);
3992 writel(bft[1], &h->transtable->BlockFetch1);
3993 writel(bft[2], &h->transtable->BlockFetch2);
3994 writel(bft[3], &h->transtable->BlockFetch3);
3995 writel(bft[4], &h->transtable->BlockFetch4);
3996 writel(bft[5], &h->transtable->BlockFetch5);
3997 writel(bft[6], &h->transtable->BlockFetch6);
3998 writel(bft[7], &h->transtable->BlockFetch7);
3999
4000 /* size of controller ring buffer */
4001 writel(h->max_commands, &h->transtable->RepQSize);
4002 writel(1, &h->transtable->RepQCount);
4003 writel(0, &h->transtable->RepQCtrAddrLow32);
4004 writel(0, &h->transtable->RepQCtrAddrHigh32);
4005 writel(h->reply_pool_dhandle, &h->transtable->RepQAddr0Low32);
4006 writel(0, &h->transtable->RepQAddr0High32);
4007 writel(CFGTBL_Trans_Performant | use_short_tags,
4008 &(h->cfgtable->HostWrite.TransportRequest));
4009
4010 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
4011 cciss_wait_for_mode_change_ack(h);
4012 register_value = readl(&(h->cfgtable->TransportActive));
4013 if (!(register_value & CFGTBL_Trans_Performant))
4014 dev_warn(&h->pdev->dev, "cciss: unable to get board into"
4015 " performant mode\n");
4016 }
4017
4018 static void cciss_put_controller_into_performant_mode(ctlr_info_t *h)
4019 {
4020 __u32 trans_support;
4021
4022 if (cciss_simple_mode)
4023 return;
4024
4025 dev_dbg(&h->pdev->dev, "Trying to put board into Performant mode\n");
4026 /* Attempt to put controller into performant mode if supported */
4027 /* Does board support performant mode? */
4028 trans_support = readl(&(h->cfgtable->TransportSupport));
4029 if (!(trans_support & PERFORMANT_MODE))
4030 return;
4031
4032 dev_dbg(&h->pdev->dev, "Placing controller into performant mode\n");
4033 /* Performant mode demands commands on a 32 byte boundary
4034 * pci_alloc_consistent aligns on page boundarys already.
4035 * Just need to check if divisible by 32
4036 */
4037 if ((sizeof(CommandList_struct) % 32) != 0) {
4038 dev_warn(&h->pdev->dev, "%s %d %s\n",
4039 "cciss info: command size[",
4040 (int)sizeof(CommandList_struct),
4041 "] not divisible by 32, no performant mode..\n");
4042 return;
4043 }
4044
4045 /* Performant mode ring buffer and supporting data structures */
4046 h->reply_pool = (__u64 *)pci_alloc_consistent(
4047 h->pdev, h->max_commands * sizeof(__u64),
4048 &(h->reply_pool_dhandle));
4049
4050 /* Need a block fetch table for performant mode */
4051 h->blockFetchTable = kmalloc(((h->maxsgentries+1) *
4052 sizeof(__u32)), GFP_KERNEL);
4053
4054 if ((h->reply_pool == NULL) || (h->blockFetchTable == NULL))
4055 goto clean_up;
4056
4057 cciss_enter_performant_mode(h,
4058 trans_support & CFGTBL_Trans_use_short_tags);
4059
4060 /* Change the access methods to the performant access methods */
4061 h->access = SA5_performant_access;
4062 h->transMethod = CFGTBL_Trans_Performant;
4063
4064 return;
4065 clean_up:
4066 kfree(h->blockFetchTable);
4067 if (h->reply_pool)
4068 pci_free_consistent(h->pdev,
4069 h->max_commands * sizeof(__u64),
4070 h->reply_pool,
4071 h->reply_pool_dhandle);
4072 return;
4073
4074 } /* cciss_put_controller_into_performant_mode */
4075
4076 /* If MSI/MSI-X is supported by the kernel we will try to enable it on
4077 * controllers that are capable. If not, we use IO-APIC mode.
4078 */
4079
4080 static void cciss_interrupt_mode(ctlr_info_t *h)
4081 {
4082 #ifdef CONFIG_PCI_MSI
4083 int err;
4084 struct msix_entry cciss_msix_entries[4] = { {0, 0}, {0, 1},
4085 {0, 2}, {0, 3}
4086 };
4087
4088 /* Some boards advertise MSI but don't really support it */
4089 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
4090 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
4091 goto default_int_mode;
4092
4093 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
4094 err = pci_enable_msix_exact(h->pdev, cciss_msix_entries, 4);
4095 if (!err) {
4096 h->intr[0] = cciss_msix_entries[0].vector;
4097 h->intr[1] = cciss_msix_entries[1].vector;
4098 h->intr[2] = cciss_msix_entries[2].vector;
4099 h->intr[3] = cciss_msix_entries[3].vector;
4100 h->msix_vector = 1;
4101 return;
4102 } else {
4103 dev_warn(&h->pdev->dev,
4104 "MSI-X init failed %d\n", err);
4105 }
4106 }
4107 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
4108 if (!pci_enable_msi(h->pdev))
4109 h->msi_vector = 1;
4110 else
4111 dev_warn(&h->pdev->dev, "MSI init failed\n");
4112 }
4113 default_int_mode:
4114 #endif /* CONFIG_PCI_MSI */
4115 /* if we get here we're going to use the default interrupt mode */
4116 h->intr[h->intr_mode] = h->pdev->irq;
4117 return;
4118 }
4119
4120 static int cciss_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
4121 {
4122 int i;
4123 u32 subsystem_vendor_id, subsystem_device_id;
4124
4125 subsystem_vendor_id = pdev->subsystem_vendor;
4126 subsystem_device_id = pdev->subsystem_device;
4127 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
4128 subsystem_vendor_id;
4129
4130 for (i = 0; i < ARRAY_SIZE(products); i++) {
4131 /* Stand aside for hpsa driver on request */
4132 if (cciss_allow_hpsa)
4133 return -ENODEV;
4134 if (*board_id == products[i].board_id)
4135 return i;
4136 }
4137 dev_warn(&pdev->dev, "unrecognized board ID: 0x%08x, ignoring.\n",
4138 *board_id);
4139 return -ENODEV;
4140 }
4141
4142 static inline bool cciss_board_disabled(ctlr_info_t *h)
4143 {
4144 u16 command;
4145
4146 (void) pci_read_config_word(h->pdev, PCI_COMMAND, &command);
4147 return ((command & PCI_COMMAND_MEMORY) == 0);
4148 }
4149
4150 static int cciss_pci_find_memory_BAR(struct pci_dev *pdev,
4151 unsigned long *memory_bar)
4152 {
4153 int i;
4154
4155 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
4156 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
4157 /* addressing mode bits already removed */
4158 *memory_bar = pci_resource_start(pdev, i);
4159 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
4160 *memory_bar);
4161 return 0;
4162 }
4163 dev_warn(&pdev->dev, "no memory BAR found\n");
4164 return -ENODEV;
4165 }
4166
4167 static int cciss_wait_for_board_state(struct pci_dev *pdev,
4168 void __iomem *vaddr, int wait_for_ready)
4169 #define BOARD_READY 1
4170 #define BOARD_NOT_READY 0
4171 {
4172 int i, iterations;
4173 u32 scratchpad;
4174
4175 if (wait_for_ready)
4176 iterations = CCISS_BOARD_READY_ITERATIONS;
4177 else
4178 iterations = CCISS_BOARD_NOT_READY_ITERATIONS;
4179
4180 for (i = 0; i < iterations; i++) {
4181 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
4182 if (wait_for_ready) {
4183 if (scratchpad == CCISS_FIRMWARE_READY)
4184 return 0;
4185 } else {
4186 if (scratchpad != CCISS_FIRMWARE_READY)
4187 return 0;
4188 }
4189 msleep(CCISS_BOARD_READY_POLL_INTERVAL_MSECS);
4190 }
4191 dev_warn(&pdev->dev, "board not ready, timed out.\n");
4192 return -ENODEV;
4193 }
4194
4195 static int cciss_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
4196 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
4197 u64 *cfg_offset)
4198 {
4199 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
4200 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
4201 *cfg_base_addr &= (u32) 0x0000ffff;
4202 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
4203 if (*cfg_base_addr_index == -1) {
4204 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index, "
4205 "*cfg_base_addr = 0x%08x\n", *cfg_base_addr);
4206 return -ENODEV;
4207 }
4208 return 0;
4209 }
4210
4211 static int cciss_find_cfgtables(ctlr_info_t *h)
4212 {
4213 u64 cfg_offset;
4214 u32 cfg_base_addr;
4215 u64 cfg_base_addr_index;
4216 u32 trans_offset;
4217 int rc;
4218
4219 rc = cciss_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
4220 &cfg_base_addr_index, &cfg_offset);
4221 if (rc)
4222 return rc;
4223 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
4224 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
4225 if (!h->cfgtable)
4226 return -ENOMEM;
4227 rc = write_driver_ver_to_cfgtable(h->cfgtable);
4228 if (rc)
4229 return rc;
4230 /* Find performant mode table. */
4231 trans_offset = readl(&h->cfgtable->TransMethodOffset);
4232 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
4233 cfg_base_addr_index)+cfg_offset+trans_offset,
4234 sizeof(*h->transtable));
4235 if (!h->transtable)
4236 return -ENOMEM;
4237 return 0;
4238 }
4239
4240 static void cciss_get_max_perf_mode_cmds(struct ctlr_info *h)
4241 {
4242 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
4243
4244 /* Limit commands in memory limited kdump scenario. */
4245 if (reset_devices && h->max_commands > 32)
4246 h->max_commands = 32;
4247
4248 if (h->max_commands < 16) {
4249 dev_warn(&h->pdev->dev, "Controller reports "
4250 "max supported commands of %d, an obvious lie. "
4251 "Using 16. Ensure that firmware is up to date.\n",
4252 h->max_commands);
4253 h->max_commands = 16;
4254 }
4255 }
4256
4257 /* Interrogate the hardware for some limits:
4258 * max commands, max SG elements without chaining, and with chaining,
4259 * SG chain block size, etc.
4260 */
4261 static void cciss_find_board_params(ctlr_info_t *h)
4262 {
4263 cciss_get_max_perf_mode_cmds(h);
4264 h->nr_cmds = h->max_commands - 4 - cciss_tape_cmds;
4265 h->maxsgentries = readl(&(h->cfgtable->MaxSGElements));
4266 /*
4267 * The P600 may exhibit poor performnace under some workloads
4268 * if we use the value in the configuration table. Limit this
4269 * controller to MAXSGENTRIES (32) instead.
4270 */
4271 if (h->board_id == 0x3225103C)
4272 h->maxsgentries = MAXSGENTRIES;
4273 /*
4274 * Limit in-command s/g elements to 32 save dma'able memory.
4275 * Howvever spec says if 0, use 31
4276 */
4277 h->max_cmd_sgentries = 31;
4278 if (h->maxsgentries > 512) {
4279 h->max_cmd_sgentries = 32;
4280 h->chainsize = h->maxsgentries - h->max_cmd_sgentries + 1;
4281 h->maxsgentries--; /* save one for chain pointer */
4282 } else {
4283 h->maxsgentries = 31; /* default to traditional values */
4284 h->chainsize = 0;
4285 }
4286 }
4287
4288 static inline bool CISS_signature_present(ctlr_info_t *h)
4289 {
4290 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
4291 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
4292 return false;
4293 }
4294 return true;
4295 }
4296
4297 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
4298 static inline void cciss_enable_scsi_prefetch(ctlr_info_t *h)
4299 {
4300 #ifdef CONFIG_X86
4301 u32 prefetch;
4302
4303 prefetch = readl(&(h->cfgtable->SCSI_Prefetch));
4304 prefetch |= 0x100;
4305 writel(prefetch, &(h->cfgtable->SCSI_Prefetch));
4306 #endif
4307 }
4308
4309 /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
4310 * in a prefetch beyond physical memory.
4311 */
4312 static inline void cciss_p600_dma_prefetch_quirk(ctlr_info_t *h)
4313 {
4314 u32 dma_prefetch;
4315 __u32 dma_refetch;
4316
4317 if (h->board_id != 0x3225103C)
4318 return;
4319 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
4320 dma_prefetch |= 0x8000;
4321 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
4322 pci_read_config_dword(h->pdev, PCI_COMMAND_PARITY, &dma_refetch);
4323 dma_refetch |= 0x1;
4324 pci_write_config_dword(h->pdev, PCI_COMMAND_PARITY, dma_refetch);
4325 }
4326
4327 static int cciss_pci_init(ctlr_info_t *h)
4328 {
4329 int prod_index, err;
4330
4331 prod_index = cciss_lookup_board_id(h->pdev, &h->board_id);
4332 if (prod_index < 0)
4333 return -ENODEV;
4334 h->product_name = products[prod_index].product_name;
4335 h->access = *(products[prod_index].access);
4336
4337 if (cciss_board_disabled(h)) {
4338 dev_warn(&h->pdev->dev, "controller appears to be disabled\n");
4339 return -ENODEV;
4340 }
4341
4342 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
4343 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
4344
4345 err = pci_enable_device(h->pdev);
4346 if (err) {
4347 dev_warn(&h->pdev->dev, "Unable to Enable PCI device\n");
4348 return err;
4349 }
4350
4351 err = pci_request_regions(h->pdev, "cciss");
4352 if (err) {
4353 dev_warn(&h->pdev->dev,
4354 "Cannot obtain PCI resources, aborting\n");
4355 return err;
4356 }
4357
4358 dev_dbg(&h->pdev->dev, "irq = %x\n", h->pdev->irq);
4359 dev_dbg(&h->pdev->dev, "board_id = %x\n", h->board_id);
4360
4361 /* If the kernel supports MSI/MSI-X we will try to enable that functionality,
4362 * else we use the IO-APIC interrupt assigned to us by system ROM.
4363 */
4364 cciss_interrupt_mode(h);
4365 err = cciss_pci_find_memory_BAR(h->pdev, &h->paddr);
4366 if (err)
4367 goto err_out_free_res;
4368 h->vaddr = remap_pci_mem(h->paddr, 0x250);
4369 if (!h->vaddr) {
4370 err = -ENOMEM;
4371 goto err_out_free_res;
4372 }
4373 err = cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
4374 if (err)
4375 goto err_out_free_res;
4376 err = cciss_find_cfgtables(h);
4377 if (err)
4378 goto err_out_free_res;
4379 print_cfg_table(h);
4380 cciss_find_board_params(h);
4381
4382 if (!CISS_signature_present(h)) {
4383 err = -ENODEV;
4384 goto err_out_free_res;
4385 }
4386 cciss_enable_scsi_prefetch(h);
4387 cciss_p600_dma_prefetch_quirk(h);
4388 err = cciss_enter_simple_mode(h);
4389 if (err)
4390 goto err_out_free_res;
4391 cciss_put_controller_into_performant_mode(h);
4392 return 0;
4393
4394 err_out_free_res:
4395 /*
4396 * Deliberately omit pci_disable_device(): it does something nasty to
4397 * Smart Array controllers that pci_enable_device does not undo
4398 */
4399 if (h->transtable)
4400 iounmap(h->transtable);
4401 if (h->cfgtable)
4402 iounmap(h->cfgtable);
4403 if (h->vaddr)
4404 iounmap(h->vaddr);
4405 pci_release_regions(h->pdev);
4406 return err;
4407 }
4408
4409 /* Function to find the first free pointer into our hba[] array
4410 * Returns -1 if no free entries are left.
4411 */
4412 static int alloc_cciss_hba(struct pci_dev *pdev)
4413 {
4414 int i;
4415
4416 for (i = 0; i < MAX_CTLR; i++) {
4417 if (!hba[i]) {
4418 ctlr_info_t *h;
4419
4420 h = kzalloc(sizeof(ctlr_info_t), GFP_KERNEL);
4421 if (!h)
4422 goto Enomem;
4423 hba[i] = h;
4424 return i;
4425 }
4426 }
4427 dev_warn(&pdev->dev, "This driver supports a maximum"
4428 " of %d controllers.\n", MAX_CTLR);
4429 return -1;
4430 Enomem:
4431 dev_warn(&pdev->dev, "out of memory.\n");
4432 return -1;
4433 }
4434
4435 static void free_hba(ctlr_info_t *h)
4436 {
4437 int i;
4438
4439 hba[h->ctlr] = NULL;
4440 for (i = 0; i < h->highest_lun + 1; i++)
4441 if (h->gendisk[i] != NULL)
4442 put_disk(h->gendisk[i]);
4443 kfree(h);
4444 }
4445
4446 /* Send a message CDB to the firmware. */
4447 static int cciss_message(struct pci_dev *pdev, unsigned char opcode,
4448 unsigned char type)
4449 {
4450 typedef struct {
4451 CommandListHeader_struct CommandHeader;
4452 RequestBlock_struct Request;
4453 ErrDescriptor_struct ErrorDescriptor;
4454 } Command;
4455 static const size_t cmd_sz = sizeof(Command) + sizeof(ErrorInfo_struct);
4456 Command *cmd;
4457 dma_addr_t paddr64;
4458 uint32_t paddr32, tag;
4459 void __iomem *vaddr;
4460 int i, err;
4461
4462 vaddr = ioremap_nocache(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
4463 if (vaddr == NULL)
4464 return -ENOMEM;
4465
4466 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
4467 CCISS commands, so they must be allocated from the lower 4GiB of
4468 memory. */
4469 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4470 if (err) {
4471 iounmap(vaddr);
4472 return -ENOMEM;
4473 }
4474
4475 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
4476 if (cmd == NULL) {
4477 iounmap(vaddr);
4478 return -ENOMEM;
4479 }
4480
4481 /* This must fit, because of the 32-bit consistent DMA mask. Also,
4482 although there's no guarantee, we assume that the address is at
4483 least 4-byte aligned (most likely, it's page-aligned). */
4484 paddr32 = paddr64;
4485
4486 cmd->CommandHeader.ReplyQueue = 0;
4487 cmd->CommandHeader.SGList = 0;
4488 cmd->CommandHeader.SGTotal = 0;
4489 cmd->CommandHeader.Tag.lower = paddr32;
4490 cmd->CommandHeader.Tag.upper = 0;
4491 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
4492
4493 cmd->Request.CDBLen = 16;
4494 cmd->Request.Type.Type = TYPE_MSG;
4495 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
4496 cmd->Request.Type.Direction = XFER_NONE;
4497 cmd->Request.Timeout = 0; /* Don't time out */
4498 cmd->Request.CDB[0] = opcode;
4499 cmd->Request.CDB[1] = type;
4500 memset(&cmd->Request.CDB[2], 0, 14); /* the rest of the CDB is reserved */
4501
4502 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(Command);
4503 cmd->ErrorDescriptor.Addr.upper = 0;
4504 cmd->ErrorDescriptor.Len = sizeof(ErrorInfo_struct);
4505
4506 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
4507
4508 for (i = 0; i < 10; i++) {
4509 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
4510 if ((tag & ~3) == paddr32)
4511 break;
4512 msleep(CCISS_POST_RESET_NOOP_TIMEOUT_MSECS);
4513 }
4514
4515 iounmap(vaddr);
4516
4517 /* we leak the DMA buffer here ... no choice since the controller could
4518 still complete the command. */
4519 if (i == 10) {
4520 dev_err(&pdev->dev,
4521 "controller message %02x:%02x timed out\n",
4522 opcode, type);
4523 return -ETIMEDOUT;
4524 }
4525
4526 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
4527
4528 if (tag & 2) {
4529 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
4530 opcode, type);
4531 return -EIO;
4532 }
4533
4534 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
4535 opcode, type);
4536 return 0;
4537 }
4538
4539 #define cciss_noop(p) cciss_message(p, 3, 0)
4540
4541 static int cciss_controller_hard_reset(struct pci_dev *pdev,
4542 void * __iomem vaddr, u32 use_doorbell)
4543 {
4544 u16 pmcsr;
4545 int pos;
4546
4547 if (use_doorbell) {
4548 /* For everything after the P600, the PCI power state method
4549 * of resetting the controller doesn't work, so we have this
4550 * other way using the doorbell register.
4551 */
4552 dev_info(&pdev->dev, "using doorbell to reset controller\n");
4553 writel(use_doorbell, vaddr + SA5_DOORBELL);
4554 } else { /* Try to do it the PCI power state way */
4555
4556 /* Quoting from the Open CISS Specification: "The Power
4557 * Management Control/Status Register (CSR) controls the power
4558 * state of the device. The normal operating state is D0,
4559 * CSR=00h. The software off state is D3, CSR=03h. To reset
4560 * the controller, place the interface device in D3 then to D0,
4561 * this causes a secondary PCI reset which will reset the
4562 * controller." */
4563
4564 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
4565 if (pos == 0) {
4566 dev_err(&pdev->dev,
4567 "cciss_controller_hard_reset: "
4568 "PCI PM not supported\n");
4569 return -ENODEV;
4570 }
4571 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
4572 /* enter the D3hot power management state */
4573 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
4574 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4575 pmcsr |= PCI_D3hot;
4576 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
4577
4578 msleep(500);
4579
4580 /* enter the D0 power management state */
4581 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4582 pmcsr |= PCI_D0;
4583 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
4584
4585 /*
4586 * The P600 requires a small delay when changing states.
4587 * Otherwise we may think the board did not reset and we bail.
4588 * This for kdump only and is particular to the P600.
4589 */
4590 msleep(500);
4591 }
4592 return 0;
4593 }
4594
4595 static void init_driver_version(char *driver_version, int len)
4596 {
4597 memset(driver_version, 0, len);
4598 strncpy(driver_version, "cciss " DRIVER_NAME, len - 1);
4599 }
4600
4601 static int write_driver_ver_to_cfgtable(CfgTable_struct __iomem *cfgtable)
4602 {
4603 char *driver_version;
4604 int i, size = sizeof(cfgtable->driver_version);
4605
4606 driver_version = kmalloc(size, GFP_KERNEL);
4607 if (!driver_version)
4608 return -ENOMEM;
4609
4610 init_driver_version(driver_version, size);
4611 for (i = 0; i < size; i++)
4612 writeb(driver_version[i], &cfgtable->driver_version[i]);
4613 kfree(driver_version);
4614 return 0;
4615 }
4616
4617 static void read_driver_ver_from_cfgtable(CfgTable_struct __iomem *cfgtable,
4618 unsigned char *driver_ver)
4619 {
4620 int i;
4621
4622 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
4623 driver_ver[i] = readb(&cfgtable->driver_version[i]);
4624 }
4625
4626 static int controller_reset_failed(CfgTable_struct __iomem *cfgtable)
4627 {
4628
4629 char *driver_ver, *old_driver_ver;
4630 int rc, size = sizeof(cfgtable->driver_version);
4631
4632 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
4633 if (!old_driver_ver)
4634 return -ENOMEM;
4635 driver_ver = old_driver_ver + size;
4636
4637 /* After a reset, the 32 bytes of "driver version" in the cfgtable
4638 * should have been changed, otherwise we know the reset failed.
4639 */
4640 init_driver_version(old_driver_ver, size);
4641 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
4642 rc = !memcmp(driver_ver, old_driver_ver, size);
4643 kfree(old_driver_ver);
4644 return rc;
4645 }
4646
4647 /* This does a hard reset of the controller using PCI power management
4648 * states or using the doorbell register. */
4649 static int cciss_kdump_hard_reset_controller(struct pci_dev *pdev)
4650 {
4651 u64 cfg_offset;
4652 u32 cfg_base_addr;
4653 u64 cfg_base_addr_index;
4654 void __iomem *vaddr;
4655 unsigned long paddr;
4656 u32 misc_fw_support;
4657 int rc;
4658 CfgTable_struct __iomem *cfgtable;
4659 u32 use_doorbell;
4660 u32 board_id;
4661 u16 command_register;
4662
4663 /* For controllers as old a the p600, this is very nearly
4664 * the same thing as
4665 *
4666 * pci_save_state(pci_dev);
4667 * pci_set_power_state(pci_dev, PCI_D3hot);
4668 * pci_set_power_state(pci_dev, PCI_D0);
4669 * pci_restore_state(pci_dev);
4670 *
4671 * For controllers newer than the P600, the pci power state
4672 * method of resetting doesn't work so we have another way
4673 * using the doorbell register.
4674 */
4675
4676 /* Exclude 640x boards. These are two pci devices in one slot
4677 * which share a battery backed cache module. One controls the
4678 * cache, the other accesses the cache through the one that controls
4679 * it. If we reset the one controlling the cache, the other will
4680 * likely not be happy. Just forbid resetting this conjoined mess.
4681 */
4682 cciss_lookup_board_id(pdev, &board_id);
4683 if (!ctlr_is_resettable(board_id)) {
4684 dev_warn(&pdev->dev, "Controller not resettable\n");
4685 return -ENODEV;
4686 }
4687
4688 /* if controller is soft- but not hard resettable... */
4689 if (!ctlr_is_hard_resettable(board_id))
4690 return -ENOTSUPP; /* try soft reset later. */
4691
4692 /* Save the PCI command register */
4693 pci_read_config_word(pdev, 4, &command_register);
4694 /* Turn the board off. This is so that later pci_restore_state()
4695 * won't turn the board on before the rest of config space is ready.
4696 */
4697 pci_disable_device(pdev);
4698 pci_save_state(pdev);
4699
4700 /* find the first memory BAR, so we can find the cfg table */
4701 rc = cciss_pci_find_memory_BAR(pdev, &paddr);
4702 if (rc)
4703 return rc;
4704 vaddr = remap_pci_mem(paddr, 0x250);
4705 if (!vaddr)
4706 return -ENOMEM;
4707
4708 /* find cfgtable in order to check if reset via doorbell is supported */
4709 rc = cciss_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
4710 &cfg_base_addr_index, &cfg_offset);
4711 if (rc)
4712 goto unmap_vaddr;
4713 cfgtable = remap_pci_mem(pci_resource_start(pdev,
4714 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
4715 if (!cfgtable) {
4716 rc = -ENOMEM;
4717 goto unmap_vaddr;
4718 }
4719 rc = write_driver_ver_to_cfgtable(cfgtable);
4720 if (rc)
4721 goto unmap_vaddr;
4722
4723 /* If reset via doorbell register is supported, use that.
4724 * There are two such methods. Favor the newest method.
4725 */
4726 misc_fw_support = readl(&cfgtable->misc_fw_support);
4727 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
4728 if (use_doorbell) {
4729 use_doorbell = DOORBELL_CTLR_RESET2;
4730 } else {
4731 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
4732 if (use_doorbell) {
4733 dev_warn(&pdev->dev, "Controller claims that "
4734 "'Bit 2 doorbell reset' is "
4735 "supported, but not 'bit 5 doorbell reset'. "
4736 "Firmware update is recommended.\n");
4737 rc = -ENOTSUPP; /* use the soft reset */
4738 goto unmap_cfgtable;
4739 }
4740 }
4741
4742 rc = cciss_controller_hard_reset(pdev, vaddr, use_doorbell);
4743 if (rc)
4744 goto unmap_cfgtable;
4745 pci_restore_state(pdev);
4746 rc = pci_enable_device(pdev);
4747 if (rc) {
4748 dev_warn(&pdev->dev, "failed to enable device.\n");
4749 goto unmap_cfgtable;
4750 }
4751 pci_write_config_word(pdev, 4, command_register);
4752
4753 /* Some devices (notably the HP Smart Array 5i Controller)
4754 need a little pause here */
4755 msleep(CCISS_POST_RESET_PAUSE_MSECS);
4756
4757 /* Wait for board to become not ready, then ready. */
4758 dev_info(&pdev->dev, "Waiting for board to reset.\n");
4759 rc = cciss_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
4760 if (rc) {
4761 dev_warn(&pdev->dev, "Failed waiting for board to hard reset."
4762 " Will try soft reset.\n");
4763 rc = -ENOTSUPP; /* Not expected, but try soft reset later */
4764 goto unmap_cfgtable;
4765 }
4766 rc = cciss_wait_for_board_state(pdev, vaddr, BOARD_READY);
4767 if (rc) {
4768 dev_warn(&pdev->dev,
4769 "failed waiting for board to become ready "
4770 "after hard reset\n");
4771 goto unmap_cfgtable;
4772 }
4773
4774 rc = controller_reset_failed(vaddr);
4775 if (rc < 0)
4776 goto unmap_cfgtable;
4777 if (rc) {
4778 dev_warn(&pdev->dev, "Unable to successfully hard reset "
4779 "controller. Will try soft reset.\n");
4780 rc = -ENOTSUPP; /* Not expected, but try soft reset later */
4781 } else {
4782 dev_info(&pdev->dev, "Board ready after hard reset.\n");
4783 }
4784
4785 unmap_cfgtable:
4786 iounmap(cfgtable);
4787
4788 unmap_vaddr:
4789 iounmap(vaddr);
4790 return rc;
4791 }
4792
4793 static int cciss_init_reset_devices(struct pci_dev *pdev)
4794 {
4795 int rc, i;
4796
4797 if (!reset_devices)
4798 return 0;
4799
4800 /* Reset the controller with a PCI power-cycle or via doorbell */
4801 rc = cciss_kdump_hard_reset_controller(pdev);
4802
4803 /* -ENOTSUPP here means we cannot reset the controller
4804 * but it's already (and still) up and running in
4805 * "performant mode". Or, it might be 640x, which can't reset
4806 * due to concerns about shared bbwc between 6402/6404 pair.
4807 */
4808 if (rc == -ENOTSUPP)
4809 return rc; /* just try to do the kdump anyhow. */
4810 if (rc)
4811 return -ENODEV;
4812
4813 /* Now try to get the controller to respond to a no-op */
4814 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4815 for (i = 0; i < CCISS_POST_RESET_NOOP_RETRIES; i++) {
4816 if (cciss_noop(pdev) == 0)
4817 break;
4818 else
4819 dev_warn(&pdev->dev, "no-op failed%s\n",
4820 (i < CCISS_POST_RESET_NOOP_RETRIES - 1 ?
4821 "; re-trying" : ""));
4822 msleep(CCISS_POST_RESET_NOOP_INTERVAL_MSECS);
4823 }
4824 return 0;
4825 }
4826
4827 static int cciss_allocate_cmd_pool(ctlr_info_t *h)
4828 {
4829 h->cmd_pool_bits = kmalloc(BITS_TO_LONGS(h->nr_cmds) *
4830 sizeof(unsigned long), GFP_KERNEL);
4831 h->cmd_pool = pci_alloc_consistent(h->pdev,
4832 h->nr_cmds * sizeof(CommandList_struct),
4833 &(h->cmd_pool_dhandle));
4834 h->errinfo_pool = pci_alloc_consistent(h->pdev,
4835 h->nr_cmds * sizeof(ErrorInfo_struct),
4836 &(h->errinfo_pool_dhandle));
4837 if ((h->cmd_pool_bits == NULL)
4838 || (h->cmd_pool == NULL)
4839 || (h->errinfo_pool == NULL)) {
4840 dev_err(&h->pdev->dev, "out of memory");
4841 return -ENOMEM;
4842 }
4843 return 0;
4844 }
4845
4846 static int cciss_allocate_scatterlists(ctlr_info_t *h)
4847 {
4848 int i;
4849
4850 /* zero it, so that on free we need not know how many were alloc'ed */
4851 h->scatter_list = kzalloc(h->max_commands *
4852 sizeof(struct scatterlist *), GFP_KERNEL);
4853 if (!h->scatter_list)
4854 return -ENOMEM;
4855
4856 for (i = 0; i < h->nr_cmds; i++) {
4857 h->scatter_list[i] = kmalloc(sizeof(struct scatterlist) *
4858 h->maxsgentries, GFP_KERNEL);
4859 if (h->scatter_list[i] == NULL) {
4860 dev_err(&h->pdev->dev, "could not allocate "
4861 "s/g lists\n");
4862 return -ENOMEM;
4863 }
4864 }
4865 return 0;
4866 }
4867
4868 static void cciss_free_scatterlists(ctlr_info_t *h)
4869 {
4870 int i;
4871
4872 if (h->scatter_list) {
4873 for (i = 0; i < h->nr_cmds; i++)
4874 kfree(h->scatter_list[i]);
4875 kfree(h->scatter_list);
4876 }
4877 }
4878
4879 static void cciss_free_cmd_pool(ctlr_info_t *h)
4880 {
4881 kfree(h->cmd_pool_bits);
4882 if (h->cmd_pool)
4883 pci_free_consistent(h->pdev,
4884 h->nr_cmds * sizeof(CommandList_struct),
4885 h->cmd_pool, h->cmd_pool_dhandle);
4886 if (h->errinfo_pool)
4887 pci_free_consistent(h->pdev,
4888 h->nr_cmds * sizeof(ErrorInfo_struct),
4889 h->errinfo_pool, h->errinfo_pool_dhandle);
4890 }
4891
4892 static int cciss_request_irq(ctlr_info_t *h,
4893 irqreturn_t (*msixhandler)(int, void *),
4894 irqreturn_t (*intxhandler)(int, void *))
4895 {
4896 if (h->msix_vector || h->msi_vector) {
4897 if (!request_irq(h->intr[h->intr_mode], msixhandler,
4898 0, h->devname, h))
4899 return 0;
4900 dev_err(&h->pdev->dev, "Unable to get msi irq %d"
4901 " for %s\n", h->intr[h->intr_mode],
4902 h->devname);
4903 return -1;
4904 }
4905
4906 if (!request_irq(h->intr[h->intr_mode], intxhandler,
4907 IRQF_SHARED, h->devname, h))
4908 return 0;
4909 dev_err(&h->pdev->dev, "Unable to get irq %d for %s\n",
4910 h->intr[h->intr_mode], h->devname);
4911 return -1;
4912 }
4913
4914 static int cciss_kdump_soft_reset(ctlr_info_t *h)
4915 {
4916 if (cciss_send_reset(h, CTLR_LUNID, CCISS_RESET_TYPE_CONTROLLER)) {
4917 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
4918 return -EIO;
4919 }
4920
4921 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
4922 if (cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
4923 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
4924 return -1;
4925 }
4926
4927 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
4928 if (cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
4929 dev_warn(&h->pdev->dev, "Board failed to become ready "
4930 "after soft reset.\n");
4931 return -1;
4932 }
4933
4934 return 0;
4935 }
4936
4937 static void cciss_undo_allocations_after_kdump_soft_reset(ctlr_info_t *h)
4938 {
4939 int ctlr = h->ctlr;
4940
4941 free_irq(h->intr[h->intr_mode], h);
4942 #ifdef CONFIG_PCI_MSI
4943 if (h->msix_vector)
4944 pci_disable_msix(h->pdev);
4945 else if (h->msi_vector)
4946 pci_disable_msi(h->pdev);
4947 #endif /* CONFIG_PCI_MSI */
4948 cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
4949 cciss_free_scatterlists(h);
4950 cciss_free_cmd_pool(h);
4951 kfree(h->blockFetchTable);
4952 if (h->reply_pool)
4953 pci_free_consistent(h->pdev, h->max_commands * sizeof(__u64),
4954 h->reply_pool, h->reply_pool_dhandle);
4955 if (h->transtable)
4956 iounmap(h->transtable);
4957 if (h->cfgtable)
4958 iounmap(h->cfgtable);
4959 if (h->vaddr)
4960 iounmap(h->vaddr);
4961 unregister_blkdev(h->major, h->devname);
4962 cciss_destroy_hba_sysfs_entry(h);
4963 pci_release_regions(h->pdev);
4964 kfree(h);
4965 hba[ctlr] = NULL;
4966 }
4967
4968 /*
4969 * This is it. Find all the controllers and register them. I really hate
4970 * stealing all these major device numbers.
4971 * returns the number of block devices registered.
4972 */
4973 static int cciss_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4974 {
4975 int i;
4976 int j = 0;
4977 int rc;
4978 int try_soft_reset = 0;
4979 int dac, return_code;
4980 InquiryData_struct *inq_buff;
4981 ctlr_info_t *h;
4982 unsigned long flags;
4983
4984 /*
4985 * By default the cciss driver is used for all older HP Smart Array
4986 * controllers. There are module paramaters that allow a user to
4987 * override this behavior and instead use the hpsa SCSI driver. If
4988 * this is the case cciss may be loaded first from the kdump initrd
4989 * image and cause a kernel panic. So if reset_devices is true and
4990 * cciss_allow_hpsa is set just bail.
4991 */
4992 if ((reset_devices) && (cciss_allow_hpsa == 1))
4993 return -ENODEV;
4994 rc = cciss_init_reset_devices(pdev);
4995 if (rc) {
4996 if (rc != -ENOTSUPP)
4997 return rc;
4998 /* If the reset fails in a particular way (it has no way to do
4999 * a proper hard reset, so returns -ENOTSUPP) we can try to do
5000 * a soft reset once we get the controller configured up to the
5001 * point that it can accept a command.
5002 */
5003 try_soft_reset = 1;
5004 rc = 0;
5005 }
5006
5007 reinit_after_soft_reset:
5008
5009 i = alloc_cciss_hba(pdev);
5010 if (i < 0)
5011 return -ENOMEM;
5012
5013 h = hba[i];
5014 h->pdev = pdev;
5015 h->busy_initializing = 1;
5016 h->intr_mode = cciss_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
5017 INIT_LIST_HEAD(&h->cmpQ);
5018 INIT_LIST_HEAD(&h->reqQ);
5019 mutex_init(&h->busy_shutting_down);
5020
5021 if (cciss_pci_init(h) != 0)
5022 goto clean_no_release_regions;
5023
5024 sprintf(h->devname, "cciss%d", i);
5025 h->ctlr = i;
5026
5027 if (cciss_tape_cmds < 2)
5028 cciss_tape_cmds = 2;
5029 if (cciss_tape_cmds > 16)
5030 cciss_tape_cmds = 16;
5031
5032 init_completion(&h->scan_wait);
5033
5034 if (cciss_create_hba_sysfs_entry(h))
5035 goto clean0;
5036
5037 /* configure PCI DMA stuff */
5038 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
5039 dac = 1;
5040 else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
5041 dac = 0;
5042 else {
5043 dev_err(&h->pdev->dev, "no suitable DMA available\n");
5044 goto clean1;
5045 }
5046
5047 /*
5048 * register with the major number, or get a dynamic major number
5049 * by passing 0 as argument. This is done for greater than
5050 * 8 controller support.
5051 */
5052 if (i < MAX_CTLR_ORIG)
5053 h->major = COMPAQ_CISS_MAJOR + i;
5054 rc = register_blkdev(h->major, h->devname);
5055 if (rc == -EBUSY || rc == -EINVAL) {
5056 dev_err(&h->pdev->dev,
5057 "Unable to get major number %d for %s "
5058 "on hba %d\n", h->major, h->devname, i);
5059 goto clean1;
5060 } else {
5061 if (i >= MAX_CTLR_ORIG)
5062 h->major = rc;
5063 }
5064
5065 /* make sure the board interrupts are off */
5066 h->access.set_intr_mask(h, CCISS_INTR_OFF);
5067 rc = cciss_request_irq(h, do_cciss_msix_intr, do_cciss_intx);
5068 if (rc)
5069 goto clean2;
5070
5071 dev_info(&h->pdev->dev, "%s: <0x%x> at PCI %s IRQ %d%s using DAC\n",
5072 h->devname, pdev->device, pci_name(pdev),
5073 h->intr[h->intr_mode], dac ? "" : " not");
5074
5075 if (cciss_allocate_cmd_pool(h))
5076 goto clean4;
5077
5078 if (cciss_allocate_scatterlists(h))
5079 goto clean4;
5080
5081 h->cmd_sg_list = cciss_allocate_sg_chain_blocks(h,
5082 h->chainsize, h->nr_cmds);
5083 if (!h->cmd_sg_list && h->chainsize > 0)
5084 goto clean4;
5085
5086 spin_lock_init(&h->lock);
5087
5088 /* Initialize the pdev driver private data.
5089 have it point to h. */
5090 pci_set_drvdata(pdev, h);
5091 /* command and error info recs zeroed out before
5092 they are used */
5093 bitmap_zero(h->cmd_pool_bits, h->nr_cmds);
5094
5095 h->num_luns = 0;
5096 h->highest_lun = -1;
5097 for (j = 0; j < CISS_MAX_LUN; j++) {
5098 h->drv[j] = NULL;
5099 h->gendisk[j] = NULL;
5100 }
5101
5102 /* At this point, the controller is ready to take commands.
5103 * Now, if reset_devices and the hard reset didn't work, try
5104 * the soft reset and see if that works.
5105 */
5106 if (try_soft_reset) {
5107
5108 /* This is kind of gross. We may or may not get a completion
5109 * from the soft reset command, and if we do, then the value
5110 * from the fifo may or may not be valid. So, we wait 10 secs
5111 * after the reset throwing away any completions we get during
5112 * that time. Unregister the interrupt handler and register
5113 * fake ones to scoop up any residual completions.
5114 */
5115 spin_lock_irqsave(&h->lock, flags);
5116 h->access.set_intr_mask(h, CCISS_INTR_OFF);
5117 spin_unlock_irqrestore(&h->lock, flags);
5118 free_irq(h->intr[h->intr_mode], h);
5119 rc = cciss_request_irq(h, cciss_msix_discard_completions,
5120 cciss_intx_discard_completions);
5121 if (rc) {
5122 dev_warn(&h->pdev->dev, "Failed to request_irq after "
5123 "soft reset.\n");
5124 goto clean4;
5125 }
5126
5127 rc = cciss_kdump_soft_reset(h);
5128 if (rc) {
5129 dev_warn(&h->pdev->dev, "Soft reset failed.\n");
5130 goto clean4;
5131 }
5132
5133 dev_info(&h->pdev->dev, "Board READY.\n");
5134 dev_info(&h->pdev->dev,
5135 "Waiting for stale completions to drain.\n");
5136 h->access.set_intr_mask(h, CCISS_INTR_ON);
5137 msleep(10000);
5138 h->access.set_intr_mask(h, CCISS_INTR_OFF);
5139
5140 rc = controller_reset_failed(h->cfgtable);
5141 if (rc)
5142 dev_info(&h->pdev->dev,
5143 "Soft reset appears to have failed.\n");
5144
5145 /* since the controller's reset, we have to go back and re-init
5146 * everything. Easiest to just forget what we've done and do it
5147 * all over again.
5148 */
5149 cciss_undo_allocations_after_kdump_soft_reset(h);
5150 try_soft_reset = 0;
5151 if (rc)
5152 /* don't go to clean4, we already unallocated */
5153 return -ENODEV;
5154
5155 goto reinit_after_soft_reset;
5156 }
5157
5158 cciss_scsi_setup(h);
5159
5160 /* Turn the interrupts on so we can service requests */
5161 h->access.set_intr_mask(h, CCISS_INTR_ON);
5162
5163 /* Get the firmware version */
5164 inq_buff = kzalloc(sizeof(InquiryData_struct), GFP_KERNEL);
5165 if (inq_buff == NULL) {
5166 dev_err(&h->pdev->dev, "out of memory\n");
5167 goto clean4;
5168 }
5169
5170 return_code = sendcmd_withirq(h, CISS_INQUIRY, inq_buff,
5171 sizeof(InquiryData_struct), 0, CTLR_LUNID, TYPE_CMD);
5172 if (return_code == IO_OK) {
5173 h->firm_ver[0] = inq_buff->data_byte[32];
5174 h->firm_ver[1] = inq_buff->data_byte[33];
5175 h->firm_ver[2] = inq_buff->data_byte[34];
5176 h->firm_ver[3] = inq_buff->data_byte[35];
5177 } else { /* send command failed */
5178 dev_warn(&h->pdev->dev, "unable to determine firmware"
5179 " version of controller\n");
5180 }
5181 kfree(inq_buff);
5182
5183 cciss_procinit(h);
5184
5185 h->cciss_max_sectors = 8192;
5186
5187 rebuild_lun_table(h, 1, 0);
5188 cciss_engage_scsi(h);
5189 h->busy_initializing = 0;
5190 return 0;
5191
5192 clean4:
5193 cciss_free_cmd_pool(h);
5194 cciss_free_scatterlists(h);
5195 cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
5196 free_irq(h->intr[h->intr_mode], h);
5197 clean2:
5198 unregister_blkdev(h->major, h->devname);
5199 clean1:
5200 cciss_destroy_hba_sysfs_entry(h);
5201 clean0:
5202 pci_release_regions(pdev);
5203 clean_no_release_regions:
5204 h->busy_initializing = 0;
5205
5206 /*
5207 * Deliberately omit pci_disable_device(): it does something nasty to
5208 * Smart Array controllers that pci_enable_device does not undo
5209 */
5210 pci_set_drvdata(pdev, NULL);
5211 free_hba(h);
5212 return -ENODEV;
5213 }
5214
5215 static void cciss_shutdown(struct pci_dev *pdev)
5216 {
5217 ctlr_info_t *h;
5218 char *flush_buf;
5219 int return_code;
5220
5221 h = pci_get_drvdata(pdev);
5222 flush_buf = kzalloc(4, GFP_KERNEL);
5223 if (!flush_buf) {
5224 dev_warn(&h->pdev->dev, "cache not flushed, out of memory.\n");
5225 return;
5226 }
5227 /* write all data in the battery backed cache to disk */
5228 return_code = sendcmd_withirq(h, CCISS_CACHE_FLUSH, flush_buf,
5229 4, 0, CTLR_LUNID, TYPE_CMD);
5230 kfree(flush_buf);
5231 if (return_code != IO_OK)
5232 dev_warn(&h->pdev->dev, "Error flushing cache\n");
5233 h->access.set_intr_mask(h, CCISS_INTR_OFF);
5234 free_irq(h->intr[h->intr_mode], h);
5235 }
5236
5237 static int cciss_enter_simple_mode(struct ctlr_info *h)
5238 {
5239 u32 trans_support;
5240
5241 trans_support = readl(&(h->cfgtable->TransportSupport));
5242 if (!(trans_support & SIMPLE_MODE))
5243 return -ENOTSUPP;
5244
5245 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
5246 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
5247 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
5248 cciss_wait_for_mode_change_ack(h);
5249 print_cfg_table(h);
5250 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) {
5251 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
5252 return -ENODEV;
5253 }
5254 h->transMethod = CFGTBL_Trans_Simple;
5255 return 0;
5256 }
5257
5258
5259 static void cciss_remove_one(struct pci_dev *pdev)
5260 {
5261 ctlr_info_t *h;
5262 int i, j;
5263
5264 if (pci_get_drvdata(pdev) == NULL) {
5265 dev_err(&pdev->dev, "Unable to remove device\n");
5266 return;
5267 }
5268
5269 h = pci_get_drvdata(pdev);
5270 i = h->ctlr;
5271 if (hba[i] == NULL) {
5272 dev_err(&pdev->dev, "device appears to already be removed\n");
5273 return;
5274 }
5275
5276 mutex_lock(&h->busy_shutting_down);
5277
5278 remove_from_scan_list(h);
5279 remove_proc_entry(h->devname, proc_cciss);
5280 unregister_blkdev(h->major, h->devname);
5281
5282 /* remove it from the disk list */
5283 for (j = 0; j < CISS_MAX_LUN; j++) {
5284 struct gendisk *disk = h->gendisk[j];
5285 if (disk) {
5286 struct request_queue *q = disk->queue;
5287
5288 if (disk->flags & GENHD_FL_UP) {
5289 cciss_destroy_ld_sysfs_entry(h, j, 1);
5290 del_gendisk(disk);
5291 }
5292 if (q)
5293 blk_cleanup_queue(q);
5294 }
5295 }
5296
5297 #ifdef CONFIG_CISS_SCSI_TAPE
5298 cciss_unregister_scsi(h); /* unhook from SCSI subsystem */
5299 #endif
5300
5301 cciss_shutdown(pdev);
5302
5303 #ifdef CONFIG_PCI_MSI
5304 if (h->msix_vector)
5305 pci_disable_msix(h->pdev);
5306 else if (h->msi_vector)
5307 pci_disable_msi(h->pdev);
5308 #endif /* CONFIG_PCI_MSI */
5309
5310 iounmap(h->transtable);
5311 iounmap(h->cfgtable);
5312 iounmap(h->vaddr);
5313
5314 cciss_free_cmd_pool(h);
5315 /* Free up sg elements */
5316 for (j = 0; j < h->nr_cmds; j++)
5317 kfree(h->scatter_list[j]);
5318 kfree(h->scatter_list);
5319 cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
5320 kfree(h->blockFetchTable);
5321 if (h->reply_pool)
5322 pci_free_consistent(h->pdev, h->max_commands * sizeof(__u64),
5323 h->reply_pool, h->reply_pool_dhandle);
5324 /*
5325 * Deliberately omit pci_disable_device(): it does something nasty to
5326 * Smart Array controllers that pci_enable_device does not undo
5327 */
5328 pci_release_regions(pdev);
5329 pci_set_drvdata(pdev, NULL);
5330 cciss_destroy_hba_sysfs_entry(h);
5331 mutex_unlock(&h->busy_shutting_down);
5332 free_hba(h);
5333 }
5334
5335 static struct pci_driver cciss_pci_driver = {
5336 .name = "cciss",
5337 .probe = cciss_init_one,
5338 .remove = cciss_remove_one,
5339 .id_table = cciss_pci_device_id, /* id_table */
5340 .shutdown = cciss_shutdown,
5341 };
5342
5343 /*
5344 * This is it. Register the PCI driver information for the cards we control
5345 * the OS will call our registered routines when it finds one of our cards.
5346 */
5347 static int __init cciss_init(void)
5348 {
5349 int err;
5350
5351 /*
5352 * The hardware requires that commands are aligned on a 64-bit
5353 * boundary. Given that we use pci_alloc_consistent() to allocate an
5354 * array of them, the size must be a multiple of 8 bytes.
5355 */
5356 BUILD_BUG_ON(sizeof(CommandList_struct) % COMMANDLIST_ALIGNMENT);
5357 printk(KERN_INFO DRIVER_NAME "\n");
5358
5359 err = bus_register(&cciss_bus_type);
5360 if (err)
5361 return err;
5362
5363 /* Start the scan thread */
5364 cciss_scan_thread = kthread_run(scan_thread, NULL, "cciss_scan");
5365 if (IS_ERR(cciss_scan_thread)) {
5366 err = PTR_ERR(cciss_scan_thread);
5367 goto err_bus_unregister;
5368 }
5369
5370 /* Register for our PCI devices */
5371 err = pci_register_driver(&cciss_pci_driver);
5372 if (err)
5373 goto err_thread_stop;
5374
5375 return err;
5376
5377 err_thread_stop:
5378 kthread_stop(cciss_scan_thread);
5379 err_bus_unregister:
5380 bus_unregister(&cciss_bus_type);
5381
5382 return err;
5383 }
5384
5385 static void __exit cciss_cleanup(void)
5386 {
5387 int i;
5388
5389 pci_unregister_driver(&cciss_pci_driver);
5390 /* double check that all controller entrys have been removed */
5391 for (i = 0; i < MAX_CTLR; i++) {
5392 if (hba[i] != NULL) {
5393 dev_warn(&hba[i]->pdev->dev,
5394 "had to remove controller\n");
5395 cciss_remove_one(hba[i]->pdev);
5396 }
5397 }
5398 kthread_stop(cciss_scan_thread);
5399 if (proc_cciss)
5400 remove_proc_entry("driver/cciss", NULL);
5401 bus_unregister(&cciss_bus_type);
5402 }
5403
5404 module_init(cciss_init);
5405 module_exit(cciss_cleanup);