2 * NVM Express device driver
3 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/blkdev.h>
22 #include <linux/errno.h>
24 #include <linux/genhd.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/moduleparam.h>
33 #include <linux/pci.h>
34 #include <linux/sched.h>
35 #include <linux/slab.h>
36 #include <linux/types.h>
37 #include <linux/version.h>
39 #define NVME_Q_DEPTH 1024
40 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
41 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
42 #define NVME_MINORS 64
44 static int nvme_major
;
45 module_param(nvme_major
, int, 0);
48 * Represents an NVM Express device. Each nvme_dev is a PCI function.
51 struct nvme_queue
**queues
;
53 struct pci_dev
*pci_dev
;
57 struct msix_entry
*entry
;
58 struct nvme_bar __iomem
*bar
;
59 struct list_head namespaces
;
66 * An NVM Express namespace is equivalent to a SCSI LUN
69 struct list_head list
;
72 struct request_queue
*queue
;
80 * An NVM Express queue. Each device has at least two (one for admin
81 * commands and one for I/O commands).
84 struct device
*q_dmadev
;
86 struct nvme_command
*sq_cmds
;
87 volatile struct nvme_completion
*cqes
;
88 dma_addr_t sq_dma_addr
;
89 dma_addr_t cq_dma_addr
;
90 wait_queue_head_t sq_full
;
91 struct bio_list sq_cong
;
99 unsigned long cmdid_data
[];
103 * Check we didin't inadvertently grow the command struct
105 static inline void _nvme_check_size(void)
107 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
108 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
109 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
110 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
111 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
112 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
113 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
114 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
115 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
119 * alloc_cmdid - Allocate a Command ID
120 * @param nvmeq The queue that will be used for this command
121 * @param ctx A pointer that will be passed to the handler
122 * @param handler The ID of the handler to call
124 * Allocate a Command ID for a queue. The data passed in will
125 * be passed to the completion handler. This is implemented by using
126 * the bottom two bits of the ctx pointer to store the handler ID.
127 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
128 * We can change this if it becomes a problem.
130 static int alloc_cmdid(struct nvme_queue
*nvmeq
, void *ctx
, int handler
)
132 int depth
= nvmeq
->q_depth
;
133 unsigned long data
= (unsigned long)ctx
| handler
;
136 BUG_ON((unsigned long)ctx
& 3);
139 cmdid
= find_first_zero_bit(nvmeq
->cmdid_data
, depth
);
142 } while (test_and_set_bit(cmdid
, nvmeq
->cmdid_data
));
144 nvmeq
->cmdid_data
[cmdid
+ BITS_TO_LONGS(depth
)] = data
;
148 static int alloc_cmdid_killable(struct nvme_queue
*nvmeq
, void *ctx
,
152 wait_event_killable(nvmeq
->sq_full
,
153 (cmdid
= alloc_cmdid(nvmeq
, ctx
, handler
)) >= 0);
154 return (cmdid
< 0) ? -EINTR
: cmdid
;
157 /* If you need more than four handlers, you'll need to change how
158 * alloc_cmdid and nvme_process_cq work
161 sync_completion_id
= 0,
165 static unsigned long free_cmdid(struct nvme_queue
*nvmeq
, int cmdid
)
169 data
= nvmeq
->cmdid_data
[cmdid
+ BITS_TO_LONGS(nvmeq
->q_depth
)];
170 clear_bit(cmdid
, nvmeq
->cmdid_data
);
171 wake_up(&nvmeq
->sq_full
);
175 static struct nvme_queue
*get_nvmeq(struct nvme_ns
*ns
)
177 int qid
, cpu
= get_cpu();
178 if (cpu
< ns
->dev
->queue_count
)
181 qid
= (cpu
% rounddown_pow_of_two(ns
->dev
->queue_count
)) + 1;
182 return ns
->dev
->queues
[qid
];
185 static void put_nvmeq(struct nvme_queue
*nvmeq
)
191 * nvme_submit_cmd: Copy a command into a queue and ring the doorbell
192 * @nvmeq: The queue to use
193 * @cmd: The command to send
195 * Safe to use from interrupt context
197 static int nvme_submit_cmd(struct nvme_queue
*nvmeq
, struct nvme_command
*cmd
)
201 /* XXX: Need to check tail isn't going to overrun head */
202 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
203 tail
= nvmeq
->sq_tail
;
204 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
205 writel(tail
, nvmeq
->q_db
);
206 if (++tail
== nvmeq
->q_depth
)
208 nvmeq
->sq_tail
= tail
;
209 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
214 struct nvme_req_info
{
217 struct scatterlist sg
[0];
220 /* XXX: use a mempool */
221 static struct nvme_req_info
*alloc_info(unsigned nseg
, gfp_t gfp
)
223 return kmalloc(sizeof(struct nvme_req_info
) +
224 sizeof(struct scatterlist
) * nseg
, gfp
);
227 static void free_info(struct nvme_req_info
*info
)
232 static void bio_completion(struct nvme_queue
*nvmeq
, void *ctx
,
233 struct nvme_completion
*cqe
)
235 struct nvme_req_info
*info
= ctx
;
236 struct bio
*bio
= info
->bio
;
237 u16 status
= le16_to_cpup(&cqe
->status
) >> 1;
239 dma_unmap_sg(nvmeq
->q_dmadev
, info
->sg
, info
->nents
,
240 bio_data_dir(bio
) ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
242 bio_endio(bio
, status
? -EIO
: 0);
245 /* length is in bytes */
246 static void nvme_setup_prps(struct nvme_common_command
*cmd
,
247 struct scatterlist
*sg
, int length
)
249 int dma_len
= sg_dma_len(sg
);
250 u64 dma_addr
= sg_dma_address(sg
);
251 int offset
= offset_in_page(dma_addr
);
253 cmd
->prp1
= cpu_to_le64(dma_addr
);
254 length
-= (PAGE_SIZE
- offset
);
258 dma_len
-= (PAGE_SIZE
- offset
);
260 dma_addr
+= (PAGE_SIZE
- offset
);
263 dma_addr
= sg_dma_address(sg
);
264 dma_len
= sg_dma_len(sg
);
267 if (length
<= PAGE_SIZE
) {
268 cmd
->prp2
= cpu_to_le64(dma_addr
);
272 /* XXX: support PRP lists */
275 static int nvme_map_bio(struct device
*dev
, struct nvme_req_info
*info
,
276 struct bio
*bio
, enum dma_data_direction dma_dir
, int psegs
)
278 struct bio_vec
*bvec
;
279 struct scatterlist
*sg
= info
->sg
;
282 sg_init_table(sg
, psegs
);
283 bio_for_each_segment(bvec
, bio
, i
) {
284 sg_set_page(sg
, bvec
->bv_page
, bvec
->bv_len
, bvec
->bv_offset
);
285 /* XXX: handle non-mergable here */
290 return dma_map_sg(dev
, info
->sg
, info
->nents
, dma_dir
);
293 static int nvme_submit_bio_queue(struct nvme_queue
*nvmeq
, struct nvme_ns
*ns
,
296 struct nvme_command
*cmnd
;
297 struct nvme_req_info
*info
;
298 enum dma_data_direction dma_dir
;
303 int psegs
= bio_phys_segments(ns
->queue
, bio
);
305 info
= alloc_info(psegs
, GFP_NOIO
);
310 cmdid
= alloc_cmdid(nvmeq
, info
, bio_completion_id
);
311 if (unlikely(cmdid
< 0))
315 if (bio
->bi_rw
& REQ_FUA
)
316 control
|= NVME_RW_FUA
;
317 if (bio
->bi_rw
& (REQ_FAILFAST_DEV
| REQ_RAHEAD
))
318 control
|= NVME_RW_LR
;
321 if (bio
->bi_rw
& REQ_RAHEAD
)
322 dsmgmt
|= NVME_RW_DSM_FREQ_PREFETCH
;
324 spin_lock_irqsave(&nvmeq
->q_lock
, flags
);
325 cmnd
= &nvmeq
->sq_cmds
[nvmeq
->sq_tail
];
327 memset(cmnd
, 0, sizeof(*cmnd
));
328 if (bio_data_dir(bio
)) {
329 cmnd
->rw
.opcode
= nvme_cmd_write
;
330 dma_dir
= DMA_TO_DEVICE
;
332 cmnd
->rw
.opcode
= nvme_cmd_read
;
333 dma_dir
= DMA_FROM_DEVICE
;
336 nvme_map_bio(nvmeq
->q_dmadev
, info
, bio
, dma_dir
, psegs
);
339 cmnd
->rw
.command_id
= cmdid
;
340 cmnd
->rw
.nsid
= cpu_to_le32(ns
->ns_id
);
341 nvme_setup_prps(&cmnd
->common
, info
->sg
, bio
->bi_size
);
342 cmnd
->rw
.slba
= cpu_to_le64(bio
->bi_sector
>> (ns
->lba_shift
- 9));
343 cmnd
->rw
.length
= cpu_to_le16((bio
->bi_size
>> ns
->lba_shift
) - 1);
344 cmnd
->rw
.control
= cpu_to_le16(control
);
345 cmnd
->rw
.dsmgmt
= cpu_to_le32(dsmgmt
);
347 writel(nvmeq
->sq_tail
, nvmeq
->q_db
);
348 if (++nvmeq
->sq_tail
== nvmeq
->q_depth
)
351 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
362 * NB: return value of non-zero would mean that we were a stacking driver.
363 * make_request must always succeed.
365 static int nvme_make_request(struct request_queue
*q
, struct bio
*bio
)
367 struct nvme_ns
*ns
= q
->queuedata
;
368 struct nvme_queue
*nvmeq
= get_nvmeq(ns
);
370 if (nvme_submit_bio_queue(nvmeq
, ns
, bio
)) {
371 blk_set_queue_congested(q
, rw_is_sync(bio
->bi_rw
));
372 bio_list_add(&nvmeq
->sq_cong
, bio
);
379 struct sync_cmd_info
{
380 struct task_struct
*task
;
385 static void sync_completion(struct nvme_queue
*nvmeq
, void *ctx
,
386 struct nvme_completion
*cqe
)
388 struct sync_cmd_info
*cmdinfo
= ctx
;
389 cmdinfo
->result
= le32_to_cpup(&cqe
->result
);
390 cmdinfo
->status
= le16_to_cpup(&cqe
->status
) >> 1;
391 wake_up_process(cmdinfo
->task
);
394 typedef void (*completion_fn
)(struct nvme_queue
*, void *,
395 struct nvme_completion
*);
397 static irqreturn_t
nvme_process_cq(struct nvme_queue
*nvmeq
)
401 static const completion_fn completions
[4] = {
402 [sync_completion_id
] = sync_completion
,
403 [bio_completion_id
] = bio_completion
,
406 head
= nvmeq
->cq_head
;
407 phase
= nvmeq
->cq_phase
;
412 unsigned char handler
;
413 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
414 if ((le16_to_cpu(cqe
.status
) & 1) != phase
)
416 nvmeq
->sq_head
= le16_to_cpu(cqe
.sq_head
);
417 if (++head
== nvmeq
->q_depth
) {
422 data
= free_cmdid(nvmeq
, cqe
.command_id
);
424 ptr
= (void *)(data
& ~3UL);
425 completions
[handler
](nvmeq
, ptr
, &cqe
);
428 /* If the controller ignores the cq head doorbell and continuously
429 * writes to the queue, it is theoretically possible to wrap around
430 * the queue twice and mistakenly return IRQ_NONE. Linux only
431 * requires that 0.1% of your interrupts are handled, so this isn't
434 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
437 writel(head
, nvmeq
->q_db
+ 1);
438 nvmeq
->cq_head
= head
;
439 nvmeq
->cq_phase
= phase
;
444 static irqreturn_t
nvme_irq(int irq
, void *data
)
446 return nvme_process_cq(data
);
450 * Returns 0 on success. If the result is negative, it's a Linux error code;
451 * if the result is positive, it's an NVM Express status code
453 static int nvme_submit_sync_cmd(struct nvme_queue
*q
, struct nvme_command
*cmd
,
457 struct sync_cmd_info cmdinfo
;
459 cmdinfo
.task
= current
;
460 cmdinfo
.status
= -EINTR
;
462 cmdid
= alloc_cmdid_killable(q
, &cmdinfo
, sync_completion_id
);
465 cmd
->common
.command_id
= cmdid
;
467 set_current_state(TASK_UNINTERRUPTIBLE
);
468 nvme_submit_cmd(q
, cmd
);
472 *result
= cmdinfo
.result
;
474 return cmdinfo
.status
;
477 static int nvme_submit_admin_cmd(struct nvme_dev
*dev
, struct nvme_command
*cmd
,
480 return nvme_submit_sync_cmd(dev
->queues
[0], cmd
, result
);
483 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
486 struct nvme_command c
;
488 memset(&c
, 0, sizeof(c
));
489 c
.delete_queue
.opcode
= opcode
;
490 c
.delete_queue
.qid
= cpu_to_le16(id
);
492 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
498 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
499 struct nvme_queue
*nvmeq
)
502 struct nvme_command c
;
503 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
505 memset(&c
, 0, sizeof(c
));
506 c
.create_cq
.opcode
= nvme_admin_create_cq
;
507 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
508 c
.create_cq
.cqid
= cpu_to_le16(qid
);
509 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
510 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
511 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
513 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
519 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
520 struct nvme_queue
*nvmeq
)
523 struct nvme_command c
;
524 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
526 memset(&c
, 0, sizeof(c
));
527 c
.create_sq
.opcode
= nvme_admin_create_sq
;
528 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
529 c
.create_sq
.sqid
= cpu_to_le16(qid
);
530 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
531 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
532 c
.create_sq
.cqid
= cpu_to_le16(qid
);
534 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
540 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
542 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
545 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
547 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
550 static void nvme_free_queue(struct nvme_dev
*dev
, int qid
)
552 struct nvme_queue
*nvmeq
= dev
->queues
[qid
];
554 free_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvmeq
);
556 /* Don't tell the adapter to delete the admin queue */
558 adapter_delete_sq(dev
, qid
);
559 adapter_delete_cq(dev
, qid
);
562 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
563 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
564 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
565 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
569 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
570 int depth
, int vector
)
572 struct device
*dmadev
= &dev
->pci_dev
->dev
;
573 unsigned extra
= (depth
+ BITS_TO_LONGS(depth
)) * sizeof(long);
574 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
) + extra
, GFP_KERNEL
);
578 nvmeq
->cqes
= dma_alloc_coherent(dmadev
, CQ_SIZE(depth
),
579 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
582 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(depth
));
584 nvmeq
->sq_cmds
= dma_alloc_coherent(dmadev
, SQ_SIZE(depth
),
585 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
589 nvmeq
->q_dmadev
= dmadev
;
590 spin_lock_init(&nvmeq
->q_lock
);
593 init_waitqueue_head(&nvmeq
->sq_full
);
594 bio_list_init(&nvmeq
->sq_cong
);
595 nvmeq
->q_db
= &dev
->dbs
[qid
* 2];
596 nvmeq
->q_depth
= depth
;
597 nvmeq
->cq_vector
= vector
;
602 dma_free_coherent(dmadev
, CQ_SIZE(nvmeq
->q_depth
), (void *)nvmeq
->cqes
,
609 static int queue_request_irq(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
612 return request_irq(dev
->entry
[nvmeq
->cq_vector
].vector
, nvme_irq
,
613 IRQF_DISABLED
| IRQF_SHARED
, name
, nvmeq
);
616 static __devinit
struct nvme_queue
*nvme_create_queue(struct nvme_dev
*dev
,
617 int qid
, int cq_size
, int vector
)
620 struct nvme_queue
*nvmeq
= nvme_alloc_queue(dev
, qid
, cq_size
, vector
);
625 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
629 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
633 result
= queue_request_irq(dev
, nvmeq
, "nvme");
640 adapter_delete_sq(dev
, qid
);
642 adapter_delete_cq(dev
, qid
);
644 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
645 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
646 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
647 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
652 static int __devinit
nvme_configure_admin_queue(struct nvme_dev
*dev
)
656 struct nvme_queue
*nvmeq
;
658 dev
->dbs
= ((void __iomem
*)dev
->bar
) + 4096;
660 nvmeq
= nvme_alloc_queue(dev
, 0, 64, 0);
664 aqa
= nvmeq
->q_depth
- 1;
667 dev
->ctrl_config
= NVME_CC_ENABLE
| NVME_CC_CSS_NVM
;
668 dev
->ctrl_config
|= (PAGE_SHIFT
- 12) << NVME_CC_MPS_SHIFT
;
669 dev
->ctrl_config
|= NVME_CC_ARB_RR
| NVME_CC_SHN_NONE
;
671 writel(0, &dev
->bar
->cc
);
672 writel(aqa
, &dev
->bar
->aqa
);
673 writeq(nvmeq
->sq_dma_addr
, &dev
->bar
->asq
);
674 writeq(nvmeq
->cq_dma_addr
, &dev
->bar
->acq
);
675 writel(dev
->ctrl_config
, &dev
->bar
->cc
);
677 while (!(readl(&dev
->bar
->csts
) & NVME_CSTS_RDY
)) {
679 if (fatal_signal_pending(current
))
683 result
= queue_request_irq(dev
, nvmeq
, "nvme admin");
684 dev
->queues
[0] = nvmeq
;
688 static int nvme_map_user_pages(struct nvme_dev
*dev
, int write
,
689 unsigned long addr
, unsigned length
,
690 struct scatterlist
**sgp
)
692 int i
, err
, count
, nents
, offset
;
693 struct scatterlist
*sg
;
701 offset
= offset_in_page(addr
);
702 count
= DIV_ROUND_UP(offset
+ length
, PAGE_SIZE
);
703 pages
= kcalloc(count
, sizeof(*pages
), GFP_KERNEL
);
705 err
= get_user_pages_fast(addr
, count
, 1, pages
);
712 sg
= kcalloc(count
, sizeof(*sg
), GFP_KERNEL
);
713 sg_init_table(sg
, count
);
714 sg_set_page(&sg
[0], pages
[0], PAGE_SIZE
- offset
, offset
);
715 length
-= (PAGE_SIZE
- offset
);
716 for (i
= 1; i
< count
; i
++) {
717 sg_set_page(&sg
[i
], pages
[i
], min_t(int, length
, PAGE_SIZE
), 0);
722 nents
= dma_map_sg(&dev
->pci_dev
->dev
, sg
, count
,
723 write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
732 for (i
= 0; i
< count
; i
++)
738 static void nvme_unmap_user_pages(struct nvme_dev
*dev
, int write
,
739 unsigned long addr
, int length
,
740 struct scatterlist
*sg
, int nents
)
744 count
= DIV_ROUND_UP(offset_in_page(addr
) + length
, PAGE_SIZE
);
745 dma_unmap_sg(&dev
->pci_dev
->dev
, sg
, nents
, DMA_FROM_DEVICE
);
747 for (i
= 0; i
< count
; i
++)
748 put_page(sg_page(&sg
[i
]));
751 static int nvme_submit_user_admin_command(struct nvme_dev
*dev
,
752 unsigned long addr
, unsigned length
,
753 struct nvme_command
*cmd
)
756 struct scatterlist
*sg
;
758 nents
= nvme_map_user_pages(dev
, 0, addr
, length
, &sg
);
761 nvme_setup_prps(&cmd
->common
, sg
, length
);
762 err
= nvme_submit_admin_cmd(dev
, cmd
, NULL
);
763 nvme_unmap_user_pages(dev
, 0, addr
, length
, sg
, nents
);
764 return err
? -EIO
: 0;
767 static int nvme_identify(struct nvme_ns
*ns
, unsigned long addr
, int cns
)
769 struct nvme_command c
;
771 memset(&c
, 0, sizeof(c
));
772 c
.identify
.opcode
= nvme_admin_identify
;
773 c
.identify
.nsid
= cns
? 0 : cpu_to_le32(ns
->ns_id
);
774 c
.identify
.cns
= cpu_to_le32(cns
);
776 return nvme_submit_user_admin_command(ns
->dev
, addr
, 4096, &c
);
779 static int nvme_get_range_type(struct nvme_ns
*ns
, unsigned long addr
)
781 struct nvme_command c
;
783 memset(&c
, 0, sizeof(c
));
784 c
.features
.opcode
= nvme_admin_get_features
;
785 c
.features
.nsid
= cpu_to_le32(ns
->ns_id
);
786 c
.features
.fid
= cpu_to_le32(NVME_FEAT_LBA_RANGE
);
788 return nvme_submit_user_admin_command(ns
->dev
, addr
, 4096, &c
);
791 static int nvme_submit_io(struct nvme_ns
*ns
, struct nvme_user_io __user
*uio
)
793 struct nvme_dev
*dev
= ns
->dev
;
794 struct nvme_queue
*nvmeq
;
795 struct nvme_user_io io
;
796 struct nvme_command c
;
800 struct scatterlist
*sg
;
802 if (copy_from_user(&io
, uio
, sizeof(io
)))
804 length
= io
.nblocks
<< io
.block_shift
;
805 nents
= nvme_map_user_pages(dev
, io
.opcode
& 1, io
.addr
, length
, &sg
);
809 memset(&c
, 0, sizeof(c
));
810 c
.rw
.opcode
= io
.opcode
;
811 c
.rw
.flags
= io
.flags
;
812 c
.rw
.nsid
= cpu_to_le32(io
.nsid
);
813 c
.rw
.slba
= cpu_to_le64(io
.slba
);
814 c
.rw
.length
= cpu_to_le16(io
.nblocks
- 1);
815 c
.rw
.control
= cpu_to_le16(io
.control
);
816 c
.rw
.dsmgmt
= cpu_to_le16(io
.dsmgmt
);
817 c
.rw
.reftag
= cpu_to_le32(io
.reftag
); /* XXX: endian? */
818 c
.rw
.apptag
= cpu_to_le16(io
.apptag
);
819 c
.rw
.appmask
= cpu_to_le16(io
.appmask
);
821 nvme_setup_prps(&c
.common
, sg
, length
);
823 nvmeq
= get_nvmeq(ns
);
824 status
= nvme_submit_sync_cmd(nvmeq
, &c
, &result
);
827 nvme_unmap_user_pages(dev
, io
.opcode
& 1, io
.addr
, length
, sg
, nents
);
828 put_user(result
, &uio
->result
);
832 static int nvme_download_firmware(struct nvme_ns
*ns
,
833 struct nvme_dlfw __user
*udlfw
)
835 struct nvme_dev
*dev
= ns
->dev
;
836 struct nvme_dlfw dlfw
;
837 struct nvme_command c
;
839 struct scatterlist
*sg
;
841 if (copy_from_user(&dlfw
, udlfw
, sizeof(dlfw
)))
843 if (dlfw
.length
>= (1 << 30))
846 nents
= nvme_map_user_pages(dev
, 1, dlfw
.addr
, dlfw
.length
* 4, &sg
);
850 memset(&c
, 0, sizeof(c
));
851 c
.dlfw
.opcode
= nvme_admin_download_fw
;
852 c
.dlfw
.numd
= cpu_to_le32(dlfw
.length
);
853 c
.dlfw
.offset
= cpu_to_le32(dlfw
.offset
);
854 nvme_setup_prps(&c
.common
, sg
, dlfw
.length
* 4);
856 status
= nvme_submit_admin_cmd(dev
, &c
, NULL
);
857 nvme_unmap_user_pages(dev
, 0, dlfw
.addr
, dlfw
.length
* 4, sg
, nents
);
861 static int nvme_activate_firmware(struct nvme_ns
*ns
, unsigned long arg
)
863 struct nvme_dev
*dev
= ns
->dev
;
864 struct nvme_command c
;
866 memset(&c
, 0, sizeof(c
));
867 c
.common
.opcode
= nvme_admin_activate_fw
;
868 c
.common
.rsvd10
[0] = cpu_to_le32(arg
);
870 return nvme_submit_admin_cmd(dev
, &c
, NULL
);
873 static int nvme_ioctl(struct block_device
*bdev
, fmode_t mode
, unsigned int cmd
,
876 struct nvme_ns
*ns
= bdev
->bd_disk
->private_data
;
879 case NVME_IOCTL_IDENTIFY_NS
:
880 return nvme_identify(ns
, arg
, 0);
881 case NVME_IOCTL_IDENTIFY_CTRL
:
882 return nvme_identify(ns
, arg
, 1);
883 case NVME_IOCTL_GET_RANGE_TYPE
:
884 return nvme_get_range_type(ns
, arg
);
885 case NVME_IOCTL_SUBMIT_IO
:
886 return nvme_submit_io(ns
, (void __user
*)arg
);
887 case NVME_IOCTL_DOWNLOAD_FW
:
888 return nvme_download_firmware(ns
, (void __user
*)arg
);
889 case NVME_IOCTL_ACTIVATE_FW
:
890 return nvme_activate_firmware(ns
, arg
);
896 static const struct block_device_operations nvme_fops
= {
897 .owner
= THIS_MODULE
,
901 static struct nvme_ns
*nvme_alloc_ns(struct nvme_dev
*dev
, int index
,
902 struct nvme_id_ns
*id
, struct nvme_lba_range_type
*rt
)
905 struct gendisk
*disk
;
908 if (rt
->attributes
& NVME_LBART_ATTRIB_HIDE
)
911 ns
= kzalloc(sizeof(*ns
), GFP_KERNEL
);
914 ns
->queue
= blk_alloc_queue(GFP_KERNEL
);
917 ns
->queue
->queue_flags
= QUEUE_FLAG_DEFAULT
| QUEUE_FLAG_NOMERGES
|
918 QUEUE_FLAG_NONROT
| QUEUE_FLAG_DISCARD
;
919 blk_queue_make_request(ns
->queue
, nvme_make_request
);
921 ns
->queue
->queuedata
= ns
;
923 disk
= alloc_disk(NVME_MINORS
);
928 lbaf
= id
->flbas
& 0xf;
929 ns
->lba_shift
= id
->lbaf
[lbaf
].ds
;
931 disk
->major
= nvme_major
;
932 disk
->minors
= NVME_MINORS
;
933 disk
->first_minor
= NVME_MINORS
* index
;
934 disk
->fops
= &nvme_fops
;
935 disk
->private_data
= ns
;
936 disk
->queue
= ns
->queue
;
937 disk
->driverfs_dev
= &dev
->pci_dev
->dev
;
938 sprintf(disk
->disk_name
, "nvme%dn%d", dev
->instance
, index
);
939 set_capacity(disk
, le64_to_cpup(&id
->nsze
) << (ns
->lba_shift
- 9));
944 blk_cleanup_queue(ns
->queue
);
950 static void nvme_ns_free(struct nvme_ns
*ns
)
953 blk_cleanup_queue(ns
->queue
);
957 static int set_queue_count(struct nvme_dev
*dev
, int count
)
961 struct nvme_command c
;
962 u32 q_count
= (count
- 1) | ((count
- 1) << 16);
964 memset(&c
, 0, sizeof(c
));
965 c
.features
.opcode
= nvme_admin_get_features
;
966 c
.features
.fid
= cpu_to_le32(NVME_FEAT_NUM_QUEUES
);
967 c
.features
.dword11
= cpu_to_le32(q_count
);
969 status
= nvme_submit_admin_cmd(dev
, &c
, &result
);
972 return min(result
& 0xffff, result
>> 16) + 1;
975 static int __devinit
nvme_setup_io_queues(struct nvme_dev
*dev
)
977 int result
, cpu
, i
, nr_queues
;
979 nr_queues
= num_online_cpus();
980 result
= set_queue_count(dev
, nr_queues
);
983 if (result
< nr_queues
)
986 /* Deregister the admin queue's interrupt */
987 free_irq(dev
->entry
[0].vector
, dev
->queues
[0]);
989 for (i
= 0; i
< nr_queues
; i
++)
990 dev
->entry
[i
].entry
= i
;
992 result
= pci_enable_msix(dev
->pci_dev
, dev
->entry
, nr_queues
);
995 } else if (result
> 0) {
1004 result
= queue_request_irq(dev
, dev
->queues
[0], "nvme admin");
1005 /* XXX: handle failure here */
1007 cpu
= cpumask_first(cpu_online_mask
);
1008 for (i
= 0; i
< nr_queues
; i
++) {
1009 irq_set_affinity_hint(dev
->entry
[i
].vector
, get_cpu_mask(cpu
));
1010 cpu
= cpumask_next(cpu
, cpu_online_mask
);
1013 for (i
= 0; i
< nr_queues
; i
++) {
1014 dev
->queues
[i
+ 1] = nvme_create_queue(dev
, i
+ 1,
1016 if (!dev
->queues
[i
+ 1])
1024 static void nvme_free_queues(struct nvme_dev
*dev
)
1028 for (i
= dev
->queue_count
- 1; i
>= 0; i
--)
1029 nvme_free_queue(dev
, i
);
1032 static int __devinit
nvme_dev_add(struct nvme_dev
*dev
)
1035 struct nvme_ns
*ns
, *next
;
1036 struct nvme_id_ctrl
*ctrl
;
1038 dma_addr_t dma_addr
;
1039 struct nvme_command cid
, crt
;
1041 res
= nvme_setup_io_queues(dev
);
1045 /* XXX: Switch to a SG list once prp2 works */
1046 id
= dma_alloc_coherent(&dev
->pci_dev
->dev
, 8192, &dma_addr
,
1049 memset(&cid
, 0, sizeof(cid
));
1050 cid
.identify
.opcode
= nvme_admin_identify
;
1051 cid
.identify
.nsid
= 0;
1052 cid
.identify
.prp1
= cpu_to_le64(dma_addr
);
1053 cid
.identify
.cns
= cpu_to_le32(1);
1055 res
= nvme_submit_admin_cmd(dev
, &cid
, NULL
);
1062 nn
= le32_to_cpup(&ctrl
->nn
);
1063 memcpy(dev
->serial
, ctrl
->sn
, sizeof(ctrl
->sn
));
1064 memcpy(dev
->model
, ctrl
->mn
, sizeof(ctrl
->mn
));
1065 memcpy(dev
->firmware_rev
, ctrl
->fr
, sizeof(ctrl
->fr
));
1067 cid
.identify
.cns
= 0;
1068 memset(&crt
, 0, sizeof(crt
));
1069 crt
.features
.opcode
= nvme_admin_get_features
;
1070 crt
.features
.prp1
= cpu_to_le64(dma_addr
+ 4096);
1071 crt
.features
.fid
= cpu_to_le32(NVME_FEAT_LBA_RANGE
);
1073 for (i
= 0; i
< nn
; i
++) {
1074 cid
.identify
.nsid
= cpu_to_le32(i
);
1075 res
= nvme_submit_admin_cmd(dev
, &cid
, NULL
);
1079 if (((struct nvme_id_ns
*)id
)->ncap
== 0)
1082 crt
.features
.nsid
= cpu_to_le32(i
);
1083 res
= nvme_submit_admin_cmd(dev
, &crt
, NULL
);
1087 ns
= nvme_alloc_ns(dev
, i
, id
, id
+ 4096);
1089 list_add_tail(&ns
->list
, &dev
->namespaces
);
1091 list_for_each_entry(ns
, &dev
->namespaces
, list
)
1094 dma_free_coherent(&dev
->pci_dev
->dev
, 4096, id
, dma_addr
);
1098 list_for_each_entry_safe(ns
, next
, &dev
->namespaces
, list
) {
1099 list_del(&ns
->list
);
1103 dma_free_coherent(&dev
->pci_dev
->dev
, 4096, id
, dma_addr
);
1107 static int nvme_dev_remove(struct nvme_dev
*dev
)
1109 struct nvme_ns
*ns
, *next
;
1111 /* TODO: wait all I/O finished or cancel them */
1113 list_for_each_entry_safe(ns
, next
, &dev
->namespaces
, list
) {
1114 list_del(&ns
->list
);
1115 del_gendisk(ns
->disk
);
1119 nvme_free_queues(dev
);
1124 /* XXX: Use an ida or something to let remove / add work correctly */
1125 static void nvme_set_instance(struct nvme_dev
*dev
)
1127 static int instance
;
1128 dev
->instance
= instance
++;
1131 static void nvme_release_instance(struct nvme_dev
*dev
)
1135 static int __devinit
nvme_probe(struct pci_dev
*pdev
,
1136 const struct pci_device_id
*id
)
1138 int bars
, result
= -ENOMEM
;
1139 struct nvme_dev
*dev
;
1141 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1144 dev
->entry
= kcalloc(num_possible_cpus(), sizeof(*dev
->entry
),
1148 dev
->queues
= kcalloc(num_possible_cpus() + 1, sizeof(void *),
1153 if (pci_enable_device_mem(pdev
))
1155 pci_set_master(pdev
);
1156 bars
= pci_select_bars(pdev
, IORESOURCE_MEM
);
1157 if (pci_request_selected_regions(pdev
, bars
, "nvme"))
1160 INIT_LIST_HEAD(&dev
->namespaces
);
1161 dev
->pci_dev
= pdev
;
1162 pci_set_drvdata(pdev
, dev
);
1163 dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1164 dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64));
1165 nvme_set_instance(dev
);
1166 dev
->entry
[0].vector
= pdev
->irq
;
1168 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
1174 result
= nvme_configure_admin_queue(dev
);
1179 result
= nvme_dev_add(dev
);
1185 nvme_free_queues(dev
);
1189 pci_disable_msix(pdev
);
1190 nvme_release_instance(dev
);
1192 pci_disable_device(pdev
);
1193 pci_release_regions(pdev
);
1201 static void __devexit
nvme_remove(struct pci_dev
*pdev
)
1203 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
1204 nvme_dev_remove(dev
);
1205 pci_disable_msix(pdev
);
1207 nvme_release_instance(dev
);
1208 pci_disable_device(pdev
);
1209 pci_release_regions(pdev
);
1215 /* These functions are yet to be implemented */
1216 #define nvme_error_detected NULL
1217 #define nvme_dump_registers NULL
1218 #define nvme_link_reset NULL
1219 #define nvme_slot_reset NULL
1220 #define nvme_error_resume NULL
1221 #define nvme_suspend NULL
1222 #define nvme_resume NULL
1224 static struct pci_error_handlers nvme_err_handler
= {
1225 .error_detected
= nvme_error_detected
,
1226 .mmio_enabled
= nvme_dump_registers
,
1227 .link_reset
= nvme_link_reset
,
1228 .slot_reset
= nvme_slot_reset
,
1229 .resume
= nvme_error_resume
,
1232 /* Move to pci_ids.h later */
1233 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
1235 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table
) = {
1236 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
1239 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
1241 static struct pci_driver nvme_driver
= {
1243 .id_table
= nvme_id_table
,
1244 .probe
= nvme_probe
,
1245 .remove
= __devexit_p(nvme_remove
),
1246 .suspend
= nvme_suspend
,
1247 .resume
= nvme_resume
,
1248 .err_handler
= &nvme_err_handler
,
1251 static int __init
nvme_init(void)
1255 nvme_major
= register_blkdev(nvme_major
, "nvme");
1256 if (nvme_major
<= 0)
1259 result
= pci_register_driver(&nvme_driver
);
1263 unregister_blkdev(nvme_major
, "nvme");
1267 static void __exit
nvme_exit(void)
1269 pci_unregister_driver(&nvme_driver
);
1270 unregister_blkdev(nvme_major
, "nvme");
1273 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1274 MODULE_LICENSE("GPL");
1275 MODULE_VERSION("0.1");
1276 module_init(nvme_init
);
1277 module_exit(nvme_exit
);