drivers/block/skd_s1120.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright 2012 STEC, Inc.
   4  * Copyright (c) 2017 Western Digital Corporation or its affiliates.
   5  */
   6
   7
   8 #ifndef SKD_S1120_H
   9 #define SKD_S1120_H
  10
  11 /*
  12  * Q-channel, 64-bit r/w
  13  */
  14 #define FIT_Q_COMMAND                   0x400u
  15 #define FIT_QCMD_QID_MASK               (0x3 << 1)
  16 #define  FIT_QCMD_QID0                  (0x0 << 1)
  17 #define  FIT_QCMD_QID_NORMAL            FIT_QCMD_QID0
  18 #define  FIT_QCMD_QID1                  (0x1 << 1)
  19 #define  FIT_QCMD_QID2                  (0x2 << 1)
  20 #define  FIT_QCMD_QID3                  (0x3 << 1)
  21 #define  FIT_QCMD_FLUSH_QUEUE           (0ull)  /* add QID */
  22 #define  FIT_QCMD_MSGSIZE_MASK          (0x3 << 4)
  23 #define  FIT_QCMD_MSGSIZE_64            (0x0 << 4)
  24 #define  FIT_QCMD_MSGSIZE_128           (0x1 << 4)
  25 #define  FIT_QCMD_MSGSIZE_256           (0x2 << 4)
  26 #define  FIT_QCMD_MSGSIZE_512           (0x3 << 4)
  27 #define  FIT_QCMD_ALIGN                 L1_CACHE_BYTES
  28
  29 /*
  30  * Control, 32-bit r/w
  31  */
  32 #define FIT_CONTROL                     0x500u
  33 #define  FIT_CR_HARD_RESET              (1u << 0u)
  34 #define  FIT_CR_SOFT_RESET              (1u << 1u)
  35 #define  FIT_CR_DIS_TIMESTAMPS          (1u << 6u)
  36 #define  FIT_CR_ENABLE_INTERRUPTS       (1u << 7u)
  37
  38 /*
  39  * Status, 32-bit, r/o
  40  */
  41 #define FIT_STATUS                      0x510u
  42 #define FIT_SR_DRIVE_STATE_MASK         0x000000FFu
  43 #define FIT_SR_SIGNATURE                (0xFF << 8)
  44 #define FIT_SR_PIO_DMA                  (1 << 16)
  45 #define FIT_SR_DRIVE_OFFLINE            0x00
  46 #define FIT_SR_DRIVE_INIT               0x01
  47 /* #define FIT_SR_DRIVE_READY           0x02 */
  48 #define FIT_SR_DRIVE_ONLINE             0x03
  49 #define FIT_SR_DRIVE_BUSY               0x04
  50 #define FIT_SR_DRIVE_FAULT              0x05
  51 #define FIT_SR_DRIVE_DEGRADED           0x06
  52 #define FIT_SR_PCIE_LINK_DOWN           0x07
  53 #define FIT_SR_DRIVE_SOFT_RESET         0x08
  54 #define FIT_SR_DRIVE_INIT_FAULT         0x09
  55 #define FIT_SR_DRIVE_BUSY_SANITIZE      0x0A
  56 #define FIT_SR_DRIVE_BUSY_ERASE         0x0B
  57 #define FIT_SR_DRIVE_FW_BOOTING         0x0C
  58 #define FIT_SR_DRIVE_NEED_FW_DOWNLOAD   0xFE
  59 #define FIT_SR_DEVICE_MISSING           0xFF
  60 #define FIT_SR__RESERVED                0xFFFFFF00u
  61
  62 /*
  63  * FIT_STATUS - Status register data definition
  64  */
  65 #define FIT_SR_STATE_MASK               (0xFF << 0)
  66 #define FIT_SR_SIGNATURE                (0xFF << 8)
  67 #define FIT_SR_PIO_DMA                  (1 << 16)
  68
  69 /*
  70  * Interrupt status, 32-bit r/w1c (w1c ==> write 1 to clear)
  71  */
  72 #define FIT_INT_STATUS_HOST             0x520u
  73 #define  FIT_ISH_FW_STATE_CHANGE        (1u << 0u)
  74 #define  FIT_ISH_COMPLETION_POSTED      (1u << 1u)
  75 #define  FIT_ISH_MSG_FROM_DEV           (1u << 2u)
  76 #define  FIT_ISH_UNDEFINED_3            (1u << 3u)
  77 #define  FIT_ISH_UNDEFINED_4            (1u << 4u)
  78 #define  FIT_ISH_Q0_FULL                (1u << 5u)
  79 #define  FIT_ISH_Q1_FULL                (1u << 6u)
  80 #define  FIT_ISH_Q2_FULL                (1u << 7u)
  81 #define  FIT_ISH_Q3_FULL                (1u << 8u)
  82 #define  FIT_ISH_QCMD_FIFO_OVERRUN      (1u << 9u)
  83 #define  FIT_ISH_BAD_EXP_ROM_READ       (1u << 10u)
  84
  85 #define FIT_INT_DEF_MASK \
  86         (FIT_ISH_FW_STATE_CHANGE | \
  87          FIT_ISH_COMPLETION_POSTED | \
  88          FIT_ISH_MSG_FROM_DEV | \
  89          FIT_ISH_Q0_FULL | \
  90          FIT_ISH_Q1_FULL | \
  91          FIT_ISH_Q2_FULL | \
  92          FIT_ISH_Q3_FULL | \
  93          FIT_ISH_QCMD_FIFO_OVERRUN | \
  94          FIT_ISH_BAD_EXP_ROM_READ)
  95
  96 #define FIT_INT_QUEUE_FULL \
  97         (FIT_ISH_Q0_FULL | \
  98          FIT_ISH_Q1_FULL | \
  99          FIT_ISH_Q2_FULL | \
 100          FIT_ISH_Q3_FULL)
 101
 102 #define MSI_MSG_NWL_ERROR_0             0x00000000
 103 #define MSI_MSG_NWL_ERROR_1             0x00000001
 104 #define MSI_MSG_NWL_ERROR_2             0x00000002
 105 #define MSI_MSG_NWL_ERROR_3             0x00000003
 106 #define MSI_MSG_STATE_CHANGE            0x00000004
 107 #define MSI_MSG_COMPLETION_POSTED       0x00000005
 108 #define MSI_MSG_MSG_FROM_DEV            0x00000006
 109 #define MSI_MSG_RESERVED_0              0x00000007
 110 #define MSI_MSG_RESERVED_1              0x00000008
 111 #define MSI_MSG_QUEUE_0_FULL            0x00000009
 112 #define MSI_MSG_QUEUE_1_FULL            0x0000000A
 113 #define MSI_MSG_QUEUE_2_FULL            0x0000000B
 114 #define MSI_MSG_QUEUE_3_FULL            0x0000000C
 115
 116 #define FIT_INT_RESERVED_MASK \
 117         (FIT_ISH_UNDEFINED_3 | \
 118          FIT_ISH_UNDEFINED_4)
 119
 120 /*
 121  * Interrupt mask, 32-bit r/w
 122  * Bit definitions are the same as FIT_INT_STATUS_HOST
 123  */
 124 #define FIT_INT_MASK_HOST               0x528u
 125
 126 /*
 127  * Message to device, 32-bit r/w
 128  */
 129 #define FIT_MSG_TO_DEVICE               0x540u
 130
 131 /*
 132  * Message from device, 32-bit, r/o
 133  */
 134 #define FIT_MSG_FROM_DEVICE             0x548u
 135
 136 /*
 137  * 32-bit messages to/from device, composition/extraction macros
 138  */
 139 #define FIT_MXD_CONS(TYPE, PARAM, DATA) \
 140         ((((TYPE)  & 0xFFu) << 24u) | \
 141         (((PARAM) & 0xFFu) << 16u) | \
 142         (((DATA)  & 0xFFFFu) << 0u))
 143 #define FIT_MXD_TYPE(MXD)               (((MXD) >> 24u) & 0xFFu)
 144 #define FIT_MXD_PARAM(MXD)              (((MXD) >> 16u) & 0xFFu)
 145 #define FIT_MXD_DATA(MXD)               (((MXD) >> 0u) & 0xFFFFu)
 146
 147 /*
 148  * Types of messages to/from device
 149  */
 150 #define FIT_MTD_FITFW_INIT              0x01u
 151 #define FIT_MTD_GET_CMDQ_DEPTH          0x02u
 152 #define FIT_MTD_SET_COMPQ_DEPTH         0x03u
 153 #define FIT_MTD_SET_COMPQ_ADDR          0x04u
 154 #define FIT_MTD_ARM_QUEUE               0x05u
 155 #define FIT_MTD_CMD_LOG_HOST_ID         0x07u
 156 #define FIT_MTD_CMD_LOG_TIME_STAMP_LO   0x08u
 157 #define FIT_MTD_CMD_LOG_TIME_STAMP_HI   0x09u
 158 #define FIT_MFD_SMART_EXCEEDED          0x10u
 159 #define FIT_MFD_POWER_DOWN              0x11u
 160 #define FIT_MFD_OFFLINE                 0x12u
 161 #define FIT_MFD_ONLINE                  0x13u
 162 #define FIT_MFD_FW_RESTARTING           0x14u
 163 #define FIT_MFD_PM_ACTIVE               0x15u
 164 #define FIT_MFD_PM_STANDBY              0x16u
 165 #define FIT_MFD_PM_SLEEP                0x17u
 166 #define FIT_MFD_CMD_PROGRESS            0x18u
 167
 168 #define FIT_MTD_DEBUG                   0xFEu
 169 #define FIT_MFD_DEBUG                   0xFFu
 170
 171 #define FIT_MFD_MASK                    (0xFFu)
 172 #define FIT_MFD_DATA_MASK               (0xFFu)
 173 #define FIT_MFD_MSG(x)                  (((x) >> 24) & FIT_MFD_MASK)
 174 #define FIT_MFD_DATA(x)                 ((x) & FIT_MFD_MASK)
 175
 176 /*
 177  * Extra arg to FIT_MSG_TO_DEVICE, 64-bit r/w
 178  * Used to set completion queue address (FIT_MTD_SET_COMPQ_ADDR)
 179  * (was Response buffer in docs)
 180  */
 181 #define FIT_MSG_TO_DEVICE_ARG           0x580u
 182
 183 /*
 184  * Hardware (ASIC) version, 32-bit r/o
 185  */
 186 #define FIT_HW_VERSION                  0x588u
 187
 188 /*
 189  * Scatter/gather list descriptor.
 190  * 32-bytes and must be aligned on a 32-byte boundary.
 191  * All fields are in little endian order.
 192  */
 193 struct fit_sg_descriptor {
 194         uint32_t control;
 195         uint32_t byte_count;
 196         uint64_t host_side_addr;
 197         uint64_t dev_side_addr;
 198         uint64_t next_desc_ptr;
 199 };
 200
 201 #define FIT_SGD_CONTROL_NOT_LAST        0x000u
 202 #define FIT_SGD_CONTROL_LAST            0x40Eu
 203
 204 /*
 205  * Header at the beginning of a FIT message. The header
 206  * is followed by SSDI requests each 64 bytes.
 207  * A FIT message can be up to 512 bytes long and must start
 208  * on a 64-byte boundary.
 209  */
 210 struct fit_msg_hdr {
 211         uint8_t protocol_id;
 212         uint8_t num_protocol_cmds_coalesced;
 213         uint8_t _reserved[62];
 214 };
 215
 216 #define FIT_PROTOCOL_ID_FIT     1
 217 #define FIT_PROTOCOL_ID_SSDI    2
 218 #define FIT_PROTOCOL_ID_SOFIT   3
 219
 220
 221 #define FIT_PROTOCOL_MINOR_VER(mtd_val) ((mtd_val >> 16) & 0xF)
 222 #define FIT_PROTOCOL_MAJOR_VER(mtd_val) ((mtd_val >> 20) & 0xF)
 223
 224 /*
 225  * Format of a completion entry. The completion queue is circular
 226  * and must have at least as many entries as the maximum number
 227  * of commands that may be issued to the device.
 228  *
 229  * There are no head/tail pointers. The cycle value is used to
 230  * infer the presence of new completion records.
 231  * Initially the cycle in all entries is 0, the index is 0, and
 232  * the cycle value to expect is 1. When completions are added
 233  * their cycle values are set to 1. When the index wraps the
 234  * cycle value to expect is incremented.
 235  *
 236  * Command_context is opaque and taken verbatim from the SSDI command.
 237  * All other fields are big endian.
 238  */
 239 #define FIT_PROTOCOL_VERSION_0          0
 240
 241 /*
 242  *  Protocol major version 1 completion entry.
 243  *  The major protocol version is found in bits
 244  *  20-23 of the FIT_MTD_FITFW_INIT response.
 245  */
 246 struct fit_completion_entry_v1 {
 247         __be32          num_returned_bytes;
 248         uint16_t        tag;
 249         uint8_t         status;  /* SCSI status */
 250         uint8_t         cycle;
 251 };
 252 #define FIT_PROTOCOL_VERSION_1          1
 253 #define FIT_PROTOCOL_VERSION_CURRENT    FIT_PROTOCOL_VERSION_1
 254
 255 struct fit_comp_error_info {
 256         uint8_t         type:7; /* 00: Bits0-6 indicates the type of sense data. */
 257         uint8_t         valid:1; /* 00: Bit 7 := 1 ==> info field is valid. */
 258         uint8_t         reserved0; /* 01: Obsolete field */
 259         uint8_t         key:4; /* 02: Bits0-3 indicate the sense key. */
 260         uint8_t         reserved2:1; /* 02: Reserved bit. */
 261         uint8_t         bad_length:1; /* 02: Incorrect Length Indicator */
 262         uint8_t         end_medium:1; /* 02: End of Medium */
 263         uint8_t         file_mark:1; /* 02: Filemark */
 264         uint8_t         info[4]; /* 03: */
 265         uint8_t         reserved1; /* 07: Additional Sense Length */
 266         uint8_t         cmd_spec[4]; /* 08: Command Specific Information */
 267         uint8_t         code; /* 0C: Additional Sense Code */
 268         uint8_t         qual; /* 0D: Additional Sense Code Qualifier */
 269         uint8_t         fruc; /* 0E: Field Replaceable Unit Code */
 270         uint8_t         sks_high:7; /* 0F: Sense Key Specific (MSB) */
 271         uint8_t         sks_valid:1; /* 0F: Sense Key Specific Valid */
 272         uint16_t        sks_low; /* 10: Sense Key Specific (LSW) */
 273         uint16_t        reserved3; /* 12: Part of additional sense bytes (unused) */
 274         uint16_t        uec; /* 14: Additional Sense Bytes */
 275         uint64_t        per __packed; /* 16: Additional Sense Bytes */
 276         uint8_t         reserved4[2]; /* 1E: Additional Sense Bytes (unused) */
 277 };
 278
 279
 280 /* Task management constants */
 281 #define SOFT_TASK_SIMPLE                0x00
 282 #define SOFT_TASK_HEAD_OF_QUEUE         0x01
 283 #define SOFT_TASK_ORDERED               0x02
 284
 285 /* Version zero has the last 32 bits reserved,
 286  * Version one has the last 32 bits sg_list_len_bytes;
 287  */
 288 struct skd_command_header {
 289         __be64          sg_list_dma_address;
 290         uint16_t        tag;
 291         uint8_t         attribute;
 292         uint8_t         add_cdb_len;     /* In 32 bit words */
 293         __be32          sg_list_len_bytes;
 294 };
 295
 296 struct skd_scsi_request {
 297         struct          skd_command_header hdr;
 298         unsigned char   cdb[16];
 299 /*      unsigned char _reserved[16]; */
 300 };
 301
 302 struct driver_inquiry_data {
 303         uint8_t         peripheral_device_type:5;
 304         uint8_t         qualifier:3;
 305         uint8_t         page_code;
 306         __be16          page_length;
 307         __be16          pcie_bus_number;
 308         uint8_t         pcie_device_number;
 309         uint8_t         pcie_function_number;
 310         uint8_t         pcie_link_speed;
 311         uint8_t         pcie_link_lanes;
 312         __be16          pcie_vendor_id;
 313         __be16          pcie_device_id;
 314         __be16          pcie_subsystem_vendor_id;
 315         __be16          pcie_subsystem_device_id;
 316         uint8_t         reserved1[2];
 317         uint8_t         reserved2[3];
 318         uint8_t         driver_version_length;
 319         uint8_t         driver_version[0x14];
 320 };
 321
 322 #endif /* SKD_S1120_H */