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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Xilinx SystemACE device driver
4 *
5 * Copyright 2007 Secret Lab Technologies Ltd.
6 */
7
8 /*
9 * The SystemACE chip is designed to configure FPGAs by loading an FPGA
10 * bitstream from a file on a CF card and squirting it into FPGAs connected
11 * to the SystemACE JTAG chain. It also has the advantage of providing an
12 * MPU interface which can be used to control the FPGA configuration process
13 * and to use the attached CF card for general purpose storage.
14 *
15 * This driver is a block device driver for the SystemACE.
16 *
17 * Initialization:
18 * The driver registers itself as a platform_device driver at module
19 * load time. The platform bus will take care of calling the
20 * ace_probe() method for all SystemACE instances in the system. Any
21 * number of SystemACE instances are supported. ace_probe() calls
22 * ace_setup() which initialized all data structures, reads the CF
23 * id structure and registers the device.
24 *
25 * Processing:
26 * Just about all of the heavy lifting in this driver is performed by
27 * a Finite State Machine (FSM). The driver needs to wait on a number
28 * of events; some raised by interrupts, some which need to be polled
29 * for. Describing all of the behaviour in a FSM seems to be the
30 * easiest way to keep the complexity low and make it easy to
31 * understand what the driver is doing. If the block ops or the
32 * request function need to interact with the hardware, then they
33 * simply need to flag the request and kick of FSM processing.
34 *
35 * The FSM itself is atomic-safe code which can be run from any
36 * context. The general process flow is:
37 * 1. obtain the ace->lock spinlock.
38 * 2. loop on ace_fsm_dostate() until the ace->fsm_continue flag is
39 * cleared.
40 * 3. release the lock.
41 *
42 * Individual states do not sleep in any way. If a condition needs to
43 * be waited for then the state much clear the fsm_continue flag and
44 * either schedule the FSM to be run again at a later time, or expect
45 * an interrupt to call the FSM when the desired condition is met.
46 *
47 * In normal operation, the FSM is processed at interrupt context
48 * either when the driver's tasklet is scheduled, or when an irq is
49 * raised by the hardware. The tasklet can be scheduled at any time.
50 * The request method in particular schedules the tasklet when a new
51 * request has been indicated by the block layer. Once started, the
52 * FSM proceeds as far as it can processing the request until it
53 * needs on a hardware event. At this point, it must yield execution.
54 *
55 * A state has two options when yielding execution:
56 * 1. ace_fsm_yield()
57 * - Call if need to poll for event.
58 * - clears the fsm_continue flag to exit the processing loop
59 * - reschedules the tasklet to run again as soon as possible
60 * 2. ace_fsm_yieldirq()
61 * - Call if an irq is expected from the HW
62 * - clears the fsm_continue flag to exit the processing loop
63 * - does not reschedule the tasklet so the FSM will not be processed
64 * again until an irq is received.
65 * After calling a yield function, the state must return control back
66 * to the FSM main loop.
67 *
68 * Additionally, the driver maintains a kernel timer which can process
69 * the FSM. If the FSM gets stalled, typically due to a missed
70 * interrupt, then the kernel timer will expire and the driver can
71 * continue where it left off.
72 *
73 * To Do:
74 * - Add FPGA configuration control interface.
75 * - Request major number from lanana
76 */
77
78 #undef DEBUG
79
80 #include <linux/module.h>
81 #include <linux/ctype.h>
82 #include <linux/init.h>
83 #include <linux/interrupt.h>
84 #include <linux/errno.h>
85 #include <linux/kernel.h>
86 #include <linux/delay.h>
87 #include <linux/slab.h>
88 #include <linux/blk-mq.h>
89 #include <linux/mutex.h>
90 #include <linux/ata.h>
91 #include <linux/hdreg.h>
92 #include <linux/platform_device.h>
93 #if defined(CONFIG_OF)
94 #include <linux/of_address.h>
95 #include <linux/of_device.h>
96 #include <linux/of_platform.h>
97 #endif
98
99 MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
100 MODULE_DESCRIPTION("Xilinx SystemACE device driver");
101 MODULE_LICENSE("GPL");
102
103 /* SystemACE register definitions */
104 #define ACE_BUSMODE (0x00)
105
106 #define ACE_STATUS (0x04)
107 #define ACE_STATUS_CFGLOCK (0x00000001)
108 #define ACE_STATUS_MPULOCK (0x00000002)
109 #define ACE_STATUS_CFGERROR (0x00000004) /* config controller error */
110 #define ACE_STATUS_CFCERROR (0x00000008) /* CF controller error */
111 #define ACE_STATUS_CFDETECT (0x00000010)
112 #define ACE_STATUS_DATABUFRDY (0x00000020)
113 #define ACE_STATUS_DATABUFMODE (0x00000040)
114 #define ACE_STATUS_CFGDONE (0x00000080)
115 #define ACE_STATUS_RDYFORCFCMD (0x00000100)
116 #define ACE_STATUS_CFGMODEPIN (0x00000200)
117 #define ACE_STATUS_CFGADDR_MASK (0x0000e000)
118 #define ACE_STATUS_CFBSY (0x00020000)
119 #define ACE_STATUS_CFRDY (0x00040000)
120 #define ACE_STATUS_CFDWF (0x00080000)
121 #define ACE_STATUS_CFDSC (0x00100000)
122 #define ACE_STATUS_CFDRQ (0x00200000)
123 #define ACE_STATUS_CFCORR (0x00400000)
124 #define ACE_STATUS_CFERR (0x00800000)
125
126 #define ACE_ERROR (0x08)
127 #define ACE_CFGLBA (0x0c)
128 #define ACE_MPULBA (0x10)
129
130 #define ACE_SECCNTCMD (0x14)
131 #define ACE_SECCNTCMD_RESET (0x0100)
132 #define ACE_SECCNTCMD_IDENTIFY (0x0200)
133 #define ACE_SECCNTCMD_READ_DATA (0x0300)
134 #define ACE_SECCNTCMD_WRITE_DATA (0x0400)
135 #define ACE_SECCNTCMD_ABORT (0x0600)
136
137 #define ACE_VERSION (0x16)
138 #define ACE_VERSION_REVISION_MASK (0x00FF)
139 #define ACE_VERSION_MINOR_MASK (0x0F00)
140 #define ACE_VERSION_MAJOR_MASK (0xF000)
141
142 #define ACE_CTRL (0x18)
143 #define ACE_CTRL_FORCELOCKREQ (0x0001)
144 #define ACE_CTRL_LOCKREQ (0x0002)
145 #define ACE_CTRL_FORCECFGADDR (0x0004)
146 #define ACE_CTRL_FORCECFGMODE (0x0008)
147 #define ACE_CTRL_CFGMODE (0x0010)
148 #define ACE_CTRL_CFGSTART (0x0020)
149 #define ACE_CTRL_CFGSEL (0x0040)
150 #define ACE_CTRL_CFGRESET (0x0080)
151 #define ACE_CTRL_DATABUFRDYIRQ (0x0100)
152 #define ACE_CTRL_ERRORIRQ (0x0200)
153 #define ACE_CTRL_CFGDONEIRQ (0x0400)
154 #define ACE_CTRL_RESETIRQ (0x0800)
155 #define ACE_CTRL_CFGPROG (0x1000)
156 #define ACE_CTRL_CFGADDR_MASK (0xe000)
157
158 #define ACE_FATSTAT (0x1c)
159
160 #define ACE_NUM_MINORS 16
161 #define ACE_SECTOR_SIZE (512)
162 #define ACE_FIFO_SIZE (32)
163 #define ACE_BUF_PER_SECTOR (ACE_SECTOR_SIZE / ACE_FIFO_SIZE)
164
165 #define ACE_BUS_WIDTH_8 0
166 #define ACE_BUS_WIDTH_16 1
167
168 struct ace_reg_ops;
169
170 struct ace_device {
171 /* driver state data */
172 int id;
173 int media_change;
174 int users;
175 struct list_head list;
176
177 /* finite state machine data */
178 struct tasklet_struct fsm_tasklet;
179 uint fsm_task; /* Current activity (ACE_TASK_*) */
180 uint fsm_state; /* Current state (ACE_FSM_STATE_*) */
181 uint fsm_continue_flag; /* cleared to exit FSM mainloop */
182 uint fsm_iter_num;
183 struct timer_list stall_timer;
184
185 /* Transfer state/result, use for both id and block request */
186 struct request *req; /* request being processed */
187 void *data_ptr; /* pointer to I/O buffer */
188 int data_count; /* number of buffers remaining */
189 int data_result; /* Result of transfer; 0 := success */
190
191 int id_req_count; /* count of id requests */
192 int id_result;
193 struct completion id_completion; /* used when id req finishes */
194 int in_irq;
195
196 /* Details of hardware device */
197 resource_size_t physaddr;
198 void __iomem *baseaddr;
199 int irq;
200 int bus_width; /* 0 := 8 bit; 1 := 16 bit */
201 struct ace_reg_ops *reg_ops;
202 int lock_count;
203
204 /* Block device data structures */
205 spinlock_t lock;
206 struct device *dev;
207 struct request_queue *queue;
208 struct gendisk *gd;
209 struct blk_mq_tag_set tag_set;
210 struct list_head rq_list;
211
212 /* Inserted CF card parameters */
213 u16 cf_id[ATA_ID_WORDS];
214 };
215
216 static DEFINE_MUTEX(xsysace_mutex);
217 static int ace_major;
218
219 /* ---------------------------------------------------------------------
220 * Low level register access
221 */
222
223 struct ace_reg_ops {
224 u16(*in) (struct ace_device * ace, int reg);
225 void (*out) (struct ace_device * ace, int reg, u16 val);
226 void (*datain) (struct ace_device * ace);
227 void (*dataout) (struct ace_device * ace);
228 };
229
230 /* 8 Bit bus width */
231 static u16 ace_in_8(struct ace_device *ace, int reg)
232 {
233 void __iomem *r = ace->baseaddr + reg;
234 return in_8(r) | (in_8(r + 1) << 8);
235 }
236
237 static void ace_out_8(struct ace_device *ace, int reg, u16 val)
238 {
239 void __iomem *r = ace->baseaddr + reg;
240 out_8(r, val);
241 out_8(r + 1, val >> 8);
242 }
243
244 static void ace_datain_8(struct ace_device *ace)
245 {
246 void __iomem *r = ace->baseaddr + 0x40;
247 u8 *dst = ace->data_ptr;
248 int i = ACE_FIFO_SIZE;
249 while (i--)
250 *dst++ = in_8(r++);
251 ace->data_ptr = dst;
252 }
253
254 static void ace_dataout_8(struct ace_device *ace)
255 {
256 void __iomem *r = ace->baseaddr + 0x40;
257 u8 *src = ace->data_ptr;
258 int i = ACE_FIFO_SIZE;
259 while (i--)
260 out_8(r++, *src++);
261 ace->data_ptr = src;
262 }
263
264 static struct ace_reg_ops ace_reg_8_ops = {
265 .in = ace_in_8,
266 .out = ace_out_8,
267 .datain = ace_datain_8,
268 .dataout = ace_dataout_8,
269 };
270
271 /* 16 bit big endian bus attachment */
272 static u16 ace_in_be16(struct ace_device *ace, int reg)
273 {
274 return in_be16(ace->baseaddr + reg);
275 }
276
277 static void ace_out_be16(struct ace_device *ace, int reg, u16 val)
278 {
279 out_be16(ace->baseaddr + reg, val);
280 }
281
282 static void ace_datain_be16(struct ace_device *ace)
283 {
284 int i = ACE_FIFO_SIZE / 2;
285 u16 *dst = ace->data_ptr;
286 while (i--)
287 *dst++ = in_le16(ace->baseaddr + 0x40);
288 ace->data_ptr = dst;
289 }
290
291 static void ace_dataout_be16(struct ace_device *ace)
292 {
293 int i = ACE_FIFO_SIZE / 2;
294 u16 *src = ace->data_ptr;
295 while (i--)
296 out_le16(ace->baseaddr + 0x40, *src++);
297 ace->data_ptr = src;
298 }
299
300 /* 16 bit little endian bus attachment */
301 static u16 ace_in_le16(struct ace_device *ace, int reg)
302 {
303 return in_le16(ace->baseaddr + reg);
304 }
305
306 static void ace_out_le16(struct ace_device *ace, int reg, u16 val)
307 {
308 out_le16(ace->baseaddr + reg, val);
309 }
310
311 static void ace_datain_le16(struct ace_device *ace)
312 {
313 int i = ACE_FIFO_SIZE / 2;
314 u16 *dst = ace->data_ptr;
315 while (i--)
316 *dst++ = in_be16(ace->baseaddr + 0x40);
317 ace->data_ptr = dst;
318 }
319
320 static void ace_dataout_le16(struct ace_device *ace)
321 {
322 int i = ACE_FIFO_SIZE / 2;
323 u16 *src = ace->data_ptr;
324 while (i--)
325 out_be16(ace->baseaddr + 0x40, *src++);
326 ace->data_ptr = src;
327 }
328
329 static struct ace_reg_ops ace_reg_be16_ops = {
330 .in = ace_in_be16,
331 .out = ace_out_be16,
332 .datain = ace_datain_be16,
333 .dataout = ace_dataout_be16,
334 };
335
336 static struct ace_reg_ops ace_reg_le16_ops = {
337 .in = ace_in_le16,
338 .out = ace_out_le16,
339 .datain = ace_datain_le16,
340 .dataout = ace_dataout_le16,
341 };
342
343 static inline u16 ace_in(struct ace_device *ace, int reg)
344 {
345 return ace->reg_ops->in(ace, reg);
346 }
347
348 static inline u32 ace_in32(struct ace_device *ace, int reg)
349 {
350 return ace_in(ace, reg) | (ace_in(ace, reg + 2) << 16);
351 }
352
353 static inline void ace_out(struct ace_device *ace, int reg, u16 val)
354 {
355 ace->reg_ops->out(ace, reg, val);
356 }
357
358 static inline void ace_out32(struct ace_device *ace, int reg, u32 val)
359 {
360 ace_out(ace, reg, val);
361 ace_out(ace, reg + 2, val >> 16);
362 }
363
364 /* ---------------------------------------------------------------------
365 * Debug support functions
366 */
367
368 #if defined(DEBUG)
369 static void ace_dump_mem(void *base, int len)
370 {
371 const char *ptr = base;
372 int i, j;
373
374 for (i = 0; i < len; i += 16) {
375 printk(KERN_INFO "%.8x:", i);
376 for (j = 0; j < 16; j++) {
377 if (!(j % 4))
378 printk(" ");
379 printk("%.2x", ptr[i + j]);
380 }
381 printk(" ");
382 for (j = 0; j < 16; j++)
383 printk("%c", isprint(ptr[i + j]) ? ptr[i + j] : '.');
384 printk("\n");
385 }
386 }
387 #else
388 static inline void ace_dump_mem(void *base, int len)
389 {
390 }
391 #endif
392
393 static void ace_dump_regs(struct ace_device *ace)
394 {
395 dev_info(ace->dev,
396 " ctrl: %.8x seccnt/cmd: %.4x ver:%.4x\n"
397 " status:%.8x mpu_lba:%.8x busmode:%4x\n"
398 " error: %.8x cfg_lba:%.8x fatstat:%.4x\n",
399 ace_in32(ace, ACE_CTRL),
400 ace_in(ace, ACE_SECCNTCMD),
401 ace_in(ace, ACE_VERSION),
402 ace_in32(ace, ACE_STATUS),
403 ace_in32(ace, ACE_MPULBA),
404 ace_in(ace, ACE_BUSMODE),
405 ace_in32(ace, ACE_ERROR),
406 ace_in32(ace, ACE_CFGLBA), ace_in(ace, ACE_FATSTAT));
407 }
408
409 static void ace_fix_driveid(u16 *id)
410 {
411 #if defined(__BIG_ENDIAN)
412 int i;
413
414 /* All half words have wrong byte order; swap the bytes */
415 for (i = 0; i < ATA_ID_WORDS; i++, id++)
416 *id = le16_to_cpu(*id);
417 #endif
418 }
419
420 /* ---------------------------------------------------------------------
421 * Finite State Machine (FSM) implementation
422 */
423
424 /* FSM tasks; used to direct state transitions */
425 #define ACE_TASK_IDLE 0
426 #define ACE_TASK_IDENTIFY 1
427 #define ACE_TASK_READ 2
428 #define ACE_TASK_WRITE 3
429 #define ACE_FSM_NUM_TASKS 4
430
431 /* FSM state definitions */
432 #define ACE_FSM_STATE_IDLE 0
433 #define ACE_FSM_STATE_REQ_LOCK 1
434 #define ACE_FSM_STATE_WAIT_LOCK 2
435 #define ACE_FSM_STATE_WAIT_CFREADY 3
436 #define ACE_FSM_STATE_IDENTIFY_PREPARE 4
437 #define ACE_FSM_STATE_IDENTIFY_TRANSFER 5
438 #define ACE_FSM_STATE_IDENTIFY_COMPLETE 6
439 #define ACE_FSM_STATE_REQ_PREPARE 7
440 #define ACE_FSM_STATE_REQ_TRANSFER 8
441 #define ACE_FSM_STATE_REQ_COMPLETE 9
442 #define ACE_FSM_STATE_ERROR 10
443 #define ACE_FSM_NUM_STATES 11
444
445 /* Set flag to exit FSM loop and reschedule tasklet */
446 static inline void ace_fsm_yieldpoll(struct ace_device *ace)
447 {
448 tasklet_schedule(&ace->fsm_tasklet);
449 ace->fsm_continue_flag = 0;
450 }
451
452 static inline void ace_fsm_yield(struct ace_device *ace)
453 {
454 dev_dbg(ace->dev, "%s()\n", __func__);
455 ace_fsm_yieldpoll(ace);
456 }
457
458 /* Set flag to exit FSM loop and wait for IRQ to reschedule tasklet */
459 static inline void ace_fsm_yieldirq(struct ace_device *ace)
460 {
461 dev_dbg(ace->dev, "ace_fsm_yieldirq()\n");
462
463 if (ace->irq > 0)
464 ace->fsm_continue_flag = 0;
465 else
466 ace_fsm_yieldpoll(ace);
467 }
468
469 static bool ace_has_next_request(struct request_queue *q)
470 {
471 struct ace_device *ace = q->queuedata;
472
473 return !list_empty(&ace->rq_list);
474 }
475
476 /* Get the next read/write request; ending requests that we don't handle */
477 static struct request *ace_get_next_request(struct request_queue *q)
478 {
479 struct ace_device *ace = q->queuedata;
480 struct request *rq;
481
482 rq = list_first_entry_or_null(&ace->rq_list, struct request, queuelist);
483 if (rq) {
484 list_del_init(&rq->queuelist);
485 blk_mq_start_request(rq);
486 }
487
488 return NULL;
489 }
490
491 static void ace_fsm_dostate(struct ace_device *ace)
492 {
493 struct request *req;
494 u32 status;
495 u16 val;
496 int count;
497
498 #if defined(DEBUG)
499 dev_dbg(ace->dev, "fsm_state=%i, id_req_count=%i\n",
500 ace->fsm_state, ace->id_req_count);
501 #endif
502
503 /* Verify that there is actually a CF in the slot. If not, then
504 * bail out back to the idle state and wake up all the waiters */
505 status = ace_in32(ace, ACE_STATUS);
506 if ((status & ACE_STATUS_CFDETECT) == 0) {
507 ace->fsm_state = ACE_FSM_STATE_IDLE;
508 ace->media_change = 1;
509 set_capacity(ace->gd, 0);
510 dev_info(ace->dev, "No CF in slot\n");
511
512 /* Drop all in-flight and pending requests */
513 if (ace->req) {
514 blk_mq_end_request(ace->req, BLK_STS_IOERR);
515 ace->req = NULL;
516 }
517 while ((req = ace_get_next_request(ace->queue)) != NULL)
518 blk_mq_end_request(req, BLK_STS_IOERR);
519
520 /* Drop back to IDLE state and notify waiters */
521 ace->fsm_state = ACE_FSM_STATE_IDLE;
522 ace->id_result = -EIO;
523 while (ace->id_req_count) {
524 complete(&ace->id_completion);
525 ace->id_req_count--;
526 }
527 }
528
529 switch (ace->fsm_state) {
530 case ACE_FSM_STATE_IDLE:
531 /* See if there is anything to do */
532 if (ace->id_req_count || ace_has_next_request(ace->queue)) {
533 ace->fsm_iter_num++;
534 ace->fsm_state = ACE_FSM_STATE_REQ_LOCK;
535 mod_timer(&ace->stall_timer, jiffies + HZ);
536 if (!timer_pending(&ace->stall_timer))
537 add_timer(&ace->stall_timer);
538 break;
539 }
540 del_timer(&ace->stall_timer);
541 ace->fsm_continue_flag = 0;
542 break;
543
544 case ACE_FSM_STATE_REQ_LOCK:
545 if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) {
546 /* Already have the lock, jump to next state */
547 ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY;
548 break;
549 }
550
551 /* Request the lock */
552 val = ace_in(ace, ACE_CTRL);
553 ace_out(ace, ACE_CTRL, val | ACE_CTRL_LOCKREQ);
554 ace->fsm_state = ACE_FSM_STATE_WAIT_LOCK;
555 break;
556
557 case ACE_FSM_STATE_WAIT_LOCK:
558 if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) {
559 /* got the lock; move to next state */
560 ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY;
561 break;
562 }
563
564 /* wait a bit for the lock */
565 ace_fsm_yield(ace);
566 break;
567
568 case ACE_FSM_STATE_WAIT_CFREADY:
569 status = ace_in32(ace, ACE_STATUS);
570 if (!(status & ACE_STATUS_RDYFORCFCMD) ||
571 (status & ACE_STATUS_CFBSY)) {
572 /* CF card isn't ready; it needs to be polled */
573 ace_fsm_yield(ace);
574 break;
575 }
576
577 /* Device is ready for command; determine what to do next */
578 if (ace->id_req_count)
579 ace->fsm_state = ACE_FSM_STATE_IDENTIFY_PREPARE;
580 else
581 ace->fsm_state = ACE_FSM_STATE_REQ_PREPARE;
582 break;
583
584 case ACE_FSM_STATE_IDENTIFY_PREPARE:
585 /* Send identify command */
586 ace->fsm_task = ACE_TASK_IDENTIFY;
587 ace->data_ptr = ace->cf_id;
588 ace->data_count = ACE_BUF_PER_SECTOR;
589 ace_out(ace, ACE_SECCNTCMD, ACE_SECCNTCMD_IDENTIFY);
590
591 /* As per datasheet, put config controller in reset */
592 val = ace_in(ace, ACE_CTRL);
593 ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET);
594
595 /* irq handler takes over from this point; wait for the
596 * transfer to complete */
597 ace->fsm_state = ACE_FSM_STATE_IDENTIFY_TRANSFER;
598 ace_fsm_yieldirq(ace);
599 break;
600
601 case ACE_FSM_STATE_IDENTIFY_TRANSFER:
602 /* Check that the sysace is ready to receive data */
603 status = ace_in32(ace, ACE_STATUS);
604 if (status & ACE_STATUS_CFBSY) {
605 dev_dbg(ace->dev, "CFBSY set; t=%i iter=%i dc=%i\n",
606 ace->fsm_task, ace->fsm_iter_num,
607 ace->data_count);
608 ace_fsm_yield(ace);
609 break;
610 }
611 if (!(status & ACE_STATUS_DATABUFRDY)) {
612 ace_fsm_yield(ace);
613 break;
614 }
615
616 /* Transfer the next buffer */
617 ace->reg_ops->datain(ace);
618 ace->data_count--;
619
620 /* If there are still buffers to be transfers; jump out here */
621 if (ace->data_count != 0) {
622 ace_fsm_yieldirq(ace);
623 break;
624 }
625
626 /* transfer finished; kick state machine */
627 dev_dbg(ace->dev, "identify finished\n");
628 ace->fsm_state = ACE_FSM_STATE_IDENTIFY_COMPLETE;
629 break;
630
631 case ACE_FSM_STATE_IDENTIFY_COMPLETE:
632 ace_fix_driveid(ace->cf_id);
633 ace_dump_mem(ace->cf_id, 512); /* Debug: Dump out disk ID */
634
635 if (ace->data_result) {
636 /* Error occurred, disable the disk */
637 ace->media_change = 1;
638 set_capacity(ace->gd, 0);
639 dev_err(ace->dev, "error fetching CF id (%i)\n",
640 ace->data_result);
641 } else {
642 ace->media_change = 0;
643
644 /* Record disk parameters */
645 set_capacity(ace->gd,
646 ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY));
647 dev_info(ace->dev, "capacity: %i sectors\n",
648 ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY));
649 }
650
651 /* We're done, drop to IDLE state and notify waiters */
652 ace->fsm_state = ACE_FSM_STATE_IDLE;
653 ace->id_result = ace->data_result;
654 while (ace->id_req_count) {
655 complete(&ace->id_completion);
656 ace->id_req_count--;
657 }
658 break;
659
660 case ACE_FSM_STATE_REQ_PREPARE:
661 req = ace_get_next_request(ace->queue);
662 if (!req) {
663 ace->fsm_state = ACE_FSM_STATE_IDLE;
664 break;
665 }
666
667 /* Okay, it's a data request, set it up for transfer */
668 dev_dbg(ace->dev,
669 "request: sec=%llx hcnt=%x, ccnt=%x, dir=%i\n",
670 (unsigned long long)blk_rq_pos(req),
671 blk_rq_sectors(req), blk_rq_cur_sectors(req),
672 rq_data_dir(req));
673
674 ace->req = req;
675 ace->data_ptr = bio_data(req->bio);
676 ace->data_count = blk_rq_cur_sectors(req) * ACE_BUF_PER_SECTOR;
677 ace_out32(ace, ACE_MPULBA, blk_rq_pos(req) & 0x0FFFFFFF);
678
679 count = blk_rq_sectors(req);
680 if (rq_data_dir(req)) {
681 /* Kick off write request */
682 dev_dbg(ace->dev, "write data\n");
683 ace->fsm_task = ACE_TASK_WRITE;
684 ace_out(ace, ACE_SECCNTCMD,
685 count | ACE_SECCNTCMD_WRITE_DATA);
686 } else {
687 /* Kick off read request */
688 dev_dbg(ace->dev, "read data\n");
689 ace->fsm_task = ACE_TASK_READ;
690 ace_out(ace, ACE_SECCNTCMD,
691 count | ACE_SECCNTCMD_READ_DATA);
692 }
693
694 /* As per datasheet, put config controller in reset */
695 val = ace_in(ace, ACE_CTRL);
696 ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET);
697
698 /* Move to the transfer state. The systemace will raise
699 * an interrupt once there is something to do
700 */
701 ace->fsm_state = ACE_FSM_STATE_REQ_TRANSFER;
702 if (ace->fsm_task == ACE_TASK_READ)
703 ace_fsm_yieldirq(ace); /* wait for data ready */
704 break;
705
706 case ACE_FSM_STATE_REQ_TRANSFER:
707 /* Check that the sysace is ready to receive data */
708 status = ace_in32(ace, ACE_STATUS);
709 if (status & ACE_STATUS_CFBSY) {
710 dev_dbg(ace->dev,
711 "CFBSY set; t=%i iter=%i c=%i dc=%i irq=%i\n",
712 ace->fsm_task, ace->fsm_iter_num,
713 blk_rq_cur_sectors(ace->req) * 16,
714 ace->data_count, ace->in_irq);
715 ace_fsm_yield(ace); /* need to poll CFBSY bit */
716 break;
717 }
718 if (!(status & ACE_STATUS_DATABUFRDY)) {
719 dev_dbg(ace->dev,
720 "DATABUF not set; t=%i iter=%i c=%i dc=%i irq=%i\n",
721 ace->fsm_task, ace->fsm_iter_num,
722 blk_rq_cur_sectors(ace->req) * 16,
723 ace->data_count, ace->in_irq);
724 ace_fsm_yieldirq(ace);
725 break;
726 }
727
728 /* Transfer the next buffer */
729 if (ace->fsm_task == ACE_TASK_WRITE)
730 ace->reg_ops->dataout(ace);
731 else
732 ace->reg_ops->datain(ace);
733 ace->data_count--;
734
735 /* If there are still buffers to be transfers; jump out here */
736 if (ace->data_count != 0) {
737 ace_fsm_yieldirq(ace);
738 break;
739 }
740
741 /* bio finished; is there another one? */
742 if (blk_update_request(ace->req, BLK_STS_OK,
743 blk_rq_cur_bytes(ace->req))) {
744 /* dev_dbg(ace->dev, "next block; h=%u c=%u\n",
745 * blk_rq_sectors(ace->req),
746 * blk_rq_cur_sectors(ace->req));
747 */
748 ace->data_ptr = bio_data(ace->req->bio);
749 ace->data_count = blk_rq_cur_sectors(ace->req) * 16;
750 ace_fsm_yieldirq(ace);
751 break;
752 }
753
754 ace->fsm_state = ACE_FSM_STATE_REQ_COMPLETE;
755 break;
756
757 case ACE_FSM_STATE_REQ_COMPLETE:
758 ace->req = NULL;
759
760 /* Finished request; go to idle state */
761 ace->fsm_state = ACE_FSM_STATE_IDLE;
762 break;
763
764 default:
765 ace->fsm_state = ACE_FSM_STATE_IDLE;
766 break;
767 }
768 }
769
770 static void ace_fsm_tasklet(unsigned long data)
771 {
772 struct ace_device *ace = (void *)data;
773 unsigned long flags;
774
775 spin_lock_irqsave(&ace->lock, flags);
776
777 /* Loop over state machine until told to stop */
778 ace->fsm_continue_flag = 1;
779 while (ace->fsm_continue_flag)
780 ace_fsm_dostate(ace);
781
782 spin_unlock_irqrestore(&ace->lock, flags);
783 }
784
785 static void ace_stall_timer(struct timer_list *t)
786 {
787 struct ace_device *ace = from_timer(ace, t, stall_timer);
788 unsigned long flags;
789
790 dev_warn(ace->dev,
791 "kicking stalled fsm; state=%i task=%i iter=%i dc=%i\n",
792 ace->fsm_state, ace->fsm_task, ace->fsm_iter_num,
793 ace->data_count);
794 spin_lock_irqsave(&ace->lock, flags);
795
796 /* Rearm the stall timer *before* entering FSM (which may then
797 * delete the timer) */
798 mod_timer(&ace->stall_timer, jiffies + HZ);
799
800 /* Loop over state machine until told to stop */
801 ace->fsm_continue_flag = 1;
802 while (ace->fsm_continue_flag)
803 ace_fsm_dostate(ace);
804
805 spin_unlock_irqrestore(&ace->lock, flags);
806 }
807
808 /* ---------------------------------------------------------------------
809 * Interrupt handling routines
810 */
811 static int ace_interrupt_checkstate(struct ace_device *ace)
812 {
813 u32 sreg = ace_in32(ace, ACE_STATUS);
814 u16 creg = ace_in(ace, ACE_CTRL);
815
816 /* Check for error occurrence */
817 if ((sreg & (ACE_STATUS_CFGERROR | ACE_STATUS_CFCERROR)) &&
818 (creg & ACE_CTRL_ERRORIRQ)) {
819 dev_err(ace->dev, "transfer failure\n");
820 ace_dump_regs(ace);
821 return -EIO;
822 }
823
824 return 0;
825 }
826
827 static irqreturn_t ace_interrupt(int irq, void *dev_id)
828 {
829 u16 creg;
830 struct ace_device *ace = dev_id;
831
832 /* be safe and get the lock */
833 spin_lock(&ace->lock);
834 ace->in_irq = 1;
835
836 /* clear the interrupt */
837 creg = ace_in(ace, ACE_CTRL);
838 ace_out(ace, ACE_CTRL, creg | ACE_CTRL_RESETIRQ);
839 ace_out(ace, ACE_CTRL, creg);
840
841 /* check for IO failures */
842 if (ace_interrupt_checkstate(ace))
843 ace->data_result = -EIO;
844
845 if (ace->fsm_task == 0) {
846 dev_err(ace->dev,
847 "spurious irq; stat=%.8x ctrl=%.8x cmd=%.4x\n",
848 ace_in32(ace, ACE_STATUS), ace_in32(ace, ACE_CTRL),
849 ace_in(ace, ACE_SECCNTCMD));
850 dev_err(ace->dev, "fsm_task=%i fsm_state=%i data_count=%i\n",
851 ace->fsm_task, ace->fsm_state, ace->data_count);
852 }
853
854 /* Loop over state machine until told to stop */
855 ace->fsm_continue_flag = 1;
856 while (ace->fsm_continue_flag)
857 ace_fsm_dostate(ace);
858
859 /* done with interrupt; drop the lock */
860 ace->in_irq = 0;
861 spin_unlock(&ace->lock);
862
863 return IRQ_HANDLED;
864 }
865
866 /* ---------------------------------------------------------------------
867 * Block ops
868 */
869 static blk_status_t ace_queue_rq(struct blk_mq_hw_ctx *hctx,
870 const struct blk_mq_queue_data *bd)
871 {
872 struct ace_device *ace = hctx->queue->queuedata;
873 struct request *req = bd->rq;
874
875 if (blk_rq_is_passthrough(req)) {
876 blk_mq_start_request(req);
877 return BLK_STS_IOERR;
878 }
879
880 spin_lock_irq(&ace->lock);
881 list_add_tail(&req->queuelist, &ace->rq_list);
882 spin_unlock_irq(&ace->lock);
883
884 tasklet_schedule(&ace->fsm_tasklet);
885 return BLK_STS_OK;
886 }
887
888 static unsigned int ace_check_events(struct gendisk *gd, unsigned int clearing)
889 {
890 struct ace_device *ace = gd->private_data;
891 dev_dbg(ace->dev, "ace_check_events(): %i\n", ace->media_change);
892
893 return ace->media_change ? DISK_EVENT_MEDIA_CHANGE : 0;
894 }
895
896 static void ace_media_changed(struct ace_device *ace)
897 {
898 unsigned long flags;
899
900 dev_dbg(ace->dev, "requesting cf id and scheduling tasklet\n");
901
902 spin_lock_irqsave(&ace->lock, flags);
903 ace->id_req_count++;
904 spin_unlock_irqrestore(&ace->lock, flags);
905
906 tasklet_schedule(&ace->fsm_tasklet);
907 wait_for_completion(&ace->id_completion);
908
909 dev_dbg(ace->dev, "revalidate complete\n");
910 }
911
912 static int ace_open(struct block_device *bdev, fmode_t mode)
913 {
914 struct ace_device *ace = bdev->bd_disk->private_data;
915 unsigned long flags;
916
917 dev_dbg(ace->dev, "ace_open() users=%i\n", ace->users + 1);
918
919 mutex_lock(&xsysace_mutex);
920 spin_lock_irqsave(&ace->lock, flags);
921 ace->users++;
922 spin_unlock_irqrestore(&ace->lock, flags);
923
924 if (bdev_check_media_change(bdev) && ace->media_change)
925 ace_media_changed(ace);
926 mutex_unlock(&xsysace_mutex);
927
928 return 0;
929 }
930
931 static void ace_release(struct gendisk *disk, fmode_t mode)
932 {
933 struct ace_device *ace = disk->private_data;
934 unsigned long flags;
935 u16 val;
936
937 dev_dbg(ace->dev, "ace_release() users=%i\n", ace->users - 1);
938
939 mutex_lock(&xsysace_mutex);
940 spin_lock_irqsave(&ace->lock, flags);
941 ace->users--;
942 if (ace->users == 0) {
943 val = ace_in(ace, ACE_CTRL);
944 ace_out(ace, ACE_CTRL, val & ~ACE_CTRL_LOCKREQ);
945 }
946 spin_unlock_irqrestore(&ace->lock, flags);
947 mutex_unlock(&xsysace_mutex);
948 }
949
950 static int ace_getgeo(struct block_device *bdev, struct hd_geometry *geo)
951 {
952 struct ace_device *ace = bdev->bd_disk->private_data;
953 u16 *cf_id = ace->cf_id;
954
955 dev_dbg(ace->dev, "ace_getgeo()\n");
956
957 geo->heads = cf_id[ATA_ID_HEADS];
958 geo->sectors = cf_id[ATA_ID_SECTORS];
959 geo->cylinders = cf_id[ATA_ID_CYLS];
960
961 return 0;
962 }
963
964 static const struct block_device_operations ace_fops = {
965 .owner = THIS_MODULE,
966 .open = ace_open,
967 .release = ace_release,
968 .check_events = ace_check_events,
969 .getgeo = ace_getgeo,
970 };
971
972 static const struct blk_mq_ops ace_mq_ops = {
973 .queue_rq = ace_queue_rq,
974 };
975
976 /* --------------------------------------------------------------------
977 * SystemACE device setup/teardown code
978 */
979 static int ace_setup(struct ace_device *ace)
980 {
981 u16 version;
982 u16 val;
983 int rc;
984
985 dev_dbg(ace->dev, "ace_setup(ace=0x%p)\n", ace);
986 dev_dbg(ace->dev, "physaddr=0x%llx irq=%i\n",
987 (unsigned long long)ace->physaddr, ace->irq);
988
989 spin_lock_init(&ace->lock);
990 init_completion(&ace->id_completion);
991 INIT_LIST_HEAD(&ace->rq_list);
992
993 /*
994 * Map the device
995 */
996 ace->baseaddr = ioremap(ace->physaddr, 0x80);
997 if (!ace->baseaddr)
998 goto err_ioremap;
999
1000 /*
1001 * Initialize the state machine tasklet and stall timer
1002 */
1003 tasklet_init(&ace->fsm_tasklet, ace_fsm_tasklet, (unsigned long)ace);
1004 timer_setup(&ace->stall_timer, ace_stall_timer, 0);
1005
1006 /*
1007 * Initialize the request queue
1008 */
1009 ace->queue = blk_mq_init_sq_queue(&ace->tag_set, &ace_mq_ops, 2,
1010 BLK_MQ_F_SHOULD_MERGE);
1011 if (IS_ERR(ace->queue)) {
1012 rc = PTR_ERR(ace->queue);
1013 ace->queue = NULL;
1014 goto err_blk_initq;
1015 }
1016 ace->queue->queuedata = ace;
1017
1018 blk_queue_logical_block_size(ace->queue, 512);
1019 blk_queue_bounce_limit(ace->queue, BLK_BOUNCE_HIGH);
1020
1021 /*
1022 * Allocate and initialize GD structure
1023 */
1024 ace->gd = alloc_disk(ACE_NUM_MINORS);
1025 if (!ace->gd)
1026 goto err_alloc_disk;
1027
1028 ace->gd->major = ace_major;
1029 ace->gd->first_minor = ace->id * ACE_NUM_MINORS;
1030 ace->gd->fops = &ace_fops;
1031 ace->gd->events = DISK_EVENT_MEDIA_CHANGE;
1032 ace->gd->queue = ace->queue;
1033 ace->gd->private_data = ace;
1034 snprintf(ace->gd->disk_name, 32, "xs%c", ace->id + 'a');
1035
1036 /* set bus width */
1037 if (ace->bus_width == ACE_BUS_WIDTH_16) {
1038 /* 0x0101 should work regardless of endianess */
1039 ace_out_le16(ace, ACE_BUSMODE, 0x0101);
1040
1041 /* read it back to determine endianess */
1042 if (ace_in_le16(ace, ACE_BUSMODE) == 0x0001)
1043 ace->reg_ops = &ace_reg_le16_ops;
1044 else
1045 ace->reg_ops = &ace_reg_be16_ops;
1046 } else {
1047 ace_out_8(ace, ACE_BUSMODE, 0x00);
1048 ace->reg_ops = &ace_reg_8_ops;
1049 }
1050
1051 /* Make sure version register is sane */
1052 version = ace_in(ace, ACE_VERSION);
1053 if ((version == 0) || (version == 0xFFFF))
1054 goto err_read;
1055
1056 /* Put sysace in a sane state by clearing most control reg bits */
1057 ace_out(ace, ACE_CTRL, ACE_CTRL_FORCECFGMODE |
1058 ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ);
1059
1060 /* Now we can hook up the irq handler */
1061 if (ace->irq > 0) {
1062 rc = request_irq(ace->irq, ace_interrupt, 0, "systemace", ace);
1063 if (rc) {
1064 /* Failure - fall back to polled mode */
1065 dev_err(ace->dev, "request_irq failed\n");
1066 ace->irq = rc;
1067 }
1068 }
1069
1070 /* Enable interrupts */
1071 val = ace_in(ace, ACE_CTRL);
1072 val |= ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ;
1073 ace_out(ace, ACE_CTRL, val);
1074
1075 /* Print the identification */
1076 dev_info(ace->dev, "Xilinx SystemACE revision %i.%i.%i\n",
1077 (version >> 12) & 0xf, (version >> 8) & 0x0f, version & 0xff);
1078 dev_dbg(ace->dev, "physaddr 0x%llx, mapped to 0x%p, irq=%i\n",
1079 (unsigned long long) ace->physaddr, ace->baseaddr, ace->irq);
1080
1081 ace->media_change = 1;
1082 ace_media_changed(ace);
1083
1084 /* Make the sysace device 'live' */
1085 add_disk(ace->gd);
1086
1087 return 0;
1088
1089 err_read:
1090 /* prevent double queue cleanup */
1091 ace->gd->queue = NULL;
1092 put_disk(ace->gd);
1093 err_alloc_disk:
1094 blk_cleanup_queue(ace->queue);
1095 blk_mq_free_tag_set(&ace->tag_set);
1096 err_blk_initq:
1097 iounmap(ace->baseaddr);
1098 err_ioremap:
1099 dev_info(ace->dev, "xsysace: error initializing device at 0x%llx\n",
1100 (unsigned long long) ace->physaddr);
1101 return -ENOMEM;
1102 }
1103
1104 static void ace_teardown(struct ace_device *ace)
1105 {
1106 if (ace->gd) {
1107 del_gendisk(ace->gd);
1108 put_disk(ace->gd);
1109 }
1110
1111 if (ace->queue) {
1112 blk_cleanup_queue(ace->queue);
1113 blk_mq_free_tag_set(&ace->tag_set);
1114 }
1115
1116 tasklet_kill(&ace->fsm_tasklet);
1117
1118 if (ace->irq > 0)
1119 free_irq(ace->irq, ace);
1120
1121 iounmap(ace->baseaddr);
1122 }
1123
1124 static int ace_alloc(struct device *dev, int id, resource_size_t physaddr,
1125 int irq, int bus_width)
1126 {
1127 struct ace_device *ace;
1128 int rc;
1129 dev_dbg(dev, "ace_alloc(%p)\n", dev);
1130
1131 /* Allocate and initialize the ace device structure */
1132 ace = kzalloc(sizeof(struct ace_device), GFP_KERNEL);
1133 if (!ace) {
1134 rc = -ENOMEM;
1135 goto err_alloc;
1136 }
1137
1138 ace->dev = dev;
1139 ace->id = id;
1140 ace->physaddr = physaddr;
1141 ace->irq = irq;
1142 ace->bus_width = bus_width;
1143
1144 /* Call the setup code */
1145 rc = ace_setup(ace);
1146 if (rc)
1147 goto err_setup;
1148
1149 dev_set_drvdata(dev, ace);
1150 return 0;
1151
1152 err_setup:
1153 dev_set_drvdata(dev, NULL);
1154 kfree(ace);
1155 err_alloc:
1156 dev_err(dev, "could not initialize device, err=%i\n", rc);
1157 return rc;
1158 }
1159
1160 static void ace_free(struct device *dev)
1161 {
1162 struct ace_device *ace = dev_get_drvdata(dev);
1163 dev_dbg(dev, "ace_free(%p)\n", dev);
1164
1165 if (ace) {
1166 ace_teardown(ace);
1167 dev_set_drvdata(dev, NULL);
1168 kfree(ace);
1169 }
1170 }
1171
1172 /* ---------------------------------------------------------------------
1173 * Platform Bus Support
1174 */
1175
1176 static int ace_probe(struct platform_device *dev)
1177 {
1178 int bus_width = ACE_BUS_WIDTH_16; /* FIXME: should not be hard coded */
1179 resource_size_t physaddr;
1180 struct resource *res;
1181 u32 id = dev->id;
1182 int irq;
1183 int i;
1184
1185 dev_dbg(&dev->dev, "ace_probe(%p)\n", dev);
1186
1187 /* device id and bus width */
1188 if (of_property_read_u32(dev->dev.of_node, "port-number", &id))
1189 id = 0;
1190 if (of_find_property(dev->dev.of_node, "8-bit", NULL))
1191 bus_width = ACE_BUS_WIDTH_8;
1192
1193 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1194 if (!res)
1195 return -EINVAL;
1196
1197 physaddr = res->start;
1198 if (!physaddr)
1199 return -ENODEV;
1200
1201 irq = platform_get_irq_optional(dev, 0);
1202
1203 /* Call the bus-independent setup code */
1204 return ace_alloc(&dev->dev, id, physaddr, irq, bus_width);
1205 }
1206
1207 /*
1208 * Platform bus remove() method
1209 */
1210 static int ace_remove(struct platform_device *dev)
1211 {
1212 ace_free(&dev->dev);
1213 return 0;
1214 }
1215
1216 #if defined(CONFIG_OF)
1217 /* Match table for of_platform binding */
1218 static const struct of_device_id ace_of_match[] = {
1219 { .compatible = "xlnx,opb-sysace-1.00.b", },
1220 { .compatible = "xlnx,opb-sysace-1.00.c", },
1221 { .compatible = "xlnx,xps-sysace-1.00.a", },
1222 { .compatible = "xlnx,sysace", },
1223 {},
1224 };
1225 MODULE_DEVICE_TABLE(of, ace_of_match);
1226 #else /* CONFIG_OF */
1227 #define ace_of_match NULL
1228 #endif /* CONFIG_OF */
1229
1230 static struct platform_driver ace_platform_driver = {
1231 .probe = ace_probe,
1232 .remove = ace_remove,
1233 .driver = {
1234 .name = "xsysace",
1235 .of_match_table = ace_of_match,
1236 },
1237 };
1238
1239 /* ---------------------------------------------------------------------
1240 * Module init/exit routines
1241 */
1242 static int __init ace_init(void)
1243 {
1244 int rc;
1245
1246 ace_major = register_blkdev(ace_major, "xsysace");
1247 if (ace_major <= 0) {
1248 rc = -ENOMEM;
1249 goto err_blk;
1250 }
1251
1252 rc = platform_driver_register(&ace_platform_driver);
1253 if (rc)
1254 goto err_plat;
1255
1256 pr_info("Xilinx SystemACE device driver, major=%i\n", ace_major);
1257 return 0;
1258
1259 err_plat:
1260 unregister_blkdev(ace_major, "xsysace");
1261 err_blk:
1262 printk(KERN_ERR "xsysace: registration failed; err=%i\n", rc);
1263 return rc;
1264 }
1265 module_init(ace_init);
1266
1267 static void __exit ace_exit(void)
1268 {
1269 pr_debug("Unregistering Xilinx SystemACE driver\n");
1270 platform_driver_unregister(&ace_platform_driver);
1271 unregister_blkdev(ace_major, "xsysace");
1272 }
1273 module_exit(ace_exit);