2 * OMAP L3 Interconnect error handling driver header
4 * Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * sricharan <r.sricharan@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 #ifndef __OMAP_L3_NOC_H
18 #define __OMAP_L3_NOC_H
20 #define MAX_L3_MODULES 3
21 #define MAX_CLKDM_TARGETS 31
23 #define CLEAR_STDERR_LOG (1 << 31)
24 #define CUSTOM_ERROR 0x2
25 #define STANDARD_ERROR 0x0
26 #define INBAND_ERROR 0x0
27 #define L3_APPLICATION_ERROR 0x0
28 #define L3_DEBUG_ERROR 0x1
30 /* L3 TARG register offsets */
31 #define L3_TARG_STDERRLOG_MAIN 0x48
32 #define L3_TARG_STDERRLOG_HDR 0x4c
33 #define L3_TARG_STDERRLOG_MSTADDR 0x50
34 #define L3_TARG_STDERRLOG_INFO 0x58
35 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
36 #define L3_TARG_STDERRLOG_CINFO_INFO 0x64
37 #define L3_TARG_STDERRLOG_CINFO_MSTADDR 0x68
38 #define L3_TARG_STDERRLOG_CINFO_OPCODE 0x6c
39 #define L3_FLAGMUX_REGERR0 0xc
40 #define L3_FLAGMUX_MASK0 0x8
42 #define L3_TARGET_NOT_SUPPORTED NULL
44 #define L3_BASE_IS_SUBMODULE ((void __iomem *)(1 << 0))
46 static const char * const l3_transaction_type
[] = {
51 /* 1 0 0 */ "Read Link",
52 /* 1 0 1 */ "Write Non-Posted",
53 /* 1 1 0 */ "Write Conditional",
54 /* 1 1 1 */ "Write Broadcast",
58 * struct l3_masters_data - L3 Master information
59 * @id: ID of the L3 Master
62 struct l3_masters_data
{
68 * struct l3_target_data - L3 Target information
69 * @offset: Offset from base for L3 Target
72 * Target information is organized indexed by bit field definitions.
74 struct l3_target_data
{
80 * struct l3_flagmux_data - Flag Mux information
81 * @offset: offset from base for flagmux register
82 * @l3_targ: array indexed by flagmux index (bit offset) pointing to the
83 * target data. unsupported ones are marked with
84 * L3_TARGET_NOT_SUPPORTED
85 * @num_targ_data: number of entries in target data
86 * @mask_app_bits: ignore these from raw application irq status
87 * @mask_dbg_bits: ignore these from raw debug irq status
89 struct l3_flagmux_data
{
91 struct l3_target_data
*l3_targ
;
99 * struct omap_l3 - Description of data relevant for L3 bus.
100 * @dev: device representing the bus (populated runtime)
101 * @l3_base: base addresses of modules (populated runtime if 0)
102 * if set to L3_BASE_IS_SUBMODULE, then uses previous
103 * module index as the base address
104 * @l3_flag_mux: array containing flag mux data per module
105 * offset from corresponding module base indexed per
107 * @num_modules: number of clock domains / modules.
108 * @l3_masters: array pointing to master data containing name and register
109 * offset for the master.
110 * @num_master: number of masters
111 * @mst_addr_mask: Mask representing MSTADDR information of NTTP packet
112 * @debug_irq: irq number of the debug interrupt (populated runtime)
113 * @app_irq: irq number of the application interrupt (populated runtime)
118 void __iomem
*l3_base
[MAX_L3_MODULES
];
119 struct l3_flagmux_data
**l3_flagmux
;
122 struct l3_masters_data
*l3_masters
;
130 static struct l3_target_data omap_l3_target_data_clk1
[] = {
135 {0x600, "CLK2PWRDISC",},
137 {0x900, "L4WAKEUP",},
140 static struct l3_flagmux_data omap_l3_flagmux_clk1
= {
142 .l3_targ
= omap_l3_target_data_clk1
,
143 .num_targ_data
= ARRAY_SIZE(omap_l3_target_data_clk1
),
147 static struct l3_target_data omap_l3_target_data_clk2
[] = {
148 {0x500, "CORTEXM3",},
156 {0x100, "GPMCsERROR",},
160 {0x1100, "PWRDISCCLK1",},
171 static struct l3_flagmux_data omap_l3_flagmux_clk2
= {
173 .l3_targ
= omap_l3_target_data_clk2
,
174 .num_targ_data
= ARRAY_SIZE(omap_l3_target_data_clk2
),
178 static struct l3_target_data omap_l3_target_data_clk3
[] = {
180 {0x0300, "DEBUG SOURCE",},
184 static struct l3_flagmux_data omap_l3_flagmux_clk3
= {
186 .l3_targ
= omap_l3_target_data_clk3
,
187 .num_targ_data
= ARRAY_SIZE(omap_l3_target_data_clk3
),
190 static struct l3_masters_data omap_l3_masters
[] = {
198 { 0x48, "FaceDetect"},
213 { 0xC0, "USBHOSTHS"},
218 static struct l3_flagmux_data
*omap_l3_flagmux
[] = {
219 &omap_l3_flagmux_clk1
,
220 &omap_l3_flagmux_clk2
,
221 &omap_l3_flagmux_clk3
,
224 static const struct omap_l3 omap_l3_data
= {
225 .l3_flagmux
= omap_l3_flagmux
,
226 .num_modules
= ARRAY_SIZE(omap_l3_flagmux
),
227 .l3_masters
= omap_l3_masters
,
228 .num_masters
= ARRAY_SIZE(omap_l3_masters
),
229 /* The 6 MSBs of register field used to distinguish initiator */
230 .mst_addr_mask
= 0xFC,
234 static struct l3_target_data dra_l3_target_data_clk1
[] = {
237 {0x0600, "DSP2_SDMA",},
241 {0x0300, "DSP1_SDMA",},
248 {0x1600, "IVA_CONFIG",},
249 {0x1800, "IVA_SL2IF",},
251 {0x1d00, "L4_WKUP",},
257 {0x2000, "TPCC_EDMA",},
258 {0x2e00, "TPTC1_EDMA",},
259 {0x2b00, "TPTC2_EDMA",},
261 {0x2500, "L4_PER2_P3",},
262 {0x0e00, "L4_PER3_P3",},
269 static struct l3_flagmux_data dra_l3_flagmux_clk1
= {
271 .l3_targ
= dra_l3_target_data_clk1
,
272 .num_targ_data
= ARRAY_SIZE(dra_l3_target_data_clk1
),
275 static struct l3_target_data dra_l3_target_data_clk2
[] = {
278 {0xdead, L3_TARGET_NOT_SUPPORTED
,},
281 {0xdead, L3_TARGET_NOT_SUPPORTED
,},
282 {0x2100, "L4_PER1_P3",},
283 {0x1c00, "L4_PER1_P1",},
284 {0x1f00, "L4_PER1_P2",},
285 {0x2300, "L4_PER2_P1",},
286 {0x2400, "L4_PER2_P2",},
287 {0x2600, "L4_PER3_P1",},
288 {0x2700, "L4_PER3_P2",},
293 {0x0f00, "OCMC_RAM1",},
294 {0x1700, "OCMC_RAM2",},
295 {0x1900, "OCMC_RAM3",},
296 {0x1e00, "OCMC_ROM",},
300 static struct l3_flagmux_data dra_l3_flagmux_clk2
= {
302 .l3_targ
= dra_l3_target_data_clk2
,
303 .num_targ_data
= ARRAY_SIZE(dra_l3_target_data_clk2
),
306 static struct l3_target_data dra_l3_target_data_clk3
[] = {
307 {0x0100, "L3_INSTR"},
308 {0x0300, "DEBUGSS_CT_TBR"},
312 static struct l3_flagmux_data dra_l3_flagmux_clk3
= {
314 .l3_targ
= dra_l3_target_data_clk3
,
315 .num_targ_data
= ARRAY_SIZE(dra_l3_target_data_clk3
),
318 static struct l3_masters_data dra_l3_masters
[] = {
321 { 0x5, "IEEE1500_2_OCP" },
322 { 0x8, "DSP1_MDMA" },
325 { 0xB, "DSP2_MDMA" },
333 { 0x14, "PRUSS1 PRU1" },
334 { 0x15, "PRUSS1 PRU2" },
335 { 0x16, "PRUSS2 PRU1" },
336 { 0x17, "PRUSS2 PRU2" },
341 { 0x1C, "TC1_EDMA" },
342 { 0x1D, "TC2_EDMA" },
357 { 0x2E, "USB2_ULPI_SS1" },
358 { 0x2F, "USB2_ULPI_SS2" },
368 static struct l3_flagmux_data
*dra_l3_flagmux
[] = {
369 &dra_l3_flagmux_clk1
,
370 &dra_l3_flagmux_clk2
,
371 &dra_l3_flagmux_clk3
,
374 static const struct omap_l3 dra_l3_data
= {
375 .l3_base
= { [1] = L3_BASE_IS_SUBMODULE
},
376 .l3_flagmux
= dra_l3_flagmux
,
377 .num_modules
= ARRAY_SIZE(dra_l3_flagmux
),
378 .l3_masters
= dra_l3_masters
,
379 .num_masters
= ARRAY_SIZE(dra_l3_masters
),
380 /* The 6 MSBs of register field used to distinguish initiator */
381 .mst_addr_mask
= 0xFC,
385 static struct l3_target_data am4372_l3_target_data_200f
[] = {
394 {0xdead, L3_TARGET_NOT_SUPPORTED
,},
399 {0x300, "MPUSS_L2_RAM",},
403 static struct l3_flagmux_data am4372_l3_flagmux_200f
= {
405 .l3_targ
= am4372_l3_target_data_200f
,
406 .num_targ_data
= ARRAY_SIZE(am4372_l3_target_data_200f
),
409 static struct l3_target_data am4372_l3_target_data_100s
[] = {
410 {0x100, "L4_PER_0",},
411 {0x200, "L4_PER_1",},
412 {0x300, "L4_PER_2",},
413 {0x400, "L4_PER_3",},
419 {0xdead, L3_TARGET_NOT_SUPPORTED
,},
422 {0xA00, "MAG_CARD",},
425 static struct l3_flagmux_data am4372_l3_flagmux_100s
= {
427 .l3_targ
= am4372_l3_target_data_100s
,
428 .num_targ_data
= ARRAY_SIZE(am4372_l3_target_data_100s
),
431 static struct l3_masters_data am4372_l3_masters
[] = {
432 { 0x0, "M1 (128-bit)"},
433 { 0x1, "M2 (64-bit)"},
438 { 0x14, "Wakeup Processor"},
439 { 0x18, "TPTC0 Read"},
440 { 0x19, "TPTC0 Write"},
441 { 0x1A, "TPTC1 Read"},
442 { 0x1B, "TPTC1 Write"},
443 { 0x1C, "TPTC2 Read"},
444 { 0x1D, "TPTC2 Write"},
446 { 0x21, "OCP WP Traffic Probe"},
447 { 0x22, "OCP WP DMA Profiling"},
448 { 0x23, "OCP WP Event Trace"},
450 { 0x28, "Crypto DMA RD"},
451 { 0x29, "Crypto DMA WR"},
461 static struct l3_flagmux_data
*am4372_l3_flagmux
[] = {
462 &am4372_l3_flagmux_200f
,
463 &am4372_l3_flagmux_100s
,
466 static const struct omap_l3 am4372_l3_data
= {
467 .l3_flagmux
= am4372_l3_flagmux
,
468 .num_modules
= ARRAY_SIZE(am4372_l3_flagmux
),
469 .l3_masters
= am4372_l3_masters
,
470 .num_masters
= ARRAY_SIZE(am4372_l3_masters
),
471 /* All 6 bits of register field used to distinguish initiator */
472 .mst_addr_mask
= 0x3F,
475 #endif /* __OMAP_L3_NOC_H */