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Merge tag 'for-linus-5.16-1' of https://github.com/cminyard/linux-ipmi
[mirror_ubuntu-kernels.git] / drivers / bus / ti-sysc.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
4 */
5
6 #include <linux/io.h>
7 #include <linux/clk.h>
8 #include <linux/clkdev.h>
9 #include <linux/delay.h>
10 #include <linux/list.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_domain.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/reset.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/slab.h>
19 #include <linux/sys_soc.h>
20 #include <linux/iopoll.h>
21
22 #include <linux/platform_data/ti-sysc.h>
23
24 #include <dt-bindings/bus/ti-sysc.h>
25
26 #define DIS_ISP BIT(2)
27 #define DIS_IVA BIT(1)
28 #define DIS_SGX BIT(0)
29
30 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
31
32 #define MAX_MODULE_SOFTRESET_WAIT 10000
33
34 enum sysc_soc {
35 SOC_UNKNOWN,
36 SOC_2420,
37 SOC_2430,
38 SOC_3430,
39 SOC_3630,
40 SOC_4430,
41 SOC_4460,
42 SOC_4470,
43 SOC_5430,
44 SOC_AM3,
45 SOC_AM4,
46 SOC_DRA7,
47 };
48
49 struct sysc_address {
50 unsigned long base;
51 struct list_head node;
52 };
53
54 struct sysc_soc_info {
55 unsigned long general_purpose:1;
56 enum sysc_soc soc;
57 struct mutex list_lock; /* disabled modules list lock */
58 struct list_head disabled_modules;
59 };
60
61 enum sysc_clocks {
62 SYSC_FCK,
63 SYSC_ICK,
64 SYSC_OPTFCK0,
65 SYSC_OPTFCK1,
66 SYSC_OPTFCK2,
67 SYSC_OPTFCK3,
68 SYSC_OPTFCK4,
69 SYSC_OPTFCK5,
70 SYSC_OPTFCK6,
71 SYSC_OPTFCK7,
72 SYSC_MAX_CLOCKS,
73 };
74
75 static struct sysc_soc_info *sysc_soc;
76 static const char * const reg_names[] = { "rev", "sysc", "syss", };
77 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
78 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
79 "opt5", "opt6", "opt7",
80 };
81
82 #define SYSC_IDLEMODE_MASK 3
83 #define SYSC_CLOCKACTIVITY_MASK 3
84
85 /**
86 * struct sysc - TI sysc interconnect target module registers and capabilities
87 * @dev: struct device pointer
88 * @module_pa: physical address of the interconnect target module
89 * @module_size: size of the interconnect target module
90 * @module_va: virtual address of the interconnect target module
91 * @offsets: register offsets from module base
92 * @mdata: ti-sysc to hwmod translation data for a module
93 * @clocks: clocks used by the interconnect target module
94 * @clock_roles: clock role names for the found clocks
95 * @nr_clocks: number of clocks used by the interconnect target module
96 * @rsts: resets used by the interconnect target module
97 * @legacy_mode: configured for legacy mode if set
98 * @cap: interconnect target module capabilities
99 * @cfg: interconnect target module configuration
100 * @cookie: data used by legacy platform callbacks
101 * @name: name if available
102 * @revision: interconnect target module revision
103 * @reserved: target module is reserved and already in use
104 * @enabled: sysc runtime enabled status
105 * @needs_resume: runtime resume needed on resume from suspend
106 * @child_needs_resume: runtime resume needed for child on resume from suspend
107 * @disable_on_idle: status flag used for disabling modules with resets
108 * @idle_work: work structure used to perform delayed idle on a module
109 * @pre_reset_quirk: module specific pre-reset quirk
110 * @post_reset_quirk: module specific post-reset quirk
111 * @reset_done_quirk: module specific reset done quirk
112 * @module_enable_quirk: module specific enable quirk
113 * @module_disable_quirk: module specific disable quirk
114 * @module_unlock_quirk: module specific sysconfig unlock quirk
115 * @module_lock_quirk: module specific sysconfig lock quirk
116 */
117 struct sysc {
118 struct device *dev;
119 u64 module_pa;
120 u32 module_size;
121 void __iomem *module_va;
122 int offsets[SYSC_MAX_REGS];
123 struct ti_sysc_module_data *mdata;
124 struct clk **clocks;
125 const char **clock_roles;
126 int nr_clocks;
127 struct reset_control *rsts;
128 const char *legacy_mode;
129 const struct sysc_capabilities *cap;
130 struct sysc_config cfg;
131 struct ti_sysc_cookie cookie;
132 const char *name;
133 u32 revision;
134 unsigned int reserved:1;
135 unsigned int enabled:1;
136 unsigned int needs_resume:1;
137 unsigned int child_needs_resume:1;
138 struct delayed_work idle_work;
139 void (*pre_reset_quirk)(struct sysc *sysc);
140 void (*post_reset_quirk)(struct sysc *sysc);
141 void (*reset_done_quirk)(struct sysc *sysc);
142 void (*module_enable_quirk)(struct sysc *sysc);
143 void (*module_disable_quirk)(struct sysc *sysc);
144 void (*module_unlock_quirk)(struct sysc *sysc);
145 void (*module_lock_quirk)(struct sysc *sysc);
146 };
147
148 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
149 bool is_child);
150
151 static void sysc_write(struct sysc *ddata, int offset, u32 value)
152 {
153 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
154 writew_relaxed(value & 0xffff, ddata->module_va + offset);
155
156 /* Only i2c revision has LO and HI register with stride of 4 */
157 if (ddata->offsets[SYSC_REVISION] >= 0 &&
158 offset == ddata->offsets[SYSC_REVISION]) {
159 u16 hi = value >> 16;
160
161 writew_relaxed(hi, ddata->module_va + offset + 4);
162 }
163
164 return;
165 }
166
167 writel_relaxed(value, ddata->module_va + offset);
168 }
169
170 static u32 sysc_read(struct sysc *ddata, int offset)
171 {
172 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
173 u32 val;
174
175 val = readw_relaxed(ddata->module_va + offset);
176
177 /* Only i2c revision has LO and HI register with stride of 4 */
178 if (ddata->offsets[SYSC_REVISION] >= 0 &&
179 offset == ddata->offsets[SYSC_REVISION]) {
180 u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
181
182 val |= tmp << 16;
183 }
184
185 return val;
186 }
187
188 return readl_relaxed(ddata->module_va + offset);
189 }
190
191 static bool sysc_opt_clks_needed(struct sysc *ddata)
192 {
193 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
194 }
195
196 static u32 sysc_read_revision(struct sysc *ddata)
197 {
198 int offset = ddata->offsets[SYSC_REVISION];
199
200 if (offset < 0)
201 return 0;
202
203 return sysc_read(ddata, offset);
204 }
205
206 static u32 sysc_read_sysconfig(struct sysc *ddata)
207 {
208 int offset = ddata->offsets[SYSC_SYSCONFIG];
209
210 if (offset < 0)
211 return 0;
212
213 return sysc_read(ddata, offset);
214 }
215
216 static u32 sysc_read_sysstatus(struct sysc *ddata)
217 {
218 int offset = ddata->offsets[SYSC_SYSSTATUS];
219
220 if (offset < 0)
221 return 0;
222
223 return sysc_read(ddata, offset);
224 }
225
226 /* Poll on reset status */
227 static int sysc_wait_softreset(struct sysc *ddata)
228 {
229 u32 sysc_mask, syss_done, rstval;
230 int syss_offset, error = 0;
231
232 if (ddata->cap->regbits->srst_shift < 0)
233 return 0;
234
235 syss_offset = ddata->offsets[SYSC_SYSSTATUS];
236 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
237
238 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
239 syss_done = 0;
240 else
241 syss_done = ddata->cfg.syss_mask;
242
243 if (syss_offset >= 0) {
244 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
245 rstval, (rstval & ddata->cfg.syss_mask) ==
246 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
247
248 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
249 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
250 rstval, !(rstval & sysc_mask),
251 100, MAX_MODULE_SOFTRESET_WAIT);
252 }
253
254 return error;
255 }
256
257 static int sysc_add_named_clock_from_child(struct sysc *ddata,
258 const char *name,
259 const char *optfck_name)
260 {
261 struct device_node *np = ddata->dev->of_node;
262 struct device_node *child;
263 struct clk_lookup *cl;
264 struct clk *clock;
265 const char *n;
266
267 if (name)
268 n = name;
269 else
270 n = optfck_name;
271
272 /* Does the clock alias already exist? */
273 clock = of_clk_get_by_name(np, n);
274 if (!IS_ERR(clock)) {
275 clk_put(clock);
276
277 return 0;
278 }
279
280 child = of_get_next_available_child(np, NULL);
281 if (!child)
282 return -ENODEV;
283
284 clock = devm_get_clk_from_child(ddata->dev, child, name);
285 if (IS_ERR(clock))
286 return PTR_ERR(clock);
287
288 /*
289 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
290 * limit for clk_get(). If cl ever needs to be freed, it should be done
291 * with clkdev_drop().
292 */
293 cl = kzalloc(sizeof(*cl), GFP_KERNEL);
294 if (!cl)
295 return -ENOMEM;
296
297 cl->con_id = n;
298 cl->dev_id = dev_name(ddata->dev);
299 cl->clk = clock;
300 clkdev_add(cl);
301
302 clk_put(clock);
303
304 return 0;
305 }
306
307 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
308 {
309 const char *optfck_name;
310 int error, index;
311
312 if (ddata->nr_clocks < SYSC_OPTFCK0)
313 index = SYSC_OPTFCK0;
314 else
315 index = ddata->nr_clocks;
316
317 if (name)
318 optfck_name = name;
319 else
320 optfck_name = clock_names[index];
321
322 error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
323 if (error)
324 return error;
325
326 ddata->clock_roles[index] = optfck_name;
327 ddata->nr_clocks++;
328
329 return 0;
330 }
331
332 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
333 {
334 int error, i, index = -ENODEV;
335
336 if (!strncmp(clock_names[SYSC_FCK], name, 3))
337 index = SYSC_FCK;
338 else if (!strncmp(clock_names[SYSC_ICK], name, 3))
339 index = SYSC_ICK;
340
341 if (index < 0) {
342 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
343 if (!ddata->clocks[i]) {
344 index = i;
345 break;
346 }
347 }
348 }
349
350 if (index < 0) {
351 dev_err(ddata->dev, "clock %s not added\n", name);
352 return index;
353 }
354
355 ddata->clocks[index] = devm_clk_get(ddata->dev, name);
356 if (IS_ERR(ddata->clocks[index])) {
357 dev_err(ddata->dev, "clock get error for %s: %li\n",
358 name, PTR_ERR(ddata->clocks[index]));
359
360 return PTR_ERR(ddata->clocks[index]);
361 }
362
363 error = clk_prepare(ddata->clocks[index]);
364 if (error) {
365 dev_err(ddata->dev, "clock prepare error for %s: %i\n",
366 name, error);
367
368 return error;
369 }
370
371 return 0;
372 }
373
374 static int sysc_get_clocks(struct sysc *ddata)
375 {
376 struct device_node *np = ddata->dev->of_node;
377 struct property *prop;
378 const char *name;
379 int nr_fck = 0, nr_ick = 0, i, error = 0;
380
381 ddata->clock_roles = devm_kcalloc(ddata->dev,
382 SYSC_MAX_CLOCKS,
383 sizeof(*ddata->clock_roles),
384 GFP_KERNEL);
385 if (!ddata->clock_roles)
386 return -ENOMEM;
387
388 of_property_for_each_string(np, "clock-names", prop, name) {
389 if (!strncmp(clock_names[SYSC_FCK], name, 3))
390 nr_fck++;
391 if (!strncmp(clock_names[SYSC_ICK], name, 3))
392 nr_ick++;
393 ddata->clock_roles[ddata->nr_clocks] = name;
394 ddata->nr_clocks++;
395 }
396
397 if (ddata->nr_clocks < 1)
398 return 0;
399
400 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
401 error = sysc_init_ext_opt_clock(ddata, NULL);
402 if (error)
403 return error;
404 }
405
406 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
407 dev_err(ddata->dev, "too many clocks for %pOF\n", np);
408
409 return -EINVAL;
410 }
411
412 if (nr_fck > 1 || nr_ick > 1) {
413 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
414
415 return -EINVAL;
416 }
417
418 /* Always add a slot for main clocks fck and ick even if unused */
419 if (!nr_fck)
420 ddata->nr_clocks++;
421 if (!nr_ick)
422 ddata->nr_clocks++;
423
424 ddata->clocks = devm_kcalloc(ddata->dev,
425 ddata->nr_clocks, sizeof(*ddata->clocks),
426 GFP_KERNEL);
427 if (!ddata->clocks)
428 return -ENOMEM;
429
430 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
431 const char *name = ddata->clock_roles[i];
432
433 if (!name)
434 continue;
435
436 error = sysc_get_one_clock(ddata, name);
437 if (error)
438 return error;
439 }
440
441 return 0;
442 }
443
444 static int sysc_enable_main_clocks(struct sysc *ddata)
445 {
446 struct clk *clock;
447 int i, error;
448
449 if (!ddata->clocks)
450 return 0;
451
452 for (i = 0; i < SYSC_OPTFCK0; i++) {
453 clock = ddata->clocks[i];
454
455 /* Main clocks may not have ick */
456 if (IS_ERR_OR_NULL(clock))
457 continue;
458
459 error = clk_enable(clock);
460 if (error)
461 goto err_disable;
462 }
463
464 return 0;
465
466 err_disable:
467 for (i--; i >= 0; i--) {
468 clock = ddata->clocks[i];
469
470 /* Main clocks may not have ick */
471 if (IS_ERR_OR_NULL(clock))
472 continue;
473
474 clk_disable(clock);
475 }
476
477 return error;
478 }
479
480 static void sysc_disable_main_clocks(struct sysc *ddata)
481 {
482 struct clk *clock;
483 int i;
484
485 if (!ddata->clocks)
486 return;
487
488 for (i = 0; i < SYSC_OPTFCK0; i++) {
489 clock = ddata->clocks[i];
490 if (IS_ERR_OR_NULL(clock))
491 continue;
492
493 clk_disable(clock);
494 }
495 }
496
497 static int sysc_enable_opt_clocks(struct sysc *ddata)
498 {
499 struct clk *clock;
500 int i, error;
501
502 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
503 return 0;
504
505 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
506 clock = ddata->clocks[i];
507
508 /* Assume no holes for opt clocks */
509 if (IS_ERR_OR_NULL(clock))
510 return 0;
511
512 error = clk_enable(clock);
513 if (error)
514 goto err_disable;
515 }
516
517 return 0;
518
519 err_disable:
520 for (i--; i >= 0; i--) {
521 clock = ddata->clocks[i];
522 if (IS_ERR_OR_NULL(clock))
523 continue;
524
525 clk_disable(clock);
526 }
527
528 return error;
529 }
530
531 static void sysc_disable_opt_clocks(struct sysc *ddata)
532 {
533 struct clk *clock;
534 int i;
535
536 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
537 return;
538
539 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
540 clock = ddata->clocks[i];
541
542 /* Assume no holes for opt clocks */
543 if (IS_ERR_OR_NULL(clock))
544 return;
545
546 clk_disable(clock);
547 }
548 }
549
550 static void sysc_clkdm_deny_idle(struct sysc *ddata)
551 {
552 struct ti_sysc_platform_data *pdata;
553
554 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
555 return;
556
557 pdata = dev_get_platdata(ddata->dev);
558 if (pdata && pdata->clkdm_deny_idle)
559 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
560 }
561
562 static void sysc_clkdm_allow_idle(struct sysc *ddata)
563 {
564 struct ti_sysc_platform_data *pdata;
565
566 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
567 return;
568
569 pdata = dev_get_platdata(ddata->dev);
570 if (pdata && pdata->clkdm_allow_idle)
571 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
572 }
573
574 /**
575 * sysc_init_resets - init rstctrl reset line if configured
576 * @ddata: device driver data
577 *
578 * See sysc_rstctrl_reset_deassert().
579 */
580 static int sysc_init_resets(struct sysc *ddata)
581 {
582 ddata->rsts =
583 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
584
585 return PTR_ERR_OR_ZERO(ddata->rsts);
586 }
587
588 /**
589 * sysc_parse_and_check_child_range - parses module IO region from ranges
590 * @ddata: device driver data
591 *
592 * In general we only need rev, syss, and sysc registers and not the whole
593 * module range. But we do want the offsets for these registers from the
594 * module base. This allows us to check them against the legacy hwmod
595 * platform data. Let's also check the ranges are configured properly.
596 */
597 static int sysc_parse_and_check_child_range(struct sysc *ddata)
598 {
599 struct device_node *np = ddata->dev->of_node;
600 const __be32 *ranges;
601 u32 nr_addr, nr_size;
602 int len, error;
603
604 ranges = of_get_property(np, "ranges", &len);
605 if (!ranges) {
606 dev_err(ddata->dev, "missing ranges for %pOF\n", np);
607
608 return -ENOENT;
609 }
610
611 len /= sizeof(*ranges);
612
613 if (len < 3) {
614 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
615
616 return -EINVAL;
617 }
618
619 error = of_property_read_u32(np, "#address-cells", &nr_addr);
620 if (error)
621 return -ENOENT;
622
623 error = of_property_read_u32(np, "#size-cells", &nr_size);
624 if (error)
625 return -ENOENT;
626
627 if (nr_addr != 1 || nr_size != 1) {
628 dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
629
630 return -EINVAL;
631 }
632
633 ranges++;
634 ddata->module_pa = of_translate_address(np, ranges++);
635 ddata->module_size = be32_to_cpup(ranges);
636
637 return 0;
638 }
639
640 /* Interconnect instances to probe before l4_per instances */
641 static struct resource early_bus_ranges[] = {
642 /* am3/4 l4_wkup */
643 { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
644 /* omap4/5 and dra7 l4_cfg */
645 { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
646 /* omap4 l4_wkup */
647 { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, },
648 /* omap5 and dra7 l4_wkup without dra7 dcan segment */
649 { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, },
650 };
651
652 static atomic_t sysc_defer = ATOMIC_INIT(10);
653
654 /**
655 * sysc_defer_non_critical - defer non_critical interconnect probing
656 * @ddata: device driver data
657 *
658 * We want to probe l4_cfg and l4_wkup interconnect instances before any
659 * l4_per instances as l4_per instances depend on resources on l4_cfg and
660 * l4_wkup interconnects.
661 */
662 static int sysc_defer_non_critical(struct sysc *ddata)
663 {
664 struct resource *res;
665 int i;
666
667 if (!atomic_read(&sysc_defer))
668 return 0;
669
670 for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
671 res = &early_bus_ranges[i];
672 if (ddata->module_pa >= res->start &&
673 ddata->module_pa <= res->end) {
674 atomic_set(&sysc_defer, 0);
675
676 return 0;
677 }
678 }
679
680 atomic_dec_if_positive(&sysc_defer);
681
682 return -EPROBE_DEFER;
683 }
684
685 static struct device_node *stdout_path;
686
687 static void sysc_init_stdout_path(struct sysc *ddata)
688 {
689 struct device_node *np = NULL;
690 const char *uart;
691
692 if (IS_ERR(stdout_path))
693 return;
694
695 if (stdout_path)
696 return;
697
698 np = of_find_node_by_path("/chosen");
699 if (!np)
700 goto err;
701
702 uart = of_get_property(np, "stdout-path", NULL);
703 if (!uart)
704 goto err;
705
706 np = of_find_node_by_path(uart);
707 if (!np)
708 goto err;
709
710 stdout_path = np;
711
712 return;
713
714 err:
715 stdout_path = ERR_PTR(-ENODEV);
716 }
717
718 static void sysc_check_quirk_stdout(struct sysc *ddata,
719 struct device_node *np)
720 {
721 sysc_init_stdout_path(ddata);
722 if (np != stdout_path)
723 return;
724
725 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
726 SYSC_QUIRK_NO_RESET_ON_INIT;
727 }
728
729 /**
730 * sysc_check_one_child - check child configuration
731 * @ddata: device driver data
732 * @np: child device node
733 *
734 * Let's avoid messy situations where we have new interconnect target
735 * node but children have "ti,hwmods". These belong to the interconnect
736 * target node and are managed by this driver.
737 */
738 static void sysc_check_one_child(struct sysc *ddata,
739 struct device_node *np)
740 {
741 const char *name;
742
743 name = of_get_property(np, "ti,hwmods", NULL);
744 if (name && !of_device_is_compatible(np, "ti,sysc"))
745 dev_warn(ddata->dev, "really a child ti,hwmods property?");
746
747 sysc_check_quirk_stdout(ddata, np);
748 sysc_parse_dts_quirks(ddata, np, true);
749 }
750
751 static void sysc_check_children(struct sysc *ddata)
752 {
753 struct device_node *child;
754
755 for_each_child_of_node(ddata->dev->of_node, child)
756 sysc_check_one_child(ddata, child);
757 }
758
759 /*
760 * So far only I2C uses 16-bit read access with clockactivity with revision
761 * in two registers with stride of 4. We can detect this based on the rev
762 * register size to configure things far enough to be able to properly read
763 * the revision register.
764 */
765 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
766 {
767 if (resource_size(res) == 8)
768 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
769 }
770
771 /**
772 * sysc_parse_one - parses the interconnect target module registers
773 * @ddata: device driver data
774 * @reg: register to parse
775 */
776 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
777 {
778 struct resource *res;
779 const char *name;
780
781 switch (reg) {
782 case SYSC_REVISION:
783 case SYSC_SYSCONFIG:
784 case SYSC_SYSSTATUS:
785 name = reg_names[reg];
786 break;
787 default:
788 return -EINVAL;
789 }
790
791 res = platform_get_resource_byname(to_platform_device(ddata->dev),
792 IORESOURCE_MEM, name);
793 if (!res) {
794 ddata->offsets[reg] = -ENODEV;
795
796 return 0;
797 }
798
799 ddata->offsets[reg] = res->start - ddata->module_pa;
800 if (reg == SYSC_REVISION)
801 sysc_check_quirk_16bit(ddata, res);
802
803 return 0;
804 }
805
806 static int sysc_parse_registers(struct sysc *ddata)
807 {
808 int i, error;
809
810 for (i = 0; i < SYSC_MAX_REGS; i++) {
811 error = sysc_parse_one(ddata, i);
812 if (error)
813 return error;
814 }
815
816 return 0;
817 }
818
819 /**
820 * sysc_check_registers - check for misconfigured register overlaps
821 * @ddata: device driver data
822 */
823 static int sysc_check_registers(struct sysc *ddata)
824 {
825 int i, j, nr_regs = 0, nr_matches = 0;
826
827 for (i = 0; i < SYSC_MAX_REGS; i++) {
828 if (ddata->offsets[i] < 0)
829 continue;
830
831 if (ddata->offsets[i] > (ddata->module_size - 4)) {
832 dev_err(ddata->dev, "register outside module range");
833
834 return -EINVAL;
835 }
836
837 for (j = 0; j < SYSC_MAX_REGS; j++) {
838 if (ddata->offsets[j] < 0)
839 continue;
840
841 if (ddata->offsets[i] == ddata->offsets[j])
842 nr_matches++;
843 }
844 nr_regs++;
845 }
846
847 if (nr_matches > nr_regs) {
848 dev_err(ddata->dev, "overlapping registers: (%i/%i)",
849 nr_regs, nr_matches);
850
851 return -EINVAL;
852 }
853
854 return 0;
855 }
856
857 /**
858 * sysc_ioremap - ioremap register space for the interconnect target module
859 * @ddata: device driver data
860 *
861 * Note that the interconnect target module registers can be anywhere
862 * within the interconnect target module range. For example, SGX has
863 * them at offset 0x1fc00 in the 32MB module address space. And cpsw
864 * has them at offset 0x1200 in the CPSW_WR child. Usually the
865 * the interconnect target module registers are at the beginning of
866 * the module range though.
867 */
868 static int sysc_ioremap(struct sysc *ddata)
869 {
870 int size;
871
872 if (ddata->offsets[SYSC_REVISION] < 0 &&
873 ddata->offsets[SYSC_SYSCONFIG] < 0 &&
874 ddata->offsets[SYSC_SYSSTATUS] < 0) {
875 size = ddata->module_size;
876 } else {
877 size = max3(ddata->offsets[SYSC_REVISION],
878 ddata->offsets[SYSC_SYSCONFIG],
879 ddata->offsets[SYSC_SYSSTATUS]);
880
881 if (size < SZ_1K)
882 size = SZ_1K;
883
884 if ((size + sizeof(u32)) > ddata->module_size)
885 size = ddata->module_size;
886 }
887
888 ddata->module_va = devm_ioremap(ddata->dev,
889 ddata->module_pa,
890 size + sizeof(u32));
891 if (!ddata->module_va)
892 return -EIO;
893
894 return 0;
895 }
896
897 /**
898 * sysc_map_and_check_registers - ioremap and check device registers
899 * @ddata: device driver data
900 */
901 static int sysc_map_and_check_registers(struct sysc *ddata)
902 {
903 struct device_node *np = ddata->dev->of_node;
904 int error;
905
906 error = sysc_parse_and_check_child_range(ddata);
907 if (error)
908 return error;
909
910 error = sysc_defer_non_critical(ddata);
911 if (error)
912 return error;
913
914 sysc_check_children(ddata);
915
916 if (!of_get_property(np, "reg", NULL))
917 return 0;
918
919 error = sysc_parse_registers(ddata);
920 if (error)
921 return error;
922
923 error = sysc_ioremap(ddata);
924 if (error)
925 return error;
926
927 error = sysc_check_registers(ddata);
928 if (error)
929 return error;
930
931 return 0;
932 }
933
934 /**
935 * sysc_show_rev - read and show interconnect target module revision
936 * @bufp: buffer to print the information to
937 * @ddata: device driver data
938 */
939 static int sysc_show_rev(char *bufp, struct sysc *ddata)
940 {
941 int len;
942
943 if (ddata->offsets[SYSC_REVISION] < 0)
944 return sprintf(bufp, ":NA");
945
946 len = sprintf(bufp, ":%08x", ddata->revision);
947
948 return len;
949 }
950
951 static int sysc_show_reg(struct sysc *ddata,
952 char *bufp, enum sysc_registers reg)
953 {
954 if (ddata->offsets[reg] < 0)
955 return sprintf(bufp, ":NA");
956
957 return sprintf(bufp, ":%x", ddata->offsets[reg]);
958 }
959
960 static int sysc_show_name(char *bufp, struct sysc *ddata)
961 {
962 if (!ddata->name)
963 return 0;
964
965 return sprintf(bufp, ":%s", ddata->name);
966 }
967
968 /**
969 * sysc_show_registers - show information about interconnect target module
970 * @ddata: device driver data
971 */
972 static void sysc_show_registers(struct sysc *ddata)
973 {
974 char buf[128];
975 char *bufp = buf;
976 int i;
977
978 for (i = 0; i < SYSC_MAX_REGS; i++)
979 bufp += sysc_show_reg(ddata, bufp, i);
980
981 bufp += sysc_show_rev(bufp, ddata);
982 bufp += sysc_show_name(bufp, ddata);
983
984 dev_dbg(ddata->dev, "%llx:%x%s\n",
985 ddata->module_pa, ddata->module_size,
986 buf);
987 }
988
989 /**
990 * sysc_write_sysconfig - handle sysconfig quirks for register write
991 * @ddata: device driver data
992 * @value: register value
993 */
994 static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
995 {
996 if (ddata->module_unlock_quirk)
997 ddata->module_unlock_quirk(ddata);
998
999 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
1000
1001 if (ddata->module_lock_quirk)
1002 ddata->module_lock_quirk(ddata);
1003 }
1004
1005 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
1006 #define SYSC_CLOCACT_ICK 2
1007
1008 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1009 static int sysc_enable_module(struct device *dev)
1010 {
1011 struct sysc *ddata;
1012 const struct sysc_regbits *regbits;
1013 u32 reg, idlemodes, best_mode;
1014 int error;
1015
1016 ddata = dev_get_drvdata(dev);
1017
1018 /*
1019 * Some modules like DSS reset automatically on idle. Enable optional
1020 * reset clocks and wait for OCP softreset to complete.
1021 */
1022 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
1023 error = sysc_enable_opt_clocks(ddata);
1024 if (error) {
1025 dev_err(ddata->dev,
1026 "Optional clocks failed for enable: %i\n",
1027 error);
1028 return error;
1029 }
1030 }
1031 /*
1032 * Some modules like i2c and hdq1w have unusable reset status unless
1033 * the module reset quirk is enabled. Skip status check on enable.
1034 */
1035 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
1036 error = sysc_wait_softreset(ddata);
1037 if (error)
1038 dev_warn(ddata->dev, "OCP softreset timed out\n");
1039 }
1040 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
1041 sysc_disable_opt_clocks(ddata);
1042
1043 /*
1044 * Some subsystem private interconnects, like DSS top level module,
1045 * need only the automatic OCP softreset handling with no sysconfig
1046 * register bits to configure.
1047 */
1048 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1049 return 0;
1050
1051 regbits = ddata->cap->regbits;
1052 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1053
1054 /*
1055 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
1056 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
1057 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
1058 */
1059 if (regbits->clkact_shift >= 0 &&
1060 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
1061 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1062
1063 /* Set SIDLE mode */
1064 idlemodes = ddata->cfg.sidlemodes;
1065 if (!idlemodes || regbits->sidle_shift < 0)
1066 goto set_midle;
1067
1068 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
1069 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1070 best_mode = SYSC_IDLE_NO;
1071 } else {
1072 best_mode = fls(ddata->cfg.sidlemodes) - 1;
1073 if (best_mode > SYSC_IDLE_MASK) {
1074 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1075 return -EINVAL;
1076 }
1077
1078 /* Set WAKEUP */
1079 if (regbits->enwkup_shift >= 0 &&
1080 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1081 reg |= BIT(regbits->enwkup_shift);
1082 }
1083
1084 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1085 reg |= best_mode << regbits->sidle_shift;
1086 sysc_write_sysconfig(ddata, reg);
1087
1088 set_midle:
1089 /* Set MIDLE mode */
1090 idlemodes = ddata->cfg.midlemodes;
1091 if (!idlemodes || regbits->midle_shift < 0)
1092 goto set_autoidle;
1093
1094 best_mode = fls(ddata->cfg.midlemodes) - 1;
1095 if (best_mode > SYSC_IDLE_MASK) {
1096 dev_err(dev, "%s: invalid midlemode\n", __func__);
1097 return -EINVAL;
1098 }
1099
1100 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1101 best_mode = SYSC_IDLE_NO;
1102
1103 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1104 reg |= best_mode << regbits->midle_shift;
1105 sysc_write_sysconfig(ddata, reg);
1106
1107 set_autoidle:
1108 /* Autoidle bit must enabled separately if available */
1109 if (regbits->autoidle_shift >= 0 &&
1110 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1111 reg |= 1 << regbits->autoidle_shift;
1112 sysc_write_sysconfig(ddata, reg);
1113 }
1114
1115 /* Flush posted write */
1116 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1117
1118 if (ddata->module_enable_quirk)
1119 ddata->module_enable_quirk(ddata);
1120
1121 return 0;
1122 }
1123
1124 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1125 {
1126 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1127 *best_mode = SYSC_IDLE_SMART_WKUP;
1128 else if (idlemodes & BIT(SYSC_IDLE_SMART))
1129 *best_mode = SYSC_IDLE_SMART;
1130 else if (idlemodes & BIT(SYSC_IDLE_FORCE))
1131 *best_mode = SYSC_IDLE_FORCE;
1132 else
1133 return -EINVAL;
1134
1135 return 0;
1136 }
1137
1138 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1139 static int sysc_disable_module(struct device *dev)
1140 {
1141 struct sysc *ddata;
1142 const struct sysc_regbits *regbits;
1143 u32 reg, idlemodes, best_mode;
1144 int ret;
1145
1146 ddata = dev_get_drvdata(dev);
1147 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1148 return 0;
1149
1150 if (ddata->module_disable_quirk)
1151 ddata->module_disable_quirk(ddata);
1152
1153 regbits = ddata->cap->regbits;
1154 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1155
1156 /* Set MIDLE mode */
1157 idlemodes = ddata->cfg.midlemodes;
1158 if (!idlemodes || regbits->midle_shift < 0)
1159 goto set_sidle;
1160
1161 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1162 if (ret) {
1163 dev_err(dev, "%s: invalid midlemode\n", __func__);
1164 return ret;
1165 }
1166
1167 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1168 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
1169 best_mode = SYSC_IDLE_FORCE;
1170
1171 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1172 reg |= best_mode << regbits->midle_shift;
1173 sysc_write_sysconfig(ddata, reg);
1174
1175 set_sidle:
1176 /* Set SIDLE mode */
1177 idlemodes = ddata->cfg.sidlemodes;
1178 if (!idlemodes || regbits->sidle_shift < 0)
1179 return 0;
1180
1181 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1182 best_mode = SYSC_IDLE_FORCE;
1183 } else {
1184 ret = sysc_best_idle_mode(idlemodes, &best_mode);
1185 if (ret) {
1186 dev_err(dev, "%s: invalid sidlemode\n", __func__);
1187 return ret;
1188 }
1189 }
1190
1191 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1192 reg |= best_mode << regbits->sidle_shift;
1193 if (regbits->autoidle_shift >= 0 &&
1194 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1195 reg |= 1 << regbits->autoidle_shift;
1196 sysc_write_sysconfig(ddata, reg);
1197
1198 /* Flush posted write */
1199 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1200
1201 return 0;
1202 }
1203
1204 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1205 struct sysc *ddata)
1206 {
1207 struct ti_sysc_platform_data *pdata;
1208 int error;
1209
1210 pdata = dev_get_platdata(ddata->dev);
1211 if (!pdata)
1212 return 0;
1213
1214 if (!pdata->idle_module)
1215 return -ENODEV;
1216
1217 error = pdata->idle_module(dev, &ddata->cookie);
1218 if (error)
1219 dev_err(dev, "%s: could not idle: %i\n",
1220 __func__, error);
1221
1222 reset_control_assert(ddata->rsts);
1223
1224 return 0;
1225 }
1226
1227 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1228 struct sysc *ddata)
1229 {
1230 struct ti_sysc_platform_data *pdata;
1231 int error;
1232
1233 pdata = dev_get_platdata(ddata->dev);
1234 if (!pdata)
1235 return 0;
1236
1237 if (!pdata->enable_module)
1238 return -ENODEV;
1239
1240 error = pdata->enable_module(dev, &ddata->cookie);
1241 if (error)
1242 dev_err(dev, "%s: could not enable: %i\n",
1243 __func__, error);
1244
1245 reset_control_deassert(ddata->rsts);
1246
1247 return 0;
1248 }
1249
1250 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1251 {
1252 struct sysc *ddata;
1253 int error = 0;
1254
1255 ddata = dev_get_drvdata(dev);
1256
1257 if (!ddata->enabled)
1258 return 0;
1259
1260 sysc_clkdm_deny_idle(ddata);
1261
1262 if (ddata->legacy_mode) {
1263 error = sysc_runtime_suspend_legacy(dev, ddata);
1264 if (error)
1265 goto err_allow_idle;
1266 } else {
1267 error = sysc_disable_module(dev);
1268 if (error)
1269 goto err_allow_idle;
1270 }
1271
1272 sysc_disable_main_clocks(ddata);
1273
1274 if (sysc_opt_clks_needed(ddata))
1275 sysc_disable_opt_clocks(ddata);
1276
1277 ddata->enabled = false;
1278
1279 err_allow_idle:
1280 sysc_clkdm_allow_idle(ddata);
1281
1282 reset_control_assert(ddata->rsts);
1283
1284 return error;
1285 }
1286
1287 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1288 {
1289 struct sysc *ddata;
1290 int error = 0;
1291
1292 ddata = dev_get_drvdata(dev);
1293
1294 if (ddata->enabled)
1295 return 0;
1296
1297
1298 sysc_clkdm_deny_idle(ddata);
1299
1300 if (sysc_opt_clks_needed(ddata)) {
1301 error = sysc_enable_opt_clocks(ddata);
1302 if (error)
1303 goto err_allow_idle;
1304 }
1305
1306 error = sysc_enable_main_clocks(ddata);
1307 if (error)
1308 goto err_opt_clocks;
1309
1310 reset_control_deassert(ddata->rsts);
1311
1312 if (ddata->legacy_mode) {
1313 error = sysc_runtime_resume_legacy(dev, ddata);
1314 if (error)
1315 goto err_main_clocks;
1316 } else {
1317 error = sysc_enable_module(dev);
1318 if (error)
1319 goto err_main_clocks;
1320 }
1321
1322 ddata->enabled = true;
1323
1324 sysc_clkdm_allow_idle(ddata);
1325
1326 return 0;
1327
1328 err_main_clocks:
1329 sysc_disable_main_clocks(ddata);
1330 err_opt_clocks:
1331 if (sysc_opt_clks_needed(ddata))
1332 sysc_disable_opt_clocks(ddata);
1333 err_allow_idle:
1334 sysc_clkdm_allow_idle(ddata);
1335
1336 return error;
1337 }
1338
1339 static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled)
1340 {
1341 struct device *dev = ddata->dev;
1342 int error;
1343
1344 /* Disable target module if it is enabled */
1345 if (ddata->enabled) {
1346 error = sysc_runtime_suspend(dev);
1347 if (error)
1348 dev_warn(dev, "reinit suspend failed: %i\n", error);
1349 }
1350
1351 /* Enable target module */
1352 error = sysc_runtime_resume(dev);
1353 if (error)
1354 dev_warn(dev, "reinit resume failed: %i\n", error);
1355
1356 if (leave_enabled)
1357 return error;
1358
1359 /* Disable target module if no leave_enabled was set */
1360 error = sysc_runtime_suspend(dev);
1361 if (error)
1362 dev_warn(dev, "reinit suspend failed: %i\n", error);
1363
1364 return error;
1365 }
1366
1367 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1368 {
1369 struct sysc *ddata;
1370
1371 ddata = dev_get_drvdata(dev);
1372
1373 if (ddata->cfg.quirks &
1374 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1375 return 0;
1376
1377 if (!ddata->enabled)
1378 return 0;
1379
1380 ddata->needs_resume = 1;
1381
1382 return sysc_runtime_suspend(dev);
1383 }
1384
1385 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1386 {
1387 struct sysc *ddata;
1388 int error = 0;
1389
1390 ddata = dev_get_drvdata(dev);
1391
1392 if (ddata->cfg.quirks &
1393 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE))
1394 return 0;
1395
1396 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) {
1397 error = sysc_reinit_module(ddata, ddata->needs_resume);
1398 if (error)
1399 dev_warn(dev, "noirq_resume failed: %i\n", error);
1400 } else if (ddata->needs_resume) {
1401 error = sysc_runtime_resume(dev);
1402 if (error)
1403 dev_warn(dev, "noirq_resume failed: %i\n", error);
1404 }
1405
1406 ddata->needs_resume = 0;
1407
1408 return error;
1409 }
1410
1411 static const struct dev_pm_ops sysc_pm_ops = {
1412 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1413 SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1414 sysc_runtime_resume,
1415 NULL)
1416 };
1417
1418 /* Module revision register based quirks */
1419 struct sysc_revision_quirk {
1420 const char *name;
1421 u32 base;
1422 int rev_offset;
1423 int sysc_offset;
1424 int syss_offset;
1425 u32 revision;
1426 u32 revision_mask;
1427 u32 quirks;
1428 };
1429
1430 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \
1431 optrev_val, optrevmask, optquirkmask) \
1432 { \
1433 .name = (optname), \
1434 .base = (optbase), \
1435 .rev_offset = (optrev), \
1436 .sysc_offset = (optsysc), \
1437 .syss_offset = (optsyss), \
1438 .revision = (optrev_val), \
1439 .revision_mask = (optrevmask), \
1440 .quirks = (optquirkmask), \
1441 }
1442
1443 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1444 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1445 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1446 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1447 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1448 SYSC_QUIRK_LEGACY_IDLE),
1449 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1450 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1451 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1452 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1453 /* Uarts on omap4 and later */
1454 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1455 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1456 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1457 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1458
1459 /* Quirks that need to be set based on the module address */
1460 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
1461 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1462 SYSC_QUIRK_SWSUP_SIDLE),
1463
1464 /* Quirks that need to be set based on detected module */
1465 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
1466 SYSC_MODULE_QUIRK_AESS),
1467 /* Errata i893 handling for dra7 dcan1 and 2 */
1468 SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1469 SYSC_QUIRK_CLKDM_NOAUTO),
1470 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1471 SYSC_QUIRK_CLKDM_NOAUTO),
1472 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1473 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1474 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
1475 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1476 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
1477 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1478 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1479 SYSC_QUIRK_CLKDM_NOAUTO),
1480 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1481 SYSC_QUIRK_CLKDM_NOAUTO),
1482 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff,
1483 SYSC_QUIRK_GPMC_DEBUG),
1484 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1485 SYSC_QUIRK_OPT_CLKS_NEEDED),
1486 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1487 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1488 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1489 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1490 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1491 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1492 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1493 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1494 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1495 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1496 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1497 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1498 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1499 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
1500 SYSC_MODULE_QUIRK_SGX),
1501 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
1502 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1503 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff,
1504 SYSC_QUIRK_SWSUP_SIDLE),
1505 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1506 SYSC_MODULE_QUIRK_RTC_UNLOCK),
1507 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1508 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1509 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1510 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1511 SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff,
1512 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1513 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1514 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1515 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1516 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1517 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1518 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1519 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1520 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1521 SYSC_QUIRK_REINIT_ON_RESUME),
1522 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1523 SYSC_MODULE_QUIRK_WDT),
1524 /* PRUSS on am3, am4 and am5 */
1525 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
1526 SYSC_MODULE_QUIRK_PRUSS),
1527 /* Watchdog on am3 and am4 */
1528 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1529 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1530
1531 #ifdef DEBUG
1532 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1533 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1534 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1535 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1536 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1537 0xffff00f0, 0),
1538 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1539 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
1540 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1541 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1542 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
1543 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
1544 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1545 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1546 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1547 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1548 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
1549 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1550 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1551 SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1552 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0),
1553 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0),
1554 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1555 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1556 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
1557 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
1558 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1559 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
1560 SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1561 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1562 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1563 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1564 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1565 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1566 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
1567 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1568 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1569 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1570 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
1571 SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1572 SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1573 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1574 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1575 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
1576 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1577 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1578 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1579 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1580 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1581 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1582 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1583 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1584 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1585 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1586 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1587 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1588 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0),
1589 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0),
1590 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1591 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1592 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1593 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1594 /* Some timers on omap4 and later */
1595 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
1596 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
1597 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
1598 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
1599 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
1600 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
1601 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1602 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1603 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
1604 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
1605 #endif
1606 };
1607
1608 /*
1609 * Early quirks based on module base and register offsets only that are
1610 * needed before the module revision can be read
1611 */
1612 static void sysc_init_early_quirks(struct sysc *ddata)
1613 {
1614 const struct sysc_revision_quirk *q;
1615 int i;
1616
1617 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1618 q = &sysc_revision_quirks[i];
1619
1620 if (!q->base)
1621 continue;
1622
1623 if (q->base != ddata->module_pa)
1624 continue;
1625
1626 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1627 continue;
1628
1629 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1630 continue;
1631
1632 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1633 continue;
1634
1635 ddata->name = q->name;
1636 ddata->cfg.quirks |= q->quirks;
1637 }
1638 }
1639
1640 /* Quirks that also consider the revision register value */
1641 static void sysc_init_revision_quirks(struct sysc *ddata)
1642 {
1643 const struct sysc_revision_quirk *q;
1644 int i;
1645
1646 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1647 q = &sysc_revision_quirks[i];
1648
1649 if (q->base && q->base != ddata->module_pa)
1650 continue;
1651
1652 if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1653 continue;
1654
1655 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1656 continue;
1657
1658 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1659 continue;
1660
1661 if (q->revision == ddata->revision ||
1662 (q->revision & q->revision_mask) ==
1663 (ddata->revision & q->revision_mask)) {
1664 ddata->name = q->name;
1665 ddata->cfg.quirks |= q->quirks;
1666 }
1667 }
1668 }
1669
1670 /*
1671 * DSS needs dispc outputs disabled to reset modules. Returns mask of
1672 * enabled DSS interrupts. Eventually we may be able to do this on
1673 * dispc init rather than top-level DSS init.
1674 */
1675 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
1676 bool disable)
1677 {
1678 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
1679 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
1680 int manager_count;
1681 bool framedonetv_irq = true;
1682 u32 val, irq_mask = 0;
1683
1684 switch (sysc_soc->soc) {
1685 case SOC_2420 ... SOC_3630:
1686 manager_count = 2;
1687 framedonetv_irq = false;
1688 break;
1689 case SOC_4430 ... SOC_4470:
1690 manager_count = 3;
1691 break;
1692 case SOC_5430:
1693 case SOC_DRA7:
1694 manager_count = 4;
1695 break;
1696 case SOC_AM4:
1697 manager_count = 1;
1698 framedonetv_irq = false;
1699 break;
1700 case SOC_UNKNOWN:
1701 default:
1702 return 0;
1703 }
1704
1705 /* Remap the whole module range to be able to reset dispc outputs */
1706 devm_iounmap(ddata->dev, ddata->module_va);
1707 ddata->module_va = devm_ioremap(ddata->dev,
1708 ddata->module_pa,
1709 ddata->module_size);
1710 if (!ddata->module_va)
1711 return -EIO;
1712
1713 /* DISP_CONTROL */
1714 val = sysc_read(ddata, dispc_offset + 0x40);
1715 lcd_en = val & lcd_en_mask;
1716 digit_en = val & digit_en_mask;
1717 if (lcd_en)
1718 irq_mask |= BIT(0); /* FRAMEDONE */
1719 if (digit_en) {
1720 if (framedonetv_irq)
1721 irq_mask |= BIT(24); /* FRAMEDONETV */
1722 else
1723 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */
1724 }
1725 if (disable & (lcd_en | digit_en))
1726 sysc_write(ddata, dispc_offset + 0x40,
1727 val & ~(lcd_en_mask | digit_en_mask));
1728
1729 if (manager_count <= 2)
1730 return irq_mask;
1731
1732 /* DISPC_CONTROL2 */
1733 val = sysc_read(ddata, dispc_offset + 0x238);
1734 lcd2_en = val & lcd_en_mask;
1735 if (lcd2_en)
1736 irq_mask |= BIT(22); /* FRAMEDONE2 */
1737 if (disable && lcd2_en)
1738 sysc_write(ddata, dispc_offset + 0x238,
1739 val & ~lcd_en_mask);
1740
1741 if (manager_count <= 3)
1742 return irq_mask;
1743
1744 /* DISPC_CONTROL3 */
1745 val = sysc_read(ddata, dispc_offset + 0x848);
1746 lcd3_en = val & lcd_en_mask;
1747 if (lcd3_en)
1748 irq_mask |= BIT(30); /* FRAMEDONE3 */
1749 if (disable && lcd3_en)
1750 sysc_write(ddata, dispc_offset + 0x848,
1751 val & ~lcd_en_mask);
1752
1753 return irq_mask;
1754 }
1755
1756 /* DSS needs child outputs disabled and SDI registers cleared for reset */
1757 static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
1758 {
1759 const int dispc_offset = 0x1000;
1760 int error;
1761 u32 irq_mask, val;
1762
1763 /* Get enabled outputs */
1764 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
1765 if (!irq_mask)
1766 return;
1767
1768 /* Clear IRQSTATUS */
1769 sysc_write(ddata, dispc_offset + 0x18, irq_mask);
1770
1771 /* Disable outputs */
1772 val = sysc_quirk_dispc(ddata, dispc_offset, true);
1773
1774 /* Poll IRQSTATUS */
1775 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
1776 val, val != irq_mask, 100, 50);
1777 if (error)
1778 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
1779 __func__, val, irq_mask);
1780
1781 if (sysc_soc->soc == SOC_3430) {
1782 /* Clear DSS_SDI_CONTROL */
1783 sysc_write(ddata, 0x44, 0);
1784
1785 /* Clear DSS_PLL_CONTROL */
1786 sysc_write(ddata, 0x48, 0);
1787 }
1788
1789 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
1790 sysc_write(ddata, 0x40, 0);
1791 }
1792
1793 /* 1-wire needs module's internal clocks enabled for reset */
1794 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1795 {
1796 int offset = 0x0c; /* HDQ_CTRL_STATUS */
1797 u16 val;
1798
1799 val = sysc_read(ddata, offset);
1800 val |= BIT(5);
1801 sysc_write(ddata, offset, val);
1802 }
1803
1804 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
1805 static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1806 {
1807 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
1808
1809 sysc_write(ddata, offset, 1);
1810 }
1811
1812 /* I2C needs to be disabled for reset */
1813 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1814 {
1815 int offset;
1816 u16 val;
1817
1818 /* I2C_CON, omap2/3 is different from omap4 and later */
1819 if ((ddata->revision & 0xffffff00) == 0x001f0000)
1820 offset = 0x24;
1821 else
1822 offset = 0xa4;
1823
1824 /* I2C_EN */
1825 val = sysc_read(ddata, offset);
1826 if (enable)
1827 val |= BIT(15);
1828 else
1829 val &= ~BIT(15);
1830 sysc_write(ddata, offset, val);
1831 }
1832
1833 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
1834 {
1835 sysc_clk_quirk_i2c(ddata, false);
1836 }
1837
1838 static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
1839 {
1840 sysc_clk_quirk_i2c(ddata, true);
1841 }
1842
1843 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
1844 static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1845 {
1846 u32 val, kick0_val = 0, kick1_val = 0;
1847 unsigned long flags;
1848 int error;
1849
1850 if (!lock) {
1851 kick0_val = 0x83e70b13;
1852 kick1_val = 0x95a4f1e0;
1853 }
1854
1855 local_irq_save(flags);
1856 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
1857 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1858 !(val & BIT(0)), 100, 50);
1859 if (error)
1860 dev_warn(ddata->dev, "rtc busy timeout\n");
1861 /* Now we have ~15 microseconds to read/write various registers */
1862 sysc_write(ddata, 0x6c, kick0_val);
1863 sysc_write(ddata, 0x70, kick1_val);
1864 local_irq_restore(flags);
1865 }
1866
1867 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1868 {
1869 sysc_quirk_rtc(ddata, false);
1870 }
1871
1872 static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1873 {
1874 sysc_quirk_rtc(ddata, true);
1875 }
1876
1877 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1878 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1879 {
1880 int offset = 0xff08; /* OCP_DEBUG_CONFIG */
1881 u32 val = BIT(31); /* THALIA_INT_BYPASS */
1882
1883 sysc_write(ddata, offset, val);
1884 }
1885
1886 /* Watchdog timer needs a disable sequence after reset */
1887 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1888 {
1889 int wps, spr, error;
1890 u32 val;
1891
1892 wps = 0x34;
1893 spr = 0x48;
1894
1895 sysc_write(ddata, spr, 0xaaaa);
1896 error = readl_poll_timeout(ddata->module_va + wps, val,
1897 !(val & 0x10), 100,
1898 MAX_MODULE_SOFTRESET_WAIT);
1899 if (error)
1900 dev_warn(ddata->dev, "wdt disable step1 failed\n");
1901
1902 sysc_write(ddata, spr, 0x5555);
1903 error = readl_poll_timeout(ddata->module_va + wps, val,
1904 !(val & 0x10), 100,
1905 MAX_MODULE_SOFTRESET_WAIT);
1906 if (error)
1907 dev_warn(ddata->dev, "wdt disable step2 failed\n");
1908 }
1909
1910 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
1911 static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
1912 {
1913 u32 reg;
1914
1915 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1916 reg |= SYSC_PRUSS_STANDBY_INIT;
1917 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1918 }
1919
1920 static void sysc_init_module_quirks(struct sysc *ddata)
1921 {
1922 if (ddata->legacy_mode || !ddata->name)
1923 return;
1924
1925 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1926 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
1927
1928 return;
1929 }
1930
1931 #ifdef CONFIG_OMAP_GPMC_DEBUG
1932 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) {
1933 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT;
1934
1935 return;
1936 }
1937 #endif
1938
1939 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1940 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
1941 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
1942
1943 return;
1944 }
1945
1946 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
1947 ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
1948
1949 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
1950 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
1951
1952 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
1953 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
1954 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
1955
1956 return;
1957 }
1958
1959 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1960 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1961
1962 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
1963 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
1964 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1965 }
1966
1967 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
1968 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
1969 }
1970
1971 static int sysc_clockdomain_init(struct sysc *ddata)
1972 {
1973 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1974 struct clk *fck = NULL, *ick = NULL;
1975 int error;
1976
1977 if (!pdata || !pdata->init_clockdomain)
1978 return 0;
1979
1980 switch (ddata->nr_clocks) {
1981 case 2:
1982 ick = ddata->clocks[SYSC_ICK];
1983 fallthrough;
1984 case 1:
1985 fck = ddata->clocks[SYSC_FCK];
1986 break;
1987 case 0:
1988 return 0;
1989 }
1990
1991 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1992 if (!error || error == -ENODEV)
1993 return 0;
1994
1995 return error;
1996 }
1997
1998 /*
1999 * Note that pdata->init_module() typically does a reset first. After
2000 * pdata->init_module() is done, PM runtime can be used for the interconnect
2001 * target module.
2002 */
2003 static int sysc_legacy_init(struct sysc *ddata)
2004 {
2005 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2006 int error;
2007
2008 if (!pdata || !pdata->init_module)
2009 return 0;
2010
2011 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
2012 if (error == -EEXIST)
2013 error = 0;
2014
2015 return error;
2016 }
2017
2018 /*
2019 * Note that the caller must ensure the interconnect target module is enabled
2020 * before calling reset. Otherwise reset will not complete.
2021 */
2022 static int sysc_reset(struct sysc *ddata)
2023 {
2024 int sysc_offset, sysc_val, error;
2025 u32 sysc_mask;
2026
2027 sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
2028
2029 if (ddata->legacy_mode ||
2030 ddata->cap->regbits->srst_shift < 0 ||
2031 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
2032 return 0;
2033
2034 sysc_mask = BIT(ddata->cap->regbits->srst_shift);
2035
2036 if (ddata->pre_reset_quirk)
2037 ddata->pre_reset_quirk(ddata);
2038
2039 if (sysc_offset >= 0) {
2040 sysc_val = sysc_read_sysconfig(ddata);
2041 sysc_val |= sysc_mask;
2042 sysc_write(ddata, sysc_offset, sysc_val);
2043 }
2044
2045 if (ddata->cfg.srst_udelay)
2046 usleep_range(ddata->cfg.srst_udelay,
2047 ddata->cfg.srst_udelay * 2);
2048
2049 if (ddata->post_reset_quirk)
2050 ddata->post_reset_quirk(ddata);
2051
2052 error = sysc_wait_softreset(ddata);
2053 if (error)
2054 dev_warn(ddata->dev, "OCP softreset timed out\n");
2055
2056 if (ddata->reset_done_quirk)
2057 ddata->reset_done_quirk(ddata);
2058
2059 return error;
2060 }
2061
2062 /*
2063 * At this point the module is configured enough to read the revision but
2064 * module may not be completely configured yet to use PM runtime. Enable
2065 * all clocks directly during init to configure the quirks needed for PM
2066 * runtime based on the revision register.
2067 */
2068 static int sysc_init_module(struct sysc *ddata)
2069 {
2070 bool rstctrl_deasserted = false;
2071 int error = 0;
2072
2073 error = sysc_clockdomain_init(ddata);
2074 if (error)
2075 return error;
2076
2077 sysc_clkdm_deny_idle(ddata);
2078
2079 /*
2080 * Always enable clocks. The bootloader may or may not have enabled
2081 * the related clocks.
2082 */
2083 error = sysc_enable_opt_clocks(ddata);
2084 if (error)
2085 return error;
2086
2087 error = sysc_enable_main_clocks(ddata);
2088 if (error)
2089 goto err_opt_clocks;
2090
2091 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
2092 error = reset_control_deassert(ddata->rsts);
2093 if (error)
2094 goto err_main_clocks;
2095 rstctrl_deasserted = true;
2096 }
2097
2098 ddata->revision = sysc_read_revision(ddata);
2099 sysc_init_revision_quirks(ddata);
2100 sysc_init_module_quirks(ddata);
2101
2102 if (ddata->legacy_mode) {
2103 error = sysc_legacy_init(ddata);
2104 if (error)
2105 goto err_main_clocks;
2106 }
2107
2108 if (!ddata->legacy_mode) {
2109 error = sysc_enable_module(ddata->dev);
2110 if (error)
2111 goto err_main_clocks;
2112 }
2113
2114 error = sysc_reset(ddata);
2115 if (error)
2116 dev_err(ddata->dev, "Reset failed with %d\n", error);
2117
2118 if (error && !ddata->legacy_mode)
2119 sysc_disable_module(ddata->dev);
2120
2121 err_main_clocks:
2122 if (error)
2123 sysc_disable_main_clocks(ddata);
2124 err_opt_clocks:
2125 /* No re-enable of clockdomain autoidle to prevent module autoidle */
2126 if (error) {
2127 sysc_disable_opt_clocks(ddata);
2128 sysc_clkdm_allow_idle(ddata);
2129 }
2130
2131 if (error && rstctrl_deasserted &&
2132 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2133 reset_control_assert(ddata->rsts);
2134
2135 return error;
2136 }
2137
2138 static int sysc_init_sysc_mask(struct sysc *ddata)
2139 {
2140 struct device_node *np = ddata->dev->of_node;
2141 int error;
2142 u32 val;
2143
2144 error = of_property_read_u32(np, "ti,sysc-mask", &val);
2145 if (error)
2146 return 0;
2147
2148 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
2149
2150 return 0;
2151 }
2152
2153 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
2154 const char *name)
2155 {
2156 struct device_node *np = ddata->dev->of_node;
2157 struct property *prop;
2158 const __be32 *p;
2159 u32 val;
2160
2161 of_property_for_each_u32(np, name, prop, p, val) {
2162 if (val >= SYSC_NR_IDLEMODES) {
2163 dev_err(ddata->dev, "invalid idlemode: %i\n", val);
2164 return -EINVAL;
2165 }
2166 *idlemodes |= (1 << val);
2167 }
2168
2169 return 0;
2170 }
2171
2172 static int sysc_init_idlemodes(struct sysc *ddata)
2173 {
2174 int error;
2175
2176 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
2177 "ti,sysc-midle");
2178 if (error)
2179 return error;
2180
2181 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
2182 "ti,sysc-sidle");
2183 if (error)
2184 return error;
2185
2186 return 0;
2187 }
2188
2189 /*
2190 * Only some devices on omap4 and later have SYSCONFIG reset done
2191 * bit. We can detect this if there is no SYSSTATUS at all, or the
2192 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
2193 * have multiple bits for the child devices like OHCI and EHCI.
2194 * Depends on SYSC being parsed first.
2195 */
2196 static int sysc_init_syss_mask(struct sysc *ddata)
2197 {
2198 struct device_node *np = ddata->dev->of_node;
2199 int error;
2200 u32 val;
2201
2202 error = of_property_read_u32(np, "ti,syss-mask", &val);
2203 if (error) {
2204 if ((ddata->cap->type == TI_SYSC_OMAP4 ||
2205 ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
2206 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2207 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2208
2209 return 0;
2210 }
2211
2212 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2213 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2214
2215 ddata->cfg.syss_mask = val;
2216
2217 return 0;
2218 }
2219
2220 /*
2221 * Many child device drivers need to have fck and opt clocks available
2222 * to get the clock rate for device internal configuration etc.
2223 */
2224 static int sysc_child_add_named_clock(struct sysc *ddata,
2225 struct device *child,
2226 const char *name)
2227 {
2228 struct clk *clk;
2229 struct clk_lookup *l;
2230 int error = 0;
2231
2232 if (!name)
2233 return 0;
2234
2235 clk = clk_get(child, name);
2236 if (!IS_ERR(clk)) {
2237 error = -EEXIST;
2238 goto put_clk;
2239 }
2240
2241 clk = clk_get(ddata->dev, name);
2242 if (IS_ERR(clk))
2243 return -ENODEV;
2244
2245 l = clkdev_create(clk, name, dev_name(child));
2246 if (!l)
2247 error = -ENOMEM;
2248 put_clk:
2249 clk_put(clk);
2250
2251 return error;
2252 }
2253
2254 static int sysc_child_add_clocks(struct sysc *ddata,
2255 struct device *child)
2256 {
2257 int i, error;
2258
2259 for (i = 0; i < ddata->nr_clocks; i++) {
2260 error = sysc_child_add_named_clock(ddata,
2261 child,
2262 ddata->clock_roles[i]);
2263 if (error && error != -EEXIST) {
2264 dev_err(ddata->dev, "could not add child clock %s: %i\n",
2265 ddata->clock_roles[i], error);
2266
2267 return error;
2268 }
2269 }
2270
2271 return 0;
2272 }
2273
2274 static struct device_type sysc_device_type = {
2275 };
2276
2277 static struct sysc *sysc_child_to_parent(struct device *dev)
2278 {
2279 struct device *parent = dev->parent;
2280
2281 if (!parent || parent->type != &sysc_device_type)
2282 return NULL;
2283
2284 return dev_get_drvdata(parent);
2285 }
2286
2287 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2288 {
2289 struct sysc *ddata;
2290 int error;
2291
2292 ddata = sysc_child_to_parent(dev);
2293
2294 error = pm_generic_runtime_suspend(dev);
2295 if (error)
2296 return error;
2297
2298 if (!ddata->enabled)
2299 return 0;
2300
2301 return sysc_runtime_suspend(ddata->dev);
2302 }
2303
2304 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2305 {
2306 struct sysc *ddata;
2307 int error;
2308
2309 ddata = sysc_child_to_parent(dev);
2310
2311 if (!ddata->enabled) {
2312 error = sysc_runtime_resume(ddata->dev);
2313 if (error < 0)
2314 dev_err(ddata->dev,
2315 "%s error: %i\n", __func__, error);
2316 }
2317
2318 return pm_generic_runtime_resume(dev);
2319 }
2320
2321 #ifdef CONFIG_PM_SLEEP
2322 static int sysc_child_suspend_noirq(struct device *dev)
2323 {
2324 struct sysc *ddata;
2325 int error;
2326
2327 ddata = sysc_child_to_parent(dev);
2328
2329 dev_dbg(ddata->dev, "%s %s\n", __func__,
2330 ddata->name ? ddata->name : "");
2331
2332 error = pm_generic_suspend_noirq(dev);
2333 if (error) {
2334 dev_err(dev, "%s error at %i: %i\n",
2335 __func__, __LINE__, error);
2336
2337 return error;
2338 }
2339
2340 if (!pm_runtime_status_suspended(dev)) {
2341 error = pm_generic_runtime_suspend(dev);
2342 if (error) {
2343 dev_dbg(dev, "%s busy at %i: %i\n",
2344 __func__, __LINE__, error);
2345
2346 return 0;
2347 }
2348
2349 error = sysc_runtime_suspend(ddata->dev);
2350 if (error) {
2351 dev_err(dev, "%s error at %i: %i\n",
2352 __func__, __LINE__, error);
2353
2354 return error;
2355 }
2356
2357 ddata->child_needs_resume = true;
2358 }
2359
2360 return 0;
2361 }
2362
2363 static int sysc_child_resume_noirq(struct device *dev)
2364 {
2365 struct sysc *ddata;
2366 int error;
2367
2368 ddata = sysc_child_to_parent(dev);
2369
2370 dev_dbg(ddata->dev, "%s %s\n", __func__,
2371 ddata->name ? ddata->name : "");
2372
2373 if (ddata->child_needs_resume) {
2374 ddata->child_needs_resume = false;
2375
2376 error = sysc_runtime_resume(ddata->dev);
2377 if (error)
2378 dev_err(ddata->dev,
2379 "%s runtime resume error: %i\n",
2380 __func__, error);
2381
2382 error = pm_generic_runtime_resume(dev);
2383 if (error)
2384 dev_err(ddata->dev,
2385 "%s generic runtime resume: %i\n",
2386 __func__, error);
2387 }
2388
2389 return pm_generic_resume_noirq(dev);
2390 }
2391 #endif
2392
2393 static struct dev_pm_domain sysc_child_pm_domain = {
2394 .ops = {
2395 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
2396 sysc_child_runtime_resume,
2397 NULL)
2398 USE_PLATFORM_PM_SLEEP_OPS
2399 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
2400 sysc_child_resume_noirq)
2401 }
2402 };
2403
2404 /**
2405 * sysc_legacy_idle_quirk - handle children in omap_device compatible way
2406 * @ddata: device driver data
2407 * @child: child device driver
2408 *
2409 * Allow idle for child devices as done with _od_runtime_suspend().
2410 * Otherwise many child devices will not idle because of the permanent
2411 * parent usecount set in pm_runtime_irq_safe().
2412 *
2413 * Note that the long term solution is to just modify the child device
2414 * drivers to not set pm_runtime_irq_safe() and then this can be just
2415 * dropped.
2416 */
2417 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
2418 {
2419 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
2420 dev_pm_domain_set(child, &sysc_child_pm_domain);
2421 }
2422
2423 static int sysc_notifier_call(struct notifier_block *nb,
2424 unsigned long event, void *device)
2425 {
2426 struct device *dev = device;
2427 struct sysc *ddata;
2428 int error;
2429
2430 ddata = sysc_child_to_parent(dev);
2431 if (!ddata)
2432 return NOTIFY_DONE;
2433
2434 switch (event) {
2435 case BUS_NOTIFY_ADD_DEVICE:
2436 error = sysc_child_add_clocks(ddata, dev);
2437 if (error)
2438 return error;
2439 sysc_legacy_idle_quirk(ddata, dev);
2440 break;
2441 default:
2442 break;
2443 }
2444
2445 return NOTIFY_DONE;
2446 }
2447
2448 static struct notifier_block sysc_nb = {
2449 .notifier_call = sysc_notifier_call,
2450 };
2451
2452 /* Device tree configured quirks */
2453 struct sysc_dts_quirk {
2454 const char *name;
2455 u32 mask;
2456 };
2457
2458 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2459 { .name = "ti,no-idle-on-init",
2460 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2461 { .name = "ti,no-reset-on-init",
2462 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2463 { .name = "ti,no-idle",
2464 .mask = SYSC_QUIRK_NO_IDLE, },
2465 };
2466
2467 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2468 bool is_child)
2469 {
2470 const struct property *prop;
2471 int i, len;
2472
2473 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2474 const char *name = sysc_dts_quirks[i].name;
2475
2476 prop = of_get_property(np, name, &len);
2477 if (!prop)
2478 continue;
2479
2480 ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2481 if (is_child) {
2482 dev_warn(ddata->dev,
2483 "dts flag should be at module level for %s\n",
2484 name);
2485 }
2486 }
2487 }
2488
2489 static int sysc_init_dts_quirks(struct sysc *ddata)
2490 {
2491 struct device_node *np = ddata->dev->of_node;
2492 int error;
2493 u32 val;
2494
2495 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2496
2497 sysc_parse_dts_quirks(ddata, np, false);
2498 error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2499 if (!error) {
2500 if (val > 255) {
2501 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2502 val);
2503 }
2504
2505 ddata->cfg.srst_udelay = (u8)val;
2506 }
2507
2508 return 0;
2509 }
2510
2511 static void sysc_unprepare(struct sysc *ddata)
2512 {
2513 int i;
2514
2515 if (!ddata->clocks)
2516 return;
2517
2518 for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2519 if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2520 clk_unprepare(ddata->clocks[i]);
2521 }
2522 }
2523
2524 /*
2525 * Common sysc register bits found on omap2, also known as type1
2526 */
2527 static const struct sysc_regbits sysc_regbits_omap2 = {
2528 .dmadisable_shift = -ENODEV,
2529 .midle_shift = 12,
2530 .sidle_shift = 3,
2531 .clkact_shift = 8,
2532 .emufree_shift = 5,
2533 .enwkup_shift = 2,
2534 .srst_shift = 1,
2535 .autoidle_shift = 0,
2536 };
2537
2538 static const struct sysc_capabilities sysc_omap2 = {
2539 .type = TI_SYSC_OMAP2,
2540 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2541 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2542 SYSC_OMAP2_AUTOIDLE,
2543 .regbits = &sysc_regbits_omap2,
2544 };
2545
2546 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2547 static const struct sysc_capabilities sysc_omap2_timer = {
2548 .type = TI_SYSC_OMAP2_TIMER,
2549 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2550 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2551 SYSC_OMAP2_AUTOIDLE,
2552 .regbits = &sysc_regbits_omap2,
2553 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2554 };
2555
2556 /*
2557 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2558 * with different sidle position
2559 */
2560 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2561 .dmadisable_shift = -ENODEV,
2562 .midle_shift = -ENODEV,
2563 .sidle_shift = 4,
2564 .clkact_shift = -ENODEV,
2565 .enwkup_shift = -ENODEV,
2566 .srst_shift = 1,
2567 .autoidle_shift = 0,
2568 .emufree_shift = -ENODEV,
2569 };
2570
2571 static const struct sysc_capabilities sysc_omap3_sham = {
2572 .type = TI_SYSC_OMAP3_SHAM,
2573 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2574 .regbits = &sysc_regbits_omap3_sham,
2575 };
2576
2577 /*
2578 * AES register bits found on omap3 and later, a variant of
2579 * sysc_regbits_omap2 with different sidle position
2580 */
2581 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2582 .dmadisable_shift = -ENODEV,
2583 .midle_shift = -ENODEV,
2584 .sidle_shift = 6,
2585 .clkact_shift = -ENODEV,
2586 .enwkup_shift = -ENODEV,
2587 .srst_shift = 1,
2588 .autoidle_shift = 0,
2589 .emufree_shift = -ENODEV,
2590 };
2591
2592 static const struct sysc_capabilities sysc_omap3_aes = {
2593 .type = TI_SYSC_OMAP3_AES,
2594 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2595 .regbits = &sysc_regbits_omap3_aes,
2596 };
2597
2598 /*
2599 * Common sysc register bits found on omap4, also known as type2
2600 */
2601 static const struct sysc_regbits sysc_regbits_omap4 = {
2602 .dmadisable_shift = 16,
2603 .midle_shift = 4,
2604 .sidle_shift = 2,
2605 .clkact_shift = -ENODEV,
2606 .enwkup_shift = -ENODEV,
2607 .emufree_shift = 1,
2608 .srst_shift = 0,
2609 .autoidle_shift = -ENODEV,
2610 };
2611
2612 static const struct sysc_capabilities sysc_omap4 = {
2613 .type = TI_SYSC_OMAP4,
2614 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2615 SYSC_OMAP4_SOFTRESET,
2616 .regbits = &sysc_regbits_omap4,
2617 };
2618
2619 static const struct sysc_capabilities sysc_omap4_timer = {
2620 .type = TI_SYSC_OMAP4_TIMER,
2621 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2622 SYSC_OMAP4_SOFTRESET,
2623 .regbits = &sysc_regbits_omap4,
2624 };
2625
2626 /*
2627 * Common sysc register bits found on omap4, also known as type3
2628 */
2629 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2630 .dmadisable_shift = -ENODEV,
2631 .midle_shift = 2,
2632 .sidle_shift = 0,
2633 .clkact_shift = -ENODEV,
2634 .enwkup_shift = -ENODEV,
2635 .srst_shift = -ENODEV,
2636 .emufree_shift = -ENODEV,
2637 .autoidle_shift = -ENODEV,
2638 };
2639
2640 static const struct sysc_capabilities sysc_omap4_simple = {
2641 .type = TI_SYSC_OMAP4_SIMPLE,
2642 .regbits = &sysc_regbits_omap4_simple,
2643 };
2644
2645 /*
2646 * SmartReflex sysc found on omap34xx
2647 */
2648 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2649 .dmadisable_shift = -ENODEV,
2650 .midle_shift = -ENODEV,
2651 .sidle_shift = -ENODEV,
2652 .clkact_shift = 20,
2653 .enwkup_shift = -ENODEV,
2654 .srst_shift = -ENODEV,
2655 .emufree_shift = -ENODEV,
2656 .autoidle_shift = -ENODEV,
2657 };
2658
2659 static const struct sysc_capabilities sysc_34xx_sr = {
2660 .type = TI_SYSC_OMAP34XX_SR,
2661 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2662 .regbits = &sysc_regbits_omap34xx_sr,
2663 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2664 SYSC_QUIRK_LEGACY_IDLE,
2665 };
2666
2667 /*
2668 * SmartReflex sysc found on omap36xx and later
2669 */
2670 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2671 .dmadisable_shift = -ENODEV,
2672 .midle_shift = -ENODEV,
2673 .sidle_shift = 24,
2674 .clkact_shift = -ENODEV,
2675 .enwkup_shift = 26,
2676 .srst_shift = -ENODEV,
2677 .emufree_shift = -ENODEV,
2678 .autoidle_shift = -ENODEV,
2679 };
2680
2681 static const struct sysc_capabilities sysc_36xx_sr = {
2682 .type = TI_SYSC_OMAP36XX_SR,
2683 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2684 .regbits = &sysc_regbits_omap36xx_sr,
2685 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2686 };
2687
2688 static const struct sysc_capabilities sysc_omap4_sr = {
2689 .type = TI_SYSC_OMAP4_SR,
2690 .regbits = &sysc_regbits_omap36xx_sr,
2691 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2692 };
2693
2694 /*
2695 * McASP register bits found on omap4 and later
2696 */
2697 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2698 .dmadisable_shift = -ENODEV,
2699 .midle_shift = -ENODEV,
2700 .sidle_shift = 0,
2701 .clkact_shift = -ENODEV,
2702 .enwkup_shift = -ENODEV,
2703 .srst_shift = -ENODEV,
2704 .emufree_shift = -ENODEV,
2705 .autoidle_shift = -ENODEV,
2706 };
2707
2708 static const struct sysc_capabilities sysc_omap4_mcasp = {
2709 .type = TI_SYSC_OMAP4_MCASP,
2710 .regbits = &sysc_regbits_omap4_mcasp,
2711 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2712 };
2713
2714 /*
2715 * McASP found on dra7 and later
2716 */
2717 static const struct sysc_capabilities sysc_dra7_mcasp = {
2718 .type = TI_SYSC_OMAP4_SIMPLE,
2719 .regbits = &sysc_regbits_omap4_simple,
2720 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2721 };
2722
2723 /*
2724 * FS USB host found on omap4 and later
2725 */
2726 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2727 .dmadisable_shift = -ENODEV,
2728 .midle_shift = -ENODEV,
2729 .sidle_shift = 24,
2730 .clkact_shift = -ENODEV,
2731 .enwkup_shift = 26,
2732 .srst_shift = -ENODEV,
2733 .emufree_shift = -ENODEV,
2734 .autoidle_shift = -ENODEV,
2735 };
2736
2737 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2738 .type = TI_SYSC_OMAP4_USB_HOST_FS,
2739 .sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2740 .regbits = &sysc_regbits_omap4_usb_host_fs,
2741 };
2742
2743 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2744 .dmadisable_shift = -ENODEV,
2745 .midle_shift = -ENODEV,
2746 .sidle_shift = -ENODEV,
2747 .clkact_shift = -ENODEV,
2748 .enwkup_shift = 4,
2749 .srst_shift = 0,
2750 .emufree_shift = -ENODEV,
2751 .autoidle_shift = -ENODEV,
2752 };
2753
2754 static const struct sysc_capabilities sysc_dra7_mcan = {
2755 .type = TI_SYSC_DRA7_MCAN,
2756 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2757 .regbits = &sysc_regbits_dra7_mcan,
2758 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2759 };
2760
2761 /*
2762 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
2763 */
2764 static const struct sysc_capabilities sysc_pruss = {
2765 .type = TI_SYSC_PRUSS,
2766 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
2767 .regbits = &sysc_regbits_omap4_simple,
2768 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
2769 };
2770
2771 static int sysc_init_pdata(struct sysc *ddata)
2772 {
2773 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2774 struct ti_sysc_module_data *mdata;
2775
2776 if (!pdata)
2777 return 0;
2778
2779 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2780 if (!mdata)
2781 return -ENOMEM;
2782
2783 if (ddata->legacy_mode) {
2784 mdata->name = ddata->legacy_mode;
2785 mdata->module_pa = ddata->module_pa;
2786 mdata->module_size = ddata->module_size;
2787 mdata->offsets = ddata->offsets;
2788 mdata->nr_offsets = SYSC_MAX_REGS;
2789 mdata->cap = ddata->cap;
2790 mdata->cfg = &ddata->cfg;
2791 }
2792
2793 ddata->mdata = mdata;
2794
2795 return 0;
2796 }
2797
2798 static int sysc_init_match(struct sysc *ddata)
2799 {
2800 const struct sysc_capabilities *cap;
2801
2802 cap = of_device_get_match_data(ddata->dev);
2803 if (!cap)
2804 return -EINVAL;
2805
2806 ddata->cap = cap;
2807 if (ddata->cap)
2808 ddata->cfg.quirks |= ddata->cap->mod_quirks;
2809
2810 return 0;
2811 }
2812
2813 static void ti_sysc_idle(struct work_struct *work)
2814 {
2815 struct sysc *ddata;
2816
2817 ddata = container_of(work, struct sysc, idle_work.work);
2818
2819 /*
2820 * One time decrement of clock usage counts if left on from init.
2821 * Note that we disable opt clocks unconditionally in this case
2822 * as they are enabled unconditionally during init without
2823 * considering sysc_opt_clks_needed() at that point.
2824 */
2825 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2826 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2827 sysc_disable_main_clocks(ddata);
2828 sysc_disable_opt_clocks(ddata);
2829 sysc_clkdm_allow_idle(ddata);
2830 }
2831
2832 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2833 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2834 return;
2835
2836 /*
2837 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2838 * and SYSC_QUIRK_NO_RESET_ON_INIT
2839 */
2840 if (pm_runtime_active(ddata->dev))
2841 pm_runtime_put_sync(ddata->dev);
2842 }
2843
2844 /*
2845 * SoC model and features detection. Only needed for SoCs that need
2846 * special handling for quirks, no need to list others.
2847 */
2848 static const struct soc_device_attribute sysc_soc_match[] = {
2849 SOC_FLAG("OMAP242*", SOC_2420),
2850 SOC_FLAG("OMAP243*", SOC_2430),
2851 SOC_FLAG("OMAP3[45]*", SOC_3430),
2852 SOC_FLAG("OMAP3[67]*", SOC_3630),
2853 SOC_FLAG("OMAP443*", SOC_4430),
2854 SOC_FLAG("OMAP446*", SOC_4460),
2855 SOC_FLAG("OMAP447*", SOC_4470),
2856 SOC_FLAG("OMAP54*", SOC_5430),
2857 SOC_FLAG("AM433", SOC_AM3),
2858 SOC_FLAG("AM43*", SOC_AM4),
2859 SOC_FLAG("DRA7*", SOC_DRA7),
2860
2861 { /* sentinel */ },
2862 };
2863
2864 /*
2865 * List of SoCs variants with disabled features. By default we assume all
2866 * devices in the device tree are available so no need to list those SoCs.
2867 */
2868 static const struct soc_device_attribute sysc_soc_feat_match[] = {
2869 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
2870 SOC_FLAG("AM3505", DIS_SGX),
2871 SOC_FLAG("OMAP3525", DIS_SGX),
2872 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
2873 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
2874
2875 /* OMAP3630/DM3730 variants with some accelerators disabled */
2876 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
2877 SOC_FLAG("DM3725", DIS_SGX),
2878 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
2879 SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
2880 SOC_FLAG("OMAP3621", DIS_ISP),
2881
2882 { /* sentinel */ },
2883 };
2884
2885 static int sysc_add_disabled(unsigned long base)
2886 {
2887 struct sysc_address *disabled_module;
2888
2889 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
2890 if (!disabled_module)
2891 return -ENOMEM;
2892
2893 disabled_module->base = base;
2894
2895 mutex_lock(&sysc_soc->list_lock);
2896 list_add(&disabled_module->node, &sysc_soc->disabled_modules);
2897 mutex_unlock(&sysc_soc->list_lock);
2898
2899 return 0;
2900 }
2901
2902 /*
2903 * One time init to detect the booted SoC and disable unavailable features.
2904 * Note that we initialize static data shared across all ti-sysc instances
2905 * so ddata is only used for SoC type. This can be called from module_init
2906 * once we no longer need to rely on platform data.
2907 */
2908 static int sysc_init_soc(struct sysc *ddata)
2909 {
2910 const struct soc_device_attribute *match;
2911 struct ti_sysc_platform_data *pdata;
2912 unsigned long features = 0;
2913 struct device_node *np;
2914
2915 if (sysc_soc)
2916 return 0;
2917
2918 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
2919 if (!sysc_soc)
2920 return -ENOMEM;
2921
2922 mutex_init(&sysc_soc->list_lock);
2923 INIT_LIST_HEAD(&sysc_soc->disabled_modules);
2924 sysc_soc->general_purpose = true;
2925
2926 pdata = dev_get_platdata(ddata->dev);
2927 if (pdata && pdata->soc_type_gp)
2928 sysc_soc->general_purpose = pdata->soc_type_gp();
2929
2930 match = soc_device_match(sysc_soc_match);
2931 if (match && match->data)
2932 sysc_soc->soc = (int)match->data;
2933
2934 /*
2935 * Check and warn about possible old incomplete dtb. We now want to see
2936 * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs.
2937 */
2938 switch (sysc_soc->soc) {
2939 case SOC_AM3:
2940 case SOC_AM4:
2941 case SOC_4430 ... SOC_4470:
2942 case SOC_5430:
2943 case SOC_DRA7:
2944 np = of_find_node_by_path("/ocp");
2945 WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"),
2946 "ti-sysc: Incomplete old dtb, please update\n");
2947 break;
2948 default:
2949 break;
2950 }
2951
2952 /* Ignore devices that are not available on HS and EMU SoCs */
2953 if (!sysc_soc->general_purpose) {
2954 switch (sysc_soc->soc) {
2955 case SOC_3430 ... SOC_3630:
2956 sysc_add_disabled(0x48304000); /* timer12 */
2957 break;
2958 case SOC_AM3:
2959 sysc_add_disabled(0x48310000); /* rng */
2960 break;
2961 default:
2962 break;
2963 }
2964 }
2965
2966 match = soc_device_match(sysc_soc_feat_match);
2967 if (!match)
2968 return 0;
2969
2970 if (match->data)
2971 features = (unsigned long)match->data;
2972
2973 /*
2974 * Add disabled devices to the list based on the module base.
2975 * Note that this must be done before we attempt to access the
2976 * device and have module revision checks working.
2977 */
2978 if (features & DIS_ISP)
2979 sysc_add_disabled(0x480bd400);
2980 if (features & DIS_IVA)
2981 sysc_add_disabled(0x5d000000);
2982 if (features & DIS_SGX)
2983 sysc_add_disabled(0x50000000);
2984
2985 return 0;
2986 }
2987
2988 static void sysc_cleanup_soc(void)
2989 {
2990 struct sysc_address *disabled_module;
2991 struct list_head *pos, *tmp;
2992
2993 if (!sysc_soc)
2994 return;
2995
2996 mutex_lock(&sysc_soc->list_lock);
2997 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
2998 disabled_module = list_entry(pos, struct sysc_address, node);
2999 list_del(pos);
3000 kfree(disabled_module);
3001 }
3002 mutex_unlock(&sysc_soc->list_lock);
3003 }
3004
3005 static int sysc_check_disabled_devices(struct sysc *ddata)
3006 {
3007 struct sysc_address *disabled_module;
3008 struct list_head *pos;
3009 int error = 0;
3010
3011 mutex_lock(&sysc_soc->list_lock);
3012 list_for_each(pos, &sysc_soc->disabled_modules) {
3013 disabled_module = list_entry(pos, struct sysc_address, node);
3014 if (ddata->module_pa == disabled_module->base) {
3015 dev_dbg(ddata->dev, "module disabled for this SoC\n");
3016 error = -ENODEV;
3017 break;
3018 }
3019 }
3020 mutex_unlock(&sysc_soc->list_lock);
3021
3022 return error;
3023 }
3024
3025 /*
3026 * Ignore timers tagged with no-reset and no-idle. These are likely in use,
3027 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
3028 * are needed, we could also look at the timer register configuration.
3029 */
3030 static int sysc_check_active_timer(struct sysc *ddata)
3031 {
3032 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
3033 ddata->cap->type != TI_SYSC_OMAP4_TIMER)
3034 return 0;
3035
3036 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
3037 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
3038 return -ENXIO;
3039
3040 return 0;
3041 }
3042
3043 static const struct of_device_id sysc_match_table[] = {
3044 { .compatible = "simple-bus", },
3045 { /* sentinel */ },
3046 };
3047
3048 static int sysc_probe(struct platform_device *pdev)
3049 {
3050 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
3051 struct sysc *ddata;
3052 int error;
3053
3054 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
3055 if (!ddata)
3056 return -ENOMEM;
3057
3058 ddata->offsets[SYSC_REVISION] = -ENODEV;
3059 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV;
3060 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV;
3061 ddata->dev = &pdev->dev;
3062 platform_set_drvdata(pdev, ddata);
3063
3064 error = sysc_init_soc(ddata);
3065 if (error)
3066 return error;
3067
3068 error = sysc_init_match(ddata);
3069 if (error)
3070 return error;
3071
3072 error = sysc_init_dts_quirks(ddata);
3073 if (error)
3074 return error;
3075
3076 error = sysc_map_and_check_registers(ddata);
3077 if (error)
3078 return error;
3079
3080 error = sysc_init_sysc_mask(ddata);
3081 if (error)
3082 return error;
3083
3084 error = sysc_init_idlemodes(ddata);
3085 if (error)
3086 return error;
3087
3088 error = sysc_init_syss_mask(ddata);
3089 if (error)
3090 return error;
3091
3092 error = sysc_init_pdata(ddata);
3093 if (error)
3094 return error;
3095
3096 sysc_init_early_quirks(ddata);
3097
3098 error = sysc_check_disabled_devices(ddata);
3099 if (error)
3100 return error;
3101
3102 error = sysc_check_active_timer(ddata);
3103 if (error == -ENXIO)
3104 ddata->reserved = true;
3105 else if (error)
3106 return error;
3107
3108 error = sysc_get_clocks(ddata);
3109 if (error)
3110 return error;
3111
3112 error = sysc_init_resets(ddata);
3113 if (error)
3114 goto unprepare;
3115
3116 error = sysc_init_module(ddata);
3117 if (error)
3118 goto unprepare;
3119
3120 pm_runtime_enable(ddata->dev);
3121 error = pm_runtime_resume_and_get(ddata->dev);
3122 if (error < 0) {
3123 pm_runtime_disable(ddata->dev);
3124 goto unprepare;
3125 }
3126
3127 /* Balance use counts as PM runtime should have enabled these all */
3128 if (!(ddata->cfg.quirks &
3129 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
3130 sysc_disable_main_clocks(ddata);
3131 sysc_disable_opt_clocks(ddata);
3132 sysc_clkdm_allow_idle(ddata);
3133 }
3134
3135 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
3136 reset_control_assert(ddata->rsts);
3137
3138 sysc_show_registers(ddata);
3139
3140 ddata->dev->type = &sysc_device_type;
3141
3142 if (!ddata->reserved) {
3143 error = of_platform_populate(ddata->dev->of_node,
3144 sysc_match_table,
3145 pdata ? pdata->auxdata : NULL,
3146 ddata->dev);
3147 if (error)
3148 goto err;
3149 }
3150
3151 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
3152
3153 /* At least earlycon won't survive without deferred idle */
3154 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3155 SYSC_QUIRK_NO_IDLE_ON_INIT |
3156 SYSC_QUIRK_NO_RESET_ON_INIT)) {
3157 schedule_delayed_work(&ddata->idle_work, 3000);
3158 } else {
3159 pm_runtime_put(&pdev->dev);
3160 }
3161
3162 return 0;
3163
3164 err:
3165 pm_runtime_put_sync(&pdev->dev);
3166 pm_runtime_disable(&pdev->dev);
3167 unprepare:
3168 sysc_unprepare(ddata);
3169
3170 return error;
3171 }
3172
3173 static int sysc_remove(struct platform_device *pdev)
3174 {
3175 struct sysc *ddata = platform_get_drvdata(pdev);
3176 int error;
3177
3178 cancel_delayed_work_sync(&ddata->idle_work);
3179
3180 error = pm_runtime_resume_and_get(ddata->dev);
3181 if (error < 0) {
3182 pm_runtime_disable(ddata->dev);
3183 goto unprepare;
3184 }
3185
3186 of_platform_depopulate(&pdev->dev);
3187
3188 pm_runtime_put_sync(&pdev->dev);
3189 pm_runtime_disable(&pdev->dev);
3190
3191 if (!reset_control_status(ddata->rsts))
3192 reset_control_assert(ddata->rsts);
3193
3194 unprepare:
3195 sysc_unprepare(ddata);
3196
3197 return 0;
3198 }
3199
3200 static const struct of_device_id sysc_match[] = {
3201 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
3202 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
3203 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
3204 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
3205 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
3206 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
3207 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
3208 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
3209 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
3210 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
3211 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
3212 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
3213 { .compatible = "ti,sysc-usb-host-fs",
3214 .data = &sysc_omap4_usb_host_fs, },
3215 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
3216 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
3217 { },
3218 };
3219 MODULE_DEVICE_TABLE(of, sysc_match);
3220
3221 static struct platform_driver sysc_driver = {
3222 .probe = sysc_probe,
3223 .remove = sysc_remove,
3224 .driver = {
3225 .name = "ti-sysc",
3226 .of_match_table = sysc_match,
3227 .pm = &sysc_pm_ops,
3228 },
3229 };
3230
3231 static int __init sysc_init(void)
3232 {
3233 bus_register_notifier(&platform_bus_type, &sysc_nb);
3234
3235 return platform_driver_register(&sysc_driver);
3236 }
3237 module_init(sysc_init);
3238
3239 static void __exit sysc_exit(void)
3240 {
3241 bus_unregister_notifier(&platform_bus_type, &sysc_nb);
3242 platform_driver_unregister(&sysc_driver);
3243 sysc_cleanup_soc();
3244 }
3245 module_exit(sysc_exit);
3246
3247 MODULE_DESCRIPTION("TI sysc interconnect target driver");
3248 MODULE_LICENSE("GPL v2");
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