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[mirror_ubuntu-hirsute-kernel.git] / drivers / char / agp / amd64-agp.c
1 /*
2 * Copyright 2001-2003 SuSE Labs.
3 * Distributed under the GNU public license, v2.
4 *
5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
6 * It also includes support for the AMD 8151 AGP bridge,
7 * although it doesn't actually do much, as all the real
8 * work is done in the northbridge(s).
9 */
10
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/agp_backend.h>
15 #include <linux/mmzone.h>
16 #include <asm/page.h> /* PAGE_SIZE */
17 #include <asm/k8.h>
18 #include "agp.h"
19
20 /* PTE bits. */
21 #define GPTE_VALID 1
22 #define GPTE_COHERENT 2
23
24 /* Aperture control register bits. */
25 #define GARTEN (1<<0)
26 #define DISGARTCPU (1<<4)
27 #define DISGARTIO (1<<5)
28
29 /* GART cache control register bits. */
30 #define INVGART (1<<0)
31 #define GARTPTEERR (1<<1)
32
33 /* K8 On-cpu GART registers */
34 #define AMD64_GARTAPERTURECTL 0x90
35 #define AMD64_GARTAPERTUREBASE 0x94
36 #define AMD64_GARTTABLEBASE 0x98
37 #define AMD64_GARTCACHECTL 0x9c
38 #define AMD64_GARTEN (1<<0)
39
40 /* NVIDIA K8 registers */
41 #define NVIDIA_X86_64_0_APBASE 0x10
42 #define NVIDIA_X86_64_1_APBASE1 0x50
43 #define NVIDIA_X86_64_1_APLIMIT1 0x54
44 #define NVIDIA_X86_64_1_APSIZE 0xa8
45 #define NVIDIA_X86_64_1_APBASE2 0xd8
46 #define NVIDIA_X86_64_1_APLIMIT2 0xdc
47
48 /* ULi K8 registers */
49 #define ULI_X86_64_BASE_ADDR 0x10
50 #define ULI_X86_64_HTT_FEA_REG 0x50
51 #define ULI_X86_64_ENU_SCR_REG 0x54
52
53 static struct resource *aperture_resource;
54 static int __initdata agp_try_unsupported = 1;
55
56 static void amd64_tlbflush(struct agp_memory *temp)
57 {
58 k8_flush_garts();
59 }
60
61 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
62 {
63 int i, j, num_entries;
64 long long tmp;
65 u32 pte;
66
67 num_entries = agp_num_entries();
68
69 if (type != 0 || mem->type != 0)
70 return -EINVAL;
71
72 /* Make sure we can fit the range in the gatt table. */
73 /* FIXME: could wrap */
74 if (((unsigned long)pg_start + mem->page_count) > num_entries)
75 return -EINVAL;
76
77 j = pg_start;
78
79 /* gatt table should be empty. */
80 while (j < (pg_start + mem->page_count)) {
81 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
82 return -EBUSY;
83 j++;
84 }
85
86 if (mem->is_flushed == FALSE) {
87 global_cache_flush();
88 mem->is_flushed = TRUE;
89 }
90
91 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
92 tmp = agp_bridge->driver->mask_memory(agp_bridge,
93 mem->memory[i], mem->type);
94
95 BUG_ON(tmp & 0xffffff0000000ffcULL);
96 pte = (tmp & 0x000000ff00000000ULL) >> 28;
97 pte |=(tmp & 0x00000000fffff000ULL);
98 pte |= GPTE_VALID | GPTE_COHERENT;
99
100 writel(pte, agp_bridge->gatt_table+j);
101 readl(agp_bridge->gatt_table+j); /* PCI Posting. */
102 }
103 amd64_tlbflush(mem);
104 return 0;
105 }
106
107 /*
108 * This hack alters the order element according
109 * to the size of a long. It sucks. I totally disown this, even
110 * though it does appear to work for the most part.
111 */
112 static struct aper_size_info_32 amd64_aperture_sizes[7] =
113 {
114 {32, 8192, 3+(sizeof(long)/8), 0 },
115 {64, 16384, 4+(sizeof(long)/8), 1<<1 },
116 {128, 32768, 5+(sizeof(long)/8), 1<<2 },
117 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
118 {512, 131072, 7+(sizeof(long)/8), 1<<3 },
119 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
120 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
121 };
122
123
124 /*
125 * Get the current Aperture size from the x86-64.
126 * Note, that there may be multiple x86-64's, but we just return
127 * the value from the first one we find. The set_size functions
128 * keep the rest coherent anyway. Or at least should do.
129 */
130 static int amd64_fetch_size(void)
131 {
132 struct pci_dev *dev;
133 int i;
134 u32 temp;
135 struct aper_size_info_32 *values;
136
137 dev = k8_northbridges[0];
138 if (dev==NULL)
139 return 0;
140
141 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
142 temp = (temp & 0xe);
143 values = A_SIZE_32(amd64_aperture_sizes);
144
145 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
146 if (temp == values[i].size_value) {
147 agp_bridge->previous_size =
148 agp_bridge->current_size = (void *) (values + i);
149
150 agp_bridge->aperture_size_idx = i;
151 return values[i].size;
152 }
153 }
154 return 0;
155 }
156
157 /*
158 * In a multiprocessor x86-64 system, this function gets
159 * called once for each CPU.
160 */
161 static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table)
162 {
163 u64 aperturebase;
164 u32 tmp;
165 u64 addr, aper_base;
166
167 /* Address to map to */
168 pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp);
169 aperturebase = tmp << 25;
170 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
171
172 /* address of the mappings table */
173 addr = (u64) gatt_table;
174 addr >>= 12;
175 tmp = (u32) addr<<4;
176 tmp &= ~0xf;
177 pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp);
178
179 /* Enable GART translation for this hammer. */
180 pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
181 tmp |= GARTEN;
182 tmp &= ~(DISGARTCPU | DISGARTIO);
183 pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp);
184
185 return aper_base;
186 }
187
188
189 static struct aper_size_info_32 amd_8151_sizes[7] =
190 {
191 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
192 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
193 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
194 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */
195 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */
196 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */
197 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */
198 };
199
200 static int amd_8151_configure(void)
201 {
202 unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real);
203 int i;
204
205 /* Configure AGP regs in each x86-64 host bridge. */
206 for (i = 0; i < num_k8_northbridges; i++) {
207 agp_bridge->gart_bus_addr =
208 amd64_configure(k8_northbridges[i], gatt_bus);
209 }
210 k8_flush_garts();
211 return 0;
212 }
213
214
215 static void amd64_cleanup(void)
216 {
217 u32 tmp;
218 int i;
219 for (i = 0; i < num_k8_northbridges; i++) {
220 struct pci_dev *dev = k8_northbridges[i];
221 /* disable gart translation */
222 pci_read_config_dword (dev, AMD64_GARTAPERTURECTL, &tmp);
223 tmp &= ~AMD64_GARTEN;
224 pci_write_config_dword (dev, AMD64_GARTAPERTURECTL, tmp);
225 }
226 }
227
228
229 static struct agp_bridge_driver amd_8151_driver = {
230 .owner = THIS_MODULE,
231 .aperture_sizes = amd_8151_sizes,
232 .size_type = U32_APER_SIZE,
233 .num_aperture_sizes = 7,
234 .configure = amd_8151_configure,
235 .fetch_size = amd64_fetch_size,
236 .cleanup = amd64_cleanup,
237 .tlb_flush = amd64_tlbflush,
238 .mask_memory = agp_generic_mask_memory,
239 .masks = NULL,
240 .agp_enable = agp_generic_enable,
241 .cache_flush = global_cache_flush,
242 .create_gatt_table = agp_generic_create_gatt_table,
243 .free_gatt_table = agp_generic_free_gatt_table,
244 .insert_memory = amd64_insert_memory,
245 .remove_memory = agp_generic_remove_memory,
246 .alloc_by_type = agp_generic_alloc_by_type,
247 .free_by_type = agp_generic_free_by_type,
248 .agp_alloc_page = agp_generic_alloc_page,
249 .agp_destroy_page = agp_generic_destroy_page,
250 };
251
252 /* Some basic sanity checks for the aperture. */
253 static int __devinit aperture_valid(u64 aper, u32 size)
254 {
255 u32 pfn, c;
256 if (aper == 0) {
257 printk(KERN_ERR PFX "No aperture\n");
258 return 0;
259 }
260 if (size < 32*1024*1024) {
261 printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20);
262 return 0;
263 }
264 if (aper + size > 0xffffffff) {
265 printk(KERN_ERR PFX "Aperture out of bounds\n");
266 return 0;
267 }
268 pfn = aper >> PAGE_SHIFT;
269 for (c = 0; c < size/PAGE_SIZE; c++) {
270 if (!pfn_valid(pfn + c))
271 break;
272 if (!PageReserved(pfn_to_page(pfn + c))) {
273 printk(KERN_ERR PFX "Aperture pointing to RAM\n");
274 return 0;
275 }
276 }
277
278 /* Request the Aperture. This catches cases when someone else
279 already put a mapping in there - happens with some very broken BIOS
280
281 Maybe better to use pci_assign_resource/pci_enable_device instead
282 trusting the bridges? */
283 if (!aperture_resource &&
284 !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
285 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
286 return 0;
287 }
288 return 1;
289 }
290
291 /*
292 * W*s centric BIOS sometimes only set up the aperture in the AGP
293 * bridge, not the northbridge. On AMD64 this is handled early
294 * in aperture.c, but when IOMMU is not enabled or we run
295 * on a 32bit kernel this needs to be redone.
296 * Unfortunately it is impossible to fix the aperture here because it's too late
297 * to allocate that much memory. But at least error out cleanly instead of
298 * crashing.
299 */
300 static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
301 u16 cap)
302 {
303 u32 aper_low, aper_hi;
304 u64 aper, nb_aper;
305 int order = 0;
306 u32 nb_order, nb_base;
307 u16 apsize;
308
309 pci_read_config_dword(nb, 0x90, &nb_order);
310 nb_order = (nb_order >> 1) & 7;
311 pci_read_config_dword(nb, 0x94, &nb_base);
312 nb_aper = nb_base << 25;
313 if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
314 return 0;
315 }
316
317 /* Northbridge seems to contain crap. Try the AGP bridge. */
318
319 pci_read_config_word(agp, cap+0x14, &apsize);
320 if (apsize == 0xffff)
321 return -1;
322
323 apsize &= 0xfff;
324 /* Some BIOS use weird encodings not in the AGPv3 table. */
325 if (apsize & 0xff)
326 apsize |= 0xf00;
327 order = 7 - hweight16(apsize);
328
329 pci_read_config_dword(agp, 0x10, &aper_low);
330 pci_read_config_dword(agp, 0x14, &aper_hi);
331 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
332 printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order);
333 if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order))
334 return -1;
335
336 pci_write_config_dword(nb, 0x90, order << 1);
337 pci_write_config_dword(nb, 0x94, aper >> 25);
338
339 return 0;
340 }
341
342 static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
343 {
344 int i;
345
346 if (cache_k8_northbridges() < 0)
347 return -ENODEV;
348
349 i = 0;
350 for (i = 0; i < num_k8_northbridges; i++) {
351 struct pci_dev *dev = k8_northbridges[i];
352 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
353 printk(KERN_ERR PFX "No usable aperture found.\n");
354 #ifdef __x86_64__
355 /* should port this to i386 */
356 printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n");
357 #endif
358 return -1;
359 }
360 }
361 return 0;
362 }
363
364 /* Handle AMD 8151 quirks */
365 static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
366 {
367 char *revstring;
368 u8 rev_id;
369
370 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
371 switch (rev_id) {
372 case 0x01: revstring="A0"; break;
373 case 0x02: revstring="A1"; break;
374 case 0x11: revstring="B0"; break;
375 case 0x12: revstring="B1"; break;
376 case 0x13: revstring="B2"; break;
377 case 0x14: revstring="B3"; break;
378 default: revstring="??"; break;
379 }
380
381 printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring);
382
383 /*
384 * Work around errata.
385 * Chips before B2 stepping incorrectly reporting v3.5
386 */
387 if (rev_id < 0x13) {
388 printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n");
389 bridge->major_version = 3;
390 bridge->minor_version = 0;
391 }
392 }
393
394
395 static const struct aper_size_info_32 uli_sizes[7] =
396 {
397 {256, 65536, 6, 10},
398 {128, 32768, 5, 9},
399 {64, 16384, 4, 8},
400 {32, 8192, 3, 7},
401 {16, 4096, 2, 6},
402 {8, 2048, 1, 4},
403 {4, 1024, 0, 3}
404 };
405 static int __devinit uli_agp_init(struct pci_dev *pdev)
406 {
407 u32 httfea,baseaddr,enuscr;
408 struct pci_dev *dev1;
409 int i;
410 unsigned size = amd64_fetch_size();
411 printk(KERN_INFO "Setting up ULi AGP.\n");
412 dev1 = pci_find_slot ((unsigned int)pdev->bus->number,PCI_DEVFN(0,0));
413 if (dev1 == NULL) {
414 printk(KERN_INFO PFX "Detected a ULi chipset, "
415 "but could not fine the secondary device.\n");
416 return -ENODEV;
417 }
418
419 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
420 if (uli_sizes[i].size == size)
421 break;
422
423 if (i == ARRAY_SIZE(uli_sizes)) {
424 printk(KERN_INFO PFX "No ULi size found for %d\n", size);
425 return -ENODEV;
426 }
427
428 /* shadow x86-64 registers into ULi registers */
429 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
430
431 /* if x86-64 aperture base is beyond 4G, exit here */
432 if ((httfea & 0x7fff) >> (32 - 25))
433 return -ENODEV;
434
435 httfea = (httfea& 0x7fff) << 25;
436
437 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
438 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
439 baseaddr|= httfea;
440 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
441
442 enuscr= httfea+ (size * 1024 * 1024) - 1;
443 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
444 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
445 return 0;
446 }
447
448
449 static const struct aper_size_info_32 nforce3_sizes[5] =
450 {
451 {512, 131072, 7, 0x00000000 },
452 {256, 65536, 6, 0x00000008 },
453 {128, 32768, 5, 0x0000000C },
454 {64, 16384, 4, 0x0000000E },
455 {32, 8192, 3, 0x0000000F }
456 };
457
458 /* Handle shadow device of the Nvidia NForce3 */
459 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
460 static int __devinit nforce3_agp_init(struct pci_dev *pdev)
461 {
462 u32 tmp, apbase, apbar, aplimit;
463 struct pci_dev *dev1;
464 int i;
465 unsigned size = amd64_fetch_size();
466
467 printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n");
468
469 dev1 = pci_find_slot((unsigned int)pdev->bus->number, PCI_DEVFN(11, 0));
470 if (dev1 == NULL) {
471 printk(KERN_INFO PFX "agpgart: Detected an NVIDIA "
472 "nForce3 chipset, but could not find "
473 "the secondary device.\n");
474 return -ENODEV;
475 }
476
477 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
478 if (nforce3_sizes[i].size == size)
479 break;
480
481 if (i == ARRAY_SIZE(nforce3_sizes)) {
482 printk(KERN_INFO PFX "No NForce3 size found for %d\n", size);
483 return -ENODEV;
484 }
485
486 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
487 tmp &= ~(0xf);
488 tmp |= nforce3_sizes[i].size_value;
489 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
490
491 /* shadow x86-64 registers into NVIDIA registers */
492 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
493
494 /* if x86-64 aperture base is beyond 4G, exit here */
495 if ( (apbase & 0x7fff) >> (32 - 25) ) {
496 printk(KERN_INFO PFX "aperture base > 4G\n");
497 return -ENODEV;
498 }
499
500 apbase = (apbase & 0x7fff) << 25;
501
502 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
503 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
504 apbar |= apbase;
505 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
506
507 aplimit = apbase + (size * 1024 * 1024) - 1;
508 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
509 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
510 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
511 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
512
513 return 0;
514 }
515
516 static int __devinit agp_amd64_probe(struct pci_dev *pdev,
517 const struct pci_device_id *ent)
518 {
519 struct agp_bridge_data *bridge;
520 u8 cap_ptr;
521
522 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
523 if (!cap_ptr)
524 return -ENODEV;
525
526 /* Could check for AGPv3 here */
527
528 bridge = agp_alloc_bridge();
529 if (!bridge)
530 return -ENOMEM;
531
532 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
533 pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
534 amd8151_init(pdev, bridge);
535 } else {
536 printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn);
537 }
538
539 bridge->driver = &amd_8151_driver;
540 bridge->dev = pdev;
541 bridge->capndx = cap_ptr;
542
543 /* Fill in the mode register */
544 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
545
546 if (cache_nbs(pdev, cap_ptr) == -1) {
547 agp_put_bridge(bridge);
548 return -ENODEV;
549 }
550
551 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
552 int ret = nforce3_agp_init(pdev);
553 if (ret) {
554 agp_put_bridge(bridge);
555 return ret;
556 }
557 }
558
559 if (pdev->vendor == PCI_VENDOR_ID_AL) {
560 int ret = uli_agp_init(pdev);
561 if (ret) {
562 agp_put_bridge(bridge);
563 return ret;
564 }
565 }
566
567 pci_set_drvdata(pdev, bridge);
568 return agp_add_bridge(bridge);
569 }
570
571 static void __devexit agp_amd64_remove(struct pci_dev *pdev)
572 {
573 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
574
575 release_mem_region(virt_to_gart(bridge->gatt_table_real),
576 amd64_aperture_sizes[bridge->aperture_size_idx].size);
577 agp_remove_bridge(bridge);
578 agp_put_bridge(bridge);
579 }
580
581 #ifdef CONFIG_PM
582
583 static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
584 {
585 pci_save_state(pdev);
586 pci_set_power_state(pdev, pci_choose_state(pdev, state));
587
588 return 0;
589 }
590
591 static int agp_amd64_resume(struct pci_dev *pdev)
592 {
593 pci_set_power_state(pdev, PCI_D0);
594 pci_restore_state(pdev);
595
596 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
597 nforce3_agp_init(pdev);
598
599 return amd_8151_configure();
600 }
601
602 #endif /* CONFIG_PM */
603
604 static struct pci_device_id agp_amd64_pci_table[] = {
605 {
606 .class = (PCI_CLASS_BRIDGE_HOST << 8),
607 .class_mask = ~0,
608 .vendor = PCI_VENDOR_ID_AMD,
609 .device = PCI_DEVICE_ID_AMD_8151_0,
610 .subvendor = PCI_ANY_ID,
611 .subdevice = PCI_ANY_ID,
612 },
613 /* ULi M1689 */
614 {
615 .class = (PCI_CLASS_BRIDGE_HOST << 8),
616 .class_mask = ~0,
617 .vendor = PCI_VENDOR_ID_AL,
618 .device = PCI_DEVICE_ID_AL_M1689,
619 .subvendor = PCI_ANY_ID,
620 .subdevice = PCI_ANY_ID,
621 },
622 /* VIA K8T800Pro */
623 {
624 .class = (PCI_CLASS_BRIDGE_HOST << 8),
625 .class_mask = ~0,
626 .vendor = PCI_VENDOR_ID_VIA,
627 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
628 .subvendor = PCI_ANY_ID,
629 .subdevice = PCI_ANY_ID,
630 },
631 /* VIA K8T800 */
632 {
633 .class = (PCI_CLASS_BRIDGE_HOST << 8),
634 .class_mask = ~0,
635 .vendor = PCI_VENDOR_ID_VIA,
636 .device = PCI_DEVICE_ID_VIA_8385_0,
637 .subvendor = PCI_ANY_ID,
638 .subdevice = PCI_ANY_ID,
639 },
640 /* VIA K8M800 / K8N800 */
641 {
642 .class = (PCI_CLASS_BRIDGE_HOST << 8),
643 .class_mask = ~0,
644 .vendor = PCI_VENDOR_ID_VIA,
645 .device = PCI_DEVICE_ID_VIA_8380_0,
646 .subvendor = PCI_ANY_ID,
647 .subdevice = PCI_ANY_ID,
648 },
649 /* VIA K8T890 */
650 {
651 .class = (PCI_CLASS_BRIDGE_HOST << 8),
652 .class_mask = ~0,
653 .vendor = PCI_VENDOR_ID_VIA,
654 .device = PCI_DEVICE_ID_VIA_3238_0,
655 .subvendor = PCI_ANY_ID,
656 .subdevice = PCI_ANY_ID,
657 },
658 /* VIA K8T800/K8M800/K8N800 */
659 {
660 .class = (PCI_CLASS_BRIDGE_HOST << 8),
661 .class_mask = ~0,
662 .vendor = PCI_VENDOR_ID_VIA,
663 .device = PCI_DEVICE_ID_VIA_838X_1,
664 .subvendor = PCI_ANY_ID,
665 .subdevice = PCI_ANY_ID,
666 },
667 /* NForce3 */
668 {
669 .class = (PCI_CLASS_BRIDGE_HOST << 8),
670 .class_mask = ~0,
671 .vendor = PCI_VENDOR_ID_NVIDIA,
672 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
673 .subvendor = PCI_ANY_ID,
674 .subdevice = PCI_ANY_ID,
675 },
676 {
677 .class = (PCI_CLASS_BRIDGE_HOST << 8),
678 .class_mask = ~0,
679 .vendor = PCI_VENDOR_ID_NVIDIA,
680 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
681 .subvendor = PCI_ANY_ID,
682 .subdevice = PCI_ANY_ID,
683 },
684 /* SIS 755 */
685 {
686 .class = (PCI_CLASS_BRIDGE_HOST << 8),
687 .class_mask = ~0,
688 .vendor = PCI_VENDOR_ID_SI,
689 .device = PCI_DEVICE_ID_SI_755,
690 .subvendor = PCI_ANY_ID,
691 .subdevice = PCI_ANY_ID,
692 },
693 /* SIS 760 */
694 {
695 .class = (PCI_CLASS_BRIDGE_HOST << 8),
696 .class_mask = ~0,
697 .vendor = PCI_VENDOR_ID_SI,
698 .device = PCI_DEVICE_ID_SI_760,
699 .subvendor = PCI_ANY_ID,
700 .subdevice = PCI_ANY_ID,
701 },
702 /* ALI/ULI M1695 */
703 {
704 .class = (PCI_CLASS_BRIDGE_HOST << 8),
705 .class_mask = ~0,
706 .vendor = PCI_VENDOR_ID_AL,
707 .device = 0x1695,
708 .subvendor = PCI_ANY_ID,
709 .subdevice = PCI_ANY_ID,
710 },
711
712 { }
713 };
714
715 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
716
717 static struct pci_driver agp_amd64_pci_driver = {
718 .name = "agpgart-amd64",
719 .id_table = agp_amd64_pci_table,
720 .probe = agp_amd64_probe,
721 .remove = agp_amd64_remove,
722 #ifdef CONFIG_PM
723 .suspend = agp_amd64_suspend,
724 .resume = agp_amd64_resume,
725 #endif
726 };
727
728
729 /* Not static due to IOMMU code calling it early. */
730 int __init agp_amd64_init(void)
731 {
732 int err = 0;
733
734 if (agp_off)
735 return -EINVAL;
736 if (pci_register_driver(&agp_amd64_pci_driver) < 0) {
737 struct pci_dev *dev;
738 if (!agp_try_unsupported && !agp_try_unsupported_boot) {
739 printk(KERN_INFO PFX "No supported AGP bridge found.\n");
740 #ifdef MODULE
741 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
742 #else
743 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
744 #endif
745 return -ENODEV;
746 }
747
748 /* First check that we have at least one AMD64 NB */
749 if (!pci_dev_present(k8_nb_ids))
750 return -ENODEV;
751
752 /* Look for any AGP bridge */
753 dev = NULL;
754 err = -ENODEV;
755 for_each_pci_dev(dev) {
756 if (!pci_find_capability(dev, PCI_CAP_ID_AGP))
757 continue;
758 /* Only one bridge supported right now */
759 if (agp_amd64_probe(dev, NULL) == 0) {
760 err = 0;
761 break;
762 }
763 }
764 }
765 return err;
766 }
767
768 static void __exit agp_amd64_cleanup(void)
769 {
770 if (aperture_resource)
771 release_resource(aperture_resource);
772 pci_unregister_driver(&agp_amd64_pci_driver);
773 }
774
775 /* On AMD64 the PCI driver needs to initialize this driver early
776 for the IOMMU, so it has to be called via a backdoor. */
777 #ifndef CONFIG_IOMMU
778 module_init(agp_amd64_init);
779 module_exit(agp_amd64_cleanup);
780 #endif
781
782 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen");
783 module_param(agp_try_unsupported, bool, 0);
784 MODULE_LICENSE("GPL");
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