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agp/intel: restore cache behavior on sandybridge
[mirror_ubuntu-bionic-kernel.git] / drivers / char / agp / intel-gtt.c
1 /*
2 * Intel GTT (Graphics Translation Table) routines
3 *
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
10 *
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
13 * here.
14 *
15 * /fairy-tale-mode off
16 */
17
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <asm/smp.h>
25 #include "agp.h"
26 #include "intel-agp.h"
27 #include <linux/intel-gtt.h>
28 #include <drm/intel-gtt.h>
29
30 /*
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_DMAR).
34 * Only newer chipsets need to bother with this, of course.
35 */
36 #ifdef CONFIG_DMAR
37 #define USE_PCI_DMA_API 1
38 #else
39 #define USE_PCI_DMA_API 0
40 #endif
41
42 /* Max amount of stolen space, anything above will be returned to Linux */
43 int intel_max_stolen = 32 * 1024 * 1024;
44
45 static const struct aper_size_info_fixed intel_i810_sizes[] =
46 {
47 {64, 16384, 4},
48 /* The 32M mode still requires a 64k gatt */
49 {32, 8192, 4}
50 };
51
52 #define AGP_DCACHE_MEMORY 1
53 #define AGP_PHYS_MEMORY 2
54 #define INTEL_AGP_CACHED_MEMORY 3
55
56 static struct gatt_mask intel_i810_masks[] =
57 {
58 {.mask = I810_PTE_VALID, .type = 0},
59 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
60 {.mask = I810_PTE_VALID, .type = 0},
61 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
62 .type = INTEL_AGP_CACHED_MEMORY}
63 };
64
65 #define INTEL_AGP_UNCACHED_MEMORY 0
66 #define INTEL_AGP_CACHED_MEMORY_LLC 1
67 #define INTEL_AGP_CACHED_MEMORY_LLC_GFDT 2
68 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC 3
69 #define INTEL_AGP_CACHED_MEMORY_LLC_MLC_GFDT 4
70
71 struct intel_gtt_driver {
72 unsigned int gen : 8;
73 unsigned int is_g33 : 1;
74 unsigned int is_pineview : 1;
75 unsigned int is_ironlake : 1;
76 unsigned int has_pgtbl_enable : 1;
77 unsigned int dma_mask_size : 8;
78 /* Chipset specific GTT setup */
79 int (*setup)(void);
80 /* This should undo anything done in ->setup() save the unmapping
81 * of the mmio register file, that's done in the generic code. */
82 void (*cleanup)(void);
83 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
84 /* Flags is a more or less chipset specific opaque value.
85 * For chipsets that need to support old ums (non-gem) code, this
86 * needs to be identical to the various supported agp memory types! */
87 bool (*check_flags)(unsigned int flags);
88 void (*chipset_flush)(void);
89 };
90
91 static struct _intel_private {
92 struct intel_gtt base;
93 const struct intel_gtt_driver *driver;
94 struct pci_dev *pcidev; /* device one */
95 struct pci_dev *bridge_dev;
96 u8 __iomem *registers;
97 phys_addr_t gtt_bus_addr;
98 phys_addr_t gma_bus_addr;
99 u32 PGETBL_save;
100 u32 __iomem *gtt; /* I915G */
101 int num_dcache_entries;
102 union {
103 void __iomem *i9xx_flush_page;
104 void *i8xx_flush_page;
105 };
106 struct page *i8xx_page;
107 struct resource ifp_resource;
108 int resource_valid;
109 struct page *scratch_page;
110 dma_addr_t scratch_page_dma;
111 } intel_private;
112
113 #define INTEL_GTT_GEN intel_private.driver->gen
114 #define IS_G33 intel_private.driver->is_g33
115 #define IS_PINEVIEW intel_private.driver->is_pineview
116 #define IS_IRONLAKE intel_private.driver->is_ironlake
117 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
118
119 static void intel_agp_free_sglist(struct agp_memory *mem)
120 {
121 struct sg_table st;
122
123 st.sgl = mem->sg_list;
124 st.orig_nents = st.nents = mem->page_count;
125
126 sg_free_table(&st);
127
128 mem->sg_list = NULL;
129 mem->num_sg = 0;
130 }
131
132 static int intel_agp_map_memory(struct agp_memory *mem)
133 {
134 struct sg_table st;
135 struct scatterlist *sg;
136 int i;
137
138 if (mem->sg_list)
139 return 0; /* already mapped (for e.g. resume */
140
141 DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
142
143 if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
144 goto err;
145
146 mem->sg_list = sg = st.sgl;
147
148 for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
149 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
150
151 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
152 mem->page_count, PCI_DMA_BIDIRECTIONAL);
153 if (unlikely(!mem->num_sg))
154 goto err;
155
156 return 0;
157
158 err:
159 sg_free_table(&st);
160 return -ENOMEM;
161 }
162
163 static void intel_agp_unmap_memory(struct agp_memory *mem)
164 {
165 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
166
167 pci_unmap_sg(intel_private.pcidev, mem->sg_list,
168 mem->page_count, PCI_DMA_BIDIRECTIONAL);
169 intel_agp_free_sglist(mem);
170 }
171
172 static int intel_i810_fetch_size(void)
173 {
174 u32 smram_miscc;
175 struct aper_size_info_fixed *values;
176
177 pci_read_config_dword(intel_private.bridge_dev,
178 I810_SMRAM_MISCC, &smram_miscc);
179 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
180
181 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
182 dev_warn(&intel_private.bridge_dev->dev, "i810 is disabled\n");
183 return 0;
184 }
185 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
186 agp_bridge->current_size = (void *) (values + 1);
187 agp_bridge->aperture_size_idx = 1;
188 return values[1].size;
189 } else {
190 agp_bridge->current_size = (void *) (values);
191 agp_bridge->aperture_size_idx = 0;
192 return values[0].size;
193 }
194
195 return 0;
196 }
197
198 static int intel_i810_configure(void)
199 {
200 struct aper_size_info_fixed *current_size;
201 u32 temp;
202 int i;
203
204 current_size = A_SIZE_FIX(agp_bridge->current_size);
205
206 if (!intel_private.registers) {
207 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
208 temp &= 0xfff80000;
209
210 intel_private.registers = ioremap(temp, 128 * 4096);
211 if (!intel_private.registers) {
212 dev_err(&intel_private.pcidev->dev,
213 "can't remap memory\n");
214 return -ENOMEM;
215 }
216 }
217
218 if ((readl(intel_private.registers+I810_DRAM_CTL)
219 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
220 /* This will need to be dynamically assigned */
221 dev_info(&intel_private.pcidev->dev,
222 "detected 4MB dedicated video ram\n");
223 intel_private.num_dcache_entries = 1024;
224 }
225 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
226 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
227 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
228 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
229
230 if (agp_bridge->driver->needs_scratch_page) {
231 for (i = 0; i < current_size->num_entries; i++) {
232 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
233 }
234 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
235 }
236 global_cache_flush();
237 return 0;
238 }
239
240 static void intel_i810_cleanup(void)
241 {
242 writel(0, intel_private.registers+I810_PGETBL_CTL);
243 readl(intel_private.registers); /* PCI Posting. */
244 iounmap(intel_private.registers);
245 }
246
247 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
248 {
249 return;
250 }
251
252 /* Exists to support ARGB cursors */
253 static struct page *i8xx_alloc_pages(void)
254 {
255 struct page *page;
256
257 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
258 if (page == NULL)
259 return NULL;
260
261 if (set_pages_uc(page, 4) < 0) {
262 set_pages_wb(page, 4);
263 __free_pages(page, 2);
264 return NULL;
265 }
266 get_page(page);
267 atomic_inc(&agp_bridge->current_memory_agp);
268 return page;
269 }
270
271 static void i8xx_destroy_pages(struct page *page)
272 {
273 if (page == NULL)
274 return;
275
276 set_pages_wb(page, 4);
277 put_page(page);
278 __free_pages(page, 2);
279 atomic_dec(&agp_bridge->current_memory_agp);
280 }
281
282 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
283 int type)
284 {
285 int i, j, num_entries;
286 void *temp;
287 int ret = -EINVAL;
288 int mask_type;
289
290 if (mem->page_count == 0)
291 goto out;
292
293 temp = agp_bridge->current_size;
294 num_entries = A_SIZE_FIX(temp)->num_entries;
295
296 if ((pg_start + mem->page_count) > num_entries)
297 goto out_err;
298
299
300 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
301 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
302 ret = -EBUSY;
303 goto out_err;
304 }
305 }
306
307 if (type != mem->type)
308 goto out_err;
309
310 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
311
312 switch (mask_type) {
313 case AGP_DCACHE_MEMORY:
314 if (!mem->is_flushed)
315 global_cache_flush();
316 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
317 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
318 intel_private.registers+I810_PTE_BASE+(i*4));
319 }
320 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
321 break;
322 case AGP_PHYS_MEMORY:
323 case AGP_NORMAL_MEMORY:
324 if (!mem->is_flushed)
325 global_cache_flush();
326 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
327 writel(agp_bridge->driver->mask_memory(agp_bridge,
328 page_to_phys(mem->pages[i]), mask_type),
329 intel_private.registers+I810_PTE_BASE+(j*4));
330 }
331 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
332 break;
333 default:
334 goto out_err;
335 }
336
337 out:
338 ret = 0;
339 out_err:
340 mem->is_flushed = true;
341 return ret;
342 }
343
344 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
345 int type)
346 {
347 int i;
348
349 if (mem->page_count == 0)
350 return 0;
351
352 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
353 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
354 }
355 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
356
357 return 0;
358 }
359
360 /*
361 * The i810/i830 requires a physical address to program its mouse
362 * pointer into hardware.
363 * However the Xserver still writes to it through the agp aperture.
364 */
365 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
366 {
367 struct agp_memory *new;
368 struct page *page;
369
370 switch (pg_count) {
371 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
372 break;
373 case 4:
374 /* kludge to get 4 physical pages for ARGB cursor */
375 page = i8xx_alloc_pages();
376 break;
377 default:
378 return NULL;
379 }
380
381 if (page == NULL)
382 return NULL;
383
384 new = agp_create_memory(pg_count);
385 if (new == NULL)
386 return NULL;
387
388 new->pages[0] = page;
389 if (pg_count == 4) {
390 /* kludge to get 4 physical pages for ARGB cursor */
391 new->pages[1] = new->pages[0] + 1;
392 new->pages[2] = new->pages[1] + 1;
393 new->pages[3] = new->pages[2] + 1;
394 }
395 new->page_count = pg_count;
396 new->num_scratch_pages = pg_count;
397 new->type = AGP_PHYS_MEMORY;
398 new->physical = page_to_phys(new->pages[0]);
399 return new;
400 }
401
402 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
403 {
404 struct agp_memory *new;
405
406 if (type == AGP_DCACHE_MEMORY) {
407 if (pg_count != intel_private.num_dcache_entries)
408 return NULL;
409
410 new = agp_create_memory(1);
411 if (new == NULL)
412 return NULL;
413
414 new->type = AGP_DCACHE_MEMORY;
415 new->page_count = pg_count;
416 new->num_scratch_pages = 0;
417 agp_free_page_array(new);
418 return new;
419 }
420 if (type == AGP_PHYS_MEMORY)
421 return alloc_agpphysmem_i8xx(pg_count, type);
422 return NULL;
423 }
424
425 static void intel_i810_free_by_type(struct agp_memory *curr)
426 {
427 agp_free_key(curr->key);
428 if (curr->type == AGP_PHYS_MEMORY) {
429 if (curr->page_count == 4)
430 i8xx_destroy_pages(curr->pages[0]);
431 else {
432 agp_bridge->driver->agp_destroy_page(curr->pages[0],
433 AGP_PAGE_DESTROY_UNMAP);
434 agp_bridge->driver->agp_destroy_page(curr->pages[0],
435 AGP_PAGE_DESTROY_FREE);
436 }
437 agp_free_page_array(curr);
438 }
439 kfree(curr);
440 }
441
442 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
443 dma_addr_t addr, int type)
444 {
445 /* Type checking must be done elsewhere */
446 return addr | bridge->driver->masks[type].mask;
447 }
448
449 static int intel_gtt_setup_scratch_page(void)
450 {
451 struct page *page;
452 dma_addr_t dma_addr;
453
454 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
455 if (page == NULL)
456 return -ENOMEM;
457 get_page(page);
458 set_pages_uc(page, 1);
459
460 if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) {
461 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
462 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
463 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
464 return -EINVAL;
465
466 intel_private.scratch_page_dma = dma_addr;
467 } else
468 intel_private.scratch_page_dma = page_to_phys(page);
469
470 intel_private.scratch_page = page;
471
472 return 0;
473 }
474
475 static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = {
476 {128, 32768, 5},
477 /* The 64M mode still requires a 128k gatt */
478 {64, 16384, 5},
479 {256, 65536, 6},
480 {512, 131072, 7},
481 };
482
483 static unsigned int intel_gtt_stolen_entries(void)
484 {
485 u16 gmch_ctrl;
486 u8 rdct;
487 int local = 0;
488 static const int ddt[4] = { 0, 16, 32, 64 };
489 unsigned int overhead_entries, stolen_entries;
490 unsigned int stolen_size = 0;
491
492 pci_read_config_word(intel_private.bridge_dev,
493 I830_GMCH_CTRL, &gmch_ctrl);
494
495 if (INTEL_GTT_GEN > 4 || IS_PINEVIEW)
496 overhead_entries = 0;
497 else
498 overhead_entries = intel_private.base.gtt_mappable_entries
499 / 1024;
500
501 overhead_entries += 1; /* BIOS popup */
502
503 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
504 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
505 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
506 case I830_GMCH_GMS_STOLEN_512:
507 stolen_size = KB(512);
508 break;
509 case I830_GMCH_GMS_STOLEN_1024:
510 stolen_size = MB(1);
511 break;
512 case I830_GMCH_GMS_STOLEN_8192:
513 stolen_size = MB(8);
514 break;
515 case I830_GMCH_GMS_LOCAL:
516 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
517 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
518 MB(ddt[I830_RDRAM_DDT(rdct)]);
519 local = 1;
520 break;
521 default:
522 stolen_size = 0;
523 break;
524 }
525 } else if (INTEL_GTT_GEN == 6) {
526 /*
527 * SandyBridge has new memory control reg at 0x50.w
528 */
529 u16 snb_gmch_ctl;
530 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
531 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
532 case SNB_GMCH_GMS_STOLEN_32M:
533 stolen_size = MB(32);
534 break;
535 case SNB_GMCH_GMS_STOLEN_64M:
536 stolen_size = MB(64);
537 break;
538 case SNB_GMCH_GMS_STOLEN_96M:
539 stolen_size = MB(96);
540 break;
541 case SNB_GMCH_GMS_STOLEN_128M:
542 stolen_size = MB(128);
543 break;
544 case SNB_GMCH_GMS_STOLEN_160M:
545 stolen_size = MB(160);
546 break;
547 case SNB_GMCH_GMS_STOLEN_192M:
548 stolen_size = MB(192);
549 break;
550 case SNB_GMCH_GMS_STOLEN_224M:
551 stolen_size = MB(224);
552 break;
553 case SNB_GMCH_GMS_STOLEN_256M:
554 stolen_size = MB(256);
555 break;
556 case SNB_GMCH_GMS_STOLEN_288M:
557 stolen_size = MB(288);
558 break;
559 case SNB_GMCH_GMS_STOLEN_320M:
560 stolen_size = MB(320);
561 break;
562 case SNB_GMCH_GMS_STOLEN_352M:
563 stolen_size = MB(352);
564 break;
565 case SNB_GMCH_GMS_STOLEN_384M:
566 stolen_size = MB(384);
567 break;
568 case SNB_GMCH_GMS_STOLEN_416M:
569 stolen_size = MB(416);
570 break;
571 case SNB_GMCH_GMS_STOLEN_448M:
572 stolen_size = MB(448);
573 break;
574 case SNB_GMCH_GMS_STOLEN_480M:
575 stolen_size = MB(480);
576 break;
577 case SNB_GMCH_GMS_STOLEN_512M:
578 stolen_size = MB(512);
579 break;
580 }
581 } else {
582 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
583 case I855_GMCH_GMS_STOLEN_1M:
584 stolen_size = MB(1);
585 break;
586 case I855_GMCH_GMS_STOLEN_4M:
587 stolen_size = MB(4);
588 break;
589 case I855_GMCH_GMS_STOLEN_8M:
590 stolen_size = MB(8);
591 break;
592 case I855_GMCH_GMS_STOLEN_16M:
593 stolen_size = MB(16);
594 break;
595 case I855_GMCH_GMS_STOLEN_32M:
596 stolen_size = MB(32);
597 break;
598 case I915_GMCH_GMS_STOLEN_48M:
599 stolen_size = MB(48);
600 break;
601 case I915_GMCH_GMS_STOLEN_64M:
602 stolen_size = MB(64);
603 break;
604 case G33_GMCH_GMS_STOLEN_128M:
605 stolen_size = MB(128);
606 break;
607 case G33_GMCH_GMS_STOLEN_256M:
608 stolen_size = MB(256);
609 break;
610 case INTEL_GMCH_GMS_STOLEN_96M:
611 stolen_size = MB(96);
612 break;
613 case INTEL_GMCH_GMS_STOLEN_160M:
614 stolen_size = MB(160);
615 break;
616 case INTEL_GMCH_GMS_STOLEN_224M:
617 stolen_size = MB(224);
618 break;
619 case INTEL_GMCH_GMS_STOLEN_352M:
620 stolen_size = MB(352);
621 break;
622 default:
623 stolen_size = 0;
624 break;
625 }
626 }
627
628 if (!local && stolen_size > intel_max_stolen) {
629 dev_info(&intel_private.bridge_dev->dev,
630 "detected %dK stolen memory, trimming to %dK\n",
631 stolen_size / KB(1), intel_max_stolen / KB(1));
632 stolen_size = intel_max_stolen;
633 } else if (stolen_size > 0) {
634 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
635 stolen_size / KB(1), local ? "local" : "stolen");
636 } else {
637 dev_info(&intel_private.bridge_dev->dev,
638 "no pre-allocated video memory detected\n");
639 stolen_size = 0;
640 }
641
642 stolen_entries = stolen_size/KB(4) - overhead_entries;
643
644 return stolen_entries;
645 }
646
647 static void i965_adjust_pgetbl_size(unsigned int size_flag)
648 {
649 u32 pgetbl_ctl, pgetbl_ctl2;
650
651 /* ensure that ppgtt is disabled */
652 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
653 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
654 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
655
656 /* write the new ggtt size */
657 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
658 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
659 pgetbl_ctl |= size_flag;
660 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
661 }
662
663 static unsigned int i965_gtt_total_entries(void)
664 {
665 int size;
666 u32 pgetbl_ctl;
667 u16 gmch_ctl;
668
669 pci_read_config_word(intel_private.bridge_dev,
670 I830_GMCH_CTRL, &gmch_ctl);
671
672 if (INTEL_GTT_GEN == 5) {
673 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
674 case G4x_GMCH_SIZE_1M:
675 case G4x_GMCH_SIZE_VT_1M:
676 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
677 break;
678 case G4x_GMCH_SIZE_VT_1_5M:
679 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
680 break;
681 case G4x_GMCH_SIZE_2M:
682 case G4x_GMCH_SIZE_VT_2M:
683 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
684 break;
685 }
686 }
687
688 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
689
690 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
691 case I965_PGETBL_SIZE_128KB:
692 size = KB(128);
693 break;
694 case I965_PGETBL_SIZE_256KB:
695 size = KB(256);
696 break;
697 case I965_PGETBL_SIZE_512KB:
698 size = KB(512);
699 break;
700 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
701 case I965_PGETBL_SIZE_1MB:
702 size = KB(1024);
703 break;
704 case I965_PGETBL_SIZE_2MB:
705 size = KB(2048);
706 break;
707 case I965_PGETBL_SIZE_1_5MB:
708 size = KB(1024 + 512);
709 break;
710 default:
711 dev_info(&intel_private.pcidev->dev,
712 "unknown page table size, assuming 512KB\n");
713 size = KB(512);
714 }
715
716 return size/4;
717 }
718
719 static unsigned int intel_gtt_total_entries(void)
720 {
721 int size;
722
723 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
724 return i965_gtt_total_entries();
725 else if (INTEL_GTT_GEN == 6) {
726 u16 snb_gmch_ctl;
727
728 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
729 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
730 default:
731 case SNB_GTT_SIZE_0M:
732 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
733 size = MB(0);
734 break;
735 case SNB_GTT_SIZE_1M:
736 size = MB(1);
737 break;
738 case SNB_GTT_SIZE_2M:
739 size = MB(2);
740 break;
741 }
742 return size/4;
743 } else {
744 /* On previous hardware, the GTT size was just what was
745 * required to map the aperture.
746 */
747 return intel_private.base.gtt_mappable_entries;
748 }
749 }
750
751 static unsigned int intel_gtt_mappable_entries(void)
752 {
753 unsigned int aperture_size;
754
755 if (INTEL_GTT_GEN == 2) {
756 u16 gmch_ctrl;
757
758 pci_read_config_word(intel_private.bridge_dev,
759 I830_GMCH_CTRL, &gmch_ctrl);
760
761 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
762 aperture_size = MB(64);
763 else
764 aperture_size = MB(128);
765 } else {
766 /* 9xx supports large sizes, just look at the length */
767 aperture_size = pci_resource_len(intel_private.pcidev, 2);
768 }
769
770 return aperture_size >> PAGE_SHIFT;
771 }
772
773 static void intel_gtt_teardown_scratch_page(void)
774 {
775 set_pages_wb(intel_private.scratch_page, 1);
776 pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
777 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
778 put_page(intel_private.scratch_page);
779 __free_page(intel_private.scratch_page);
780 }
781
782 static void intel_gtt_cleanup(void)
783 {
784 intel_private.driver->cleanup();
785
786 iounmap(intel_private.gtt);
787 iounmap(intel_private.registers);
788
789 intel_gtt_teardown_scratch_page();
790 }
791
792 static int intel_gtt_init(void)
793 {
794 u32 gtt_map_size;
795 int ret;
796
797 ret = intel_private.driver->setup();
798 if (ret != 0)
799 return ret;
800
801 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
802 intel_private.base.gtt_total_entries = intel_gtt_total_entries();
803
804 /* save the PGETBL reg for resume */
805 intel_private.PGETBL_save =
806 readl(intel_private.registers+I810_PGETBL_CTL)
807 & ~I810_PGETBL_ENABLED;
808 /* we only ever restore the register when enabling the PGTBL... */
809 if (HAS_PGTBL_EN)
810 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
811
812 dev_info(&intel_private.bridge_dev->dev,
813 "detected gtt size: %dK total, %dK mappable\n",
814 intel_private.base.gtt_total_entries * 4,
815 intel_private.base.gtt_mappable_entries * 4);
816
817 gtt_map_size = intel_private.base.gtt_total_entries * 4;
818
819 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
820 gtt_map_size);
821 if (!intel_private.gtt) {
822 intel_private.driver->cleanup();
823 iounmap(intel_private.registers);
824 return -ENOMEM;
825 }
826
827 global_cache_flush(); /* FIXME: ? */
828
829 /* we have to call this as early as possible after the MMIO base address is known */
830 intel_private.base.gtt_stolen_entries = intel_gtt_stolen_entries();
831 if (intel_private.base.gtt_stolen_entries == 0) {
832 intel_private.driver->cleanup();
833 iounmap(intel_private.registers);
834 iounmap(intel_private.gtt);
835 return -ENOMEM;
836 }
837
838 ret = intel_gtt_setup_scratch_page();
839 if (ret != 0) {
840 intel_gtt_cleanup();
841 return ret;
842 }
843
844 return 0;
845 }
846
847 static int intel_fake_agp_fetch_size(void)
848 {
849 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
850 unsigned int aper_size;
851 int i;
852
853 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
854 / MB(1);
855
856 for (i = 0; i < num_sizes; i++) {
857 if (aper_size == intel_fake_agp_sizes[i].size) {
858 agp_bridge->current_size =
859 (void *) (intel_fake_agp_sizes + i);
860 return aper_size;
861 }
862 }
863
864 return 0;
865 }
866
867 static void i830_cleanup(void)
868 {
869 kunmap(intel_private.i8xx_page);
870 intel_private.i8xx_flush_page = NULL;
871
872 __free_page(intel_private.i8xx_page);
873 intel_private.i8xx_page = NULL;
874 }
875
876 static void intel_i830_setup_flush(void)
877 {
878 /* return if we've already set the flush mechanism up */
879 if (intel_private.i8xx_page)
880 return;
881
882 intel_private.i8xx_page = alloc_page(GFP_KERNEL);
883 if (!intel_private.i8xx_page)
884 return;
885
886 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
887 if (!intel_private.i8xx_flush_page)
888 i830_cleanup();
889 }
890
891 /* The chipset_flush interface needs to get data that has already been
892 * flushed out of the CPU all the way out to main memory, because the GPU
893 * doesn't snoop those buffers.
894 *
895 * The 8xx series doesn't have the same lovely interface for flushing the
896 * chipset write buffers that the later chips do. According to the 865
897 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
898 * that buffer out, we just fill 1KB and clflush it out, on the assumption
899 * that it'll push whatever was in there out. It appears to work.
900 */
901 static void i830_chipset_flush(void)
902 {
903 unsigned int *pg = intel_private.i8xx_flush_page;
904
905 memset(pg, 0, 1024);
906
907 if (cpu_has_clflush)
908 clflush_cache_range(pg, 1024);
909 else if (wbinvd_on_all_cpus() != 0)
910 printk(KERN_ERR "Timed out waiting for cache flush.\n");
911 }
912
913 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
914 unsigned int flags)
915 {
916 u32 pte_flags = I810_PTE_VALID;
917
918 switch (flags) {
919 case AGP_DCACHE_MEMORY:
920 pte_flags |= I810_PTE_LOCAL;
921 break;
922 case AGP_USER_CACHED_MEMORY:
923 pte_flags |= I830_PTE_SYSTEM_CACHED;
924 break;
925 }
926
927 writel(addr | pte_flags, intel_private.gtt + entry);
928 }
929
930 static bool intel_enable_gtt(void)
931 {
932 u32 gma_addr;
933 u8 __iomem *reg;
934
935 if (INTEL_GTT_GEN == 2)
936 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
937 &gma_addr);
938 else
939 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
940 &gma_addr);
941
942 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
943
944 if (INTEL_GTT_GEN >= 6)
945 return true;
946
947 if (INTEL_GTT_GEN == 2) {
948 u16 gmch_ctrl;
949
950 pci_read_config_word(intel_private.bridge_dev,
951 I830_GMCH_CTRL, &gmch_ctrl);
952 gmch_ctrl |= I830_GMCH_ENABLED;
953 pci_write_config_word(intel_private.bridge_dev,
954 I830_GMCH_CTRL, gmch_ctrl);
955
956 pci_read_config_word(intel_private.bridge_dev,
957 I830_GMCH_CTRL, &gmch_ctrl);
958 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
959 dev_err(&intel_private.pcidev->dev,
960 "failed to enable the GTT: GMCH_CTRL=%x\n",
961 gmch_ctrl);
962 return false;
963 }
964 }
965
966 reg = intel_private.registers+I810_PGETBL_CTL;
967 writel(intel_private.PGETBL_save, reg);
968 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
969 dev_err(&intel_private.pcidev->dev,
970 "failed to enable the GTT: PGETBL=%x [expected %x]\n",
971 readl(reg), intel_private.PGETBL_save);
972 return false;
973 }
974
975 return true;
976 }
977
978 static int i830_setup(void)
979 {
980 u32 reg_addr;
981
982 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
983 reg_addr &= 0xfff80000;
984
985 intel_private.registers = ioremap(reg_addr, KB(64));
986 if (!intel_private.registers)
987 return -ENOMEM;
988
989 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
990
991 intel_i830_setup_flush();
992
993 return 0;
994 }
995
996 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
997 {
998 agp_bridge->gatt_table_real = NULL;
999 agp_bridge->gatt_table = NULL;
1000 agp_bridge->gatt_bus_addr = 0;
1001
1002 return 0;
1003 }
1004
1005 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
1006 {
1007 return 0;
1008 }
1009
1010 static int intel_fake_agp_configure(void)
1011 {
1012 int i;
1013
1014 if (!intel_enable_gtt())
1015 return -EIO;
1016
1017 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
1018
1019 for (i = intel_private.base.gtt_stolen_entries;
1020 i < intel_private.base.gtt_total_entries; i++) {
1021 intel_private.driver->write_entry(intel_private.scratch_page_dma,
1022 i, 0);
1023 }
1024 readl(intel_private.gtt+i-1); /* PCI Posting. */
1025
1026 global_cache_flush();
1027
1028 return 0;
1029 }
1030
1031 static bool i830_check_flags(unsigned int flags)
1032 {
1033 switch (flags) {
1034 case 0:
1035 case AGP_PHYS_MEMORY:
1036 case AGP_USER_CACHED_MEMORY:
1037 case AGP_USER_MEMORY:
1038 return true;
1039 }
1040
1041 return false;
1042 }
1043
1044 static void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
1045 unsigned int sg_len,
1046 unsigned int pg_start,
1047 unsigned int flags)
1048 {
1049 struct scatterlist *sg;
1050 unsigned int len, m;
1051 int i, j;
1052
1053 j = pg_start;
1054
1055 /* sg may merge pages, but we have to separate
1056 * per-page addr for GTT */
1057 for_each_sg(sg_list, sg, sg_len, i) {
1058 len = sg_dma_len(sg) >> PAGE_SHIFT;
1059 for (m = 0; m < len; m++) {
1060 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
1061 intel_private.driver->write_entry(addr,
1062 j, flags);
1063 j++;
1064 }
1065 }
1066 readl(intel_private.gtt+j-1);
1067 }
1068
1069 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
1070 off_t pg_start, int type)
1071 {
1072 int i, j;
1073 int ret = -EINVAL;
1074
1075 if (mem->page_count == 0)
1076 goto out;
1077
1078 if (pg_start < intel_private.base.gtt_stolen_entries) {
1079 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1080 "pg_start == 0x%.8lx, gtt_stolen_entries == 0x%.8x\n",
1081 pg_start, intel_private.base.gtt_stolen_entries);
1082
1083 dev_info(&intel_private.pcidev->dev,
1084 "trying to insert into local/stolen memory\n");
1085 goto out_err;
1086 }
1087
1088 if ((pg_start + mem->page_count) > intel_private.base.gtt_total_entries)
1089 goto out_err;
1090
1091 if (type != mem->type)
1092 goto out_err;
1093
1094 if (!intel_private.driver->check_flags(type))
1095 goto out_err;
1096
1097 if (!mem->is_flushed)
1098 global_cache_flush();
1099
1100 if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) {
1101 ret = intel_agp_map_memory(mem);
1102 if (ret != 0)
1103 return ret;
1104
1105 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg,
1106 pg_start, type);
1107 } else {
1108 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1109 dma_addr_t addr = page_to_phys(mem->pages[i]);
1110 intel_private.driver->write_entry(addr,
1111 j, type);
1112 }
1113 readl(intel_private.gtt+j-1);
1114 }
1115
1116 out:
1117 ret = 0;
1118 out_err:
1119 mem->is_flushed = true;
1120 return ret;
1121 }
1122
1123 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
1124 off_t pg_start, int type)
1125 {
1126 int i;
1127
1128 if (mem->page_count == 0)
1129 return 0;
1130
1131 if (pg_start < intel_private.base.gtt_stolen_entries) {
1132 dev_info(&intel_private.pcidev->dev,
1133 "trying to disable local/stolen memory\n");
1134 return -EINVAL;
1135 }
1136
1137 if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2)
1138 intel_agp_unmap_memory(mem);
1139
1140 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1141 intel_private.driver->write_entry(intel_private.scratch_page_dma,
1142 i, 0);
1143 }
1144 readl(intel_private.gtt+i-1);
1145
1146 return 0;
1147 }
1148
1149 static void intel_fake_agp_chipset_flush(struct agp_bridge_data *bridge)
1150 {
1151 intel_private.driver->chipset_flush();
1152 }
1153
1154 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
1155 int type)
1156 {
1157 if (type == AGP_PHYS_MEMORY)
1158 return alloc_agpphysmem_i8xx(pg_count, type);
1159 /* always return NULL for other allocation types for now */
1160 return NULL;
1161 }
1162
1163 static int intel_alloc_chipset_flush_resource(void)
1164 {
1165 int ret;
1166 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1167 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1168 pcibios_align_resource, intel_private.bridge_dev);
1169
1170 return ret;
1171 }
1172
1173 static void intel_i915_setup_chipset_flush(void)
1174 {
1175 int ret;
1176 u32 temp;
1177
1178 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1179 if (!(temp & 0x1)) {
1180 intel_alloc_chipset_flush_resource();
1181 intel_private.resource_valid = 1;
1182 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1183 } else {
1184 temp &= ~1;
1185
1186 intel_private.resource_valid = 1;
1187 intel_private.ifp_resource.start = temp;
1188 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1189 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1190 /* some BIOSes reserve this area in a pnp some don't */
1191 if (ret)
1192 intel_private.resource_valid = 0;
1193 }
1194 }
1195
1196 static void intel_i965_g33_setup_chipset_flush(void)
1197 {
1198 u32 temp_hi, temp_lo;
1199 int ret;
1200
1201 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1202 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1203
1204 if (!(temp_lo & 0x1)) {
1205
1206 intel_alloc_chipset_flush_resource();
1207
1208 intel_private.resource_valid = 1;
1209 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1210 upper_32_bits(intel_private.ifp_resource.start));
1211 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1212 } else {
1213 u64 l64;
1214
1215 temp_lo &= ~0x1;
1216 l64 = ((u64)temp_hi << 32) | temp_lo;
1217
1218 intel_private.resource_valid = 1;
1219 intel_private.ifp_resource.start = l64;
1220 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1221 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1222 /* some BIOSes reserve this area in a pnp some don't */
1223 if (ret)
1224 intel_private.resource_valid = 0;
1225 }
1226 }
1227
1228 static void intel_i9xx_setup_flush(void)
1229 {
1230 /* return if already configured */
1231 if (intel_private.ifp_resource.start)
1232 return;
1233
1234 if (INTEL_GTT_GEN == 6)
1235 return;
1236
1237 /* setup a resource for this object */
1238 intel_private.ifp_resource.name = "Intel Flush Page";
1239 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1240
1241 /* Setup chipset flush for 915 */
1242 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1243 intel_i965_g33_setup_chipset_flush();
1244 } else {
1245 intel_i915_setup_chipset_flush();
1246 }
1247
1248 if (intel_private.ifp_resource.start)
1249 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1250 if (!intel_private.i9xx_flush_page)
1251 dev_err(&intel_private.pcidev->dev,
1252 "can't ioremap flush page - no chipset flushing\n");
1253 }
1254
1255 static void i9xx_cleanup(void)
1256 {
1257 if (intel_private.i9xx_flush_page)
1258 iounmap(intel_private.i9xx_flush_page);
1259 if (intel_private.resource_valid)
1260 release_resource(&intel_private.ifp_resource);
1261 intel_private.ifp_resource.start = 0;
1262 intel_private.resource_valid = 0;
1263 }
1264
1265 static void i9xx_chipset_flush(void)
1266 {
1267 if (intel_private.i9xx_flush_page)
1268 writel(1, intel_private.i9xx_flush_page);
1269 }
1270
1271 static void i965_write_entry(dma_addr_t addr, unsigned int entry,
1272 unsigned int flags)
1273 {
1274 /* Shift high bits down */
1275 addr |= (addr >> 28) & 0xf0;
1276 writel(addr | I810_PTE_VALID, intel_private.gtt + entry);
1277 }
1278
1279 static bool gen6_check_flags(unsigned int flags)
1280 {
1281 return true;
1282 }
1283
1284 static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1285 unsigned int flags)
1286 {
1287 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1288 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1289 u32 pte_flags;
1290
1291 if (type_mask == AGP_USER_MEMORY)
1292 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1293 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1294 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1295 if (gfdt)
1296 pte_flags |= GEN6_PTE_GFDT;
1297 } else { /* set 'normal'/'cached' to LLC by default */
1298 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1299 if (gfdt)
1300 pte_flags |= GEN6_PTE_GFDT;
1301 }
1302
1303 /* gen6 has bit11-4 for physical addr bit39-32 */
1304 addr |= (addr >> 28) & 0xff0;
1305 writel(addr | pte_flags, intel_private.gtt + entry);
1306 }
1307
1308 static void gen6_cleanup(void)
1309 {
1310 }
1311
1312 static int i9xx_setup(void)
1313 {
1314 u32 reg_addr;
1315
1316 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1317
1318 reg_addr &= 0xfff80000;
1319
1320 intel_private.registers = ioremap(reg_addr, 128 * 4096);
1321 if (!intel_private.registers)
1322 return -ENOMEM;
1323
1324 if (INTEL_GTT_GEN == 3) {
1325 u32 gtt_addr;
1326
1327 pci_read_config_dword(intel_private.pcidev,
1328 I915_PTEADDR, &gtt_addr);
1329 intel_private.gtt_bus_addr = gtt_addr;
1330 } else {
1331 u32 gtt_offset;
1332
1333 switch (INTEL_GTT_GEN) {
1334 case 5:
1335 case 6:
1336 gtt_offset = MB(2);
1337 break;
1338 case 4:
1339 default:
1340 gtt_offset = KB(512);
1341 break;
1342 }
1343 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1344 }
1345
1346 intel_i9xx_setup_flush();
1347
1348 return 0;
1349 }
1350
1351 static const struct agp_bridge_driver intel_810_driver = {
1352 .owner = THIS_MODULE,
1353 .aperture_sizes = intel_i810_sizes,
1354 .size_type = FIXED_APER_SIZE,
1355 .num_aperture_sizes = 2,
1356 .needs_scratch_page = true,
1357 .configure = intel_i810_configure,
1358 .fetch_size = intel_i810_fetch_size,
1359 .cleanup = intel_i810_cleanup,
1360 .mask_memory = intel_i810_mask_memory,
1361 .masks = intel_i810_masks,
1362 .agp_enable = intel_fake_agp_enable,
1363 .cache_flush = global_cache_flush,
1364 .create_gatt_table = agp_generic_create_gatt_table,
1365 .free_gatt_table = agp_generic_free_gatt_table,
1366 .insert_memory = intel_i810_insert_entries,
1367 .remove_memory = intel_i810_remove_entries,
1368 .alloc_by_type = intel_i810_alloc_by_type,
1369 .free_by_type = intel_i810_free_by_type,
1370 .agp_alloc_page = agp_generic_alloc_page,
1371 .agp_alloc_pages = agp_generic_alloc_pages,
1372 .agp_destroy_page = agp_generic_destroy_page,
1373 .agp_destroy_pages = agp_generic_destroy_pages,
1374 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1375 };
1376
1377 static const struct agp_bridge_driver intel_fake_agp_driver = {
1378 .owner = THIS_MODULE,
1379 .size_type = FIXED_APER_SIZE,
1380 .aperture_sizes = intel_fake_agp_sizes,
1381 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1382 .configure = intel_fake_agp_configure,
1383 .fetch_size = intel_fake_agp_fetch_size,
1384 .cleanup = intel_gtt_cleanup,
1385 .agp_enable = intel_fake_agp_enable,
1386 .cache_flush = global_cache_flush,
1387 .create_gatt_table = intel_fake_agp_create_gatt_table,
1388 .free_gatt_table = intel_fake_agp_free_gatt_table,
1389 .insert_memory = intel_fake_agp_insert_entries,
1390 .remove_memory = intel_fake_agp_remove_entries,
1391 .alloc_by_type = intel_fake_agp_alloc_by_type,
1392 .free_by_type = intel_i810_free_by_type,
1393 .agp_alloc_page = agp_generic_alloc_page,
1394 .agp_alloc_pages = agp_generic_alloc_pages,
1395 .agp_destroy_page = agp_generic_destroy_page,
1396 .agp_destroy_pages = agp_generic_destroy_pages,
1397 .chipset_flush = intel_fake_agp_chipset_flush,
1398 };
1399
1400 static const struct intel_gtt_driver i81x_gtt_driver = {
1401 .gen = 1,
1402 .dma_mask_size = 32,
1403 };
1404 static const struct intel_gtt_driver i8xx_gtt_driver = {
1405 .gen = 2,
1406 .has_pgtbl_enable = 1,
1407 .setup = i830_setup,
1408 .cleanup = i830_cleanup,
1409 .write_entry = i830_write_entry,
1410 .dma_mask_size = 32,
1411 .check_flags = i830_check_flags,
1412 .chipset_flush = i830_chipset_flush,
1413 };
1414 static const struct intel_gtt_driver i915_gtt_driver = {
1415 .gen = 3,
1416 .has_pgtbl_enable = 1,
1417 .setup = i9xx_setup,
1418 .cleanup = i9xx_cleanup,
1419 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1420 .write_entry = i830_write_entry,
1421 .dma_mask_size = 32,
1422 .check_flags = i830_check_flags,
1423 .chipset_flush = i9xx_chipset_flush,
1424 };
1425 static const struct intel_gtt_driver g33_gtt_driver = {
1426 .gen = 3,
1427 .is_g33 = 1,
1428 .setup = i9xx_setup,
1429 .cleanup = i9xx_cleanup,
1430 .write_entry = i965_write_entry,
1431 .dma_mask_size = 36,
1432 .check_flags = i830_check_flags,
1433 .chipset_flush = i9xx_chipset_flush,
1434 };
1435 static const struct intel_gtt_driver pineview_gtt_driver = {
1436 .gen = 3,
1437 .is_pineview = 1, .is_g33 = 1,
1438 .setup = i9xx_setup,
1439 .cleanup = i9xx_cleanup,
1440 .write_entry = i965_write_entry,
1441 .dma_mask_size = 36,
1442 .check_flags = i830_check_flags,
1443 .chipset_flush = i9xx_chipset_flush,
1444 };
1445 static const struct intel_gtt_driver i965_gtt_driver = {
1446 .gen = 4,
1447 .has_pgtbl_enable = 1,
1448 .setup = i9xx_setup,
1449 .cleanup = i9xx_cleanup,
1450 .write_entry = i965_write_entry,
1451 .dma_mask_size = 36,
1452 .check_flags = i830_check_flags,
1453 .chipset_flush = i9xx_chipset_flush,
1454 };
1455 static const struct intel_gtt_driver g4x_gtt_driver = {
1456 .gen = 5,
1457 .setup = i9xx_setup,
1458 .cleanup = i9xx_cleanup,
1459 .write_entry = i965_write_entry,
1460 .dma_mask_size = 36,
1461 .check_flags = i830_check_flags,
1462 .chipset_flush = i9xx_chipset_flush,
1463 };
1464 static const struct intel_gtt_driver ironlake_gtt_driver = {
1465 .gen = 5,
1466 .is_ironlake = 1,
1467 .setup = i9xx_setup,
1468 .cleanup = i9xx_cleanup,
1469 .write_entry = i965_write_entry,
1470 .dma_mask_size = 36,
1471 .check_flags = i830_check_flags,
1472 .chipset_flush = i9xx_chipset_flush,
1473 };
1474 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1475 .gen = 6,
1476 .setup = i9xx_setup,
1477 .cleanup = gen6_cleanup,
1478 .write_entry = gen6_write_entry,
1479 .dma_mask_size = 40,
1480 .check_flags = gen6_check_flags,
1481 .chipset_flush = i9xx_chipset_flush,
1482 };
1483
1484 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1485 * driver and gmch_driver must be non-null, and find_gmch will determine
1486 * which one should be used if a gmch_chip_id is present.
1487 */
1488 static const struct intel_gtt_driver_description {
1489 unsigned int gmch_chip_id;
1490 char *name;
1491 const struct agp_bridge_driver *gmch_driver;
1492 const struct intel_gtt_driver *gtt_driver;
1493 } intel_gtt_chipsets[] = {
1494 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", &intel_810_driver,
1495 &i81x_gtt_driver},
1496 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", &intel_810_driver,
1497 &i81x_gtt_driver},
1498 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", &intel_810_driver,
1499 &i81x_gtt_driver},
1500 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", &intel_810_driver,
1501 &i81x_gtt_driver},
1502 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1503 &intel_fake_agp_driver, &i8xx_gtt_driver},
1504 { PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1505 &intel_fake_agp_driver, &i8xx_gtt_driver},
1506 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1507 &intel_fake_agp_driver, &i8xx_gtt_driver},
1508 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1509 &intel_fake_agp_driver, &i8xx_gtt_driver},
1510 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1511 &intel_fake_agp_driver, &i8xx_gtt_driver},
1512 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1513 &intel_fake_agp_driver, &i915_gtt_driver },
1514 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1515 &intel_fake_agp_driver, &i915_gtt_driver },
1516 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1517 &intel_fake_agp_driver, &i915_gtt_driver },
1518 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1519 &intel_fake_agp_driver, &i915_gtt_driver },
1520 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1521 &intel_fake_agp_driver, &i915_gtt_driver },
1522 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1523 &intel_fake_agp_driver, &i915_gtt_driver },
1524 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1525 &intel_fake_agp_driver, &i965_gtt_driver },
1526 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1527 &intel_fake_agp_driver, &i965_gtt_driver },
1528 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1529 &intel_fake_agp_driver, &i965_gtt_driver },
1530 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1531 &intel_fake_agp_driver, &i965_gtt_driver },
1532 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1533 &intel_fake_agp_driver, &i965_gtt_driver },
1534 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1535 &intel_fake_agp_driver, &i965_gtt_driver },
1536 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1537 &intel_fake_agp_driver, &g33_gtt_driver },
1538 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1539 &intel_fake_agp_driver, &g33_gtt_driver },
1540 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1541 &intel_fake_agp_driver, &g33_gtt_driver },
1542 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1543 &intel_fake_agp_driver, &pineview_gtt_driver },
1544 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1545 &intel_fake_agp_driver, &pineview_gtt_driver },
1546 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1547 &intel_fake_agp_driver, &g4x_gtt_driver },
1548 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1549 &intel_fake_agp_driver, &g4x_gtt_driver },
1550 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1551 &intel_fake_agp_driver, &g4x_gtt_driver },
1552 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1553 &intel_fake_agp_driver, &g4x_gtt_driver },
1554 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1555 &intel_fake_agp_driver, &g4x_gtt_driver },
1556 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1557 &intel_fake_agp_driver, &g4x_gtt_driver },
1558 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1559 &intel_fake_agp_driver, &g4x_gtt_driver },
1560 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1561 "HD Graphics", &intel_fake_agp_driver, &ironlake_gtt_driver },
1562 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1563 "HD Graphics", &intel_fake_agp_driver, &ironlake_gtt_driver },
1564 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1565 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1566 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1567 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1568 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1569 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1570 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1571 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1572 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1573 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1574 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1575 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1576 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1577 "Sandybridge", &intel_fake_agp_driver, &sandybridge_gtt_driver },
1578 { 0, NULL, NULL }
1579 };
1580
1581 static int find_gmch(u16 device)
1582 {
1583 struct pci_dev *gmch_device;
1584
1585 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1586 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1587 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1588 device, gmch_device);
1589 }
1590
1591 if (!gmch_device)
1592 return 0;
1593
1594 intel_private.pcidev = gmch_device;
1595 return 1;
1596 }
1597
1598 int intel_gmch_probe(struct pci_dev *pdev,
1599 struct agp_bridge_data *bridge)
1600 {
1601 int i, mask;
1602 bridge->driver = NULL;
1603
1604 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1605 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1606 bridge->driver =
1607 intel_gtt_chipsets[i].gmch_driver;
1608 intel_private.driver =
1609 intel_gtt_chipsets[i].gtt_driver;
1610 break;
1611 }
1612 }
1613
1614 if (!bridge->driver)
1615 return 0;
1616
1617 bridge->dev_private_data = &intel_private;
1618 bridge->dev = pdev;
1619
1620 intel_private.bridge_dev = pci_dev_get(pdev);
1621
1622 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1623
1624 mask = intel_private.driver->dma_mask_size;
1625 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1626 dev_err(&intel_private.pcidev->dev,
1627 "set gfx device dma mask %d-bit failed!\n", mask);
1628 else
1629 pci_set_consistent_dma_mask(intel_private.pcidev,
1630 DMA_BIT_MASK(mask));
1631
1632 if (bridge->driver == &intel_810_driver)
1633 return 1;
1634
1635 if (intel_gtt_init() != 0)
1636 return 0;
1637
1638 return 1;
1639 }
1640 EXPORT_SYMBOL(intel_gmch_probe);
1641
1642 struct intel_gtt *intel_gtt_get(void)
1643 {
1644 return &intel_private.base;
1645 }
1646 EXPORT_SYMBOL(intel_gtt_get);
1647
1648 void intel_gmch_remove(struct pci_dev *pdev)
1649 {
1650 if (intel_private.pcidev)
1651 pci_dev_put(intel_private.pcidev);
1652 if (intel_private.bridge_dev)
1653 pci_dev_put(intel_private.bridge_dev);
1654 }
1655 EXPORT_SYMBOL(intel_gmch_remove);
1656
1657 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1658 MODULE_LICENSE("GPL and additional rights");
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