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Merge branch 'slab/next' into slab/for-linus
[mirror_ubuntu-jammy-kernel.git] / drivers / char / agp / intel-gtt.c
1 /*
2 * Intel GTT (Graphics Translation Table) routines
3 *
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
10 *
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
13 * here.
14 *
15 * /fairy-tale-mode off
16 */
17
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <linux/delay.h>
25 #include <asm/smp.h>
26 #include "agp.h"
27 #include "intel-agp.h"
28 #include <drm/intel-gtt.h>
29
30 /*
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
34 * Only newer chipsets need to bother with this, of course.
35 */
36 #ifdef CONFIG_INTEL_IOMMU
37 #define USE_PCI_DMA_API 1
38 #else
39 #define USE_PCI_DMA_API 0
40 #endif
41
42 struct intel_gtt_driver {
43 unsigned int gen : 8;
44 unsigned int is_g33 : 1;
45 unsigned int is_pineview : 1;
46 unsigned int is_ironlake : 1;
47 unsigned int has_pgtbl_enable : 1;
48 unsigned int dma_mask_size : 8;
49 /* Chipset specific GTT setup */
50 int (*setup)(void);
51 /* This should undo anything done in ->setup() save the unmapping
52 * of the mmio register file, that's done in the generic code. */
53 void (*cleanup)(void);
54 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
55 /* Flags is a more or less chipset specific opaque value.
56 * For chipsets that need to support old ums (non-gem) code, this
57 * needs to be identical to the various supported agp memory types! */
58 bool (*check_flags)(unsigned int flags);
59 void (*chipset_flush)(void);
60 };
61
62 static struct _intel_private {
63 const struct intel_gtt_driver *driver;
64 struct pci_dev *pcidev; /* device one */
65 struct pci_dev *bridge_dev;
66 u8 __iomem *registers;
67 phys_addr_t gtt_bus_addr;
68 u32 PGETBL_save;
69 u32 __iomem *gtt; /* I915G */
70 bool clear_fake_agp; /* on first access via agp, fill with scratch */
71 int num_dcache_entries;
72 void __iomem *i9xx_flush_page;
73 char *i81x_gtt_table;
74 struct resource ifp_resource;
75 int resource_valid;
76 struct page *scratch_page;
77 phys_addr_t scratch_page_dma;
78 int refcount;
79 /* Whether i915 needs to use the dmar apis or not. */
80 unsigned int needs_dmar : 1;
81 phys_addr_t gma_bus_addr;
82 /* Size of memory reserved for graphics by the BIOS */
83 unsigned int stolen_size;
84 /* Total number of gtt entries. */
85 unsigned int gtt_total_entries;
86 /* Part of the gtt that is mappable by the cpu, for those chips where
87 * this is not the full gtt. */
88 unsigned int gtt_mappable_entries;
89 } intel_private;
90
91 #define INTEL_GTT_GEN intel_private.driver->gen
92 #define IS_G33 intel_private.driver->is_g33
93 #define IS_PINEVIEW intel_private.driver->is_pineview
94 #define IS_IRONLAKE intel_private.driver->is_ironlake
95 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
96
97 static int intel_gtt_map_memory(struct page **pages,
98 unsigned int num_entries,
99 struct sg_table *st)
100 {
101 struct scatterlist *sg;
102 int i;
103
104 DBG("try mapping %lu pages\n", (unsigned long)num_entries);
105
106 if (sg_alloc_table(st, num_entries, GFP_KERNEL))
107 goto err;
108
109 for_each_sg(st->sgl, sg, num_entries, i)
110 sg_set_page(sg, pages[i], PAGE_SIZE, 0);
111
112 if (!pci_map_sg(intel_private.pcidev,
113 st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL))
114 goto err;
115
116 return 0;
117
118 err:
119 sg_free_table(st);
120 return -ENOMEM;
121 }
122
123 static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg)
124 {
125 struct sg_table st;
126 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
127
128 pci_unmap_sg(intel_private.pcidev, sg_list,
129 num_sg, PCI_DMA_BIDIRECTIONAL);
130
131 st.sgl = sg_list;
132 st.orig_nents = st.nents = num_sg;
133
134 sg_free_table(&st);
135 }
136
137 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
138 {
139 return;
140 }
141
142 /* Exists to support ARGB cursors */
143 static struct page *i8xx_alloc_pages(void)
144 {
145 struct page *page;
146
147 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
148 if (page == NULL)
149 return NULL;
150
151 if (set_pages_uc(page, 4) < 0) {
152 set_pages_wb(page, 4);
153 __free_pages(page, 2);
154 return NULL;
155 }
156 get_page(page);
157 atomic_inc(&agp_bridge->current_memory_agp);
158 return page;
159 }
160
161 static void i8xx_destroy_pages(struct page *page)
162 {
163 if (page == NULL)
164 return;
165
166 set_pages_wb(page, 4);
167 put_page(page);
168 __free_pages(page, 2);
169 atomic_dec(&agp_bridge->current_memory_agp);
170 }
171
172 #define I810_GTT_ORDER 4
173 static int i810_setup(void)
174 {
175 u32 reg_addr;
176 char *gtt_table;
177
178 /* i81x does not preallocate the gtt. It's always 64kb in size. */
179 gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
180 if (gtt_table == NULL)
181 return -ENOMEM;
182 intel_private.i81x_gtt_table = gtt_table;
183
184 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
185 reg_addr &= 0xfff80000;
186
187 intel_private.registers = ioremap(reg_addr, KB(64));
188 if (!intel_private.registers)
189 return -ENOMEM;
190
191 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
192 intel_private.registers+I810_PGETBL_CTL);
193
194 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
195
196 if ((readl(intel_private.registers+I810_DRAM_CTL)
197 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
198 dev_info(&intel_private.pcidev->dev,
199 "detected 4MB dedicated video ram\n");
200 intel_private.num_dcache_entries = 1024;
201 }
202
203 return 0;
204 }
205
206 static void i810_cleanup(void)
207 {
208 writel(0, intel_private.registers+I810_PGETBL_CTL);
209 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
210 }
211
212 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
213 int type)
214 {
215 int i;
216
217 if ((pg_start + mem->page_count)
218 > intel_private.num_dcache_entries)
219 return -EINVAL;
220
221 if (!mem->is_flushed)
222 global_cache_flush();
223
224 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
225 dma_addr_t addr = i << PAGE_SHIFT;
226 intel_private.driver->write_entry(addr,
227 i, type);
228 }
229 readl(intel_private.gtt+i-1);
230
231 return 0;
232 }
233
234 /*
235 * The i810/i830 requires a physical address to program its mouse
236 * pointer into hardware.
237 * However the Xserver still writes to it through the agp aperture.
238 */
239 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
240 {
241 struct agp_memory *new;
242 struct page *page;
243
244 switch (pg_count) {
245 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
246 break;
247 case 4:
248 /* kludge to get 4 physical pages for ARGB cursor */
249 page = i8xx_alloc_pages();
250 break;
251 default:
252 return NULL;
253 }
254
255 if (page == NULL)
256 return NULL;
257
258 new = agp_create_memory(pg_count);
259 if (new == NULL)
260 return NULL;
261
262 new->pages[0] = page;
263 if (pg_count == 4) {
264 /* kludge to get 4 physical pages for ARGB cursor */
265 new->pages[1] = new->pages[0] + 1;
266 new->pages[2] = new->pages[1] + 1;
267 new->pages[3] = new->pages[2] + 1;
268 }
269 new->page_count = pg_count;
270 new->num_scratch_pages = pg_count;
271 new->type = AGP_PHYS_MEMORY;
272 new->physical = page_to_phys(new->pages[0]);
273 return new;
274 }
275
276 static void intel_i810_free_by_type(struct agp_memory *curr)
277 {
278 agp_free_key(curr->key);
279 if (curr->type == AGP_PHYS_MEMORY) {
280 if (curr->page_count == 4)
281 i8xx_destroy_pages(curr->pages[0]);
282 else {
283 agp_bridge->driver->agp_destroy_page(curr->pages[0],
284 AGP_PAGE_DESTROY_UNMAP);
285 agp_bridge->driver->agp_destroy_page(curr->pages[0],
286 AGP_PAGE_DESTROY_FREE);
287 }
288 agp_free_page_array(curr);
289 }
290 kfree(curr);
291 }
292
293 static int intel_gtt_setup_scratch_page(void)
294 {
295 struct page *page;
296 dma_addr_t dma_addr;
297
298 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
299 if (page == NULL)
300 return -ENOMEM;
301 get_page(page);
302 set_pages_uc(page, 1);
303
304 if (intel_private.needs_dmar) {
305 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
306 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
307 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
308 return -EINVAL;
309
310 intel_private.scratch_page_dma = dma_addr;
311 } else
312 intel_private.scratch_page_dma = page_to_phys(page);
313
314 intel_private.scratch_page = page;
315
316 return 0;
317 }
318
319 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
320 unsigned int flags)
321 {
322 u32 pte_flags = I810_PTE_VALID;
323
324 switch (flags) {
325 case AGP_DCACHE_MEMORY:
326 pte_flags |= I810_PTE_LOCAL;
327 break;
328 case AGP_USER_CACHED_MEMORY:
329 pte_flags |= I830_PTE_SYSTEM_CACHED;
330 break;
331 }
332
333 writel(addr | pte_flags, intel_private.gtt + entry);
334 }
335
336 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = {
337 {32, 8192, 3},
338 {64, 16384, 4},
339 {128, 32768, 5},
340 {256, 65536, 6},
341 {512, 131072, 7},
342 };
343
344 static unsigned int intel_gtt_stolen_size(void)
345 {
346 u16 gmch_ctrl;
347 u8 rdct;
348 int local = 0;
349 static const int ddt[4] = { 0, 16, 32, 64 };
350 unsigned int stolen_size = 0;
351
352 if (INTEL_GTT_GEN == 1)
353 return 0; /* no stolen mem on i81x */
354
355 pci_read_config_word(intel_private.bridge_dev,
356 I830_GMCH_CTRL, &gmch_ctrl);
357
358 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
359 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
360 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
361 case I830_GMCH_GMS_STOLEN_512:
362 stolen_size = KB(512);
363 break;
364 case I830_GMCH_GMS_STOLEN_1024:
365 stolen_size = MB(1);
366 break;
367 case I830_GMCH_GMS_STOLEN_8192:
368 stolen_size = MB(8);
369 break;
370 case I830_GMCH_GMS_LOCAL:
371 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
372 stolen_size = (I830_RDRAM_ND(rdct) + 1) *
373 MB(ddt[I830_RDRAM_DDT(rdct)]);
374 local = 1;
375 break;
376 default:
377 stolen_size = 0;
378 break;
379 }
380 } else {
381 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
382 case I855_GMCH_GMS_STOLEN_1M:
383 stolen_size = MB(1);
384 break;
385 case I855_GMCH_GMS_STOLEN_4M:
386 stolen_size = MB(4);
387 break;
388 case I855_GMCH_GMS_STOLEN_8M:
389 stolen_size = MB(8);
390 break;
391 case I855_GMCH_GMS_STOLEN_16M:
392 stolen_size = MB(16);
393 break;
394 case I855_GMCH_GMS_STOLEN_32M:
395 stolen_size = MB(32);
396 break;
397 case I915_GMCH_GMS_STOLEN_48M:
398 stolen_size = MB(48);
399 break;
400 case I915_GMCH_GMS_STOLEN_64M:
401 stolen_size = MB(64);
402 break;
403 case G33_GMCH_GMS_STOLEN_128M:
404 stolen_size = MB(128);
405 break;
406 case G33_GMCH_GMS_STOLEN_256M:
407 stolen_size = MB(256);
408 break;
409 case INTEL_GMCH_GMS_STOLEN_96M:
410 stolen_size = MB(96);
411 break;
412 case INTEL_GMCH_GMS_STOLEN_160M:
413 stolen_size = MB(160);
414 break;
415 case INTEL_GMCH_GMS_STOLEN_224M:
416 stolen_size = MB(224);
417 break;
418 case INTEL_GMCH_GMS_STOLEN_352M:
419 stolen_size = MB(352);
420 break;
421 default:
422 stolen_size = 0;
423 break;
424 }
425 }
426
427 if (stolen_size > 0) {
428 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
429 stolen_size / KB(1), local ? "local" : "stolen");
430 } else {
431 dev_info(&intel_private.bridge_dev->dev,
432 "no pre-allocated video memory detected\n");
433 stolen_size = 0;
434 }
435
436 return stolen_size;
437 }
438
439 static void i965_adjust_pgetbl_size(unsigned int size_flag)
440 {
441 u32 pgetbl_ctl, pgetbl_ctl2;
442
443 /* ensure that ppgtt is disabled */
444 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
445 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
446 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
447
448 /* write the new ggtt size */
449 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
450 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
451 pgetbl_ctl |= size_flag;
452 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
453 }
454
455 static unsigned int i965_gtt_total_entries(void)
456 {
457 int size;
458 u32 pgetbl_ctl;
459 u16 gmch_ctl;
460
461 pci_read_config_word(intel_private.bridge_dev,
462 I830_GMCH_CTRL, &gmch_ctl);
463
464 if (INTEL_GTT_GEN == 5) {
465 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
466 case G4x_GMCH_SIZE_1M:
467 case G4x_GMCH_SIZE_VT_1M:
468 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
469 break;
470 case G4x_GMCH_SIZE_VT_1_5M:
471 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
472 break;
473 case G4x_GMCH_SIZE_2M:
474 case G4x_GMCH_SIZE_VT_2M:
475 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
476 break;
477 }
478 }
479
480 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
481
482 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
483 case I965_PGETBL_SIZE_128KB:
484 size = KB(128);
485 break;
486 case I965_PGETBL_SIZE_256KB:
487 size = KB(256);
488 break;
489 case I965_PGETBL_SIZE_512KB:
490 size = KB(512);
491 break;
492 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
493 case I965_PGETBL_SIZE_1MB:
494 size = KB(1024);
495 break;
496 case I965_PGETBL_SIZE_2MB:
497 size = KB(2048);
498 break;
499 case I965_PGETBL_SIZE_1_5MB:
500 size = KB(1024 + 512);
501 break;
502 default:
503 dev_info(&intel_private.pcidev->dev,
504 "unknown page table size, assuming 512KB\n");
505 size = KB(512);
506 }
507
508 return size/4;
509 }
510
511 static unsigned int intel_gtt_total_entries(void)
512 {
513 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
514 return i965_gtt_total_entries();
515 else {
516 /* On previous hardware, the GTT size was just what was
517 * required to map the aperture.
518 */
519 return intel_private.gtt_mappable_entries;
520 }
521 }
522
523 static unsigned int intel_gtt_mappable_entries(void)
524 {
525 unsigned int aperture_size;
526
527 if (INTEL_GTT_GEN == 1) {
528 u32 smram_miscc;
529
530 pci_read_config_dword(intel_private.bridge_dev,
531 I810_SMRAM_MISCC, &smram_miscc);
532
533 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
534 == I810_GFX_MEM_WIN_32M)
535 aperture_size = MB(32);
536 else
537 aperture_size = MB(64);
538 } else if (INTEL_GTT_GEN == 2) {
539 u16 gmch_ctrl;
540
541 pci_read_config_word(intel_private.bridge_dev,
542 I830_GMCH_CTRL, &gmch_ctrl);
543
544 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
545 aperture_size = MB(64);
546 else
547 aperture_size = MB(128);
548 } else {
549 /* 9xx supports large sizes, just look at the length */
550 aperture_size = pci_resource_len(intel_private.pcidev, 2);
551 }
552
553 return aperture_size >> PAGE_SHIFT;
554 }
555
556 static void intel_gtt_teardown_scratch_page(void)
557 {
558 set_pages_wb(intel_private.scratch_page, 1);
559 pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
560 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
561 put_page(intel_private.scratch_page);
562 __free_page(intel_private.scratch_page);
563 }
564
565 static void intel_gtt_cleanup(void)
566 {
567 intel_private.driver->cleanup();
568
569 iounmap(intel_private.gtt);
570 iounmap(intel_private.registers);
571
572 intel_gtt_teardown_scratch_page();
573 }
574
575 /* Certain Gen5 chipsets require require idling the GPU before
576 * unmapping anything from the GTT when VT-d is enabled.
577 */
578 static inline int needs_ilk_vtd_wa(void)
579 {
580 #ifdef CONFIG_INTEL_IOMMU
581 const unsigned short gpu_devid = intel_private.pcidev->device;
582
583 /* Query intel_iommu to see if we need the workaround. Presumably that
584 * was loaded first.
585 */
586 if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
587 gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
588 intel_iommu_gfx_mapped)
589 return 1;
590 #endif
591 return 0;
592 }
593
594 static bool intel_gtt_can_wc(void)
595 {
596 if (INTEL_GTT_GEN <= 2)
597 return false;
598
599 if (INTEL_GTT_GEN >= 6)
600 return false;
601
602 /* Reports of major corruption with ILK vt'd enabled */
603 if (needs_ilk_vtd_wa())
604 return false;
605
606 return true;
607 }
608
609 static int intel_gtt_init(void)
610 {
611 u32 gma_addr;
612 u32 gtt_map_size;
613 int ret;
614
615 ret = intel_private.driver->setup();
616 if (ret != 0)
617 return ret;
618
619 intel_private.gtt_mappable_entries = intel_gtt_mappable_entries();
620 intel_private.gtt_total_entries = intel_gtt_total_entries();
621
622 /* save the PGETBL reg for resume */
623 intel_private.PGETBL_save =
624 readl(intel_private.registers+I810_PGETBL_CTL)
625 & ~I810_PGETBL_ENABLED;
626 /* we only ever restore the register when enabling the PGTBL... */
627 if (HAS_PGTBL_EN)
628 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
629
630 dev_info(&intel_private.bridge_dev->dev,
631 "detected gtt size: %dK total, %dK mappable\n",
632 intel_private.gtt_total_entries * 4,
633 intel_private.gtt_mappable_entries * 4);
634
635 gtt_map_size = intel_private.gtt_total_entries * 4;
636
637 intel_private.gtt = NULL;
638 if (intel_gtt_can_wc())
639 intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
640 gtt_map_size);
641 if (intel_private.gtt == NULL)
642 intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
643 gtt_map_size);
644 if (intel_private.gtt == NULL) {
645 intel_private.driver->cleanup();
646 iounmap(intel_private.registers);
647 return -ENOMEM;
648 }
649
650 global_cache_flush(); /* FIXME: ? */
651
652 intel_private.stolen_size = intel_gtt_stolen_size();
653
654 intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
655
656 ret = intel_gtt_setup_scratch_page();
657 if (ret != 0) {
658 intel_gtt_cleanup();
659 return ret;
660 }
661
662 if (INTEL_GTT_GEN <= 2)
663 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
664 &gma_addr);
665 else
666 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
667 &gma_addr);
668
669 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
670
671 return 0;
672 }
673
674 static int intel_fake_agp_fetch_size(void)
675 {
676 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
677 unsigned int aper_size;
678 int i;
679
680 aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1);
681
682 for (i = 0; i < num_sizes; i++) {
683 if (aper_size == intel_fake_agp_sizes[i].size) {
684 agp_bridge->current_size =
685 (void *) (intel_fake_agp_sizes + i);
686 return aper_size;
687 }
688 }
689
690 return 0;
691 }
692
693 static void i830_cleanup(void)
694 {
695 }
696
697 /* The chipset_flush interface needs to get data that has already been
698 * flushed out of the CPU all the way out to main memory, because the GPU
699 * doesn't snoop those buffers.
700 *
701 * The 8xx series doesn't have the same lovely interface for flushing the
702 * chipset write buffers that the later chips do. According to the 865
703 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
704 * that buffer out, we just fill 1KB and clflush it out, on the assumption
705 * that it'll push whatever was in there out. It appears to work.
706 */
707 static void i830_chipset_flush(void)
708 {
709 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
710
711 /* Forcibly evict everything from the CPU write buffers.
712 * clflush appears to be insufficient.
713 */
714 wbinvd_on_all_cpus();
715
716 /* Now we've only seen documents for this magic bit on 855GM,
717 * we hope it exists for the other gen2 chipsets...
718 *
719 * Also works as advertised on my 845G.
720 */
721 writel(readl(intel_private.registers+I830_HIC) | (1<<31),
722 intel_private.registers+I830_HIC);
723
724 while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
725 if (time_after(jiffies, timeout))
726 break;
727
728 udelay(50);
729 }
730 }
731
732 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
733 unsigned int flags)
734 {
735 u32 pte_flags = I810_PTE_VALID;
736
737 if (flags == AGP_USER_CACHED_MEMORY)
738 pte_flags |= I830_PTE_SYSTEM_CACHED;
739
740 writel(addr | pte_flags, intel_private.gtt + entry);
741 }
742
743 bool intel_enable_gtt(void)
744 {
745 u8 __iomem *reg;
746
747 if (INTEL_GTT_GEN == 2) {
748 u16 gmch_ctrl;
749
750 pci_read_config_word(intel_private.bridge_dev,
751 I830_GMCH_CTRL, &gmch_ctrl);
752 gmch_ctrl |= I830_GMCH_ENABLED;
753 pci_write_config_word(intel_private.bridge_dev,
754 I830_GMCH_CTRL, gmch_ctrl);
755
756 pci_read_config_word(intel_private.bridge_dev,
757 I830_GMCH_CTRL, &gmch_ctrl);
758 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
759 dev_err(&intel_private.pcidev->dev,
760 "failed to enable the GTT: GMCH_CTRL=%x\n",
761 gmch_ctrl);
762 return false;
763 }
764 }
765
766 /* On the resume path we may be adjusting the PGTBL value, so
767 * be paranoid and flush all chipset write buffers...
768 */
769 if (INTEL_GTT_GEN >= 3)
770 writel(0, intel_private.registers+GFX_FLSH_CNTL);
771
772 reg = intel_private.registers+I810_PGETBL_CTL;
773 writel(intel_private.PGETBL_save, reg);
774 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
775 dev_err(&intel_private.pcidev->dev,
776 "failed to enable the GTT: PGETBL=%x [expected %x]\n",
777 readl(reg), intel_private.PGETBL_save);
778 return false;
779 }
780
781 if (INTEL_GTT_GEN >= 3)
782 writel(0, intel_private.registers+GFX_FLSH_CNTL);
783
784 return true;
785 }
786 EXPORT_SYMBOL(intel_enable_gtt);
787
788 static int i830_setup(void)
789 {
790 u32 reg_addr;
791
792 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
793 reg_addr &= 0xfff80000;
794
795 intel_private.registers = ioremap(reg_addr, KB(64));
796 if (!intel_private.registers)
797 return -ENOMEM;
798
799 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
800
801 return 0;
802 }
803
804 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
805 {
806 agp_bridge->gatt_table_real = NULL;
807 agp_bridge->gatt_table = NULL;
808 agp_bridge->gatt_bus_addr = 0;
809
810 return 0;
811 }
812
813 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
814 {
815 return 0;
816 }
817
818 static int intel_fake_agp_configure(void)
819 {
820 if (!intel_enable_gtt())
821 return -EIO;
822
823 intel_private.clear_fake_agp = true;
824 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
825
826 return 0;
827 }
828
829 static bool i830_check_flags(unsigned int flags)
830 {
831 switch (flags) {
832 case 0:
833 case AGP_PHYS_MEMORY:
834 case AGP_USER_CACHED_MEMORY:
835 case AGP_USER_MEMORY:
836 return true;
837 }
838
839 return false;
840 }
841
842 void intel_gtt_insert_sg_entries(struct sg_table *st,
843 unsigned int pg_start,
844 unsigned int flags)
845 {
846 struct scatterlist *sg;
847 unsigned int len, m;
848 int i, j;
849
850 j = pg_start;
851
852 /* sg may merge pages, but we have to separate
853 * per-page addr for GTT */
854 for_each_sg(st->sgl, sg, st->nents, i) {
855 len = sg_dma_len(sg) >> PAGE_SHIFT;
856 for (m = 0; m < len; m++) {
857 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
858 intel_private.driver->write_entry(addr, j, flags);
859 j++;
860 }
861 }
862 readl(intel_private.gtt+j-1);
863 }
864 EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
865
866 static void intel_gtt_insert_pages(unsigned int first_entry,
867 unsigned int num_entries,
868 struct page **pages,
869 unsigned int flags)
870 {
871 int i, j;
872
873 for (i = 0, j = first_entry; i < num_entries; i++, j++) {
874 dma_addr_t addr = page_to_phys(pages[i]);
875 intel_private.driver->write_entry(addr,
876 j, flags);
877 }
878 readl(intel_private.gtt+j-1);
879 }
880
881 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
882 off_t pg_start, int type)
883 {
884 int ret = -EINVAL;
885
886 if (intel_private.clear_fake_agp) {
887 int start = intel_private.stolen_size / PAGE_SIZE;
888 int end = intel_private.gtt_mappable_entries;
889 intel_gtt_clear_range(start, end - start);
890 intel_private.clear_fake_agp = false;
891 }
892
893 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
894 return i810_insert_dcache_entries(mem, pg_start, type);
895
896 if (mem->page_count == 0)
897 goto out;
898
899 if (pg_start + mem->page_count > intel_private.gtt_total_entries)
900 goto out_err;
901
902 if (type != mem->type)
903 goto out_err;
904
905 if (!intel_private.driver->check_flags(type))
906 goto out_err;
907
908 if (!mem->is_flushed)
909 global_cache_flush();
910
911 if (intel_private.needs_dmar) {
912 struct sg_table st;
913
914 ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
915 if (ret != 0)
916 return ret;
917
918 intel_gtt_insert_sg_entries(&st, pg_start, type);
919 mem->sg_list = st.sgl;
920 mem->num_sg = st.nents;
921 } else
922 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
923 type);
924
925 out:
926 ret = 0;
927 out_err:
928 mem->is_flushed = true;
929 return ret;
930 }
931
932 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
933 {
934 unsigned int i;
935
936 for (i = first_entry; i < (first_entry + num_entries); i++) {
937 intel_private.driver->write_entry(intel_private.scratch_page_dma,
938 i, 0);
939 }
940 readl(intel_private.gtt+i-1);
941 }
942 EXPORT_SYMBOL(intel_gtt_clear_range);
943
944 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
945 off_t pg_start, int type)
946 {
947 if (mem->page_count == 0)
948 return 0;
949
950 intel_gtt_clear_range(pg_start, mem->page_count);
951
952 if (intel_private.needs_dmar) {
953 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg);
954 mem->sg_list = NULL;
955 mem->num_sg = 0;
956 }
957
958 return 0;
959 }
960
961 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
962 int type)
963 {
964 struct agp_memory *new;
965
966 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
967 if (pg_count != intel_private.num_dcache_entries)
968 return NULL;
969
970 new = agp_create_memory(1);
971 if (new == NULL)
972 return NULL;
973
974 new->type = AGP_DCACHE_MEMORY;
975 new->page_count = pg_count;
976 new->num_scratch_pages = 0;
977 agp_free_page_array(new);
978 return new;
979 }
980 if (type == AGP_PHYS_MEMORY)
981 return alloc_agpphysmem_i8xx(pg_count, type);
982 /* always return NULL for other allocation types for now */
983 return NULL;
984 }
985
986 static int intel_alloc_chipset_flush_resource(void)
987 {
988 int ret;
989 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
990 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
991 pcibios_align_resource, intel_private.bridge_dev);
992
993 return ret;
994 }
995
996 static void intel_i915_setup_chipset_flush(void)
997 {
998 int ret;
999 u32 temp;
1000
1001 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1002 if (!(temp & 0x1)) {
1003 intel_alloc_chipset_flush_resource();
1004 intel_private.resource_valid = 1;
1005 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1006 } else {
1007 temp &= ~1;
1008
1009 intel_private.resource_valid = 1;
1010 intel_private.ifp_resource.start = temp;
1011 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1012 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1013 /* some BIOSes reserve this area in a pnp some don't */
1014 if (ret)
1015 intel_private.resource_valid = 0;
1016 }
1017 }
1018
1019 static void intel_i965_g33_setup_chipset_flush(void)
1020 {
1021 u32 temp_hi, temp_lo;
1022 int ret;
1023
1024 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1025 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1026
1027 if (!(temp_lo & 0x1)) {
1028
1029 intel_alloc_chipset_flush_resource();
1030
1031 intel_private.resource_valid = 1;
1032 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1033 upper_32_bits(intel_private.ifp_resource.start));
1034 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1035 } else {
1036 u64 l64;
1037
1038 temp_lo &= ~0x1;
1039 l64 = ((u64)temp_hi << 32) | temp_lo;
1040
1041 intel_private.resource_valid = 1;
1042 intel_private.ifp_resource.start = l64;
1043 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1044 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1045 /* some BIOSes reserve this area in a pnp some don't */
1046 if (ret)
1047 intel_private.resource_valid = 0;
1048 }
1049 }
1050
1051 static void intel_i9xx_setup_flush(void)
1052 {
1053 /* return if already configured */
1054 if (intel_private.ifp_resource.start)
1055 return;
1056
1057 if (INTEL_GTT_GEN == 6)
1058 return;
1059
1060 /* setup a resource for this object */
1061 intel_private.ifp_resource.name = "Intel Flush Page";
1062 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1063
1064 /* Setup chipset flush for 915 */
1065 if (IS_G33 || INTEL_GTT_GEN >= 4) {
1066 intel_i965_g33_setup_chipset_flush();
1067 } else {
1068 intel_i915_setup_chipset_flush();
1069 }
1070
1071 if (intel_private.ifp_resource.start)
1072 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1073 if (!intel_private.i9xx_flush_page)
1074 dev_err(&intel_private.pcidev->dev,
1075 "can't ioremap flush page - no chipset flushing\n");
1076 }
1077
1078 static void i9xx_cleanup(void)
1079 {
1080 if (intel_private.i9xx_flush_page)
1081 iounmap(intel_private.i9xx_flush_page);
1082 if (intel_private.resource_valid)
1083 release_resource(&intel_private.ifp_resource);
1084 intel_private.ifp_resource.start = 0;
1085 intel_private.resource_valid = 0;
1086 }
1087
1088 static void i9xx_chipset_flush(void)
1089 {
1090 if (intel_private.i9xx_flush_page)
1091 writel(1, intel_private.i9xx_flush_page);
1092 }
1093
1094 static void i965_write_entry(dma_addr_t addr,
1095 unsigned int entry,
1096 unsigned int flags)
1097 {
1098 u32 pte_flags;
1099
1100 pte_flags = I810_PTE_VALID;
1101 if (flags == AGP_USER_CACHED_MEMORY)
1102 pte_flags |= I830_PTE_SYSTEM_CACHED;
1103
1104 /* Shift high bits down */
1105 addr |= (addr >> 28) & 0xf0;
1106 writel(addr | pte_flags, intel_private.gtt + entry);
1107 }
1108
1109 static int i9xx_setup(void)
1110 {
1111 u32 reg_addr, gtt_addr;
1112 int size = KB(512);
1113
1114 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1115
1116 reg_addr &= 0xfff80000;
1117
1118 intel_private.registers = ioremap(reg_addr, size);
1119 if (!intel_private.registers)
1120 return -ENOMEM;
1121
1122 switch (INTEL_GTT_GEN) {
1123 case 3:
1124 pci_read_config_dword(intel_private.pcidev,
1125 I915_PTEADDR, &gtt_addr);
1126 intel_private.gtt_bus_addr = gtt_addr;
1127 break;
1128 case 5:
1129 intel_private.gtt_bus_addr = reg_addr + MB(2);
1130 break;
1131 default:
1132 intel_private.gtt_bus_addr = reg_addr + KB(512);
1133 break;
1134 }
1135
1136 intel_i9xx_setup_flush();
1137
1138 return 0;
1139 }
1140
1141 static const struct agp_bridge_driver intel_fake_agp_driver = {
1142 .owner = THIS_MODULE,
1143 .size_type = FIXED_APER_SIZE,
1144 .aperture_sizes = intel_fake_agp_sizes,
1145 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes),
1146 .configure = intel_fake_agp_configure,
1147 .fetch_size = intel_fake_agp_fetch_size,
1148 .cleanup = intel_gtt_cleanup,
1149 .agp_enable = intel_fake_agp_enable,
1150 .cache_flush = global_cache_flush,
1151 .create_gatt_table = intel_fake_agp_create_gatt_table,
1152 .free_gatt_table = intel_fake_agp_free_gatt_table,
1153 .insert_memory = intel_fake_agp_insert_entries,
1154 .remove_memory = intel_fake_agp_remove_entries,
1155 .alloc_by_type = intel_fake_agp_alloc_by_type,
1156 .free_by_type = intel_i810_free_by_type,
1157 .agp_alloc_page = agp_generic_alloc_page,
1158 .agp_alloc_pages = agp_generic_alloc_pages,
1159 .agp_destroy_page = agp_generic_destroy_page,
1160 .agp_destroy_pages = agp_generic_destroy_pages,
1161 };
1162
1163 static const struct intel_gtt_driver i81x_gtt_driver = {
1164 .gen = 1,
1165 .has_pgtbl_enable = 1,
1166 .dma_mask_size = 32,
1167 .setup = i810_setup,
1168 .cleanup = i810_cleanup,
1169 .check_flags = i830_check_flags,
1170 .write_entry = i810_write_entry,
1171 };
1172 static const struct intel_gtt_driver i8xx_gtt_driver = {
1173 .gen = 2,
1174 .has_pgtbl_enable = 1,
1175 .setup = i830_setup,
1176 .cleanup = i830_cleanup,
1177 .write_entry = i830_write_entry,
1178 .dma_mask_size = 32,
1179 .check_flags = i830_check_flags,
1180 .chipset_flush = i830_chipset_flush,
1181 };
1182 static const struct intel_gtt_driver i915_gtt_driver = {
1183 .gen = 3,
1184 .has_pgtbl_enable = 1,
1185 .setup = i9xx_setup,
1186 .cleanup = i9xx_cleanup,
1187 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1188 .write_entry = i830_write_entry,
1189 .dma_mask_size = 32,
1190 .check_flags = i830_check_flags,
1191 .chipset_flush = i9xx_chipset_flush,
1192 };
1193 static const struct intel_gtt_driver g33_gtt_driver = {
1194 .gen = 3,
1195 .is_g33 = 1,
1196 .setup = i9xx_setup,
1197 .cleanup = i9xx_cleanup,
1198 .write_entry = i965_write_entry,
1199 .dma_mask_size = 36,
1200 .check_flags = i830_check_flags,
1201 .chipset_flush = i9xx_chipset_flush,
1202 };
1203 static const struct intel_gtt_driver pineview_gtt_driver = {
1204 .gen = 3,
1205 .is_pineview = 1, .is_g33 = 1,
1206 .setup = i9xx_setup,
1207 .cleanup = i9xx_cleanup,
1208 .write_entry = i965_write_entry,
1209 .dma_mask_size = 36,
1210 .check_flags = i830_check_flags,
1211 .chipset_flush = i9xx_chipset_flush,
1212 };
1213 static const struct intel_gtt_driver i965_gtt_driver = {
1214 .gen = 4,
1215 .has_pgtbl_enable = 1,
1216 .setup = i9xx_setup,
1217 .cleanup = i9xx_cleanup,
1218 .write_entry = i965_write_entry,
1219 .dma_mask_size = 36,
1220 .check_flags = i830_check_flags,
1221 .chipset_flush = i9xx_chipset_flush,
1222 };
1223 static const struct intel_gtt_driver g4x_gtt_driver = {
1224 .gen = 5,
1225 .setup = i9xx_setup,
1226 .cleanup = i9xx_cleanup,
1227 .write_entry = i965_write_entry,
1228 .dma_mask_size = 36,
1229 .check_flags = i830_check_flags,
1230 .chipset_flush = i9xx_chipset_flush,
1231 };
1232 static const struct intel_gtt_driver ironlake_gtt_driver = {
1233 .gen = 5,
1234 .is_ironlake = 1,
1235 .setup = i9xx_setup,
1236 .cleanup = i9xx_cleanup,
1237 .write_entry = i965_write_entry,
1238 .dma_mask_size = 36,
1239 .check_flags = i830_check_flags,
1240 .chipset_flush = i9xx_chipset_flush,
1241 };
1242
1243 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1244 * driver and gmch_driver must be non-null, and find_gmch will determine
1245 * which one should be used if a gmch_chip_id is present.
1246 */
1247 static const struct intel_gtt_driver_description {
1248 unsigned int gmch_chip_id;
1249 char *name;
1250 const struct intel_gtt_driver *gtt_driver;
1251 } intel_gtt_chipsets[] = {
1252 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1253 &i81x_gtt_driver},
1254 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1255 &i81x_gtt_driver},
1256 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1257 &i81x_gtt_driver},
1258 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1259 &i81x_gtt_driver},
1260 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1261 &i8xx_gtt_driver},
1262 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G",
1263 &i8xx_gtt_driver},
1264 { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1265 &i8xx_gtt_driver},
1266 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1267 &i8xx_gtt_driver},
1268 { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1269 &i8xx_gtt_driver},
1270 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1271 &i915_gtt_driver },
1272 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1273 &i915_gtt_driver },
1274 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1275 &i915_gtt_driver },
1276 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1277 &i915_gtt_driver },
1278 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1279 &i915_gtt_driver },
1280 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1281 &i915_gtt_driver },
1282 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1283 &i965_gtt_driver },
1284 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1285 &i965_gtt_driver },
1286 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1287 &i965_gtt_driver },
1288 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1289 &i965_gtt_driver },
1290 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1291 &i965_gtt_driver },
1292 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1293 &i965_gtt_driver },
1294 { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1295 &g33_gtt_driver },
1296 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1297 &g33_gtt_driver },
1298 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1299 &g33_gtt_driver },
1300 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1301 &pineview_gtt_driver },
1302 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1303 &pineview_gtt_driver },
1304 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1305 &g4x_gtt_driver },
1306 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1307 &g4x_gtt_driver },
1308 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1309 &g4x_gtt_driver },
1310 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1311 &g4x_gtt_driver },
1312 { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1313 &g4x_gtt_driver },
1314 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1315 &g4x_gtt_driver },
1316 { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1317 &g4x_gtt_driver },
1318 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1319 "HD Graphics", &ironlake_gtt_driver },
1320 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1321 "HD Graphics", &ironlake_gtt_driver },
1322 { 0, NULL, NULL }
1323 };
1324
1325 static int find_gmch(u16 device)
1326 {
1327 struct pci_dev *gmch_device;
1328
1329 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1330 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1331 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1332 device, gmch_device);
1333 }
1334
1335 if (!gmch_device)
1336 return 0;
1337
1338 intel_private.pcidev = gmch_device;
1339 return 1;
1340 }
1341
1342 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
1343 struct agp_bridge_data *bridge)
1344 {
1345 int i, mask;
1346
1347 /*
1348 * Can be called from the fake agp driver but also directly from
1349 * drm/i915.ko. Hence we need to check whether everything is set up
1350 * already.
1351 */
1352 if (intel_private.driver) {
1353 intel_private.refcount++;
1354 return 1;
1355 }
1356
1357 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1358 if (gpu_pdev) {
1359 if (gpu_pdev->device ==
1360 intel_gtt_chipsets[i].gmch_chip_id) {
1361 intel_private.pcidev = pci_dev_get(gpu_pdev);
1362 intel_private.driver =
1363 intel_gtt_chipsets[i].gtt_driver;
1364
1365 break;
1366 }
1367 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1368 intel_private.driver =
1369 intel_gtt_chipsets[i].gtt_driver;
1370 break;
1371 }
1372 }
1373
1374 if (!intel_private.driver)
1375 return 0;
1376
1377 intel_private.refcount++;
1378
1379 if (bridge) {
1380 bridge->driver = &intel_fake_agp_driver;
1381 bridge->dev_private_data = &intel_private;
1382 bridge->dev = bridge_pdev;
1383 }
1384
1385 intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1386
1387 dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1388
1389 mask = intel_private.driver->dma_mask_size;
1390 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1391 dev_err(&intel_private.pcidev->dev,
1392 "set gfx device dma mask %d-bit failed!\n", mask);
1393 else
1394 pci_set_consistent_dma_mask(intel_private.pcidev,
1395 DMA_BIT_MASK(mask));
1396
1397 if (intel_gtt_init() != 0) {
1398 intel_gmch_remove();
1399
1400 return 0;
1401 }
1402
1403 return 1;
1404 }
1405 EXPORT_SYMBOL(intel_gmch_probe);
1406
1407 void intel_gtt_get(size_t *gtt_total, size_t *stolen_size,
1408 phys_addr_t *mappable_base, unsigned long *mappable_end)
1409 {
1410 *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
1411 *stolen_size = intel_private.stolen_size;
1412 *mappable_base = intel_private.gma_bus_addr;
1413 *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
1414 }
1415 EXPORT_SYMBOL(intel_gtt_get);
1416
1417 void intel_gtt_chipset_flush(void)
1418 {
1419 if (intel_private.driver->chipset_flush)
1420 intel_private.driver->chipset_flush();
1421 }
1422 EXPORT_SYMBOL(intel_gtt_chipset_flush);
1423
1424 void intel_gmch_remove(void)
1425 {
1426 if (--intel_private.refcount)
1427 return;
1428
1429 if (intel_private.pcidev)
1430 pci_dev_put(intel_private.pcidev);
1431 if (intel_private.bridge_dev)
1432 pci_dev_put(intel_private.bridge_dev);
1433 intel_private.driver = NULL;
1434 }
1435 EXPORT_SYMBOL(intel_gmch_remove);
1436
1437 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1438 MODULE_LICENSE("GPL and additional rights");
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