2 * Intel GTT (Graphics Translation Table) routines
4 * Caveat: This driver implements the linux agp interface, but this is far from
5 * a agp driver! GTT support ended up here for purely historical reasons: The
6 * old userspace intel graphics drivers needed an interface to map memory into
7 * the GTT. And the drm provides a default interface for graphic devices sitting
8 * on an agp port. So it made sense to fake the GTT support as an agp port to
9 * avoid having to create a new api.
11 * With gem this does not make much sense anymore, just needlessly complicates
12 * the code. But as long as the old graphics stack is still support, it's stuck
15 * /fairy-tale-mode off
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/pagemap.h>
23 #include <linux/agp_backend.h>
24 #include <linux/delay.h>
27 #include "intel-agp.h"
28 #include <drm/intel-gtt.h>
31 * If we have Intel graphics, we're not going to have anything other than
32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
33 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
34 * Only newer chipsets need to bother with this, of course.
36 #ifdef CONFIG_INTEL_IOMMU
37 #define USE_PCI_DMA_API 1
39 #define USE_PCI_DMA_API 0
42 struct intel_gtt_driver
{
44 unsigned int is_g33
: 1;
45 unsigned int is_pineview
: 1;
46 unsigned int is_ironlake
: 1;
47 unsigned int has_pgtbl_enable
: 1;
48 unsigned int dma_mask_size
: 8;
49 /* Chipset specific GTT setup */
51 /* This should undo anything done in ->setup() save the unmapping
52 * of the mmio register file, that's done in the generic code. */
53 void (*cleanup
)(void);
54 void (*write_entry
)(dma_addr_t addr
, unsigned int entry
, unsigned int flags
);
55 /* Flags is a more or less chipset specific opaque value.
56 * For chipsets that need to support old ums (non-gem) code, this
57 * needs to be identical to the various supported agp memory types! */
58 bool (*check_flags
)(unsigned int flags
);
59 void (*chipset_flush
)(void);
62 static struct _intel_private
{
63 const struct intel_gtt_driver
*driver
;
64 struct pci_dev
*pcidev
; /* device one */
65 struct pci_dev
*bridge_dev
;
66 u8 __iomem
*registers
;
67 phys_addr_t gtt_bus_addr
;
69 u32 __iomem
*gtt
; /* I915G */
70 bool clear_fake_agp
; /* on first access via agp, fill with scratch */
71 int num_dcache_entries
;
72 void __iomem
*i9xx_flush_page
;
74 struct resource ifp_resource
;
76 struct page
*scratch_page
;
77 phys_addr_t scratch_page_dma
;
79 /* Whether i915 needs to use the dmar apis or not. */
80 unsigned int needs_dmar
: 1;
81 phys_addr_t gma_bus_addr
;
82 /* Size of memory reserved for graphics by the BIOS */
83 unsigned int stolen_size
;
84 /* Total number of gtt entries. */
85 unsigned int gtt_total_entries
;
86 /* Part of the gtt that is mappable by the cpu, for those chips where
87 * this is not the full gtt. */
88 unsigned int gtt_mappable_entries
;
91 #define INTEL_GTT_GEN intel_private.driver->gen
92 #define IS_G33 intel_private.driver->is_g33
93 #define IS_PINEVIEW intel_private.driver->is_pineview
94 #define IS_IRONLAKE intel_private.driver->is_ironlake
95 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
97 #if IS_ENABLED(CONFIG_AGP_INTEL)
98 static int intel_gtt_map_memory(struct page
**pages
,
99 unsigned int num_entries
,
102 struct scatterlist
*sg
;
105 DBG("try mapping %lu pages\n", (unsigned long)num_entries
);
107 if (sg_alloc_table(st
, num_entries
, GFP_KERNEL
))
110 for_each_sg(st
->sgl
, sg
, num_entries
, i
)
111 sg_set_page(sg
, pages
[i
], PAGE_SIZE
, 0);
113 if (!pci_map_sg(intel_private
.pcidev
,
114 st
->sgl
, st
->nents
, PCI_DMA_BIDIRECTIONAL
))
124 static void intel_gtt_unmap_memory(struct scatterlist
*sg_list
, int num_sg
)
127 DBG("try unmapping %lu pages\n", (unsigned long)mem
->page_count
);
129 pci_unmap_sg(intel_private
.pcidev
, sg_list
,
130 num_sg
, PCI_DMA_BIDIRECTIONAL
);
133 st
.orig_nents
= st
.nents
= num_sg
;
138 static void intel_fake_agp_enable(struct agp_bridge_data
*bridge
, u32 mode
)
143 /* Exists to support ARGB cursors */
144 static struct page
*i8xx_alloc_pages(void)
148 page
= alloc_pages(GFP_KERNEL
| GFP_DMA32
, 2);
152 if (set_pages_uc(page
, 4) < 0) {
153 set_pages_wb(page
, 4);
154 __free_pages(page
, 2);
158 atomic_inc(&agp_bridge
->current_memory_agp
);
162 static void i8xx_destroy_pages(struct page
*page
)
167 set_pages_wb(page
, 4);
169 __free_pages(page
, 2);
170 atomic_dec(&agp_bridge
->current_memory_agp
);
174 #define I810_GTT_ORDER 4
175 static int i810_setup(void)
180 /* i81x does not preallocate the gtt. It's always 64kb in size. */
181 gtt_table
= alloc_gatt_pages(I810_GTT_ORDER
);
182 if (gtt_table
== NULL
)
184 intel_private
.i81x_gtt_table
= gtt_table
;
186 pci_read_config_dword(intel_private
.pcidev
, I810_MMADDR
, ®_addr
);
187 reg_addr
&= 0xfff80000;
189 intel_private
.registers
= ioremap(reg_addr
, KB(64));
190 if (!intel_private
.registers
)
193 writel(virt_to_phys(gtt_table
) | I810_PGETBL_ENABLED
,
194 intel_private
.registers
+I810_PGETBL_CTL
);
196 intel_private
.gtt_bus_addr
= reg_addr
+ I810_PTE_BASE
;
198 if ((readl(intel_private
.registers
+I810_DRAM_CTL
)
199 & I810_DRAM_ROW_0
) == I810_DRAM_ROW_0_SDRAM
) {
200 dev_info(&intel_private
.pcidev
->dev
,
201 "detected 4MB dedicated video ram\n");
202 intel_private
.num_dcache_entries
= 1024;
208 static void i810_cleanup(void)
210 writel(0, intel_private
.registers
+I810_PGETBL_CTL
);
211 free_gatt_pages(intel_private
.i81x_gtt_table
, I810_GTT_ORDER
);
214 #if IS_ENABLED(CONFIG_AGP_INTEL)
215 static int i810_insert_dcache_entries(struct agp_memory
*mem
, off_t pg_start
,
220 if ((pg_start
+ mem
->page_count
)
221 > intel_private
.num_dcache_entries
)
224 if (!mem
->is_flushed
)
225 global_cache_flush();
227 for (i
= pg_start
; i
< (pg_start
+ mem
->page_count
); i
++) {
228 dma_addr_t addr
= i
<< PAGE_SHIFT
;
229 intel_private
.driver
->write_entry(addr
,
232 readl(intel_private
.gtt
+i
-1);
238 * The i810/i830 requires a physical address to program its mouse
239 * pointer into hardware.
240 * However the Xserver still writes to it through the agp aperture.
242 static struct agp_memory
*alloc_agpphysmem_i8xx(size_t pg_count
, int type
)
244 struct agp_memory
*new;
248 case 1: page
= agp_bridge
->driver
->agp_alloc_page(agp_bridge
);
251 /* kludge to get 4 physical pages for ARGB cursor */
252 page
= i8xx_alloc_pages();
261 new = agp_create_memory(pg_count
);
265 new->pages
[0] = page
;
267 /* kludge to get 4 physical pages for ARGB cursor */
268 new->pages
[1] = new->pages
[0] + 1;
269 new->pages
[2] = new->pages
[1] + 1;
270 new->pages
[3] = new->pages
[2] + 1;
272 new->page_count
= pg_count
;
273 new->num_scratch_pages
= pg_count
;
274 new->type
= AGP_PHYS_MEMORY
;
275 new->physical
= page_to_phys(new->pages
[0]);
279 static void intel_i810_free_by_type(struct agp_memory
*curr
)
281 agp_free_key(curr
->key
);
282 if (curr
->type
== AGP_PHYS_MEMORY
) {
283 if (curr
->page_count
== 4)
284 i8xx_destroy_pages(curr
->pages
[0]);
286 agp_bridge
->driver
->agp_destroy_page(curr
->pages
[0],
287 AGP_PAGE_DESTROY_UNMAP
);
288 agp_bridge
->driver
->agp_destroy_page(curr
->pages
[0],
289 AGP_PAGE_DESTROY_FREE
);
291 agp_free_page_array(curr
);
297 static int intel_gtt_setup_scratch_page(void)
302 page
= alloc_page(GFP_KERNEL
| GFP_DMA32
| __GFP_ZERO
);
306 set_pages_uc(page
, 1);
308 if (intel_private
.needs_dmar
) {
309 dma_addr
= pci_map_page(intel_private
.pcidev
, page
, 0,
310 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
311 if (pci_dma_mapping_error(intel_private
.pcidev
, dma_addr
))
314 intel_private
.scratch_page_dma
= dma_addr
;
316 intel_private
.scratch_page_dma
= page_to_phys(page
);
318 intel_private
.scratch_page
= page
;
323 static void i810_write_entry(dma_addr_t addr
, unsigned int entry
,
326 u32 pte_flags
= I810_PTE_VALID
;
329 case AGP_DCACHE_MEMORY
:
330 pte_flags
|= I810_PTE_LOCAL
;
332 case AGP_USER_CACHED_MEMORY
:
333 pte_flags
|= I830_PTE_SYSTEM_CACHED
;
337 writel(addr
| pte_flags
, intel_private
.gtt
+ entry
);
340 static const struct aper_size_info_fixed intel_fake_agp_sizes
[] = {
348 static unsigned int intel_gtt_stolen_size(void)
353 static const int ddt
[4] = { 0, 16, 32, 64 };
354 unsigned int stolen_size
= 0;
356 if (INTEL_GTT_GEN
== 1)
357 return 0; /* no stolen mem on i81x */
359 pci_read_config_word(intel_private
.bridge_dev
,
360 I830_GMCH_CTRL
, &gmch_ctrl
);
362 if (intel_private
.bridge_dev
->device
== PCI_DEVICE_ID_INTEL_82830_HB
||
363 intel_private
.bridge_dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
) {
364 switch (gmch_ctrl
& I830_GMCH_GMS_MASK
) {
365 case I830_GMCH_GMS_STOLEN_512
:
366 stolen_size
= KB(512);
368 case I830_GMCH_GMS_STOLEN_1024
:
371 case I830_GMCH_GMS_STOLEN_8192
:
374 case I830_GMCH_GMS_LOCAL
:
375 rdct
= readb(intel_private
.registers
+I830_RDRAM_CHANNEL_TYPE
);
376 stolen_size
= (I830_RDRAM_ND(rdct
) + 1) *
377 MB(ddt
[I830_RDRAM_DDT(rdct
)]);
385 switch (gmch_ctrl
& I855_GMCH_GMS_MASK
) {
386 case I855_GMCH_GMS_STOLEN_1M
:
389 case I855_GMCH_GMS_STOLEN_4M
:
392 case I855_GMCH_GMS_STOLEN_8M
:
395 case I855_GMCH_GMS_STOLEN_16M
:
396 stolen_size
= MB(16);
398 case I855_GMCH_GMS_STOLEN_32M
:
399 stolen_size
= MB(32);
401 case I915_GMCH_GMS_STOLEN_48M
:
402 stolen_size
= MB(48);
404 case I915_GMCH_GMS_STOLEN_64M
:
405 stolen_size
= MB(64);
407 case G33_GMCH_GMS_STOLEN_128M
:
408 stolen_size
= MB(128);
410 case G33_GMCH_GMS_STOLEN_256M
:
411 stolen_size
= MB(256);
413 case INTEL_GMCH_GMS_STOLEN_96M
:
414 stolen_size
= MB(96);
416 case INTEL_GMCH_GMS_STOLEN_160M
:
417 stolen_size
= MB(160);
419 case INTEL_GMCH_GMS_STOLEN_224M
:
420 stolen_size
= MB(224);
422 case INTEL_GMCH_GMS_STOLEN_352M
:
423 stolen_size
= MB(352);
431 if (stolen_size
> 0) {
432 dev_info(&intel_private
.bridge_dev
->dev
, "detected %dK %s memory\n",
433 stolen_size
/ KB(1), local
? "local" : "stolen");
435 dev_info(&intel_private
.bridge_dev
->dev
,
436 "no pre-allocated video memory detected\n");
443 static void i965_adjust_pgetbl_size(unsigned int size_flag
)
445 u32 pgetbl_ctl
, pgetbl_ctl2
;
447 /* ensure that ppgtt is disabled */
448 pgetbl_ctl2
= readl(intel_private
.registers
+I965_PGETBL_CTL2
);
449 pgetbl_ctl2
&= ~I810_PGETBL_ENABLED
;
450 writel(pgetbl_ctl2
, intel_private
.registers
+I965_PGETBL_CTL2
);
452 /* write the new ggtt size */
453 pgetbl_ctl
= readl(intel_private
.registers
+I810_PGETBL_CTL
);
454 pgetbl_ctl
&= ~I965_PGETBL_SIZE_MASK
;
455 pgetbl_ctl
|= size_flag
;
456 writel(pgetbl_ctl
, intel_private
.registers
+I810_PGETBL_CTL
);
459 static unsigned int i965_gtt_total_entries(void)
465 pci_read_config_word(intel_private
.bridge_dev
,
466 I830_GMCH_CTRL
, &gmch_ctl
);
468 if (INTEL_GTT_GEN
== 5) {
469 switch (gmch_ctl
& G4x_GMCH_SIZE_MASK
) {
470 case G4x_GMCH_SIZE_1M
:
471 case G4x_GMCH_SIZE_VT_1M
:
472 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB
);
474 case G4x_GMCH_SIZE_VT_1_5M
:
475 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB
);
477 case G4x_GMCH_SIZE_2M
:
478 case G4x_GMCH_SIZE_VT_2M
:
479 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB
);
484 pgetbl_ctl
= readl(intel_private
.registers
+I810_PGETBL_CTL
);
486 switch (pgetbl_ctl
& I965_PGETBL_SIZE_MASK
) {
487 case I965_PGETBL_SIZE_128KB
:
490 case I965_PGETBL_SIZE_256KB
:
493 case I965_PGETBL_SIZE_512KB
:
496 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
497 case I965_PGETBL_SIZE_1MB
:
500 case I965_PGETBL_SIZE_2MB
:
503 case I965_PGETBL_SIZE_1_5MB
:
504 size
= KB(1024 + 512);
507 dev_info(&intel_private
.pcidev
->dev
,
508 "unknown page table size, assuming 512KB\n");
515 static unsigned int intel_gtt_total_entries(void)
517 if (IS_G33
|| INTEL_GTT_GEN
== 4 || INTEL_GTT_GEN
== 5)
518 return i965_gtt_total_entries();
520 /* On previous hardware, the GTT size was just what was
521 * required to map the aperture.
523 return intel_private
.gtt_mappable_entries
;
527 static unsigned int intel_gtt_mappable_entries(void)
529 unsigned int aperture_size
;
531 if (INTEL_GTT_GEN
== 1) {
534 pci_read_config_dword(intel_private
.bridge_dev
,
535 I810_SMRAM_MISCC
, &smram_miscc
);
537 if ((smram_miscc
& I810_GFX_MEM_WIN_SIZE
)
538 == I810_GFX_MEM_WIN_32M
)
539 aperture_size
= MB(32);
541 aperture_size
= MB(64);
542 } else if (INTEL_GTT_GEN
== 2) {
545 pci_read_config_word(intel_private
.bridge_dev
,
546 I830_GMCH_CTRL
, &gmch_ctrl
);
548 if ((gmch_ctrl
& I830_GMCH_MEM_MASK
) == I830_GMCH_MEM_64M
)
549 aperture_size
= MB(64);
551 aperture_size
= MB(128);
553 /* 9xx supports large sizes, just look at the length */
554 aperture_size
= pci_resource_len(intel_private
.pcidev
, 2);
557 return aperture_size
>> PAGE_SHIFT
;
560 static void intel_gtt_teardown_scratch_page(void)
562 set_pages_wb(intel_private
.scratch_page
, 1);
563 pci_unmap_page(intel_private
.pcidev
, intel_private
.scratch_page_dma
,
564 PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
565 put_page(intel_private
.scratch_page
);
566 __free_page(intel_private
.scratch_page
);
569 static void intel_gtt_cleanup(void)
571 intel_private
.driver
->cleanup();
573 iounmap(intel_private
.gtt
);
574 iounmap(intel_private
.registers
);
576 intel_gtt_teardown_scratch_page();
579 /* Certain Gen5 chipsets require require idling the GPU before
580 * unmapping anything from the GTT when VT-d is enabled.
582 static inline int needs_ilk_vtd_wa(void)
584 #ifdef CONFIG_INTEL_IOMMU
585 const unsigned short gpu_devid
= intel_private
.pcidev
->device
;
587 /* Query intel_iommu to see if we need the workaround. Presumably that
590 if ((gpu_devid
== PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB
||
591 gpu_devid
== PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG
) &&
592 intel_iommu_gfx_mapped
)
598 static bool intel_gtt_can_wc(void)
600 if (INTEL_GTT_GEN
<= 2)
603 if (INTEL_GTT_GEN
>= 6)
606 /* Reports of major corruption with ILK vt'd enabled */
607 if (needs_ilk_vtd_wa())
613 static int intel_gtt_init(void)
619 ret
= intel_private
.driver
->setup();
623 intel_private
.gtt_mappable_entries
= intel_gtt_mappable_entries();
624 intel_private
.gtt_total_entries
= intel_gtt_total_entries();
626 /* save the PGETBL reg for resume */
627 intel_private
.PGETBL_save
=
628 readl(intel_private
.registers
+I810_PGETBL_CTL
)
629 & ~I810_PGETBL_ENABLED
;
630 /* we only ever restore the register when enabling the PGTBL... */
632 intel_private
.PGETBL_save
|= I810_PGETBL_ENABLED
;
634 dev_info(&intel_private
.bridge_dev
->dev
,
635 "detected gtt size: %dK total, %dK mappable\n",
636 intel_private
.gtt_total_entries
* 4,
637 intel_private
.gtt_mappable_entries
* 4);
639 gtt_map_size
= intel_private
.gtt_total_entries
* 4;
641 intel_private
.gtt
= NULL
;
642 if (intel_gtt_can_wc())
643 intel_private
.gtt
= ioremap_wc(intel_private
.gtt_bus_addr
,
645 if (intel_private
.gtt
== NULL
)
646 intel_private
.gtt
= ioremap(intel_private
.gtt_bus_addr
,
648 if (intel_private
.gtt
== NULL
) {
649 intel_private
.driver
->cleanup();
650 iounmap(intel_private
.registers
);
654 #if IS_ENABLED(CONFIG_AGP_INTEL)
655 global_cache_flush(); /* FIXME: ? */
658 intel_private
.stolen_size
= intel_gtt_stolen_size();
660 intel_private
.needs_dmar
= USE_PCI_DMA_API
&& INTEL_GTT_GEN
> 2;
662 ret
= intel_gtt_setup_scratch_page();
668 if (INTEL_GTT_GEN
<= 2)
669 pci_read_config_dword(intel_private
.pcidev
, I810_GMADDR
,
672 pci_read_config_dword(intel_private
.pcidev
, I915_GMADDR
,
675 intel_private
.gma_bus_addr
= (gma_addr
& PCI_BASE_ADDRESS_MEM_MASK
);
680 #if IS_ENABLED(CONFIG_AGP_INTEL)
681 static int intel_fake_agp_fetch_size(void)
683 int num_sizes
= ARRAY_SIZE(intel_fake_agp_sizes
);
684 unsigned int aper_size
;
687 aper_size
= (intel_private
.gtt_mappable_entries
<< PAGE_SHIFT
) / MB(1);
689 for (i
= 0; i
< num_sizes
; i
++) {
690 if (aper_size
== intel_fake_agp_sizes
[i
].size
) {
691 agp_bridge
->current_size
=
692 (void *) (intel_fake_agp_sizes
+ i
);
701 static void i830_cleanup(void)
705 /* The chipset_flush interface needs to get data that has already been
706 * flushed out of the CPU all the way out to main memory, because the GPU
707 * doesn't snoop those buffers.
709 * The 8xx series doesn't have the same lovely interface for flushing the
710 * chipset write buffers that the later chips do. According to the 865
711 * specs, it's 64 octwords, or 1KB. So, to get those previous things in
712 * that buffer out, we just fill 1KB and clflush it out, on the assumption
713 * that it'll push whatever was in there out. It appears to work.
715 static void i830_chipset_flush(void)
717 unsigned long timeout
= jiffies
+ msecs_to_jiffies(1000);
719 /* Forcibly evict everything from the CPU write buffers.
720 * clflush appears to be insufficient.
722 wbinvd_on_all_cpus();
724 /* Now we've only seen documents for this magic bit on 855GM,
725 * we hope it exists for the other gen2 chipsets...
727 * Also works as advertised on my 845G.
729 writel(readl(intel_private
.registers
+I830_HIC
) | (1<<31),
730 intel_private
.registers
+I830_HIC
);
732 while (readl(intel_private
.registers
+I830_HIC
) & (1<<31)) {
733 if (time_after(jiffies
, timeout
))
740 static void i830_write_entry(dma_addr_t addr
, unsigned int entry
,
743 u32 pte_flags
= I810_PTE_VALID
;
745 if (flags
== AGP_USER_CACHED_MEMORY
)
746 pte_flags
|= I830_PTE_SYSTEM_CACHED
;
748 writel(addr
| pte_flags
, intel_private
.gtt
+ entry
);
751 bool intel_enable_gtt(void)
755 if (INTEL_GTT_GEN
== 2) {
758 pci_read_config_word(intel_private
.bridge_dev
,
759 I830_GMCH_CTRL
, &gmch_ctrl
);
760 gmch_ctrl
|= I830_GMCH_ENABLED
;
761 pci_write_config_word(intel_private
.bridge_dev
,
762 I830_GMCH_CTRL
, gmch_ctrl
);
764 pci_read_config_word(intel_private
.bridge_dev
,
765 I830_GMCH_CTRL
, &gmch_ctrl
);
766 if ((gmch_ctrl
& I830_GMCH_ENABLED
) == 0) {
767 dev_err(&intel_private
.pcidev
->dev
,
768 "failed to enable the GTT: GMCH_CTRL=%x\n",
774 /* On the resume path we may be adjusting the PGTBL value, so
775 * be paranoid and flush all chipset write buffers...
777 if (INTEL_GTT_GEN
>= 3)
778 writel(0, intel_private
.registers
+GFX_FLSH_CNTL
);
780 reg
= intel_private
.registers
+I810_PGETBL_CTL
;
781 writel(intel_private
.PGETBL_save
, reg
);
782 if (HAS_PGTBL_EN
&& (readl(reg
) & I810_PGETBL_ENABLED
) == 0) {
783 dev_err(&intel_private
.pcidev
->dev
,
784 "failed to enable the GTT: PGETBL=%x [expected %x]\n",
785 readl(reg
), intel_private
.PGETBL_save
);
789 if (INTEL_GTT_GEN
>= 3)
790 writel(0, intel_private
.registers
+GFX_FLSH_CNTL
);
794 EXPORT_SYMBOL(intel_enable_gtt
);
796 static int i830_setup(void)
800 pci_read_config_dword(intel_private
.pcidev
, I810_MMADDR
, ®_addr
);
801 reg_addr
&= 0xfff80000;
803 intel_private
.registers
= ioremap(reg_addr
, KB(64));
804 if (!intel_private
.registers
)
807 intel_private
.gtt_bus_addr
= reg_addr
+ I810_PTE_BASE
;
812 #if IS_ENABLED(CONFIG_AGP_INTEL)
813 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data
*bridge
)
815 agp_bridge
->gatt_table_real
= NULL
;
816 agp_bridge
->gatt_table
= NULL
;
817 agp_bridge
->gatt_bus_addr
= 0;
822 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data
*bridge
)
827 static int intel_fake_agp_configure(void)
829 if (!intel_enable_gtt())
832 intel_private
.clear_fake_agp
= true;
833 agp_bridge
->gart_bus_addr
= intel_private
.gma_bus_addr
;
839 static bool i830_check_flags(unsigned int flags
)
843 case AGP_PHYS_MEMORY
:
844 case AGP_USER_CACHED_MEMORY
:
845 case AGP_USER_MEMORY
:
852 void intel_gtt_insert_sg_entries(struct sg_table
*st
,
853 unsigned int pg_start
,
856 struct scatterlist
*sg
;
862 /* sg may merge pages, but we have to separate
863 * per-page addr for GTT */
864 for_each_sg(st
->sgl
, sg
, st
->nents
, i
) {
865 len
= sg_dma_len(sg
) >> PAGE_SHIFT
;
866 for (m
= 0; m
< len
; m
++) {
867 dma_addr_t addr
= sg_dma_address(sg
) + (m
<< PAGE_SHIFT
);
868 intel_private
.driver
->write_entry(addr
, j
, flags
);
872 readl(intel_private
.gtt
+j
-1);
874 EXPORT_SYMBOL(intel_gtt_insert_sg_entries
);
876 #if IS_ENABLED(CONFIG_AGP_INTEL)
877 static void intel_gtt_insert_pages(unsigned int first_entry
,
878 unsigned int num_entries
,
884 for (i
= 0, j
= first_entry
; i
< num_entries
; i
++, j
++) {
885 dma_addr_t addr
= page_to_phys(pages
[i
]);
886 intel_private
.driver
->write_entry(addr
,
889 readl(intel_private
.gtt
+j
-1);
892 static int intel_fake_agp_insert_entries(struct agp_memory
*mem
,
893 off_t pg_start
, int type
)
897 if (intel_private
.clear_fake_agp
) {
898 int start
= intel_private
.stolen_size
/ PAGE_SIZE
;
899 int end
= intel_private
.gtt_mappable_entries
;
900 intel_gtt_clear_range(start
, end
- start
);
901 intel_private
.clear_fake_agp
= false;
904 if (INTEL_GTT_GEN
== 1 && type
== AGP_DCACHE_MEMORY
)
905 return i810_insert_dcache_entries(mem
, pg_start
, type
);
907 if (mem
->page_count
== 0)
910 if (pg_start
+ mem
->page_count
> intel_private
.gtt_total_entries
)
913 if (type
!= mem
->type
)
916 if (!intel_private
.driver
->check_flags(type
))
919 if (!mem
->is_flushed
)
920 global_cache_flush();
922 if (intel_private
.needs_dmar
) {
925 ret
= intel_gtt_map_memory(mem
->pages
, mem
->page_count
, &st
);
929 intel_gtt_insert_sg_entries(&st
, pg_start
, type
);
930 mem
->sg_list
= st
.sgl
;
931 mem
->num_sg
= st
.nents
;
933 intel_gtt_insert_pages(pg_start
, mem
->page_count
, mem
->pages
,
939 mem
->is_flushed
= true;
944 void intel_gtt_clear_range(unsigned int first_entry
, unsigned int num_entries
)
948 for (i
= first_entry
; i
< (first_entry
+ num_entries
); i
++) {
949 intel_private
.driver
->write_entry(intel_private
.scratch_page_dma
,
952 readl(intel_private
.gtt
+i
-1);
954 EXPORT_SYMBOL(intel_gtt_clear_range
);
956 #if IS_ENABLED(CONFIG_AGP_INTEL)
957 static int intel_fake_agp_remove_entries(struct agp_memory
*mem
,
958 off_t pg_start
, int type
)
960 if (mem
->page_count
== 0)
963 intel_gtt_clear_range(pg_start
, mem
->page_count
);
965 if (intel_private
.needs_dmar
) {
966 intel_gtt_unmap_memory(mem
->sg_list
, mem
->num_sg
);
974 static struct agp_memory
*intel_fake_agp_alloc_by_type(size_t pg_count
,
977 struct agp_memory
*new;
979 if (type
== AGP_DCACHE_MEMORY
&& INTEL_GTT_GEN
== 1) {
980 if (pg_count
!= intel_private
.num_dcache_entries
)
983 new = agp_create_memory(1);
987 new->type
= AGP_DCACHE_MEMORY
;
988 new->page_count
= pg_count
;
989 new->num_scratch_pages
= 0;
990 agp_free_page_array(new);
993 if (type
== AGP_PHYS_MEMORY
)
994 return alloc_agpphysmem_i8xx(pg_count
, type
);
995 /* always return NULL for other allocation types for now */
1000 static int intel_alloc_chipset_flush_resource(void)
1003 ret
= pci_bus_alloc_resource(intel_private
.bridge_dev
->bus
, &intel_private
.ifp_resource
, PAGE_SIZE
,
1004 PAGE_SIZE
, PCIBIOS_MIN_MEM
, 0,
1005 pcibios_align_resource
, intel_private
.bridge_dev
);
1010 static void intel_i915_setup_chipset_flush(void)
1015 pci_read_config_dword(intel_private
.bridge_dev
, I915_IFPADDR
, &temp
);
1016 if (!(temp
& 0x1)) {
1017 intel_alloc_chipset_flush_resource();
1018 intel_private
.resource_valid
= 1;
1019 pci_write_config_dword(intel_private
.bridge_dev
, I915_IFPADDR
, (intel_private
.ifp_resource
.start
& 0xffffffff) | 0x1);
1023 intel_private
.resource_valid
= 1;
1024 intel_private
.ifp_resource
.start
= temp
;
1025 intel_private
.ifp_resource
.end
= temp
+ PAGE_SIZE
;
1026 ret
= request_resource(&iomem_resource
, &intel_private
.ifp_resource
);
1027 /* some BIOSes reserve this area in a pnp some don't */
1029 intel_private
.resource_valid
= 0;
1033 static void intel_i965_g33_setup_chipset_flush(void)
1035 u32 temp_hi
, temp_lo
;
1038 pci_read_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
+ 4, &temp_hi
);
1039 pci_read_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
, &temp_lo
);
1041 if (!(temp_lo
& 0x1)) {
1043 intel_alloc_chipset_flush_resource();
1045 intel_private
.resource_valid
= 1;
1046 pci_write_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
+ 4,
1047 upper_32_bits(intel_private
.ifp_resource
.start
));
1048 pci_write_config_dword(intel_private
.bridge_dev
, I965_IFPADDR
, (intel_private
.ifp_resource
.start
& 0xffffffff) | 0x1);
1053 l64
= ((u64
)temp_hi
<< 32) | temp_lo
;
1055 intel_private
.resource_valid
= 1;
1056 intel_private
.ifp_resource
.start
= l64
;
1057 intel_private
.ifp_resource
.end
= l64
+ PAGE_SIZE
;
1058 ret
= request_resource(&iomem_resource
, &intel_private
.ifp_resource
);
1059 /* some BIOSes reserve this area in a pnp some don't */
1061 intel_private
.resource_valid
= 0;
1065 static void intel_i9xx_setup_flush(void)
1067 /* return if already configured */
1068 if (intel_private
.ifp_resource
.start
)
1071 if (INTEL_GTT_GEN
== 6)
1074 /* setup a resource for this object */
1075 intel_private
.ifp_resource
.name
= "Intel Flush Page";
1076 intel_private
.ifp_resource
.flags
= IORESOURCE_MEM
;
1078 /* Setup chipset flush for 915 */
1079 if (IS_G33
|| INTEL_GTT_GEN
>= 4) {
1080 intel_i965_g33_setup_chipset_flush();
1082 intel_i915_setup_chipset_flush();
1085 if (intel_private
.ifp_resource
.start
)
1086 intel_private
.i9xx_flush_page
= ioremap_nocache(intel_private
.ifp_resource
.start
, PAGE_SIZE
);
1087 if (!intel_private
.i9xx_flush_page
)
1088 dev_err(&intel_private
.pcidev
->dev
,
1089 "can't ioremap flush page - no chipset flushing\n");
1092 static void i9xx_cleanup(void)
1094 if (intel_private
.i9xx_flush_page
)
1095 iounmap(intel_private
.i9xx_flush_page
);
1096 if (intel_private
.resource_valid
)
1097 release_resource(&intel_private
.ifp_resource
);
1098 intel_private
.ifp_resource
.start
= 0;
1099 intel_private
.resource_valid
= 0;
1102 static void i9xx_chipset_flush(void)
1104 if (intel_private
.i9xx_flush_page
)
1105 writel(1, intel_private
.i9xx_flush_page
);
1108 static void i965_write_entry(dma_addr_t addr
,
1114 pte_flags
= I810_PTE_VALID
;
1115 if (flags
== AGP_USER_CACHED_MEMORY
)
1116 pte_flags
|= I830_PTE_SYSTEM_CACHED
;
1118 /* Shift high bits down */
1119 addr
|= (addr
>> 28) & 0xf0;
1120 writel(addr
| pte_flags
, intel_private
.gtt
+ entry
);
1123 static int i9xx_setup(void)
1125 u32 reg_addr
, gtt_addr
;
1128 pci_read_config_dword(intel_private
.pcidev
, I915_MMADDR
, ®_addr
);
1130 reg_addr
&= 0xfff80000;
1132 intel_private
.registers
= ioremap(reg_addr
, size
);
1133 if (!intel_private
.registers
)
1136 switch (INTEL_GTT_GEN
) {
1138 pci_read_config_dword(intel_private
.pcidev
,
1139 I915_PTEADDR
, >t_addr
);
1140 intel_private
.gtt_bus_addr
= gtt_addr
;
1143 intel_private
.gtt_bus_addr
= reg_addr
+ MB(2);
1146 intel_private
.gtt_bus_addr
= reg_addr
+ KB(512);
1150 intel_i9xx_setup_flush();
1155 #if IS_ENABLED(CONFIG_AGP_INTEL)
1156 static const struct agp_bridge_driver intel_fake_agp_driver
= {
1157 .owner
= THIS_MODULE
,
1158 .size_type
= FIXED_APER_SIZE
,
1159 .aperture_sizes
= intel_fake_agp_sizes
,
1160 .num_aperture_sizes
= ARRAY_SIZE(intel_fake_agp_sizes
),
1161 .configure
= intel_fake_agp_configure
,
1162 .fetch_size
= intel_fake_agp_fetch_size
,
1163 .cleanup
= intel_gtt_cleanup
,
1164 .agp_enable
= intel_fake_agp_enable
,
1165 .cache_flush
= global_cache_flush
,
1166 .create_gatt_table
= intel_fake_agp_create_gatt_table
,
1167 .free_gatt_table
= intel_fake_agp_free_gatt_table
,
1168 .insert_memory
= intel_fake_agp_insert_entries
,
1169 .remove_memory
= intel_fake_agp_remove_entries
,
1170 .alloc_by_type
= intel_fake_agp_alloc_by_type
,
1171 .free_by_type
= intel_i810_free_by_type
,
1172 .agp_alloc_page
= agp_generic_alloc_page
,
1173 .agp_alloc_pages
= agp_generic_alloc_pages
,
1174 .agp_destroy_page
= agp_generic_destroy_page
,
1175 .agp_destroy_pages
= agp_generic_destroy_pages
,
1179 static const struct intel_gtt_driver i81x_gtt_driver
= {
1181 .has_pgtbl_enable
= 1,
1182 .dma_mask_size
= 32,
1183 .setup
= i810_setup
,
1184 .cleanup
= i810_cleanup
,
1185 .check_flags
= i830_check_flags
,
1186 .write_entry
= i810_write_entry
,
1188 static const struct intel_gtt_driver i8xx_gtt_driver
= {
1190 .has_pgtbl_enable
= 1,
1191 .setup
= i830_setup
,
1192 .cleanup
= i830_cleanup
,
1193 .write_entry
= i830_write_entry
,
1194 .dma_mask_size
= 32,
1195 .check_flags
= i830_check_flags
,
1196 .chipset_flush
= i830_chipset_flush
,
1198 static const struct intel_gtt_driver i915_gtt_driver
= {
1200 .has_pgtbl_enable
= 1,
1201 .setup
= i9xx_setup
,
1202 .cleanup
= i9xx_cleanup
,
1203 /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1204 .write_entry
= i830_write_entry
,
1205 .dma_mask_size
= 32,
1206 .check_flags
= i830_check_flags
,
1207 .chipset_flush
= i9xx_chipset_flush
,
1209 static const struct intel_gtt_driver g33_gtt_driver
= {
1212 .setup
= i9xx_setup
,
1213 .cleanup
= i9xx_cleanup
,
1214 .write_entry
= i965_write_entry
,
1215 .dma_mask_size
= 36,
1216 .check_flags
= i830_check_flags
,
1217 .chipset_flush
= i9xx_chipset_flush
,
1219 static const struct intel_gtt_driver pineview_gtt_driver
= {
1221 .is_pineview
= 1, .is_g33
= 1,
1222 .setup
= i9xx_setup
,
1223 .cleanup
= i9xx_cleanup
,
1224 .write_entry
= i965_write_entry
,
1225 .dma_mask_size
= 36,
1226 .check_flags
= i830_check_flags
,
1227 .chipset_flush
= i9xx_chipset_flush
,
1229 static const struct intel_gtt_driver i965_gtt_driver
= {
1231 .has_pgtbl_enable
= 1,
1232 .setup
= i9xx_setup
,
1233 .cleanup
= i9xx_cleanup
,
1234 .write_entry
= i965_write_entry
,
1235 .dma_mask_size
= 36,
1236 .check_flags
= i830_check_flags
,
1237 .chipset_flush
= i9xx_chipset_flush
,
1239 static const struct intel_gtt_driver g4x_gtt_driver
= {
1241 .setup
= i9xx_setup
,
1242 .cleanup
= i9xx_cleanup
,
1243 .write_entry
= i965_write_entry
,
1244 .dma_mask_size
= 36,
1245 .check_flags
= i830_check_flags
,
1246 .chipset_flush
= i9xx_chipset_flush
,
1248 static const struct intel_gtt_driver ironlake_gtt_driver
= {
1251 .setup
= i9xx_setup
,
1252 .cleanup
= i9xx_cleanup
,
1253 .write_entry
= i965_write_entry
,
1254 .dma_mask_size
= 36,
1255 .check_flags
= i830_check_flags
,
1256 .chipset_flush
= i9xx_chipset_flush
,
1259 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1260 * driver and gmch_driver must be non-null, and find_gmch will determine
1261 * which one should be used if a gmch_chip_id is present.
1263 static const struct intel_gtt_driver_description
{
1264 unsigned int gmch_chip_id
;
1266 const struct intel_gtt_driver
*gtt_driver
;
1267 } intel_gtt_chipsets
[] = {
1268 { PCI_DEVICE_ID_INTEL_82810_IG1
, "i810",
1270 { PCI_DEVICE_ID_INTEL_82810_IG3
, "i810",
1272 { PCI_DEVICE_ID_INTEL_82810E_IG
, "i810",
1274 { PCI_DEVICE_ID_INTEL_82815_CGC
, "i815",
1276 { PCI_DEVICE_ID_INTEL_82830_CGC
, "830M",
1278 { PCI_DEVICE_ID_INTEL_82845G_IG
, "845G",
1280 { PCI_DEVICE_ID_INTEL_82854_IG
, "854",
1282 { PCI_DEVICE_ID_INTEL_82855GM_IG
, "855GM",
1284 { PCI_DEVICE_ID_INTEL_82865_IG
, "865",
1286 { PCI_DEVICE_ID_INTEL_E7221_IG
, "E7221 (i915)",
1288 { PCI_DEVICE_ID_INTEL_82915G_IG
, "915G",
1290 { PCI_DEVICE_ID_INTEL_82915GM_IG
, "915GM",
1292 { PCI_DEVICE_ID_INTEL_82945G_IG
, "945G",
1294 { PCI_DEVICE_ID_INTEL_82945GM_IG
, "945GM",
1296 { PCI_DEVICE_ID_INTEL_82945GME_IG
, "945GME",
1298 { PCI_DEVICE_ID_INTEL_82946GZ_IG
, "946GZ",
1300 { PCI_DEVICE_ID_INTEL_82G35_IG
, "G35",
1302 { PCI_DEVICE_ID_INTEL_82965Q_IG
, "965Q",
1304 { PCI_DEVICE_ID_INTEL_82965G_IG
, "965G",
1306 { PCI_DEVICE_ID_INTEL_82965GM_IG
, "965GM",
1308 { PCI_DEVICE_ID_INTEL_82965GME_IG
, "965GME/GLE",
1310 { PCI_DEVICE_ID_INTEL_G33_IG
, "G33",
1312 { PCI_DEVICE_ID_INTEL_Q35_IG
, "Q35",
1314 { PCI_DEVICE_ID_INTEL_Q33_IG
, "Q33",
1316 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG
, "GMA3150",
1317 &pineview_gtt_driver
},
1318 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG
, "GMA3150",
1319 &pineview_gtt_driver
},
1320 { PCI_DEVICE_ID_INTEL_GM45_IG
, "GM45",
1322 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG
, "Eaglelake",
1324 { PCI_DEVICE_ID_INTEL_Q45_IG
, "Q45/Q43",
1326 { PCI_DEVICE_ID_INTEL_G45_IG
, "G45/G43",
1328 { PCI_DEVICE_ID_INTEL_B43_IG
, "B43",
1330 { PCI_DEVICE_ID_INTEL_B43_1_IG
, "B43",
1332 { PCI_DEVICE_ID_INTEL_G41_IG
, "G41",
1334 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG
,
1335 "HD Graphics", &ironlake_gtt_driver
},
1336 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG
,
1337 "HD Graphics", &ironlake_gtt_driver
},
1341 static int find_gmch(u16 device
)
1343 struct pci_dev
*gmch_device
;
1345 gmch_device
= pci_get_device(PCI_VENDOR_ID_INTEL
, device
, NULL
);
1346 if (gmch_device
&& PCI_FUNC(gmch_device
->devfn
) != 0) {
1347 gmch_device
= pci_get_device(PCI_VENDOR_ID_INTEL
,
1348 device
, gmch_device
);
1354 intel_private
.pcidev
= gmch_device
;
1358 int intel_gmch_probe(struct pci_dev
*bridge_pdev
, struct pci_dev
*gpu_pdev
,
1359 struct agp_bridge_data
*bridge
)
1364 * Can be called from the fake agp driver but also directly from
1365 * drm/i915.ko. Hence we need to check whether everything is set up
1368 if (intel_private
.driver
) {
1369 intel_private
.refcount
++;
1373 for (i
= 0; intel_gtt_chipsets
[i
].name
!= NULL
; i
++) {
1375 if (gpu_pdev
->device
==
1376 intel_gtt_chipsets
[i
].gmch_chip_id
) {
1377 intel_private
.pcidev
= pci_dev_get(gpu_pdev
);
1378 intel_private
.driver
=
1379 intel_gtt_chipsets
[i
].gtt_driver
;
1383 } else if (find_gmch(intel_gtt_chipsets
[i
].gmch_chip_id
)) {
1384 intel_private
.driver
=
1385 intel_gtt_chipsets
[i
].gtt_driver
;
1390 if (!intel_private
.driver
)
1393 intel_private
.refcount
++;
1395 #if IS_ENABLED(CONFIG_AGP_INTEL)
1397 bridge
->driver
= &intel_fake_agp_driver
;
1398 bridge
->dev_private_data
= &intel_private
;
1399 bridge
->dev
= bridge_pdev
;
1403 intel_private
.bridge_dev
= pci_dev_get(bridge_pdev
);
1405 dev_info(&bridge_pdev
->dev
, "Intel %s Chipset\n", intel_gtt_chipsets
[i
].name
);
1407 mask
= intel_private
.driver
->dma_mask_size
;
1408 if (pci_set_dma_mask(intel_private
.pcidev
, DMA_BIT_MASK(mask
)))
1409 dev_err(&intel_private
.pcidev
->dev
,
1410 "set gfx device dma mask %d-bit failed!\n", mask
);
1412 pci_set_consistent_dma_mask(intel_private
.pcidev
,
1413 DMA_BIT_MASK(mask
));
1415 if (intel_gtt_init() != 0) {
1416 intel_gmch_remove();
1423 EXPORT_SYMBOL(intel_gmch_probe
);
1425 void intel_gtt_get(size_t *gtt_total
, size_t *stolen_size
,
1426 phys_addr_t
*mappable_base
, unsigned long *mappable_end
)
1428 *gtt_total
= intel_private
.gtt_total_entries
<< PAGE_SHIFT
;
1429 *stolen_size
= intel_private
.stolen_size
;
1430 *mappable_base
= intel_private
.gma_bus_addr
;
1431 *mappable_end
= intel_private
.gtt_mappable_entries
<< PAGE_SHIFT
;
1433 EXPORT_SYMBOL(intel_gtt_get
);
1435 void intel_gtt_chipset_flush(void)
1437 if (intel_private
.driver
->chipset_flush
)
1438 intel_private
.driver
->chipset_flush();
1440 EXPORT_SYMBOL(intel_gtt_chipset_flush
);
1442 void intel_gmch_remove(void)
1444 if (--intel_private
.refcount
)
1447 if (intel_private
.pcidev
)
1448 pci_dev_put(intel_private
.pcidev
);
1449 if (intel_private
.bridge_dev
)
1450 pci_dev_put(intel_private
.bridge_dev
);
1451 intel_private
.driver
= NULL
;
1453 EXPORT_SYMBOL(intel_gmch_remove
);
1455 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1456 MODULE_LICENSE("GPL and additional rights");