1 /* i830_dma.c -- DMA support for the I830 -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Abraham vd Merwe <abraham@2d3d.co.za>
38 #include <linux/interrupt.h> /* For task queue support */
39 #include <linux/pagemap.h> /* For FASTCALL on unlock_page() */
40 #include <linux/delay.h>
41 #include <asm/uaccess.h>
43 #define I830_BUF_FREE 2
44 #define I830_BUF_CLIENT 1
45 #define I830_BUF_HARDWARE 0
47 #define I830_BUF_UNMAPPED 0
48 #define I830_BUF_MAPPED 1
50 static drm_buf_t
*i830_freelist_get(drm_device_t
* dev
)
52 drm_device_dma_t
*dma
= dev
->dma
;
56 /* Linear search might not be the best solution */
58 for (i
= 0; i
< dma
->buf_count
; i
++) {
59 drm_buf_t
*buf
= dma
->buflist
[i
];
60 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
61 /* In use is already a pointer */
62 used
= cmpxchg(buf_priv
->in_use
, I830_BUF_FREE
,
64 if (used
== I830_BUF_FREE
) {
71 /* This should only be called if the buffer is not sent to the hardware
72 * yet, the hardware updates in use for us once its on the ring buffer.
75 static int i830_freelist_put(drm_device_t
* dev
, drm_buf_t
* buf
)
77 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
80 /* In use is already a pointer */
81 used
= cmpxchg(buf_priv
->in_use
, I830_BUF_CLIENT
, I830_BUF_FREE
);
82 if (used
!= I830_BUF_CLIENT
) {
83 DRM_ERROR("Freeing buffer thats not in use : %d\n", buf
->idx
);
90 static int i830_mmap_buffers(struct file
*filp
, struct vm_area_struct
*vma
)
92 drm_file_t
*priv
= filp
->private_data
;
94 drm_i830_private_t
*dev_priv
;
96 drm_i830_buf_priv_t
*buf_priv
;
99 dev
= priv
->head
->dev
;
100 dev_priv
= dev
->dev_private
;
101 buf
= dev_priv
->mmap_buffer
;
102 buf_priv
= buf
->dev_private
;
104 vma
->vm_flags
|= (VM_IO
| VM_DONTCOPY
);
107 buf_priv
->currently_mapped
= I830_BUF_MAPPED
;
110 if (io_remap_pfn_range(vma
, vma
->vm_start
,
111 VM_OFFSET(vma
) >> PAGE_SHIFT
,
112 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
))
117 static struct file_operations i830_buffer_fops
= {
119 .release
= drm_release
,
121 .mmap
= i830_mmap_buffers
,
122 .fasync
= drm_fasync
,
125 static int i830_map_buffer(drm_buf_t
* buf
, struct file
*filp
)
127 drm_file_t
*priv
= filp
->private_data
;
128 drm_device_t
*dev
= priv
->head
->dev
;
129 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
130 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
131 struct file_operations
*old_fops
;
132 unsigned long virtual;
135 if (buf_priv
->currently_mapped
== I830_BUF_MAPPED
)
138 down_write(¤t
->mm
->mmap_sem
);
139 old_fops
= filp
->f_op
;
140 filp
->f_op
= &i830_buffer_fops
;
141 dev_priv
->mmap_buffer
= buf
;
142 virtual = do_mmap(filp
, 0, buf
->total
, PROT_READ
| PROT_WRITE
,
143 MAP_SHARED
, buf
->bus_address
);
144 dev_priv
->mmap_buffer
= NULL
;
145 filp
->f_op
= old_fops
;
146 if (IS_ERR((void *)virtual)) { /* ugh */
148 DRM_ERROR("mmap error\n");
150 buf_priv
->virtual = NULL
;
152 buf_priv
->virtual = (void __user
*)virtual;
154 up_write(¤t
->mm
->mmap_sem
);
159 static int i830_unmap_buffer(drm_buf_t
* buf
)
161 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
164 if (buf_priv
->currently_mapped
!= I830_BUF_MAPPED
)
167 down_write(¤t
->mm
->mmap_sem
);
168 retcode
= do_munmap(current
->mm
,
169 (unsigned long)buf_priv
->virtual,
170 (size_t) buf
->total
);
171 up_write(¤t
->mm
->mmap_sem
);
173 buf_priv
->currently_mapped
= I830_BUF_UNMAPPED
;
174 buf_priv
->virtual = NULL
;
179 static int i830_dma_get_buffer(drm_device_t
* dev
, drm_i830_dma_t
* d
,
183 drm_i830_buf_priv_t
*buf_priv
;
186 buf
= i830_freelist_get(dev
);
189 DRM_DEBUG("retcode=%d\n", retcode
);
193 retcode
= i830_map_buffer(buf
, filp
);
195 i830_freelist_put(dev
, buf
);
196 DRM_ERROR("mapbuf failed, retcode %d\n", retcode
);
200 buf_priv
= buf
->dev_private
;
202 d
->request_idx
= buf
->idx
;
203 d
->request_size
= buf
->total
;
204 d
->virtual = buf_priv
->virtual;
209 static int i830_dma_cleanup(drm_device_t
* dev
)
211 drm_device_dma_t
*dma
= dev
->dma
;
213 /* Make sure interrupts are disabled here because the uninstall ioctl
214 * may not have been called from userspace and after dev_private
215 * is freed, it's too late.
217 if (dev
->irq_enabled
)
218 drm_irq_uninstall(dev
);
220 if (dev
->dev_private
) {
222 drm_i830_private_t
*dev_priv
=
223 (drm_i830_private_t
*) dev
->dev_private
;
225 if (dev_priv
->ring
.virtual_start
) {
226 drm_ioremapfree((void *)dev_priv
->ring
.virtual_start
,
227 dev_priv
->ring
.Size
, dev
);
229 if (dev_priv
->hw_status_page
) {
230 pci_free_consistent(dev
->pdev
, PAGE_SIZE
,
231 dev_priv
->hw_status_page
,
232 dev_priv
->dma_status_page
);
233 /* Need to rewrite hardware status page */
234 I830_WRITE(0x02080, 0x1ffff000);
237 drm_free(dev
->dev_private
, sizeof(drm_i830_private_t
),
239 dev
->dev_private
= NULL
;
241 for (i
= 0; i
< dma
->buf_count
; i
++) {
242 drm_buf_t
*buf
= dma
->buflist
[i
];
243 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
244 if (buf_priv
->kernel_virtual
&& buf
->total
)
245 drm_ioremapfree(buf_priv
->kernel_virtual
,
252 int i830_wait_ring(drm_device_t
* dev
, int n
, const char *caller
)
254 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
255 drm_i830_ring_buffer_t
*ring
= &(dev_priv
->ring
);
258 unsigned int last_head
= I830_READ(LP_RING
+ RING_HEAD
) & HEAD_ADDR
;
260 end
= jiffies
+ (HZ
* 3);
261 while (ring
->space
< n
) {
262 ring
->head
= I830_READ(LP_RING
+ RING_HEAD
) & HEAD_ADDR
;
263 ring
->space
= ring
->head
- (ring
->tail
+ 8);
265 ring
->space
+= ring
->Size
;
267 if (ring
->head
!= last_head
) {
268 end
= jiffies
+ (HZ
* 3);
269 last_head
= ring
->head
;
273 if (time_before(end
, jiffies
)) {
274 DRM_ERROR("space: %d wanted %d\n", ring
->space
, n
);
275 DRM_ERROR("lockup\n");
279 dev_priv
->sarea_priv
->perf_boxes
|= I830_BOX_WAIT
;
286 static void i830_kernel_lost_context(drm_device_t
* dev
)
288 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
289 drm_i830_ring_buffer_t
*ring
= &(dev_priv
->ring
);
291 ring
->head
= I830_READ(LP_RING
+ RING_HEAD
) & HEAD_ADDR
;
292 ring
->tail
= I830_READ(LP_RING
+ RING_TAIL
) & TAIL_ADDR
;
293 ring
->space
= ring
->head
- (ring
->tail
+ 8);
295 ring
->space
+= ring
->Size
;
297 if (ring
->head
== ring
->tail
)
298 dev_priv
->sarea_priv
->perf_boxes
|= I830_BOX_RING_EMPTY
;
301 static int i830_freelist_init(drm_device_t
* dev
, drm_i830_private_t
* dev_priv
)
303 drm_device_dma_t
*dma
= dev
->dma
;
305 u32
*hw_status
= (u32
*) (dev_priv
->hw_status_page
+ my_idx
);
308 if (dma
->buf_count
> 1019) {
309 /* Not enough space in the status page for the freelist */
313 for (i
= 0; i
< dma
->buf_count
; i
++) {
314 drm_buf_t
*buf
= dma
->buflist
[i
];
315 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
317 buf_priv
->in_use
= hw_status
++;
318 buf_priv
->my_use_idx
= my_idx
;
321 *buf_priv
->in_use
= I830_BUF_FREE
;
323 buf_priv
->kernel_virtual
= drm_ioremap(buf
->bus_address
,
329 static int i830_dma_initialize(drm_device_t
* dev
,
330 drm_i830_private_t
* dev_priv
,
331 drm_i830_init_t
* init
)
333 struct list_head
*list
;
335 memset(dev_priv
, 0, sizeof(drm_i830_private_t
));
337 list_for_each(list
, &dev
->maplist
->head
) {
338 drm_map_list_t
*r_list
= list_entry(list
, drm_map_list_t
, head
);
340 r_list
->map
->type
== _DRM_SHM
&&
341 r_list
->map
->flags
& _DRM_CONTAINS_LOCK
) {
342 dev_priv
->sarea_map
= r_list
->map
;
347 if (!dev_priv
->sarea_map
) {
348 dev
->dev_private
= (void *)dev_priv
;
349 i830_dma_cleanup(dev
);
350 DRM_ERROR("can not find sarea!\n");
353 dev_priv
->mmio_map
= drm_core_findmap(dev
, init
->mmio_offset
);
354 if (!dev_priv
->mmio_map
) {
355 dev
->dev_private
= (void *)dev_priv
;
356 i830_dma_cleanup(dev
);
357 DRM_ERROR("can not find mmio map!\n");
360 dev
->agp_buffer_token
= init
->buffers_offset
;
361 dev
->agp_buffer_map
= drm_core_findmap(dev
, init
->buffers_offset
);
362 if (!dev
->agp_buffer_map
) {
363 dev
->dev_private
= (void *)dev_priv
;
364 i830_dma_cleanup(dev
);
365 DRM_ERROR("can not find dma buffer map!\n");
369 dev_priv
->sarea_priv
= (drm_i830_sarea_t
*)
370 ((u8
*) dev_priv
->sarea_map
->handle
+ init
->sarea_priv_offset
);
372 dev_priv
->ring
.Start
= init
->ring_start
;
373 dev_priv
->ring
.End
= init
->ring_end
;
374 dev_priv
->ring
.Size
= init
->ring_size
;
376 dev_priv
->ring
.virtual_start
= drm_ioremap(dev
->agp
->base
+
378 init
->ring_size
, dev
);
380 if (dev_priv
->ring
.virtual_start
== NULL
) {
381 dev
->dev_private
= (void *)dev_priv
;
382 i830_dma_cleanup(dev
);
383 DRM_ERROR("can not ioremap virtual address for"
388 dev_priv
->ring
.tail_mask
= dev_priv
->ring
.Size
- 1;
390 dev_priv
->w
= init
->w
;
391 dev_priv
->h
= init
->h
;
392 dev_priv
->pitch
= init
->pitch
;
393 dev_priv
->back_offset
= init
->back_offset
;
394 dev_priv
->depth_offset
= init
->depth_offset
;
395 dev_priv
->front_offset
= init
->front_offset
;
397 dev_priv
->front_di1
= init
->front_offset
| init
->pitch_bits
;
398 dev_priv
->back_di1
= init
->back_offset
| init
->pitch_bits
;
399 dev_priv
->zi1
= init
->depth_offset
| init
->pitch_bits
;
401 DRM_DEBUG("front_di1 %x\n", dev_priv
->front_di1
);
402 DRM_DEBUG("back_offset %x\n", dev_priv
->back_offset
);
403 DRM_DEBUG("back_di1 %x\n", dev_priv
->back_di1
);
404 DRM_DEBUG("pitch_bits %x\n", init
->pitch_bits
);
406 dev_priv
->cpp
= init
->cpp
;
407 /* We are using separate values as placeholders for mechanisms for
408 * private backbuffer/depthbuffer usage.
411 dev_priv
->back_pitch
= init
->back_pitch
;
412 dev_priv
->depth_pitch
= init
->depth_pitch
;
413 dev_priv
->do_boxes
= 0;
414 dev_priv
->use_mi_batchbuffer_start
= 0;
416 /* Program Hardware Status Page */
417 dev_priv
->hw_status_page
=
418 pci_alloc_consistent(dev
->pdev
, PAGE_SIZE
,
419 &dev_priv
->dma_status_page
);
420 if (!dev_priv
->hw_status_page
) {
421 dev
->dev_private
= (void *)dev_priv
;
422 i830_dma_cleanup(dev
);
423 DRM_ERROR("Can not allocate hardware status page\n");
426 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
427 DRM_DEBUG("hw status page @ %p\n", dev_priv
->hw_status_page
);
429 I830_WRITE(0x02080, dev_priv
->dma_status_page
);
430 DRM_DEBUG("Enabled hardware status page\n");
432 /* Now we need to init our freelist */
433 if (i830_freelist_init(dev
, dev_priv
) != 0) {
434 dev
->dev_private
= (void *)dev_priv
;
435 i830_dma_cleanup(dev
);
436 DRM_ERROR("Not enough space in the status page for"
440 dev
->dev_private
= (void *)dev_priv
;
445 static int i830_dma_init(struct inode
*inode
, struct file
*filp
,
446 unsigned int cmd
, unsigned long arg
)
448 drm_file_t
*priv
= filp
->private_data
;
449 drm_device_t
*dev
= priv
->head
->dev
;
450 drm_i830_private_t
*dev_priv
;
451 drm_i830_init_t init
;
454 if (copy_from_user(&init
, (void *__user
)arg
, sizeof(init
)))
459 dev_priv
= drm_alloc(sizeof(drm_i830_private_t
),
461 if (dev_priv
== NULL
)
463 retcode
= i830_dma_initialize(dev
, dev_priv
, &init
);
465 case I830_CLEANUP_DMA
:
466 retcode
= i830_dma_cleanup(dev
);
476 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
477 #define ST1_ENABLE (1<<16)
478 #define ST1_MASK (0xffff)
480 /* Most efficient way to verify state for the i830 is as it is
481 * emitted. Non-conformant state is silently dropped.
483 static void i830EmitContextVerified(drm_device_t
* dev
, unsigned int *code
)
485 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
490 BEGIN_LP_RING(I830_CTX_SETUP_SIZE
+ 4);
492 for (i
= 0; i
< I830_CTXREG_BLENDCOLR0
; i
++) {
494 if ((tmp
& (7 << 29)) == CMD_3D
&&
495 (tmp
& (0x1f << 24)) < (0x1d << 24)) {
499 DRM_ERROR("Skipping %d\n", i
);
503 OUT_RING(STATE3D_CONST_BLEND_COLOR_CMD
);
504 OUT_RING(code
[I830_CTXREG_BLENDCOLR
]);
507 for (i
= I830_CTXREG_VF
; i
< I830_CTXREG_MCSB0
; i
++) {
509 if ((tmp
& (7 << 29)) == CMD_3D
&&
510 (tmp
& (0x1f << 24)) < (0x1d << 24)) {
514 DRM_ERROR("Skipping %d\n", i
);
518 OUT_RING(STATE3D_MAP_COORD_SETBIND_CMD
);
519 OUT_RING(code
[I830_CTXREG_MCSB1
]);
528 static void i830EmitTexVerified(drm_device_t
* dev
, unsigned int *code
)
530 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
535 if (code
[I830_TEXREG_MI0
] == GFX_OP_MAP_INFO
||
536 (code
[I830_TEXREG_MI0
] & ~(0xf * LOAD_TEXTURE_MAP0
)) ==
537 (STATE3D_LOAD_STATE_IMMEDIATE_2
| 4)) {
539 BEGIN_LP_RING(I830_TEX_SETUP_SIZE
);
541 OUT_RING(code
[I830_TEXREG_MI0
]); /* TM0LI */
542 OUT_RING(code
[I830_TEXREG_MI1
]); /* TM0S0 */
543 OUT_RING(code
[I830_TEXREG_MI2
]); /* TM0S1 */
544 OUT_RING(code
[I830_TEXREG_MI3
]); /* TM0S2 */
545 OUT_RING(code
[I830_TEXREG_MI4
]); /* TM0S3 */
546 OUT_RING(code
[I830_TEXREG_MI5
]); /* TM0S4 */
548 for (i
= 6; i
< I830_TEX_SETUP_SIZE
; i
++) {
559 printk("rejected packet %x\n", code
[0]);
562 static void i830EmitTexBlendVerified(drm_device_t
* dev
,
563 unsigned int *code
, unsigned int num
)
565 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
573 BEGIN_LP_RING(num
+ 1);
575 for (i
= 0; i
< num
; i
++) {
587 static void i830EmitTexPalette(drm_device_t
* dev
,
588 unsigned int *palette
, int number
, int is_shared
)
590 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
598 if (is_shared
== 1) {
599 OUT_RING(CMD_OP_MAP_PALETTE_LOAD
|
600 MAP_PALETTE_NUM(0) | MAP_PALETTE_BOTH
);
602 OUT_RING(CMD_OP_MAP_PALETTE_LOAD
| MAP_PALETTE_NUM(number
));
604 for (i
= 0; i
< 256; i
++) {
605 OUT_RING(palette
[i
]);
608 /* KW: WHERE IS THE ADVANCE_LP_RING? This is effectively a noop!
612 /* Need to do some additional checking when setting the dest buffer.
614 static void i830EmitDestVerified(drm_device_t
* dev
, unsigned int *code
)
616 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
620 BEGIN_LP_RING(I830_DEST_SETUP_SIZE
+ 10);
622 tmp
= code
[I830_DESTREG_CBUFADDR
];
623 if (tmp
== dev_priv
->front_di1
|| tmp
== dev_priv
->back_di1
) {
624 if (((int)outring
) & 8) {
629 OUT_RING(CMD_OP_DESTBUFFER_INFO
);
630 OUT_RING(BUF_3D_ID_COLOR_BACK
|
631 BUF_3D_PITCH(dev_priv
->back_pitch
* dev_priv
->cpp
) |
636 OUT_RING(CMD_OP_DESTBUFFER_INFO
);
637 OUT_RING(BUF_3D_ID_DEPTH
| BUF_3D_USE_FENCE
|
638 BUF_3D_PITCH(dev_priv
->depth_pitch
* dev_priv
->cpp
));
639 OUT_RING(dev_priv
->zi1
);
642 DRM_ERROR("bad di1 %x (allow %x or %x)\n",
643 tmp
, dev_priv
->front_di1
, dev_priv
->back_di1
);
649 OUT_RING(GFX_OP_DESTBUFFER_VARS
);
650 OUT_RING(code
[I830_DESTREG_DV1
]);
652 OUT_RING(GFX_OP_DRAWRECT_INFO
);
653 OUT_RING(code
[I830_DESTREG_DR1
]);
654 OUT_RING(code
[I830_DESTREG_DR2
]);
655 OUT_RING(code
[I830_DESTREG_DR3
]);
656 OUT_RING(code
[I830_DESTREG_DR4
]);
658 /* Need to verify this */
659 tmp
= code
[I830_DESTREG_SENABLE
];
660 if ((tmp
& ~0x3) == GFX_OP_SCISSOR_ENABLE
) {
663 DRM_ERROR("bad scissor enable\n");
667 OUT_RING(GFX_OP_SCISSOR_RECT
);
668 OUT_RING(code
[I830_DESTREG_SR1
]);
669 OUT_RING(code
[I830_DESTREG_SR2
]);
675 static void i830EmitStippleVerified(drm_device_t
* dev
, unsigned int *code
)
677 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
681 OUT_RING(GFX_OP_STIPPLE
);
686 static void i830EmitState(drm_device_t
* dev
)
688 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
689 drm_i830_sarea_t
*sarea_priv
= dev_priv
->sarea_priv
;
690 unsigned int dirty
= sarea_priv
->dirty
;
692 DRM_DEBUG("%s %x\n", __FUNCTION__
, dirty
);
694 if (dirty
& I830_UPLOAD_BUFFERS
) {
695 i830EmitDestVerified(dev
, sarea_priv
->BufferState
);
696 sarea_priv
->dirty
&= ~I830_UPLOAD_BUFFERS
;
699 if (dirty
& I830_UPLOAD_CTX
) {
700 i830EmitContextVerified(dev
, sarea_priv
->ContextState
);
701 sarea_priv
->dirty
&= ~I830_UPLOAD_CTX
;
704 if (dirty
& I830_UPLOAD_TEX0
) {
705 i830EmitTexVerified(dev
, sarea_priv
->TexState
[0]);
706 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX0
;
709 if (dirty
& I830_UPLOAD_TEX1
) {
710 i830EmitTexVerified(dev
, sarea_priv
->TexState
[1]);
711 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX1
;
714 if (dirty
& I830_UPLOAD_TEXBLEND0
) {
715 i830EmitTexBlendVerified(dev
, sarea_priv
->TexBlendState
[0],
716 sarea_priv
->TexBlendStateWordsUsed
[0]);
717 sarea_priv
->dirty
&= ~I830_UPLOAD_TEXBLEND0
;
720 if (dirty
& I830_UPLOAD_TEXBLEND1
) {
721 i830EmitTexBlendVerified(dev
, sarea_priv
->TexBlendState
[1],
722 sarea_priv
->TexBlendStateWordsUsed
[1]);
723 sarea_priv
->dirty
&= ~I830_UPLOAD_TEXBLEND1
;
726 if (dirty
& I830_UPLOAD_TEX_PALETTE_SHARED
) {
727 i830EmitTexPalette(dev
, sarea_priv
->Palette
[0], 0, 1);
729 if (dirty
& I830_UPLOAD_TEX_PALETTE_N(0)) {
730 i830EmitTexPalette(dev
, sarea_priv
->Palette
[0], 0, 0);
731 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX_PALETTE_N(0);
733 if (dirty
& I830_UPLOAD_TEX_PALETTE_N(1)) {
734 i830EmitTexPalette(dev
, sarea_priv
->Palette
[1], 1, 0);
735 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX_PALETTE_N(1);
741 if (dirty
& I830_UPLOAD_TEX_PALETTE_N(2)) {
742 i830EmitTexPalette(dev
, sarea_priv
->Palette2
[0], 0, 0);
743 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX_PALETTE_N(2);
745 if (dirty
& I830_UPLOAD_TEX_PALETTE_N(3)) {
746 i830EmitTexPalette(dev
, sarea_priv
->Palette2
[1], 1, 0);
747 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX_PALETTE_N(2);
754 if (dirty
& I830_UPLOAD_STIPPLE
) {
755 i830EmitStippleVerified(dev
, sarea_priv
->StippleState
);
756 sarea_priv
->dirty
&= ~I830_UPLOAD_STIPPLE
;
759 if (dirty
& I830_UPLOAD_TEX2
) {
760 i830EmitTexVerified(dev
, sarea_priv
->TexState2
);
761 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX2
;
764 if (dirty
& I830_UPLOAD_TEX3
) {
765 i830EmitTexVerified(dev
, sarea_priv
->TexState3
);
766 sarea_priv
->dirty
&= ~I830_UPLOAD_TEX3
;
769 if (dirty
& I830_UPLOAD_TEXBLEND2
) {
770 i830EmitTexBlendVerified(dev
,
771 sarea_priv
->TexBlendState2
,
772 sarea_priv
->TexBlendStateWordsUsed2
);
774 sarea_priv
->dirty
&= ~I830_UPLOAD_TEXBLEND2
;
777 if (dirty
& I830_UPLOAD_TEXBLEND3
) {
778 i830EmitTexBlendVerified(dev
,
779 sarea_priv
->TexBlendState3
,
780 sarea_priv
->TexBlendStateWordsUsed3
);
781 sarea_priv
->dirty
&= ~I830_UPLOAD_TEXBLEND3
;
785 /* ================================================================
786 * Performance monitoring functions
789 static void i830_fill_box(drm_device_t
* dev
,
790 int x
, int y
, int w
, int h
, int r
, int g
, int b
)
792 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
794 unsigned int BR13
, CMD
;
797 BR13
= (0xF0 << 16) | (dev_priv
->pitch
* dev_priv
->cpp
) | (1 << 24);
798 CMD
= XY_COLOR_BLT_CMD
;
799 x
+= dev_priv
->sarea_priv
->boxes
[0].x1
;
800 y
+= dev_priv
->sarea_priv
->boxes
[0].y1
;
802 if (dev_priv
->cpp
== 4) {
804 CMD
|= (XY_COLOR_BLT_WRITE_ALPHA
| XY_COLOR_BLT_WRITE_RGB
);
805 color
= (((0xff) << 24) | (r
<< 16) | (g
<< 8) | b
);
807 color
= (((r
& 0xf8) << 8) |
808 ((g
& 0xfc) << 3) | ((b
& 0xf8) >> 3));
814 OUT_RING((y
<< 16) | x
);
815 OUT_RING(((y
+ h
) << 16) | (x
+ w
));
817 if (dev_priv
->current_page
== 1) {
818 OUT_RING(dev_priv
->front_offset
);
820 OUT_RING(dev_priv
->back_offset
);
827 static void i830_cp_performance_boxes(drm_device_t
* dev
)
829 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
831 /* Purple box for page flipping
833 if (dev_priv
->sarea_priv
->perf_boxes
& I830_BOX_FLIP
)
834 i830_fill_box(dev
, 4, 4, 8, 8, 255, 0, 255);
836 /* Red box if we have to wait for idle at any point
838 if (dev_priv
->sarea_priv
->perf_boxes
& I830_BOX_WAIT
)
839 i830_fill_box(dev
, 16, 4, 8, 8, 255, 0, 0);
841 /* Blue box: lost context?
843 if (dev_priv
->sarea_priv
->perf_boxes
& I830_BOX_LOST_CONTEXT
)
844 i830_fill_box(dev
, 28, 4, 8, 8, 0, 0, 255);
846 /* Yellow box for texture swaps
848 if (dev_priv
->sarea_priv
->perf_boxes
& I830_BOX_TEXTURE_LOAD
)
849 i830_fill_box(dev
, 40, 4, 8, 8, 255, 255, 0);
851 /* Green box if hardware never idles (as far as we can tell)
853 if (!(dev_priv
->sarea_priv
->perf_boxes
& I830_BOX_RING_EMPTY
))
854 i830_fill_box(dev
, 64, 4, 8, 8, 0, 255, 0);
856 /* Draw bars indicating number of buffers allocated
857 * (not a great measure, easily confused)
859 if (dev_priv
->dma_used
) {
860 int bar
= dev_priv
->dma_used
/ 10240;
865 i830_fill_box(dev
, 4, 16, bar
, 4, 196, 128, 128);
866 dev_priv
->dma_used
= 0;
869 dev_priv
->sarea_priv
->perf_boxes
= 0;
872 static void i830_dma_dispatch_clear(drm_device_t
* dev
, int flags
,
873 unsigned int clear_color
,
874 unsigned int clear_zval
,
875 unsigned int clear_depthmask
)
877 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
878 drm_i830_sarea_t
*sarea_priv
= dev_priv
->sarea_priv
;
879 int nbox
= sarea_priv
->nbox
;
880 drm_clip_rect_t
*pbox
= sarea_priv
->boxes
;
881 int pitch
= dev_priv
->pitch
;
882 int cpp
= dev_priv
->cpp
;
884 unsigned int BR13
, CMD
, D_CMD
;
887 if (dev_priv
->current_page
== 1) {
888 unsigned int tmp
= flags
;
890 flags
&= ~(I830_FRONT
| I830_BACK
);
891 if (tmp
& I830_FRONT
)
897 i830_kernel_lost_context(dev
);
901 BR13
= (0xF0 << 16) | (pitch
* cpp
) | (1 << 24);
902 D_CMD
= CMD
= XY_COLOR_BLT_CMD
;
905 BR13
= (0xF0 << 16) | (pitch
* cpp
) | (1 << 24) | (1 << 25);
906 CMD
= (XY_COLOR_BLT_CMD
| XY_COLOR_BLT_WRITE_ALPHA
|
907 XY_COLOR_BLT_WRITE_RGB
);
908 D_CMD
= XY_COLOR_BLT_CMD
;
909 if (clear_depthmask
& 0x00ffffff)
910 D_CMD
|= XY_COLOR_BLT_WRITE_RGB
;
911 if (clear_depthmask
& 0xff000000)
912 D_CMD
|= XY_COLOR_BLT_WRITE_ALPHA
;
915 BR13
= (0xF0 << 16) | (pitch
* cpp
) | (1 << 24);
916 D_CMD
= CMD
= XY_COLOR_BLT_CMD
;
920 if (nbox
> I830_NR_SAREA_CLIPRECTS
)
921 nbox
= I830_NR_SAREA_CLIPRECTS
;
923 for (i
= 0; i
< nbox
; i
++, pbox
++) {
924 if (pbox
->x1
> pbox
->x2
||
925 pbox
->y1
> pbox
->y2
||
926 pbox
->x2
> dev_priv
->w
|| pbox
->y2
> dev_priv
->h
)
929 if (flags
& I830_FRONT
) {
930 DRM_DEBUG("clear front\n");
934 OUT_RING((pbox
->y1
<< 16) | pbox
->x1
);
935 OUT_RING((pbox
->y2
<< 16) | pbox
->x2
);
936 OUT_RING(dev_priv
->front_offset
);
937 OUT_RING(clear_color
);
941 if (flags
& I830_BACK
) {
942 DRM_DEBUG("clear back\n");
946 OUT_RING((pbox
->y1
<< 16) | pbox
->x1
);
947 OUT_RING((pbox
->y2
<< 16) | pbox
->x2
);
948 OUT_RING(dev_priv
->back_offset
);
949 OUT_RING(clear_color
);
953 if (flags
& I830_DEPTH
) {
954 DRM_DEBUG("clear depth\n");
958 OUT_RING((pbox
->y1
<< 16) | pbox
->x1
);
959 OUT_RING((pbox
->y2
<< 16) | pbox
->x2
);
960 OUT_RING(dev_priv
->depth_offset
);
961 OUT_RING(clear_zval
);
967 static void i830_dma_dispatch_swap(drm_device_t
* dev
)
969 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
970 drm_i830_sarea_t
*sarea_priv
= dev_priv
->sarea_priv
;
971 int nbox
= sarea_priv
->nbox
;
972 drm_clip_rect_t
*pbox
= sarea_priv
->boxes
;
973 int pitch
= dev_priv
->pitch
;
974 int cpp
= dev_priv
->cpp
;
976 unsigned int CMD
, BR13
;
979 DRM_DEBUG("swapbuffers\n");
981 i830_kernel_lost_context(dev
);
983 if (dev_priv
->do_boxes
)
984 i830_cp_performance_boxes(dev
);
988 BR13
= (pitch
* cpp
) | (0xCC << 16) | (1 << 24);
989 CMD
= XY_SRC_COPY_BLT_CMD
;
992 BR13
= (pitch
* cpp
) | (0xCC << 16) | (1 << 24) | (1 << 25);
993 CMD
= (XY_SRC_COPY_BLT_CMD
| XY_SRC_COPY_BLT_WRITE_ALPHA
|
994 XY_SRC_COPY_BLT_WRITE_RGB
);
997 BR13
= (pitch
* cpp
) | (0xCC << 16) | (1 << 24);
998 CMD
= XY_SRC_COPY_BLT_CMD
;
1002 if (nbox
> I830_NR_SAREA_CLIPRECTS
)
1003 nbox
= I830_NR_SAREA_CLIPRECTS
;
1005 for (i
= 0; i
< nbox
; i
++, pbox
++) {
1006 if (pbox
->x1
> pbox
->x2
||
1007 pbox
->y1
> pbox
->y2
||
1008 pbox
->x2
> dev_priv
->w
|| pbox
->y2
> dev_priv
->h
)
1011 DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n",
1012 pbox
->x1
, pbox
->y1
, pbox
->x2
, pbox
->y2
);
1017 OUT_RING((pbox
->y1
<< 16) | pbox
->x1
);
1018 OUT_RING((pbox
->y2
<< 16) | pbox
->x2
);
1020 if (dev_priv
->current_page
== 0)
1021 OUT_RING(dev_priv
->front_offset
);
1023 OUT_RING(dev_priv
->back_offset
);
1025 OUT_RING((pbox
->y1
<< 16) | pbox
->x1
);
1026 OUT_RING(BR13
& 0xffff);
1028 if (dev_priv
->current_page
== 0)
1029 OUT_RING(dev_priv
->back_offset
);
1031 OUT_RING(dev_priv
->front_offset
);
1037 static void i830_dma_dispatch_flip(drm_device_t
* dev
)
1039 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1042 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
1044 dev_priv
->current_page
,
1045 dev_priv
->sarea_priv
->pf_current_page
);
1047 i830_kernel_lost_context(dev
);
1049 if (dev_priv
->do_boxes
) {
1050 dev_priv
->sarea_priv
->perf_boxes
|= I830_BOX_FLIP
;
1051 i830_cp_performance_boxes(dev
);
1055 OUT_RING(INST_PARSER_CLIENT
| INST_OP_FLUSH
| INST_FLUSH_MAP_CACHE
);
1060 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO
| ASYNC_FLIP
);
1062 if (dev_priv
->current_page
== 0) {
1063 OUT_RING(dev_priv
->back_offset
);
1064 dev_priv
->current_page
= 1;
1066 OUT_RING(dev_priv
->front_offset
);
1067 dev_priv
->current_page
= 0;
1073 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_PLANE_A_FLIP
);
1077 dev_priv
->sarea_priv
->pf_current_page
= dev_priv
->current_page
;
1080 static void i830_dma_dispatch_vertex(drm_device_t
* dev
,
1081 drm_buf_t
* buf
, int discard
, int used
)
1083 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1084 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
1085 drm_i830_sarea_t
*sarea_priv
= dev_priv
->sarea_priv
;
1086 drm_clip_rect_t
*box
= sarea_priv
->boxes
;
1087 int nbox
= sarea_priv
->nbox
;
1088 unsigned long address
= (unsigned long)buf
->bus_address
;
1089 unsigned long start
= address
- dev
->agp
->base
;
1093 i830_kernel_lost_context(dev
);
1095 if (nbox
> I830_NR_SAREA_CLIPRECTS
)
1096 nbox
= I830_NR_SAREA_CLIPRECTS
;
1099 u
= cmpxchg(buf_priv
->in_use
, I830_BUF_CLIENT
,
1101 if (u
!= I830_BUF_CLIENT
) {
1102 DRM_DEBUG("xxxx 2\n");
1106 if (used
> 4 * 1023)
1109 if (sarea_priv
->dirty
)
1112 DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n",
1113 address
, used
, nbox
);
1115 dev_priv
->counter
++;
1116 DRM_DEBUG("dispatch counter : %ld\n", dev_priv
->counter
);
1117 DRM_DEBUG("i830_dma_dispatch\n");
1118 DRM_DEBUG("start : %lx\n", start
);
1119 DRM_DEBUG("used : %d\n", used
);
1120 DRM_DEBUG("start + used - 4 : %ld\n", start
+ used
- 4);
1122 if (buf_priv
->currently_mapped
== I830_BUF_MAPPED
) {
1123 u32
*vp
= buf_priv
->kernel_virtual
;
1125 vp
[0] = (GFX_OP_PRIMITIVE
|
1126 sarea_priv
->vertex_prim
| ((used
/ 4) - 2));
1128 if (dev_priv
->use_mi_batchbuffer_start
) {
1129 vp
[used
/ 4] = MI_BATCH_BUFFER_END
;
1138 i830_unmap_buffer(buf
);
1145 OUT_RING(GFX_OP_DRAWRECT_INFO
);
1146 OUT_RING(sarea_priv
->
1147 BufferState
[I830_DESTREG_DR1
]);
1148 OUT_RING(box
[i
].x1
| (box
[i
].y1
<< 16));
1149 OUT_RING(box
[i
].x2
| (box
[i
].y2
<< 16));
1150 OUT_RING(sarea_priv
->
1151 BufferState
[I830_DESTREG_DR4
]);
1156 if (dev_priv
->use_mi_batchbuffer_start
) {
1158 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6));
1159 OUT_RING(start
| MI_BATCH_NON_SECURE
);
1163 OUT_RING(MI_BATCH_BUFFER
);
1164 OUT_RING(start
| MI_BATCH_NON_SECURE
);
1165 OUT_RING(start
+ used
- 4);
1170 } while (++i
< nbox
);
1174 dev_priv
->counter
++;
1176 (void)cmpxchg(buf_priv
->in_use
, I830_BUF_CLIENT
,
1180 OUT_RING(CMD_STORE_DWORD_IDX
);
1182 OUT_RING(dev_priv
->counter
);
1183 OUT_RING(CMD_STORE_DWORD_IDX
);
1184 OUT_RING(buf_priv
->my_use_idx
);
1185 OUT_RING(I830_BUF_FREE
);
1186 OUT_RING(CMD_REPORT_HEAD
);
1192 static void i830_dma_quiescent(drm_device_t
* dev
)
1194 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1197 i830_kernel_lost_context(dev
);
1200 OUT_RING(INST_PARSER_CLIENT
| INST_OP_FLUSH
| INST_FLUSH_MAP_CACHE
);
1201 OUT_RING(CMD_REPORT_HEAD
);
1206 i830_wait_ring(dev
, dev_priv
->ring
.Size
- 8, __FUNCTION__
);
1209 static int i830_flush_queue(drm_device_t
* dev
)
1211 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1212 drm_device_dma_t
*dma
= dev
->dma
;
1216 i830_kernel_lost_context(dev
);
1219 OUT_RING(CMD_REPORT_HEAD
);
1223 i830_wait_ring(dev
, dev_priv
->ring
.Size
- 8, __FUNCTION__
);
1225 for (i
= 0; i
< dma
->buf_count
; i
++) {
1226 drm_buf_t
*buf
= dma
->buflist
[i
];
1227 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
1229 int used
= cmpxchg(buf_priv
->in_use
, I830_BUF_HARDWARE
,
1232 if (used
== I830_BUF_HARDWARE
)
1233 DRM_DEBUG("reclaimed from HARDWARE\n");
1234 if (used
== I830_BUF_CLIENT
)
1235 DRM_DEBUG("still on client\n");
1241 /* Must be called with the lock held */
1242 static void i830_reclaim_buffers(drm_device_t
* dev
, struct file
*filp
)
1244 drm_device_dma_t
*dma
= dev
->dma
;
1249 if (!dev
->dev_private
)
1254 i830_flush_queue(dev
);
1256 for (i
= 0; i
< dma
->buf_count
; i
++) {
1257 drm_buf_t
*buf
= dma
->buflist
[i
];
1258 drm_i830_buf_priv_t
*buf_priv
= buf
->dev_private
;
1260 if (buf
->filp
== filp
&& buf_priv
) {
1261 int used
= cmpxchg(buf_priv
->in_use
, I830_BUF_CLIENT
,
1264 if (used
== I830_BUF_CLIENT
)
1265 DRM_DEBUG("reclaimed from client\n");
1266 if (buf_priv
->currently_mapped
== I830_BUF_MAPPED
)
1267 buf_priv
->currently_mapped
= I830_BUF_UNMAPPED
;
1272 static int i830_flush_ioctl(struct inode
*inode
, struct file
*filp
,
1273 unsigned int cmd
, unsigned long arg
)
1275 drm_file_t
*priv
= filp
->private_data
;
1276 drm_device_t
*dev
= priv
->head
->dev
;
1278 LOCK_TEST_WITH_RETURN(dev
, filp
);
1280 i830_flush_queue(dev
);
1284 static int i830_dma_vertex(struct inode
*inode
, struct file
*filp
,
1285 unsigned int cmd
, unsigned long arg
)
1287 drm_file_t
*priv
= filp
->private_data
;
1288 drm_device_t
*dev
= priv
->head
->dev
;
1289 drm_device_dma_t
*dma
= dev
->dma
;
1290 drm_i830_private_t
*dev_priv
= (drm_i830_private_t
*) dev
->dev_private
;
1291 u32
*hw_status
= dev_priv
->hw_status_page
;
1292 drm_i830_sarea_t
*sarea_priv
= (drm_i830_sarea_t
*)
1293 dev_priv
->sarea_priv
;
1294 drm_i830_vertex_t vertex
;
1297 (&vertex
, (drm_i830_vertex_t __user
*) arg
, sizeof(vertex
)))
1300 LOCK_TEST_WITH_RETURN(dev
, filp
);
1302 DRM_DEBUG("i830 dma vertex, idx %d used %d discard %d\n",
1303 vertex
.idx
, vertex
.used
, vertex
.discard
);
1305 if (vertex
.idx
< 0 || vertex
.idx
> dma
->buf_count
)
1308 i830_dma_dispatch_vertex(dev
,
1309 dma
->buflist
[vertex
.idx
],
1310 vertex
.discard
, vertex
.used
);
1312 sarea_priv
->last_enqueue
= dev_priv
->counter
- 1;
1313 sarea_priv
->last_dispatch
= (int)hw_status
[5];
1318 static int i830_clear_bufs(struct inode
*inode
, struct file
*filp
,
1319 unsigned int cmd
, unsigned long arg
)
1321 drm_file_t
*priv
= filp
->private_data
;
1322 drm_device_t
*dev
= priv
->head
->dev
;
1323 drm_i830_clear_t clear
;
1326 (&clear
, (drm_i830_clear_t __user
*) arg
, sizeof(clear
)))
1329 LOCK_TEST_WITH_RETURN(dev
, filp
);
1331 /* GH: Someone's doing nasty things... */
1332 if (!dev
->dev_private
) {
1336 i830_dma_dispatch_clear(dev
, clear
.flags
,
1338 clear
.clear_depth
, clear
.clear_depthmask
);
1342 static int i830_swap_bufs(struct inode
*inode
, struct file
*filp
,
1343 unsigned int cmd
, unsigned long arg
)
1345 drm_file_t
*priv
= filp
->private_data
;
1346 drm_device_t
*dev
= priv
->head
->dev
;
1348 DRM_DEBUG("i830_swap_bufs\n");
1350 LOCK_TEST_WITH_RETURN(dev
, filp
);
1352 i830_dma_dispatch_swap(dev
);
1356 /* Not sure why this isn't set all the time:
1358 static void i830_do_init_pageflip(drm_device_t
* dev
)
1360 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1362 DRM_DEBUG("%s\n", __FUNCTION__
);
1363 dev_priv
->page_flipping
= 1;
1364 dev_priv
->current_page
= 0;
1365 dev_priv
->sarea_priv
->pf_current_page
= dev_priv
->current_page
;
1368 static int i830_do_cleanup_pageflip(drm_device_t
* dev
)
1370 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1372 DRM_DEBUG("%s\n", __FUNCTION__
);
1373 if (dev_priv
->current_page
!= 0)
1374 i830_dma_dispatch_flip(dev
);
1376 dev_priv
->page_flipping
= 0;
1380 static int i830_flip_bufs(struct inode
*inode
, struct file
*filp
,
1381 unsigned int cmd
, unsigned long arg
)
1383 drm_file_t
*priv
= filp
->private_data
;
1384 drm_device_t
*dev
= priv
->head
->dev
;
1385 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1387 DRM_DEBUG("%s\n", __FUNCTION__
);
1389 LOCK_TEST_WITH_RETURN(dev
, filp
);
1391 if (!dev_priv
->page_flipping
)
1392 i830_do_init_pageflip(dev
);
1394 i830_dma_dispatch_flip(dev
);
1398 static int i830_getage(struct inode
*inode
, struct file
*filp
, unsigned int cmd
,
1401 drm_file_t
*priv
= filp
->private_data
;
1402 drm_device_t
*dev
= priv
->head
->dev
;
1403 drm_i830_private_t
*dev_priv
= (drm_i830_private_t
*) dev
->dev_private
;
1404 u32
*hw_status
= dev_priv
->hw_status_page
;
1405 drm_i830_sarea_t
*sarea_priv
= (drm_i830_sarea_t
*)
1406 dev_priv
->sarea_priv
;
1408 sarea_priv
->last_dispatch
= (int)hw_status
[5];
1412 static int i830_getbuf(struct inode
*inode
, struct file
*filp
, unsigned int cmd
,
1415 drm_file_t
*priv
= filp
->private_data
;
1416 drm_device_t
*dev
= priv
->head
->dev
;
1419 drm_i830_private_t
*dev_priv
= (drm_i830_private_t
*) dev
->dev_private
;
1420 u32
*hw_status
= dev_priv
->hw_status_page
;
1421 drm_i830_sarea_t
*sarea_priv
= (drm_i830_sarea_t
*)
1422 dev_priv
->sarea_priv
;
1424 DRM_DEBUG("getbuf\n");
1425 if (copy_from_user(&d
, (drm_i830_dma_t __user
*) arg
, sizeof(d
)))
1428 LOCK_TEST_WITH_RETURN(dev
, filp
);
1432 retcode
= i830_dma_get_buffer(dev
, &d
, filp
);
1434 DRM_DEBUG("i830_dma: %d returning %d, granted = %d\n",
1435 current
->pid
, retcode
, d
.granted
);
1437 if (copy_to_user((drm_dma_t __user
*) arg
, &d
, sizeof(d
)))
1439 sarea_priv
->last_dispatch
= (int)hw_status
[5];
1444 static int i830_copybuf(struct inode
*inode
,
1445 struct file
*filp
, unsigned int cmd
, unsigned long arg
)
1447 /* Never copy - 2.4.x doesn't need it */
1451 static int i830_docopy(struct inode
*inode
, struct file
*filp
, unsigned int cmd
,
1457 static int i830_getparam(struct inode
*inode
, struct file
*filp
,
1458 unsigned int cmd
, unsigned long arg
)
1460 drm_file_t
*priv
= filp
->private_data
;
1461 drm_device_t
*dev
= priv
->head
->dev
;
1462 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1463 drm_i830_getparam_t param
;
1467 DRM_ERROR("%s called with no initialization\n", __FUNCTION__
);
1472 (¶m
, (drm_i830_getparam_t __user
*) arg
, sizeof(param
)))
1475 switch (param
.param
) {
1476 case I830_PARAM_IRQ_ACTIVE
:
1477 value
= dev
->irq_enabled
;
1483 if (copy_to_user(param
.value
, &value
, sizeof(int))) {
1484 DRM_ERROR("copy_to_user\n");
1491 static int i830_setparam(struct inode
*inode
, struct file
*filp
,
1492 unsigned int cmd
, unsigned long arg
)
1494 drm_file_t
*priv
= filp
->private_data
;
1495 drm_device_t
*dev
= priv
->head
->dev
;
1496 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1497 drm_i830_setparam_t param
;
1500 DRM_ERROR("%s called with no initialization\n", __FUNCTION__
);
1505 (¶m
, (drm_i830_setparam_t __user
*) arg
, sizeof(param
)))
1508 switch (param
.param
) {
1509 case I830_SETPARAM_USE_MI_BATCHBUFFER_START
:
1510 dev_priv
->use_mi_batchbuffer_start
= param
.value
;
1519 int i830_driver_load(drm_device_t
*dev
, unsigned long flags
)
1521 /* i830 has 4 more counters */
1523 dev
->types
[6] = _DRM_STAT_IRQ
;
1524 dev
->types
[7] = _DRM_STAT_PRIMARY
;
1525 dev
->types
[8] = _DRM_STAT_SECONDARY
;
1526 dev
->types
[9] = _DRM_STAT_DMA
;
1531 void i830_driver_lastclose(drm_device_t
* dev
)
1533 i830_dma_cleanup(dev
);
1536 void i830_driver_preclose(drm_device_t
* dev
, DRMFILE filp
)
1538 if (dev
->dev_private
) {
1539 drm_i830_private_t
*dev_priv
= dev
->dev_private
;
1540 if (dev_priv
->page_flipping
) {
1541 i830_do_cleanup_pageflip(dev
);
1546 void i830_driver_reclaim_buffers_locked(drm_device_t
* dev
, struct file
*filp
)
1548 i830_reclaim_buffers(dev
, filp
);
1551 int i830_driver_dma_quiescent(drm_device_t
* dev
)
1553 i830_dma_quiescent(dev
);
1557 drm_ioctl_desc_t i830_ioctls
[] = {
1558 [DRM_IOCTL_NR(DRM_I830_INIT
)] = {i830_dma_init
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
},
1559 [DRM_IOCTL_NR(DRM_I830_VERTEX
)] = {i830_dma_vertex
, DRM_AUTH
},
1560 [DRM_IOCTL_NR(DRM_I830_CLEAR
)] = {i830_clear_bufs
, DRM_AUTH
},
1561 [DRM_IOCTL_NR(DRM_I830_FLUSH
)] = {i830_flush_ioctl
, DRM_AUTH
},
1562 [DRM_IOCTL_NR(DRM_I830_GETAGE
)] = {i830_getage
, DRM_AUTH
},
1563 [DRM_IOCTL_NR(DRM_I830_GETBUF
)] = {i830_getbuf
, DRM_AUTH
},
1564 [DRM_IOCTL_NR(DRM_I830_SWAP
)] = {i830_swap_bufs
, DRM_AUTH
},
1565 [DRM_IOCTL_NR(DRM_I830_COPY
)] = {i830_copybuf
, DRM_AUTH
},
1566 [DRM_IOCTL_NR(DRM_I830_DOCOPY
)] = {i830_docopy
, DRM_AUTH
},
1567 [DRM_IOCTL_NR(DRM_I830_FLIP
)] = {i830_flip_bufs
, DRM_AUTH
},
1568 [DRM_IOCTL_NR(DRM_I830_IRQ_EMIT
)] = {i830_irq_emit
, DRM_AUTH
},
1569 [DRM_IOCTL_NR(DRM_I830_IRQ_WAIT
)] = {i830_irq_wait
, DRM_AUTH
},
1570 [DRM_IOCTL_NR(DRM_I830_GETPARAM
)] = {i830_getparam
, DRM_AUTH
},
1571 [DRM_IOCTL_NR(DRM_I830_SETPARAM
)] = {i830_setparam
, DRM_AUTH
}
1574 int i830_max_ioctl
= DRM_ARRAY_SIZE(i830_ioctls
);
1577 * Determine if the device really is AGP or not.
1579 * All Intel graphics chipsets are treated as AGP, even if they are really
1582 * \param dev The device to be tested.
1585 * A value of 1 is always retured to indictate every i8xx is AGP.
1587 int i830_driver_device_is_agp(drm_device_t
* dev
)