1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #define IS_I965G(dev) (dev->pci_device == 0x2972 || \
35 dev->pci_device == 0x2982 || \
36 dev->pci_device == 0x2992 || \
37 dev->pci_device == 0x29A2)
39 /* Really want an OS-independent resettable timer. Would like to have
40 * this loop run for (eg) 3 sec, but have the timer reset every time
41 * the head pointer changes, so that EBUSY only happens if the ring
42 * actually stalls for (eg) 3 seconds.
44 int i915_wait_ring(drm_device_t
* dev
, int n
, const char *caller
)
46 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
47 drm_i915_ring_buffer_t
*ring
= &(dev_priv
->ring
);
48 u32 last_head
= I915_READ(LP_RING
+ RING_HEAD
) & HEAD_ADDR
;
51 for (i
= 0; i
< 10000; i
++) {
52 ring
->head
= I915_READ(LP_RING
+ RING_HEAD
) & HEAD_ADDR
;
53 ring
->space
= ring
->head
- (ring
->tail
+ 8);
55 ring
->space
+= ring
->Size
;
59 dev_priv
->sarea_priv
->perf_boxes
|= I915_BOX_WAIT
;
61 if (ring
->head
!= last_head
)
64 last_head
= ring
->head
;
67 return DRM_ERR(EBUSY
);
70 void i915_kernel_lost_context(drm_device_t
* dev
)
72 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
73 drm_i915_ring_buffer_t
*ring
= &(dev_priv
->ring
);
75 ring
->head
= I915_READ(LP_RING
+ RING_HEAD
) & HEAD_ADDR
;
76 ring
->tail
= I915_READ(LP_RING
+ RING_TAIL
) & TAIL_ADDR
;
77 ring
->space
= ring
->head
- (ring
->tail
+ 8);
79 ring
->space
+= ring
->Size
;
81 if (ring
->head
== ring
->tail
)
82 dev_priv
->sarea_priv
->perf_boxes
|= I915_BOX_RING_EMPTY
;
85 static int i915_dma_cleanup(drm_device_t
* dev
)
87 /* Make sure interrupts are disabled here because the uninstall ioctl
88 * may not have been called from userspace and after dev_private
89 * is freed, it's too late.
92 drm_irq_uninstall(dev
);
94 if (dev
->dev_private
) {
95 drm_i915_private_t
*dev_priv
=
96 (drm_i915_private_t
*) dev
->dev_private
;
98 if (dev_priv
->ring
.virtual_start
) {
99 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
102 if (dev_priv
->status_page_dmah
) {
103 drm_pci_free(dev
, dev_priv
->status_page_dmah
);
104 /* Need to rewrite hardware status page */
105 I915_WRITE(0x02080, 0x1ffff000);
108 drm_free(dev
->dev_private
, sizeof(drm_i915_private_t
),
111 dev
->dev_private
= NULL
;
117 static int i915_initialize(drm_device_t
* dev
,
118 drm_i915_private_t
* dev_priv
,
119 drm_i915_init_t
* init
)
121 memset(dev_priv
, 0, sizeof(drm_i915_private_t
));
124 if (!dev_priv
->sarea
) {
125 DRM_ERROR("can not find sarea!\n");
126 dev
->dev_private
= (void *)dev_priv
;
127 i915_dma_cleanup(dev
);
128 return DRM_ERR(EINVAL
);
131 dev_priv
->mmio_map
= drm_core_findmap(dev
, init
->mmio_offset
);
132 if (!dev_priv
->mmio_map
) {
133 dev
->dev_private
= (void *)dev_priv
;
134 i915_dma_cleanup(dev
);
135 DRM_ERROR("can not find mmio map!\n");
136 return DRM_ERR(EINVAL
);
139 dev_priv
->sarea_priv
= (drm_i915_sarea_t
*)
140 ((u8
*) dev_priv
->sarea
->handle
+ init
->sarea_priv_offset
);
142 dev_priv
->ring
.Start
= init
->ring_start
;
143 dev_priv
->ring
.End
= init
->ring_end
;
144 dev_priv
->ring
.Size
= init
->ring_size
;
145 dev_priv
->ring
.tail_mask
= dev_priv
->ring
.Size
- 1;
147 dev_priv
->ring
.map
.offset
= init
->ring_start
;
148 dev_priv
->ring
.map
.size
= init
->ring_size
;
149 dev_priv
->ring
.map
.type
= 0;
150 dev_priv
->ring
.map
.flags
= 0;
151 dev_priv
->ring
.map
.mtrr
= 0;
153 drm_core_ioremap(&dev_priv
->ring
.map
, dev
);
155 if (dev_priv
->ring
.map
.handle
== NULL
) {
156 dev
->dev_private
= (void *)dev_priv
;
157 i915_dma_cleanup(dev
);
158 DRM_ERROR("can not ioremap virtual address for"
160 return DRM_ERR(ENOMEM
);
163 dev_priv
->ring
.virtual_start
= dev_priv
->ring
.map
.handle
;
165 dev_priv
->back_offset
= init
->back_offset
;
166 dev_priv
->front_offset
= init
->front_offset
;
167 dev_priv
->current_page
= 0;
168 dev_priv
->sarea_priv
->pf_current_page
= dev_priv
->current_page
;
170 /* We are using separate values as placeholders for mechanisms for
171 * private backbuffer/depthbuffer usage.
173 dev_priv
->use_mi_batchbuffer_start
= 0;
175 /* Allow hardware batchbuffers unless told otherwise.
177 dev_priv
->allow_batchbuffer
= 1;
179 /* Program Hardware Status Page */
180 dev_priv
->status_page_dmah
= drm_pci_alloc(dev
, PAGE_SIZE
, PAGE_SIZE
,
183 if (!dev_priv
->status_page_dmah
) {
184 dev
->dev_private
= (void *)dev_priv
;
185 i915_dma_cleanup(dev
);
186 DRM_ERROR("Can not allocate hardware status page\n");
187 return DRM_ERR(ENOMEM
);
189 dev_priv
->hw_status_page
= dev_priv
->status_page_dmah
->vaddr
;
190 dev_priv
->dma_status_page
= dev_priv
->status_page_dmah
->busaddr
;
192 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
193 DRM_DEBUG("hw status page @ %p\n", dev_priv
->hw_status_page
);
195 I915_WRITE(0x02080, dev_priv
->dma_status_page
);
196 DRM_DEBUG("Enabled hardware status page\n");
198 dev
->dev_private
= (void *)dev_priv
;
203 static int i915_dma_resume(drm_device_t
* dev
)
205 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
207 DRM_DEBUG("%s\n", __FUNCTION__
);
209 if (!dev_priv
->sarea
) {
210 DRM_ERROR("can not find sarea!\n");
211 return DRM_ERR(EINVAL
);
214 if (!dev_priv
->mmio_map
) {
215 DRM_ERROR("can not find mmio map!\n");
216 return DRM_ERR(EINVAL
);
219 if (dev_priv
->ring
.map
.handle
== NULL
) {
220 DRM_ERROR("can not ioremap virtual address for"
222 return DRM_ERR(ENOMEM
);
225 /* Program Hardware Status Page */
226 if (!dev_priv
->hw_status_page
) {
227 DRM_ERROR("Can not find hardware status page\n");
228 return DRM_ERR(EINVAL
);
230 DRM_DEBUG("hw status page @ %p\n", dev_priv
->hw_status_page
);
232 I915_WRITE(0x02080, dev_priv
->dma_status_page
);
233 DRM_DEBUG("Enabled hardware status page\n");
238 static int i915_dma_init(DRM_IOCTL_ARGS
)
241 drm_i915_private_t
*dev_priv
;
242 drm_i915_init_t init
;
245 DRM_COPY_FROM_USER_IOCTL(init
, (drm_i915_init_t __user
*) data
,
250 dev_priv
= drm_alloc(sizeof(drm_i915_private_t
),
252 if (dev_priv
== NULL
)
253 return DRM_ERR(ENOMEM
);
254 retcode
= i915_initialize(dev
, dev_priv
, &init
);
256 case I915_CLEANUP_DMA
:
257 retcode
= i915_dma_cleanup(dev
);
259 case I915_RESUME_DMA
:
260 retcode
= i915_dma_resume(dev
);
263 retcode
= DRM_ERR(EINVAL
);
270 /* Implement basically the same security restrictions as hardware does
271 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
273 * Most of the calculations below involve calculating the size of a
274 * particular instruction. It's important to get the size right as
275 * that tells us where the next instruction to check is. Any illegal
276 * instruction detected will be given a size of zero, which is a
277 * signal to abort the rest of the buffer.
279 static int do_validate_cmd(int cmd
)
281 switch (((cmd
>> 29) & 0x7)) {
283 switch ((cmd
>> 23) & 0x3f) {
285 return 1; /* MI_NOOP */
287 return 1; /* MI_FLUSH */
289 return 0; /* disallow everything else */
293 return 0; /* reserved */
295 return (cmd
& 0xff) + 2; /* 2d commands */
297 if (((cmd
>> 24) & 0x1f) <= 0x18)
300 switch ((cmd
>> 24) & 0x1f) {
304 switch ((cmd
>> 16) & 0xff) {
306 return (cmd
& 0x1f) + 2;
308 return (cmd
& 0xf) + 2;
310 return (cmd
& 0xffff) + 2;
314 return (cmd
& 0xffff) + 1;
318 if ((cmd
& (1 << 23)) == 0) /* inline vertices */
319 return (cmd
& 0x1ffff) + 2;
320 else if (cmd
& (1 << 17)) /* indirect random */
321 if ((cmd
& 0xffff) == 0)
322 return 0; /* unknown length, too hard */
324 return (((cmd
& 0xffff) + 1) / 2) + 1;
326 return 2; /* indirect sequential */
337 static int validate_cmd(int cmd
)
339 int ret
= do_validate_cmd(cmd
);
341 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
346 static int i915_emit_cmds(drm_device_t
* dev
, int __user
* buffer
, int dwords
)
348 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
352 if ((dwords
+1) * sizeof(int) >= dev_priv
->ring
.Size
- 8)
353 return DRM_ERR(EINVAL
);
355 BEGIN_LP_RING((dwords
+1)&~1);
357 for (i
= 0; i
< dwords
;) {
360 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd
, &buffer
[i
], sizeof(cmd
)))
361 return DRM_ERR(EINVAL
);
363 if ((sz
= validate_cmd(cmd
)) == 0 || i
+ sz
> dwords
)
364 return DRM_ERR(EINVAL
);
369 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd
, &buffer
[i
],
371 return DRM_ERR(EINVAL
);
385 static int i915_emit_box(drm_device_t
* dev
,
386 drm_clip_rect_t __user
* boxes
,
387 int i
, int DR1
, int DR4
)
389 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
393 if (DRM_COPY_FROM_USER_UNCHECKED(&box
, &boxes
[i
], sizeof(box
))) {
394 return DRM_ERR(EFAULT
);
397 if (box
.y2
<= box
.y1
|| box
.x2
<= box
.x1
|| box
.y2
<= 0 || box
.x2
<= 0) {
398 DRM_ERROR("Bad box %d,%d..%d,%d\n",
399 box
.x1
, box
.y1
, box
.x2
, box
.y2
);
400 return DRM_ERR(EINVAL
);
405 OUT_RING(GFX_OP_DRAWRECT_INFO_I965
);
406 OUT_RING((box
.x1
& 0xffff) | (box
.y1
<< 16));
407 OUT_RING(((box
.x2
- 1) & 0xffff) | ((box
.y2
- 1) << 16));
412 OUT_RING(GFX_OP_DRAWRECT_INFO
);
414 OUT_RING((box
.x1
& 0xffff) | (box
.y1
<< 16));
415 OUT_RING(((box
.x2
- 1) & 0xffff) | ((box
.y2
- 1) << 16));
424 /* XXX: Emitting the counter should really be moved to part of the IRQ
425 * emit. For now, do it in both places:
428 static void i915_emit_breadcrumb(drm_device_t
*dev
)
430 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
433 dev_priv
->sarea_priv
->last_enqueue
= ++dev_priv
->counter
;
435 if (dev_priv
->counter
> 0x7FFFFFFFUL
)
436 dev_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
= 1;
439 OUT_RING(CMD_STORE_DWORD_IDX
);
441 OUT_RING(dev_priv
->counter
);
446 static int i915_dispatch_cmdbuffer(drm_device_t
* dev
,
447 drm_i915_cmdbuffer_t
* cmd
)
449 int nbox
= cmd
->num_cliprects
;
450 int i
= 0, count
, ret
;
453 DRM_ERROR("alignment");
454 return DRM_ERR(EINVAL
);
457 i915_kernel_lost_context(dev
);
459 count
= nbox
? nbox
: 1;
461 for (i
= 0; i
< count
; i
++) {
463 ret
= i915_emit_box(dev
, cmd
->cliprects
, i
,
469 ret
= i915_emit_cmds(dev
, (int __user
*)cmd
->buf
, cmd
->sz
/ 4);
474 i915_emit_breadcrumb(dev
);
478 static int i915_dispatch_batchbuffer(drm_device_t
* dev
,
479 drm_i915_batchbuffer_t
* batch
)
481 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
482 drm_clip_rect_t __user
*boxes
= batch
->cliprects
;
483 int nbox
= batch
->num_cliprects
;
487 if ((batch
->start
| batch
->used
) & 0x7) {
488 DRM_ERROR("alignment");
489 return DRM_ERR(EINVAL
);
492 i915_kernel_lost_context(dev
);
494 count
= nbox
? nbox
: 1;
496 for (i
= 0; i
< count
; i
++) {
498 int ret
= i915_emit_box(dev
, boxes
, i
,
499 batch
->DR1
, batch
->DR4
);
504 if (dev_priv
->use_mi_batchbuffer_start
) {
506 OUT_RING(MI_BATCH_BUFFER_START
| (2 << 6));
507 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
511 OUT_RING(MI_BATCH_BUFFER
);
512 OUT_RING(batch
->start
| MI_BATCH_NON_SECURE
);
513 OUT_RING(batch
->start
+ batch
->used
- 4);
519 i915_emit_breadcrumb(dev
);
524 static int i915_dispatch_flip(drm_device_t
* dev
)
526 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
529 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
531 dev_priv
->current_page
,
532 dev_priv
->sarea_priv
->pf_current_page
);
534 i915_kernel_lost_context(dev
);
537 OUT_RING(INST_PARSER_CLIENT
| INST_OP_FLUSH
| INST_FLUSH_MAP_CACHE
);
542 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO
| ASYNC_FLIP
);
544 if (dev_priv
->current_page
== 0) {
545 OUT_RING(dev_priv
->back_offset
);
546 dev_priv
->current_page
= 1;
548 OUT_RING(dev_priv
->front_offset
);
549 dev_priv
->current_page
= 0;
555 OUT_RING(MI_WAIT_FOR_EVENT
| MI_WAIT_FOR_PLANE_A_FLIP
);
559 dev_priv
->sarea_priv
->last_enqueue
= dev_priv
->counter
++;
562 OUT_RING(CMD_STORE_DWORD_IDX
);
564 OUT_RING(dev_priv
->counter
);
568 dev_priv
->sarea_priv
->pf_current_page
= dev_priv
->current_page
;
572 static int i915_quiescent(drm_device_t
* dev
)
574 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
576 i915_kernel_lost_context(dev
);
577 return i915_wait_ring(dev
, dev_priv
->ring
.Size
- 8, __FUNCTION__
);
580 static int i915_flush_ioctl(DRM_IOCTL_ARGS
)
584 LOCK_TEST_WITH_RETURN(dev
, filp
);
586 return i915_quiescent(dev
);
589 static int i915_batchbuffer(DRM_IOCTL_ARGS
)
592 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
593 u32
*hw_status
= dev_priv
->hw_status_page
;
594 drm_i915_sarea_t
*sarea_priv
= (drm_i915_sarea_t
*)
595 dev_priv
->sarea_priv
;
596 drm_i915_batchbuffer_t batch
;
599 if (!dev_priv
->allow_batchbuffer
) {
600 DRM_ERROR("Batchbuffer ioctl disabled\n");
601 return DRM_ERR(EINVAL
);
604 DRM_COPY_FROM_USER_IOCTL(batch
, (drm_i915_batchbuffer_t __user
*) data
,
607 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
608 batch
.start
, batch
.used
, batch
.num_cliprects
);
610 LOCK_TEST_WITH_RETURN(dev
, filp
);
612 if (batch
.num_cliprects
&& DRM_VERIFYAREA_READ(batch
.cliprects
,
613 batch
.num_cliprects
*
614 sizeof(drm_clip_rect_t
)))
615 return DRM_ERR(EFAULT
);
617 ret
= i915_dispatch_batchbuffer(dev
, &batch
);
619 sarea_priv
->last_dispatch
= (int)hw_status
[5];
623 static int i915_cmdbuffer(DRM_IOCTL_ARGS
)
626 drm_i915_private_t
*dev_priv
= (drm_i915_private_t
*) dev
->dev_private
;
627 u32
*hw_status
= dev_priv
->hw_status_page
;
628 drm_i915_sarea_t
*sarea_priv
= (drm_i915_sarea_t
*)
629 dev_priv
->sarea_priv
;
630 drm_i915_cmdbuffer_t cmdbuf
;
633 DRM_COPY_FROM_USER_IOCTL(cmdbuf
, (drm_i915_cmdbuffer_t __user
*) data
,
636 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
637 cmdbuf
.buf
, cmdbuf
.sz
, cmdbuf
.num_cliprects
);
639 LOCK_TEST_WITH_RETURN(dev
, filp
);
641 if (cmdbuf
.num_cliprects
&&
642 DRM_VERIFYAREA_READ(cmdbuf
.cliprects
,
643 cmdbuf
.num_cliprects
*
644 sizeof(drm_clip_rect_t
))) {
645 DRM_ERROR("Fault accessing cliprects\n");
646 return DRM_ERR(EFAULT
);
649 ret
= i915_dispatch_cmdbuffer(dev
, &cmdbuf
);
651 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
655 sarea_priv
->last_dispatch
= (int)hw_status
[5];
659 static int i915_flip_bufs(DRM_IOCTL_ARGS
)
663 DRM_DEBUG("%s\n", __FUNCTION__
);
665 LOCK_TEST_WITH_RETURN(dev
, filp
);
667 return i915_dispatch_flip(dev
);
670 static int i915_getparam(DRM_IOCTL_ARGS
)
673 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
674 drm_i915_getparam_t param
;
678 DRM_ERROR("%s called with no initialization\n", __FUNCTION__
);
679 return DRM_ERR(EINVAL
);
682 DRM_COPY_FROM_USER_IOCTL(param
, (drm_i915_getparam_t __user
*) data
,
685 switch (param
.param
) {
686 case I915_PARAM_IRQ_ACTIVE
:
687 value
= dev
->irq
? 1 : 0;
689 case I915_PARAM_ALLOW_BATCHBUFFER
:
690 value
= dev_priv
->allow_batchbuffer
? 1 : 0;
692 case I915_PARAM_LAST_DISPATCH
:
693 value
= READ_BREADCRUMB(dev_priv
);
696 DRM_ERROR("Unknown parameter %d\n", param
.param
);
697 return DRM_ERR(EINVAL
);
700 if (DRM_COPY_TO_USER(param
.value
, &value
, sizeof(int))) {
701 DRM_ERROR("DRM_COPY_TO_USER failed\n");
702 return DRM_ERR(EFAULT
);
708 static int i915_setparam(DRM_IOCTL_ARGS
)
711 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
712 drm_i915_setparam_t param
;
715 DRM_ERROR("%s called with no initialization\n", __FUNCTION__
);
716 return DRM_ERR(EINVAL
);
719 DRM_COPY_FROM_USER_IOCTL(param
, (drm_i915_setparam_t __user
*) data
,
722 switch (param
.param
) {
723 case I915_SETPARAM_USE_MI_BATCHBUFFER_START
:
724 dev_priv
->use_mi_batchbuffer_start
= param
.value
;
726 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY
:
727 dev_priv
->tex_lru_log_granularity
= param
.value
;
729 case I915_SETPARAM_ALLOW_BATCHBUFFER
:
730 dev_priv
->allow_batchbuffer
= param
.value
;
733 DRM_ERROR("unknown parameter %d\n", param
.param
);
734 return DRM_ERR(EINVAL
);
740 int i915_driver_load(drm_device_t
*dev
, unsigned long flags
)
742 /* i915 has 4 more counters */
744 dev
->types
[6] = _DRM_STAT_IRQ
;
745 dev
->types
[7] = _DRM_STAT_PRIMARY
;
746 dev
->types
[8] = _DRM_STAT_SECONDARY
;
747 dev
->types
[9] = _DRM_STAT_DMA
;
752 void i915_driver_lastclose(drm_device_t
* dev
)
754 if (dev
->dev_private
) {
755 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
756 i915_mem_takedown(&(dev_priv
->agp_heap
));
758 i915_dma_cleanup(dev
);
761 void i915_driver_preclose(drm_device_t
* dev
, DRMFILE filp
)
763 if (dev
->dev_private
) {
764 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
765 i915_mem_release(dev
, filp
, dev_priv
->agp_heap
);
769 drm_ioctl_desc_t i915_ioctls
[] = {
770 [DRM_IOCTL_NR(DRM_I915_INIT
)] = {i915_dma_init
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
},
771 [DRM_IOCTL_NR(DRM_I915_FLUSH
)] = {i915_flush_ioctl
, DRM_AUTH
},
772 [DRM_IOCTL_NR(DRM_I915_FLIP
)] = {i915_flip_bufs
, DRM_AUTH
},
773 [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER
)] = {i915_batchbuffer
, DRM_AUTH
},
774 [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT
)] = {i915_irq_emit
, DRM_AUTH
},
775 [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT
)] = {i915_irq_wait
, DRM_AUTH
},
776 [DRM_IOCTL_NR(DRM_I915_GETPARAM
)] = {i915_getparam
, DRM_AUTH
},
777 [DRM_IOCTL_NR(DRM_I915_SETPARAM
)] = {i915_setparam
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
},
778 [DRM_IOCTL_NR(DRM_I915_ALLOC
)] = {i915_mem_alloc
, DRM_AUTH
},
779 [DRM_IOCTL_NR(DRM_I915_FREE
)] = {i915_mem_free
, DRM_AUTH
},
780 [DRM_IOCTL_NR(DRM_I915_INIT_HEAP
)] = {i915_mem_init_heap
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
},
781 [DRM_IOCTL_NR(DRM_I915_CMDBUFFER
)] = {i915_cmdbuffer
, DRM_AUTH
},
782 [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP
)] = { i915_mem_destroy_heap
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
},
783 [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE
)] = { i915_vblank_pipe_set
, DRM_AUTH
|DRM_MASTER
|DRM_ROOT_ONLY
},
784 [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE
)] = { i915_vblank_pipe_get
, DRM_AUTH
},
787 int i915_max_ioctl
= DRM_ARRAY_SIZE(i915_ioctls
);
790 * Determine if the device really is AGP or not.
792 * All Intel graphics chipsets are treated as AGP, even if they are really
795 * \param dev The device to be tested.
798 * A value of 1 is always retured to indictate every i9x5 is AGP.
800 int i915_driver_device_is_agp(drm_device_t
* dev
)