drivers/char/mwave/3780i.c

   1 /*
   2 *
   3 * 3780i.c -- helper routines for the 3780i DSP
   4 *
   5 *
   6 * Written By: Mike Sullivan IBM Corporation
   7 *
   8 * Copyright (C) 1999 IBM Corporation
   9 *
  10 * This program is free software; you can redistribute it and/or modify
  11 * it under the terms of the GNU General Public License as published by
  12 * the Free Software Foundation; either version 2 of the License, or
  13 * (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * NO WARRANTY
  21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  25 * solely responsible for determining the appropriateness of using and
  26 * distributing the Program and assumes all risks associated with its
  27 * exercise of rights under this Agreement, including but not limited to
  28 * the risks and costs of program errors, damage to or loss of data,
  29 * programs or equipment, and unavailability or interruption of operations.
  30 *
  31 * DISCLAIMER OF LIABILITY
  32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  39 *
  40 * You should have received a copy of the GNU General Public License
  41 * along with this program; if not, write to the Free Software
  42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  43 *
  44 *
  45 * 10/23/2000 - Alpha Release
  46 *       First release to the public
  47 */
  48
  49 #include <linux/config.h>
  50 #include <linux/kernel.h>
  51 #include <linux/unistd.h>
  52 #include <linux/delay.h>
  53 #include <linux/ioport.h>
  54 #include <linux/init.h>
  55 #include <linux/bitops.h>
  56 #include <asm/io.h>
  57 #include <asm/uaccess.h>
  58 #include <asm/system.h>
  59 #include <asm/irq.h>
  60 #include "smapi.h"
  61 #include "mwavedd.h"
  62 #include "3780i.h"
  63
  64 static DEFINE_SPINLOCK(dsp_lock);
  65 static unsigned long flags;
  66
  67
  68 static void PaceMsaAccess(unsigned short usDspBaseIO)
  69 {
  70         cond_resched();
  71         udelay(100);
  72         cond_resched();
  73 }
  74
  75 unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO,
  76                                    unsigned long ulMsaAddr)
  77 {
  78         unsigned short val;
  79
  80         PRINTK_3(TRACE_3780I,
  81                 "3780i::dsp3780I_ReadMsaCfg entry usDspBaseIO %x ulMsaAddr %lx\n",
  82                 usDspBaseIO, ulMsaAddr);
  83
  84         spin_lock_irqsave(&dsp_lock, flags);
  85         OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);
  86         OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));
  87         val = InWordDsp(DSP_MsaDataDSISHigh);
  88         spin_unlock_irqrestore(&dsp_lock, flags);
  89
  90         PRINTK_2(TRACE_3780I, "3780i::dsp3780I_ReadMsaCfg exit val %x\n", val);
  91
  92         return val;
  93 }
  94
  95 void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO,
  96                           unsigned long ulMsaAddr, unsigned short usValue)
  97 {
  98
  99         PRINTK_4(TRACE_3780I,
 100                 "3780i::dsp3780i_WriteMsaCfg entry usDspBaseIO %x ulMsaAddr %lx usValue %x\n",
 101                 usDspBaseIO, ulMsaAddr, usValue);
 102
 103         spin_lock_irqsave(&dsp_lock, flags);
 104         OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr);
 105         OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16));
 106         OutWordDsp(DSP_MsaDataDSISHigh, usValue);
 107         spin_unlock_irqrestore(&dsp_lock, flags);
 108 }
 109
 110 void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex,
 111                           unsigned char ucValue)
 112 {
 113         DSP_ISA_SLAVE_CONTROL rSlaveControl;
 114         DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;
 115
 116
 117         PRINTK_4(TRACE_3780I,
 118                 "3780i::dsp3780i_WriteGenCfg entry usDspBaseIO %x uIndex %x ucValue %x\n",
 119                 usDspBaseIO, uIndex, ucValue);
 120
 121         MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);
 122
 123         PRINTK_2(TRACE_3780I,
 124                 "3780i::dsp3780i_WriteGenCfg rSlaveControl %x\n",
 125                 MKBYTE(rSlaveControl));
 126
 127         rSlaveControl_Save = rSlaveControl;
 128         rSlaveControl.ConfigMode = TRUE;
 129
 130         PRINTK_2(TRACE_3780I,
 131                 "3780i::dsp3780i_WriteGenCfg entry rSlaveControl+ConfigMode %x\n",
 132                 MKBYTE(rSlaveControl));
 133
 134         OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));
 135         OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);
 136         OutByteDsp(DSP_ConfigData, ucValue);
 137         OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));
 138
 139         PRINTK_1(TRACE_3780I, "3780i::dsp3780i_WriteGenCfg exit\n");
 140
 141
 142 }
 143
 144 unsigned char dsp3780I_ReadGenCfg(unsigned short usDspBaseIO,
 145                                   unsigned uIndex)
 146 {
 147         DSP_ISA_SLAVE_CONTROL rSlaveControl;
 148         DSP_ISA_SLAVE_CONTROL rSlaveControl_Save;
 149         unsigned char ucValue;
 150
 151
 152         PRINTK_3(TRACE_3780I,
 153                 "3780i::dsp3780i_ReadGenCfg entry usDspBaseIO %x uIndex %x\n",
 154                 usDspBaseIO, uIndex);
 155
 156         MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl);
 157         rSlaveControl_Save = rSlaveControl;
 158         rSlaveControl.ConfigMode = TRUE;
 159         OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl));
 160         OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex);
 161         ucValue = InByteDsp(DSP_ConfigData);
 162         OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save));
 163
 164         PRINTK_2(TRACE_3780I,
 165                 "3780i::dsp3780i_ReadGenCfg exit ucValue %x\n", ucValue);
 166
 167
 168         return ucValue;
 169 }
 170
 171 int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings,
 172                        unsigned short *pIrqMap,
 173                        unsigned short *pDmaMap)
 174 {
 175         unsigned short usDspBaseIO = pSettings->usDspBaseIO;
 176         int i;
 177         DSP_UART_CFG_1 rUartCfg1;
 178         DSP_UART_CFG_2 rUartCfg2;
 179         DSP_HBRIDGE_CFG_1 rHBridgeCfg1;
 180         DSP_HBRIDGE_CFG_2 rHBridgeCfg2;
 181         DSP_BUSMASTER_CFG_1 rBusmasterCfg1;
 182         DSP_BUSMASTER_CFG_2 rBusmasterCfg2;
 183         DSP_ISA_PROT_CFG rIsaProtCfg;
 184         DSP_POWER_MGMT_CFG rPowerMgmtCfg;
 185         DSP_HBUS_TIMER_CFG rHBusTimerCfg;
 186         DSP_LBUS_TIMEOUT_DISABLE rLBusTimeoutDisable;
 187         DSP_CHIP_RESET rChipReset;
 188         DSP_CLOCK_CONTROL_1 rClockControl1;
 189         DSP_CLOCK_CONTROL_2 rClockControl2;
 190         DSP_ISA_SLAVE_CONTROL rSlaveControl;
 191         DSP_HBRIDGE_CONTROL rHBridgeControl;
 192         unsigned short ChipID = 0;
 193         unsigned short tval;
 194
 195
 196         PRINTK_2(TRACE_3780I,
 197                 "3780i::dsp3780I_EnableDSP entry pSettings->bDSPEnabled %x\n",
 198                 pSettings->bDSPEnabled);
 199
 200
 201         if (!pSettings->bDSPEnabled) {
 202                 PRINTK_ERROR( KERN_ERR "3780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting.\n" );
 203                 return -EIO;
 204         }
 205
 206
 207         PRINTK_2(TRACE_3780I,
 208                 "3780i::dsp3780i_EnableDSP entry pSettings->bModemEnabled %x\n",
 209                 pSettings->bModemEnabled);
 210
 211         if (pSettings->bModemEnabled) {
 212                 rUartCfg1.Reserved = rUartCfg2.Reserved = 0;
 213                 rUartCfg1.IrqActiveLow = pSettings->bUartIrqActiveLow;
 214                 rUartCfg1.IrqPulse = pSettings->bUartIrqPulse;
 215                 rUartCfg1.Irq =
 216                         (unsigned char) pIrqMap[pSettings->usUartIrq];
 217                 switch (pSettings->usUartBaseIO) {
 218                 case 0x03F8:
 219                         rUartCfg1.BaseIO = 0;
 220                         break;
 221                 case 0x02F8:
 222                         rUartCfg1.BaseIO = 1;
 223                         break;
 224                 case 0x03E8:
 225                         rUartCfg1.BaseIO = 2;
 226                         break;
 227                 case 0x02E8:
 228                         rUartCfg1.BaseIO = 3;
 229                         break;
 230                 }
 231                 rUartCfg2.Enable = TRUE;
 232         }
 233
 234         rHBridgeCfg1.Reserved = rHBridgeCfg2.Reserved = 0;
 235         rHBridgeCfg1.IrqActiveLow = pSettings->bDspIrqActiveLow;
 236         rHBridgeCfg1.IrqPulse = pSettings->bDspIrqPulse;
 237         rHBridgeCfg1.Irq = (unsigned char) pIrqMap[pSettings->usDspIrq];
 238         rHBridgeCfg1.AccessMode = 1;
 239         rHBridgeCfg2.Enable = TRUE;
 240
 241
 242         rBusmasterCfg2.Reserved = 0;
 243         rBusmasterCfg1.Dma = (unsigned char) pDmaMap[pSettings->usDspDma];
 244         rBusmasterCfg1.NumTransfers =
 245                 (unsigned char) pSettings->usNumTransfers;
 246         rBusmasterCfg1.ReRequest = (unsigned char) pSettings->usReRequest;
 247         rBusmasterCfg1.MEMCS16 = pSettings->bEnableMEMCS16;
 248         rBusmasterCfg2.IsaMemCmdWidth =
 249                 (unsigned char) pSettings->usIsaMemCmdWidth;
 250
 251
 252         rIsaProtCfg.Reserved = 0;
 253         rIsaProtCfg.GateIOCHRDY = pSettings->bGateIOCHRDY;
 254
 255         rPowerMgmtCfg.Reserved = 0;
 256         rPowerMgmtCfg.Enable = pSettings->bEnablePwrMgmt;
 257
 258         rHBusTimerCfg.LoadValue =
 259                 (unsigned char) pSettings->usHBusTimerLoadValue;
 260
 261         rLBusTimeoutDisable.Reserved = 0;
 262         rLBusTimeoutDisable.DisableTimeout =
 263                 pSettings->bDisableLBusTimeout;
 264
 265         MKWORD(rChipReset) = ~pSettings->usChipletEnable;
 266
 267         rClockControl1.Reserved1 = rClockControl1.Reserved2 = 0;
 268         rClockControl1.N_Divisor = pSettings->usN_Divisor;
 269         rClockControl1.M_Multiplier = pSettings->usM_Multiplier;
 270
 271         rClockControl2.Reserved = 0;
 272         rClockControl2.PllBypass = pSettings->bPllBypass;
 273
 274         /* Issue a soft reset to the chip */
 275         /* Note: Since we may be coming in with 3780i clocks suspended, we must keep
 276         * soft-reset active for 10ms.
 277         */
 278         rSlaveControl.ClockControl = 0;
 279         rSlaveControl.SoftReset = TRUE;
 280         rSlaveControl.ConfigMode = FALSE;
 281         rSlaveControl.Reserved = 0;
 282
 283         PRINTK_4(TRACE_3780I,
 284                 "3780i::dsp3780i_EnableDSP usDspBaseIO %x index %x taddr %x\n",
 285                 usDspBaseIO, DSP_IsaSlaveControl,
 286                 usDspBaseIO + DSP_IsaSlaveControl);
 287
 288         PRINTK_2(TRACE_3780I,
 289                 "3780i::dsp3780i_EnableDSP rSlaveContrl %x\n",
 290                 MKWORD(rSlaveControl));
 291
 292         spin_lock_irqsave(&dsp_lock, flags);
 293         OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
 294         MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);
 295
 296         PRINTK_2(TRACE_3780I,
 297                 "3780i::dsp3780i_EnableDSP rSlaveControl 2 %x\n", tval);
 298
 299
 300         for (i = 0; i < 11; i++)
 301                 udelay(2000);
 302
 303         rSlaveControl.SoftReset = FALSE;
 304         OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
 305
 306         MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl);
 307
 308         PRINTK_2(TRACE_3780I,
 309                 "3780i::dsp3780i_EnableDSP rSlaveControl 3 %x\n", tval);
 310
 311
 312         /* Program our general configuration registers */
 313         WriteGenCfg(DSP_HBridgeCfg1Index, MKBYTE(rHBridgeCfg1));
 314         WriteGenCfg(DSP_HBridgeCfg2Index, MKBYTE(rHBridgeCfg2));
 315         WriteGenCfg(DSP_BusMasterCfg1Index, MKBYTE(rBusmasterCfg1));
 316         WriteGenCfg(DSP_BusMasterCfg2Index, MKBYTE(rBusmasterCfg2));
 317         WriteGenCfg(DSP_IsaProtCfgIndex, MKBYTE(rIsaProtCfg));
 318         WriteGenCfg(DSP_PowerMgCfgIndex, MKBYTE(rPowerMgmtCfg));
 319         WriteGenCfg(DSP_HBusTimerCfgIndex, MKBYTE(rHBusTimerCfg));
 320
 321         if (pSettings->bModemEnabled) {
 322                 WriteGenCfg(DSP_UartCfg1Index, MKBYTE(rUartCfg1));
 323                 WriteGenCfg(DSP_UartCfg2Index, MKBYTE(rUartCfg2));
 324         }
 325
 326
 327         rHBridgeControl.EnableDspInt = FALSE;
 328         rHBridgeControl.MemAutoInc = TRUE;
 329         rHBridgeControl.IoAutoInc = FALSE;
 330         rHBridgeControl.DiagnosticMode = FALSE;
 331
 332         PRINTK_3(TRACE_3780I,
 333                 "3780i::dsp3780i_EnableDSP DSP_HBridgeControl %x rHBridgeControl %x\n",
 334                 DSP_HBridgeControl, MKWORD(rHBridgeControl));
 335
 336         OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
 337         spin_unlock_irqrestore(&dsp_lock, flags);
 338         WriteMsaCfg(DSP_LBusTimeoutDisable, MKWORD(rLBusTimeoutDisable));
 339         WriteMsaCfg(DSP_ClockControl_1, MKWORD(rClockControl1));
 340         WriteMsaCfg(DSP_ClockControl_2, MKWORD(rClockControl2));
 341         WriteMsaCfg(DSP_ChipReset, MKWORD(rChipReset));
 342
 343         ChipID = ReadMsaCfg(DSP_ChipID);
 344
 345         PRINTK_2(TRACE_3780I,
 346                 "3780i::dsp3780I_EnableDSP exiting bRC=TRUE, ChipID %x\n",
 347                 ChipID);
 348
 349         return 0;
 350 }
 351
 352 int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings)
 353 {
 354         unsigned short usDspBaseIO = pSettings->usDspBaseIO;
 355         DSP_ISA_SLAVE_CONTROL rSlaveControl;
 356
 357
 358         PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP entry\n");
 359
 360         rSlaveControl.ClockControl = 0;
 361         rSlaveControl.SoftReset = TRUE;
 362         rSlaveControl.ConfigMode = FALSE;
 363         rSlaveControl.Reserved = 0;
 364         spin_lock_irqsave(&dsp_lock, flags);
 365         OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
 366
 367         udelay(5);
 368
 369         rSlaveControl.ClockControl = 1;
 370         OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl));
 371         spin_unlock_irqrestore(&dsp_lock, flags);
 372
 373         udelay(5);
 374
 375
 376         PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP exit\n");
 377
 378         return 0;
 379 }
 380
 381 int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings)
 382 {
 383         unsigned short usDspBaseIO = pSettings->usDspBaseIO;
 384         DSP_BOOT_DOMAIN rBootDomain;
 385         DSP_HBRIDGE_CONTROL rHBridgeControl;
 386
 387
 388         PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset entry\n");
 389
 390         spin_lock_irqsave(&dsp_lock, flags);
 391         /* Mask DSP to PC interrupt */
 392         MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
 393
 394         PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rHBridgeControl %x\n",
 395                 MKWORD(rHBridgeControl));
 396
 397         rHBridgeControl.EnableDspInt = FALSE;
 398         OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
 399         spin_unlock_irqrestore(&dsp_lock, flags);
 400
 401         /* Reset the core via the boot domain register */
 402         rBootDomain.ResetCore = TRUE;
 403         rBootDomain.Halt = TRUE;
 404         rBootDomain.NMI = TRUE;
 405         rBootDomain.Reserved = 0;
 406
 407         PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rBootDomain %x\n",
 408                 MKWORD(rBootDomain));
 409
 410         WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
 411
 412         /* Reset all the chiplets and then reactivate them */
 413         WriteMsaCfg(DSP_ChipReset, 0xFFFF);
 414         udelay(5);
 415         WriteMsaCfg(DSP_ChipReset,
 416                         (unsigned short) (~pSettings->usChipletEnable));
 417
 418
 419         PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset exit bRC=0\n");
 420
 421         return 0;
 422 }
 423
 424
 425 int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings)
 426 {
 427         unsigned short usDspBaseIO = pSettings->usDspBaseIO;
 428         DSP_BOOT_DOMAIN rBootDomain;
 429         DSP_HBRIDGE_CONTROL rHBridgeControl;
 430
 431
 432         PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run entry\n");
 433
 434
 435         /* Transition the core to a running state */
 436         rBootDomain.ResetCore = TRUE;
 437         rBootDomain.Halt = FALSE;
 438         rBootDomain.NMI = TRUE;
 439         rBootDomain.Reserved = 0;
 440         WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
 441
 442         udelay(5);
 443
 444         rBootDomain.ResetCore = FALSE;
 445         WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
 446         udelay(5);
 447
 448         rBootDomain.NMI = FALSE;
 449         WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain));
 450         udelay(5);
 451
 452         /* Enable DSP to PC interrupt */
 453         spin_lock_irqsave(&dsp_lock, flags);
 454         MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
 455         rHBridgeControl.EnableDspInt = TRUE;
 456
 457         PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Run rHBridgeControl %x\n",
 458                 MKWORD(rHBridgeControl));
 459
 460         OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
 461         spin_unlock_irqrestore(&dsp_lock, flags);
 462
 463
 464         PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run exit bRC=TRUE\n");
 465
 466         return 0;
 467 }
 468
 469
 470 int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
 471                         unsigned uCount, unsigned long ulDSPAddr)
 472 {
 473         unsigned short __user *pusBuffer = pvBuffer;
 474         unsigned short val;
 475
 476
 477         PRINTK_5(TRACE_3780I,
 478                 "3780i::dsp3780I_ReadDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
 479                 usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
 480
 481
 482         /* Set the initial MSA address. No adjustments need to be made to data store addresses */
 483         spin_lock_irqsave(&dsp_lock, flags);
 484         OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
 485         OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
 486         spin_unlock_irqrestore(&dsp_lock, flags);
 487
 488         /* Transfer the memory block */
 489         while (uCount-- != 0) {
 490                 spin_lock_irqsave(&dsp_lock, flags);
 491                 val = InWordDsp(DSP_MsaDataDSISHigh);
 492                 spin_unlock_irqrestore(&dsp_lock, flags);
 493                 if(put_user(val, pusBuffer++))
 494                         return -EFAULT;
 495
 496                 PRINTK_3(TRACE_3780I,
 497                         "3780I::dsp3780I_ReadDStore uCount %x val %x\n",
 498                         uCount, val);
 499
 500                 PaceMsaAccess(usDspBaseIO);
 501         }
 502
 503
 504         PRINTK_1(TRACE_3780I,
 505                 "3780I::dsp3780I_ReadDStore exit bRC=TRUE\n");
 506
 507         return 0;
 508 }
 509
 510 int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO,
 511                                 void __user *pvBuffer, unsigned uCount,
 512                                 unsigned long ulDSPAddr)
 513 {
 514         unsigned short __user *pusBuffer = pvBuffer;
 515         unsigned short val;
 516
 517
 518         PRINTK_5(TRACE_3780I,
 519                 "3780i::dsp3780I_ReadAndDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
 520                 usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
 521
 522
 523         /* Set the initial MSA address. No adjustments need to be made to data store addresses */
 524         spin_lock_irqsave(&dsp_lock, flags);
 525         OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
 526         OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
 527         spin_unlock_irqrestore(&dsp_lock, flags);
 528
 529         /* Transfer the memory block */
 530         while (uCount-- != 0) {
 531                 spin_lock_irqsave(&dsp_lock, flags);
 532                 val = InWordDsp(DSP_ReadAndClear);
 533                 spin_unlock_irqrestore(&dsp_lock, flags);
 534                 if(put_user(val, pusBuffer++))
 535                         return -EFAULT;
 536
 537                 PRINTK_3(TRACE_3780I,
 538                         "3780I::dsp3780I_ReadAndCleanDStore uCount %x val %x\n",
 539                         uCount, val);
 540
 541                 PaceMsaAccess(usDspBaseIO);
 542         }
 543
 544
 545         PRINTK_1(TRACE_3780I,
 546                 "3780I::dsp3780I_ReadAndClearDStore exit bRC=TRUE\n");
 547
 548         return 0;
 549 }
 550
 551
 552 int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer,
 553                          unsigned uCount, unsigned long ulDSPAddr)
 554 {
 555         unsigned short __user *pusBuffer = pvBuffer;
 556
 557
 558         PRINTK_5(TRACE_3780I,
 559                 "3780i::dsp3780D_WriteDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
 560                 usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
 561
 562
 563         /* Set the initial MSA address. No adjustments need to be made to data store addresses */
 564         spin_lock_irqsave(&dsp_lock, flags);
 565         OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
 566         OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
 567         spin_unlock_irqrestore(&dsp_lock, flags);
 568
 569         /* Transfer the memory block */
 570         while (uCount-- != 0) {
 571                 unsigned short val;
 572                 if(get_user(val, pusBuffer++))
 573                         return -EFAULT;
 574                 spin_lock_irqsave(&dsp_lock, flags);
 575                 OutWordDsp(DSP_MsaDataDSISHigh, val);
 576                 spin_unlock_irqrestore(&dsp_lock, flags);
 577
 578                 PRINTK_3(TRACE_3780I,
 579                         "3780I::dsp3780I_WriteDStore uCount %x val %x\n",
 580                         uCount, val);
 581
 582                 PaceMsaAccess(usDspBaseIO);
 583         }
 584
 585
 586         PRINTK_1(TRACE_3780I,
 587                 "3780I::dsp3780D_WriteDStore exit bRC=TRUE\n");
 588
 589         return 0;
 590 }
 591
 592
 593 int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
 594                         unsigned uCount, unsigned long ulDSPAddr)
 595 {
 596         unsigned short __user *pusBuffer = pvBuffer;
 597
 598         PRINTK_5(TRACE_3780I,
 599                 "3780i::dsp3780I_ReadIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
 600                 usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
 601
 602         /*
 603         * Set the initial MSA address. To convert from an instruction store
 604         * address to an MSA address
 605         * shift the address two bits to the left and set bit 22
 606         */
 607         ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);
 608         spin_lock_irqsave(&dsp_lock, flags);
 609         OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
 610         OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
 611         spin_unlock_irqrestore(&dsp_lock, flags);
 612
 613         /* Transfer the memory block */
 614         while (uCount-- != 0) {
 615                 unsigned short val_lo, val_hi;
 616                 spin_lock_irqsave(&dsp_lock, flags);
 617                 val_lo = InWordDsp(DSP_MsaDataISLow);
 618                 val_hi = InWordDsp(DSP_MsaDataDSISHigh);
 619                 spin_unlock_irqrestore(&dsp_lock, flags);
 620                 if(put_user(val_lo, pusBuffer++))
 621                         return -EFAULT;
 622                 if(put_user(val_hi, pusBuffer++))
 623                         return -EFAULT;
 624
 625                 PRINTK_4(TRACE_3780I,
 626                         "3780I::dsp3780I_ReadIStore uCount %x val_lo %x val_hi %x\n",
 627                         uCount, val_lo, val_hi);
 628
 629                 PaceMsaAccess(usDspBaseIO);
 630
 631         }
 632
 633         PRINTK_1(TRACE_3780I,
 634                 "3780I::dsp3780I_ReadIStore exit bRC=TRUE\n");
 635
 636         return 0;
 637 }
 638
 639
 640 int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer,
 641                          unsigned uCount, unsigned long ulDSPAddr)
 642 {
 643         unsigned short __user *pusBuffer = pvBuffer;
 644
 645         PRINTK_5(TRACE_3780I,
 646                 "3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n",
 647                 usDspBaseIO, pusBuffer, uCount, ulDSPAddr);
 648
 649
 650         /*
 651         * Set the initial MSA address. To convert from an instruction store
 652         * address to an MSA address
 653         * shift the address two bits to the left and set bit 22
 654         */
 655         ulDSPAddr = (ulDSPAddr << 2) | (1 << 22);
 656         spin_lock_irqsave(&dsp_lock, flags);
 657         OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr);
 658         OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16));
 659         spin_unlock_irqrestore(&dsp_lock, flags);
 660
 661         /* Transfer the memory block */
 662         while (uCount-- != 0) {
 663                 unsigned short val_lo, val_hi;
 664                 if(get_user(val_lo, pusBuffer++))
 665                         return -EFAULT;
 666                 if(get_user(val_hi, pusBuffer++))
 667                         return -EFAULT;
 668                 spin_lock_irqsave(&dsp_lock, flags);
 669                 OutWordDsp(DSP_MsaDataISLow, val_lo);
 670                 OutWordDsp(DSP_MsaDataDSISHigh, val_hi);
 671                 spin_unlock_irqrestore(&dsp_lock, flags);
 672
 673                 PRINTK_4(TRACE_3780I,
 674                         "3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x\n",
 675                         uCount, val_lo, val_hi);
 676
 677                 PaceMsaAccess(usDspBaseIO);
 678
 679         }
 680
 681         PRINTK_1(TRACE_3780I,
 682                 "3780I::dsp3780I_WriteIStore exit bRC=TRUE\n");
 683
 684         return 0;
 685 }
 686
 687
 688 int dsp3780I_GetIPCSource(unsigned short usDspBaseIO,
 689                           unsigned short *pusIPCSource)
 690 {
 691         DSP_HBRIDGE_CONTROL rHBridgeControl;
 692         unsigned short temp;
 693
 694
 695         PRINTK_3(TRACE_3780I,
 696                 "3780i::dsp3780I_GetIPCSource entry usDspBaseIO %x pusIPCSource %p\n",
 697                 usDspBaseIO, pusIPCSource);
 698
 699         /*
 700         * Disable DSP to PC interrupts, read the interrupt register,
 701         * clear the pending IPC bits, and reenable DSP to PC interrupts
 702         */
 703         spin_lock_irqsave(&dsp_lock, flags);
 704         MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl);
 705         rHBridgeControl.EnableDspInt = FALSE;
 706         OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
 707
 708         *pusIPCSource = InWordDsp(DSP_Interrupt);
 709         temp = (unsigned short) ~(*pusIPCSource);
 710
 711         PRINTK_3(TRACE_3780I,
 712                 "3780i::dsp3780I_GetIPCSource, usIPCSource %x ~ %x\n",
 713                 *pusIPCSource, temp);
 714
 715         OutWordDsp(DSP_Interrupt, (unsigned short) ~(*pusIPCSource));
 716
 717         rHBridgeControl.EnableDspInt = TRUE;
 718         OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl));
 719         spin_unlock_irqrestore(&dsp_lock, flags);
 720
 721
 722         PRINTK_2(TRACE_3780I,
 723                 "3780i::dsp3780I_GetIPCSource exit usIPCSource %x\n",
 724                 *pusIPCSource);
 725
 726         return 0;
 727 }