2 * linux/drivers/char/synclink.c
4 * $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
12 * Microgate and SyncLink are trademarks of Microgate Corporation
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
16 * Original release 01/11/99
18 * This code is released under the GNU General Public License (GPL)
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
57 # define BREAKPOINT() asm(" int $3");
59 # define BREAKPOINT() { }
62 #define MAX_ISA_DEVICES 10
63 #define MAX_PCI_DEVICES 10
64 #define MAX_TOTAL_DEVICES 20
66 #include <linux/config.h>
67 #include <linux/module.h>
68 #include <linux/errno.h>
69 #include <linux/signal.h>
70 #include <linux/sched.h>
71 #include <linux/timer.h>
72 #include <linux/interrupt.h>
73 #include <linux/pci.h>
74 #include <linux/tty.h>
75 #include <linux/tty_flip.h>
76 #include <linux/serial.h>
77 #include <linux/major.h>
78 #include <linux/string.h>
79 #include <linux/fcntl.h>
80 #include <linux/ptrace.h>
81 #include <linux/ioport.h>
83 #include <linux/slab.h>
84 #include <linux/delay.h>
86 #include <linux/netdevice.h>
88 #include <linux/vmalloc.h>
89 #include <linux/init.h>
90 #include <asm/serial.h>
92 #include <linux/delay.h>
93 #include <linux/ioctl.h>
95 #include <asm/system.h>
99 #include <linux/bitops.h>
100 #include <asm/types.h>
101 #include <linux/termios.h>
102 #include <linux/workqueue.h>
103 #include <linux/hdlc.h>
104 #include <linux/dma-mapping.h>
106 #ifdef CONFIG_HDLC_MODULE
107 #define CONFIG_HDLC 1
110 #define GET_USER(error,value,addr) error = get_user(value,addr)
111 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
112 #define PUT_USER(error,value,addr) error = put_user(value,addr)
113 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
115 #include <asm/uaccess.h>
117 #include "linux/synclink.h"
119 #define RCLRVALUE 0xffff
121 static MGSL_PARAMS default_params
= {
122 MGSL_MODE_HDLC
, /* unsigned long mode */
123 0, /* unsigned char loopback; */
124 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
125 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
126 0, /* unsigned long clock_speed; */
127 0xff, /* unsigned char addr_filter; */
128 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
129 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
130 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
131 9600, /* unsigned long data_rate; */
132 8, /* unsigned char data_bits; */
133 1, /* unsigned char stop_bits; */
134 ASYNC_PARITY_NONE
/* unsigned char parity; */
137 #define SHARED_MEM_ADDRESS_SIZE 0x40000
138 #define BUFFERLISTSIZE (PAGE_SIZE)
139 #define DMABUFFERSIZE (PAGE_SIZE)
140 #define MAXRXFRAMES 7
142 typedef struct _DMABUFFERENTRY
144 u32 phys_addr
; /* 32-bit flat physical address of data buffer */
145 volatile u16 count
; /* buffer size/data count */
146 volatile u16 status
; /* Control/status field */
147 volatile u16 rcc
; /* character count field */
148 u16 reserved
; /* padding required by 16C32 */
149 u32 link
; /* 32-bit flat link to next buffer entry */
150 char *virt_addr
; /* virtual address of data buffer */
151 u32 phys_entry
; /* physical address of this buffer entry */
153 } DMABUFFERENTRY
, *DMAPBUFFERENTRY
;
155 /* The queue of BH actions to be performed */
158 #define BH_TRANSMIT 2
161 #define IO_PIN_SHUTDOWN_LIMIT 100
163 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
165 struct _input_signal_events
{
176 /* transmit holding buffer definitions*/
177 #define MAX_TX_HOLDING_BUFFERS 5
178 struct tx_holding_buffer
{
180 unsigned char * buffer
;
185 * Device instance data structure
191 int count
; /* count of opens */
194 unsigned short close_delay
;
195 unsigned short closing_wait
; /* time to wait before closing */
197 struct mgsl_icount icount
;
199 struct tty_struct
*tty
;
201 int x_char
; /* xon/xoff character */
202 int blocked_open
; /* # of blocked opens */
203 u16 read_status_mask
;
204 u16 ignore_status_mask
;
205 unsigned char *xmit_buf
;
210 wait_queue_head_t open_wait
;
211 wait_queue_head_t close_wait
;
213 wait_queue_head_t status_event_wait_q
;
214 wait_queue_head_t event_wait_q
;
215 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
216 struct mgsl_struct
*next_device
; /* device list link */
218 spinlock_t irq_spinlock
; /* spinlock for synchronizing with ISR */
219 struct work_struct task
; /* task structure for scheduling bh */
221 u32 EventMask
; /* event trigger mask */
222 u32 RecordedEvents
; /* pending events */
224 u32 max_frame_size
; /* as set by device config */
228 int bh_running
; /* Protection from multiple */
232 int dcd_chkcount
; /* check counts to prevent */
233 int cts_chkcount
; /* too many IRQs if a signal */
234 int dsr_chkcount
; /* is floating */
237 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
238 u32 buffer_list_phys
;
239 dma_addr_t buffer_list_dma_addr
;
241 unsigned int rx_buffer_count
; /* count of total allocated Rx buffers */
242 DMABUFFERENTRY
*rx_buffer_list
; /* list of receive buffer entries */
243 unsigned int current_rx_buffer
;
245 int num_tx_dma_buffers
; /* number of tx dma frames required */
246 int tx_dma_buffers_used
;
247 unsigned int tx_buffer_count
; /* count of total allocated Tx buffers */
248 DMABUFFERENTRY
*tx_buffer_list
; /* list of transmit buffer entries */
249 int start_tx_dma_buffer
; /* tx dma buffer to start tx dma operation */
250 int current_tx_buffer
; /* next tx dma buffer to be loaded */
252 unsigned char *intermediate_rxbuffer
;
254 int num_tx_holding_buffers
; /* number of tx holding buffer allocated */
255 int get_tx_holding_index
; /* next tx holding buffer for adapter to load */
256 int put_tx_holding_index
; /* next tx holding buffer to store user request */
257 int tx_holding_count
; /* number of tx holding buffers waiting */
258 struct tx_holding_buffer tx_holding_buffers
[MAX_TX_HOLDING_BUFFERS
];
271 char device_name
[25]; /* device instance name */
273 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
274 unsigned char bus
; /* expansion bus number (zero based) */
275 unsigned char function
; /* PCI device number */
277 unsigned int io_base
; /* base I/O address of adapter */
278 unsigned int io_addr_size
; /* size of the I/O address range */
279 int io_addr_requested
; /* nonzero if I/O address requested */
281 unsigned int irq_level
; /* interrupt level */
282 unsigned long irq_flags
;
283 int irq_requested
; /* nonzero if IRQ requested */
285 unsigned int dma_level
; /* DMA channel */
286 int dma_requested
; /* nonzero if dma channel requested */
292 MGSL_PARAMS params
; /* communications parameters */
294 unsigned char serial_signals
; /* current serial signal states */
296 int irq_occurred
; /* for diagnostics use */
297 unsigned int init_error
; /* Initialization startup error (DIAGS) */
298 int fDiagnosticsmode
; /* Driver in Diagnostic mode? (DIAGS) */
301 unsigned char* memory_base
; /* shared memory address (PCI only) */
302 u32 phys_memory_base
;
303 int shared_mem_requested
;
305 unsigned char* lcr_base
; /* local config registers (PCI only) */
308 int lcr_mem_requested
;
311 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
312 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
313 BOOLEAN drop_rts_on_tx_done
;
315 BOOLEAN loopmode_insert_requested
;
316 BOOLEAN loopmode_send_done_requested
;
318 struct _input_signal_events input_signal_events
;
320 /* generic HDLC device parts */
326 struct net_device
*netdev
;
330 #define MGSL_MAGIC 0x5401
333 * The size of the serial xmit buffer is 1 page, or 4096 bytes
335 #ifndef SERIAL_XMIT_SIZE
336 #define SERIAL_XMIT_SIZE 4096
340 * These macros define the offsets used in calculating the
341 * I/O address of the specified USC registers.
345 #define DCPIN 2 /* Bit 1 of I/O address */
346 #define SDPIN 4 /* Bit 2 of I/O address */
348 #define DCAR 0 /* DMA command/address register */
349 #define CCAR SDPIN /* channel command/address register */
350 #define DATAREG DCPIN + SDPIN /* serial data register */
355 * These macros define the register address (ordinal number)
356 * used for writing address/value pairs to the USC.
359 #define CMR 0x02 /* Channel mode Register */
360 #define CCSR 0x04 /* Channel Command/status Register */
361 #define CCR 0x06 /* Channel Control Register */
362 #define PSR 0x08 /* Port status Register */
363 #define PCR 0x0a /* Port Control Register */
364 #define TMDR 0x0c /* Test mode Data Register */
365 #define TMCR 0x0e /* Test mode Control Register */
366 #define CMCR 0x10 /* Clock mode Control Register */
367 #define HCR 0x12 /* Hardware Configuration Register */
368 #define IVR 0x14 /* Interrupt Vector Register */
369 #define IOCR 0x16 /* Input/Output Control Register */
370 #define ICR 0x18 /* Interrupt Control Register */
371 #define DCCR 0x1a /* Daisy Chain Control Register */
372 #define MISR 0x1c /* Misc Interrupt status Register */
373 #define SICR 0x1e /* status Interrupt Control Register */
374 #define RDR 0x20 /* Receive Data Register */
375 #define RMR 0x22 /* Receive mode Register */
376 #define RCSR 0x24 /* Receive Command/status Register */
377 #define RICR 0x26 /* Receive Interrupt Control Register */
378 #define RSR 0x28 /* Receive Sync Register */
379 #define RCLR 0x2a /* Receive count Limit Register */
380 #define RCCR 0x2c /* Receive Character count Register */
381 #define TC0R 0x2e /* Time Constant 0 Register */
382 #define TDR 0x30 /* Transmit Data Register */
383 #define TMR 0x32 /* Transmit mode Register */
384 #define TCSR 0x34 /* Transmit Command/status Register */
385 #define TICR 0x36 /* Transmit Interrupt Control Register */
386 #define TSR 0x38 /* Transmit Sync Register */
387 #define TCLR 0x3a /* Transmit count Limit Register */
388 #define TCCR 0x3c /* Transmit Character count Register */
389 #define TC1R 0x3e /* Time Constant 1 Register */
393 * MACRO DEFINITIONS FOR DMA REGISTERS
396 #define DCR 0x06 /* DMA Control Register (shared) */
397 #define DACR 0x08 /* DMA Array count Register (shared) */
398 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
399 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
400 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
401 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
402 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
404 #define TDMR 0x02 /* Transmit DMA mode Register */
405 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
406 #define TBCR 0x2a /* Transmit Byte count Register */
407 #define TARL 0x2c /* Transmit Address Register (low) */
408 #define TARU 0x2e /* Transmit Address Register (high) */
409 #define NTBCR 0x3a /* Next Transmit Byte count Register */
410 #define NTARL 0x3c /* Next Transmit Address Register (low) */
411 #define NTARU 0x3e /* Next Transmit Address Register (high) */
413 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
414 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
415 #define RBCR 0xaa /* Receive Byte count Register */
416 #define RARL 0xac /* Receive Address Register (low) */
417 #define RARU 0xae /* Receive Address Register (high) */
418 #define NRBCR 0xba /* Next Receive Byte count Register */
419 #define NRARL 0xbc /* Next Receive Address Register (low) */
420 #define NRARU 0xbe /* Next Receive Address Register (high) */
424 * MACRO DEFINITIONS FOR MODEM STATUS BITS
427 #define MODEMSTATUS_DTR 0x80
428 #define MODEMSTATUS_DSR 0x40
429 #define MODEMSTATUS_RTS 0x20
430 #define MODEMSTATUS_CTS 0x10
431 #define MODEMSTATUS_RI 0x04
432 #define MODEMSTATUS_DCD 0x01
436 * Channel Command/Address Register (CCAR) Command Codes
439 #define RTCmd_Null 0x0000
440 #define RTCmd_ResetHighestIus 0x1000
441 #define RTCmd_TriggerChannelLoadDma 0x2000
442 #define RTCmd_TriggerRxDma 0x2800
443 #define RTCmd_TriggerTxDma 0x3000
444 #define RTCmd_TriggerRxAndTxDma 0x3800
445 #define RTCmd_PurgeRxFifo 0x4800
446 #define RTCmd_PurgeTxFifo 0x5000
447 #define RTCmd_PurgeRxAndTxFifo 0x5800
448 #define RTCmd_LoadRcc 0x6800
449 #define RTCmd_LoadTcc 0x7000
450 #define RTCmd_LoadRccAndTcc 0x7800
451 #define RTCmd_LoadTC0 0x8800
452 #define RTCmd_LoadTC1 0x9000
453 #define RTCmd_LoadTC0AndTC1 0x9800
454 #define RTCmd_SerialDataLSBFirst 0xa000
455 #define RTCmd_SerialDataMSBFirst 0xa800
456 #define RTCmd_SelectBigEndian 0xb000
457 #define RTCmd_SelectLittleEndian 0xb800
461 * DMA Command/Address Register (DCAR) Command Codes
464 #define DmaCmd_Null 0x0000
465 #define DmaCmd_ResetTxChannel 0x1000
466 #define DmaCmd_ResetRxChannel 0x1200
467 #define DmaCmd_StartTxChannel 0x2000
468 #define DmaCmd_StartRxChannel 0x2200
469 #define DmaCmd_ContinueTxChannel 0x3000
470 #define DmaCmd_ContinueRxChannel 0x3200
471 #define DmaCmd_PauseTxChannel 0x4000
472 #define DmaCmd_PauseRxChannel 0x4200
473 #define DmaCmd_AbortTxChannel 0x5000
474 #define DmaCmd_AbortRxChannel 0x5200
475 #define DmaCmd_InitTxChannel 0x7000
476 #define DmaCmd_InitRxChannel 0x7200
477 #define DmaCmd_ResetHighestDmaIus 0x8000
478 #define DmaCmd_ResetAllChannels 0x9000
479 #define DmaCmd_StartAllChannels 0xa000
480 #define DmaCmd_ContinueAllChannels 0xb000
481 #define DmaCmd_PauseAllChannels 0xc000
482 #define DmaCmd_AbortAllChannels 0xd000
483 #define DmaCmd_InitAllChannels 0xf000
485 #define TCmd_Null 0x0000
486 #define TCmd_ClearTxCRC 0x2000
487 #define TCmd_SelectTicrTtsaData 0x4000
488 #define TCmd_SelectTicrTxFifostatus 0x5000
489 #define TCmd_SelectTicrIntLevel 0x6000
490 #define TCmd_SelectTicrdma_level 0x7000
491 #define TCmd_SendFrame 0x8000
492 #define TCmd_SendAbort 0x9000
493 #define TCmd_EnableDleInsertion 0xc000
494 #define TCmd_DisableDleInsertion 0xd000
495 #define TCmd_ClearEofEom 0xe000
496 #define TCmd_SetEofEom 0xf000
498 #define RCmd_Null 0x0000
499 #define RCmd_ClearRxCRC 0x2000
500 #define RCmd_EnterHuntmode 0x3000
501 #define RCmd_SelectRicrRtsaData 0x4000
502 #define RCmd_SelectRicrRxFifostatus 0x5000
503 #define RCmd_SelectRicrIntLevel 0x6000
504 #define RCmd_SelectRicrdma_level 0x7000
507 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
510 #define RECEIVE_STATUS BIT5
511 #define RECEIVE_DATA BIT4
512 #define TRANSMIT_STATUS BIT3
513 #define TRANSMIT_DATA BIT2
519 * Receive status Bits in Receive Command/status Register RCSR
522 #define RXSTATUS_SHORT_FRAME BIT8
523 #define RXSTATUS_CODE_VIOLATION BIT8
524 #define RXSTATUS_EXITED_HUNT BIT7
525 #define RXSTATUS_IDLE_RECEIVED BIT6
526 #define RXSTATUS_BREAK_RECEIVED BIT5
527 #define RXSTATUS_ABORT_RECEIVED BIT5
528 #define RXSTATUS_RXBOUND BIT4
529 #define RXSTATUS_CRC_ERROR BIT3
530 #define RXSTATUS_FRAMING_ERROR BIT3
531 #define RXSTATUS_ABORT BIT2
532 #define RXSTATUS_PARITY_ERROR BIT2
533 #define RXSTATUS_OVERRUN BIT1
534 #define RXSTATUS_DATA_AVAILABLE BIT0
535 #define RXSTATUS_ALL 0x01f6
536 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
539 * Values for setting transmit idle mode in
540 * Transmit Control/status Register (TCSR)
542 #define IDLEMODE_FLAGS 0x0000
543 #define IDLEMODE_ALT_ONE_ZERO 0x0100
544 #define IDLEMODE_ZERO 0x0200
545 #define IDLEMODE_ONE 0x0300
546 #define IDLEMODE_ALT_MARK_SPACE 0x0500
547 #define IDLEMODE_SPACE 0x0600
548 #define IDLEMODE_MARK 0x0700
549 #define IDLEMODE_MASK 0x0700
552 * IUSC revision identifiers
554 #define IUSC_SL1660 0x4d44
555 #define IUSC_PRE_SL1660 0x4553
558 * Transmit status Bits in Transmit Command/status Register (TCSR)
561 #define TCSR_PRESERVE 0x0F00
563 #define TCSR_UNDERWAIT BIT11
564 #define TXSTATUS_PREAMBLE_SENT BIT7
565 #define TXSTATUS_IDLE_SENT BIT6
566 #define TXSTATUS_ABORT_SENT BIT5
567 #define TXSTATUS_EOF_SENT BIT4
568 #define TXSTATUS_EOM_SENT BIT4
569 #define TXSTATUS_CRC_SENT BIT3
570 #define TXSTATUS_ALL_SENT BIT2
571 #define TXSTATUS_UNDERRUN BIT1
572 #define TXSTATUS_FIFO_EMPTY BIT0
573 #define TXSTATUS_ALL 0x00fa
574 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
577 #define MISCSTATUS_RXC_LATCHED BIT15
578 #define MISCSTATUS_RXC BIT14
579 #define MISCSTATUS_TXC_LATCHED BIT13
580 #define MISCSTATUS_TXC BIT12
581 #define MISCSTATUS_RI_LATCHED BIT11
582 #define MISCSTATUS_RI BIT10
583 #define MISCSTATUS_DSR_LATCHED BIT9
584 #define MISCSTATUS_DSR BIT8
585 #define MISCSTATUS_DCD_LATCHED BIT7
586 #define MISCSTATUS_DCD BIT6
587 #define MISCSTATUS_CTS_LATCHED BIT5
588 #define MISCSTATUS_CTS BIT4
589 #define MISCSTATUS_RCC_UNDERRUN BIT3
590 #define MISCSTATUS_DPLL_NO_SYNC BIT2
591 #define MISCSTATUS_BRG1_ZERO BIT1
592 #define MISCSTATUS_BRG0_ZERO BIT0
594 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
595 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
597 #define SICR_RXC_ACTIVE BIT15
598 #define SICR_RXC_INACTIVE BIT14
599 #define SICR_RXC (BIT15+BIT14)
600 #define SICR_TXC_ACTIVE BIT13
601 #define SICR_TXC_INACTIVE BIT12
602 #define SICR_TXC (BIT13+BIT12)
603 #define SICR_RI_ACTIVE BIT11
604 #define SICR_RI_INACTIVE BIT10
605 #define SICR_RI (BIT11+BIT10)
606 #define SICR_DSR_ACTIVE BIT9
607 #define SICR_DSR_INACTIVE BIT8
608 #define SICR_DSR (BIT9+BIT8)
609 #define SICR_DCD_ACTIVE BIT7
610 #define SICR_DCD_INACTIVE BIT6
611 #define SICR_DCD (BIT7+BIT6)
612 #define SICR_CTS_ACTIVE BIT5
613 #define SICR_CTS_INACTIVE BIT4
614 #define SICR_CTS (BIT5+BIT4)
615 #define SICR_RCC_UNDERFLOW BIT3
616 #define SICR_DPLL_NO_SYNC BIT2
617 #define SICR_BRG1_ZERO BIT1
618 #define SICR_BRG0_ZERO BIT0
620 void usc_DisableMasterIrqBit( struct mgsl_struct
*info
);
621 void usc_EnableMasterIrqBit( struct mgsl_struct
*info
);
622 void usc_EnableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
623 void usc_DisableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
624 void usc_ClearIrqPendingBits( struct mgsl_struct
*info
, u16 IrqMask
);
626 #define usc_EnableInterrupts( a, b ) \
627 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
629 #define usc_DisableInterrupts( a, b ) \
630 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
632 #define usc_EnableMasterIrqBit(a) \
633 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
635 #define usc_DisableMasterIrqBit(a) \
636 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
638 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
641 * Transmit status Bits in Transmit Control status Register (TCSR)
642 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
645 #define TXSTATUS_PREAMBLE_SENT BIT7
646 #define TXSTATUS_IDLE_SENT BIT6
647 #define TXSTATUS_ABORT_SENT BIT5
648 #define TXSTATUS_EOF BIT4
649 #define TXSTATUS_CRC_SENT BIT3
650 #define TXSTATUS_ALL_SENT BIT2
651 #define TXSTATUS_UNDERRUN BIT1
652 #define TXSTATUS_FIFO_EMPTY BIT0
654 #define DICR_MASTER BIT15
655 #define DICR_TRANSMIT BIT0
656 #define DICR_RECEIVE BIT1
658 #define usc_EnableDmaInterrupts(a,b) \
659 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
661 #define usc_DisableDmaInterrupts(a,b) \
662 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
664 #define usc_EnableStatusIrqs(a,b) \
665 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
667 #define usc_DisablestatusIrqs(a,b) \
668 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
670 /* Transmit status Bits in Transmit Control status Register (TCSR) */
671 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
674 #define DISABLE_UNCONDITIONAL 0
675 #define DISABLE_END_OF_FRAME 1
676 #define ENABLE_UNCONDITIONAL 2
677 #define ENABLE_AUTO_CTS 3
678 #define ENABLE_AUTO_DCD 3
679 #define usc_EnableTransmitter(a,b) \
680 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
681 #define usc_EnableReceiver(a,b) \
682 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
684 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 Port
);
685 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
686 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
);
688 static u16
usc_InReg( struct mgsl_struct
*info
, u16 Port
);
689 static void usc_OutReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
690 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
);
691 void usc_RCmd( struct mgsl_struct
*info
, u16 Cmd
);
692 void usc_TCmd( struct mgsl_struct
*info
, u16 Cmd
);
694 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
695 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
697 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
699 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
);
700 static void usc_start_receiver( struct mgsl_struct
*info
);
701 static void usc_stop_receiver( struct mgsl_struct
*info
);
703 static void usc_start_transmitter( struct mgsl_struct
*info
);
704 static void usc_stop_transmitter( struct mgsl_struct
*info
);
705 static void usc_set_txidle( struct mgsl_struct
*info
);
706 static void usc_load_txfifo( struct mgsl_struct
*info
);
708 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 DataRate
);
709 static void usc_enable_loopback( struct mgsl_struct
*info
, int enable
);
711 static void usc_get_serial_signals( struct mgsl_struct
*info
);
712 static void usc_set_serial_signals( struct mgsl_struct
*info
);
714 static void usc_reset( struct mgsl_struct
*info
);
716 static void usc_set_sync_mode( struct mgsl_struct
*info
);
717 static void usc_set_sdlc_mode( struct mgsl_struct
*info
);
718 static void usc_set_async_mode( struct mgsl_struct
*info
);
719 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 DataRate
);
721 static void usc_loopback_frame( struct mgsl_struct
*info
);
723 static void mgsl_tx_timeout(unsigned long context
);
726 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
);
727 static void usc_loopmode_insert_request( struct mgsl_struct
* info
);
728 static int usc_loopmode_active( struct mgsl_struct
* info
);
729 static void usc_loopmode_send_done( struct mgsl_struct
* info
);
731 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
);
734 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
735 static void hdlcdev_tx_done(struct mgsl_struct
*info
);
736 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
);
737 static int hdlcdev_init(struct mgsl_struct
*info
);
738 static void hdlcdev_exit(struct mgsl_struct
*info
);
742 * Defines a BUS descriptor value for the PCI adapter
743 * local bus address ranges.
746 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
757 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
);
760 * Adapter diagnostic routines
762 static BOOLEAN
mgsl_register_test( struct mgsl_struct
*info
);
763 static BOOLEAN
mgsl_irq_test( struct mgsl_struct
*info
);
764 static BOOLEAN
mgsl_dma_test( struct mgsl_struct
*info
);
765 static BOOLEAN
mgsl_memory_test( struct mgsl_struct
*info
);
766 static int mgsl_adapter_test( struct mgsl_struct
*info
);
769 * device and resource management routines
771 static int mgsl_claim_resources(struct mgsl_struct
*info
);
772 static void mgsl_release_resources(struct mgsl_struct
*info
);
773 static void mgsl_add_device(struct mgsl_struct
*info
);
774 static struct mgsl_struct
* mgsl_allocate_device(void);
777 * DMA buffer manupulation functions.
779 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
);
780 static int mgsl_get_rx_frame( struct mgsl_struct
*info
);
781 static int mgsl_get_raw_rx_frame( struct mgsl_struct
*info
);
782 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
);
783 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
);
784 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
);
785 static void mgsl_load_tx_dma_buffer( struct mgsl_struct
*info
, const char *Buffer
, unsigned int BufferSize
);
786 static void mgsl_load_pci_memory(char* TargetPtr
, const char* SourcePtr
, unsigned short count
);
789 * DMA and Shared Memory buffer allocation and formatting
791 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
);
792 static void mgsl_free_dma_buffers(struct mgsl_struct
*info
);
793 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
794 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
795 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct
*info
);
796 static void mgsl_free_buffer_list_memory(struct mgsl_struct
*info
);
797 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
798 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
799 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
800 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
);
801 static int load_next_tx_holding_buffer(struct mgsl_struct
*info
);
802 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
);
805 * Bottom half interrupt handlers
807 static void mgsl_bh_handler(void* Context
);
808 static void mgsl_bh_receive(struct mgsl_struct
*info
);
809 static void mgsl_bh_transmit(struct mgsl_struct
*info
);
810 static void mgsl_bh_status(struct mgsl_struct
*info
);
813 * Interrupt handler routines and dispatch table.
815 static void mgsl_isr_null( struct mgsl_struct
*info
);
816 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
);
817 static void mgsl_isr_receive_data( struct mgsl_struct
*info
);
818 static void mgsl_isr_receive_status( struct mgsl_struct
*info
);
819 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
);
820 static void mgsl_isr_io_pin( struct mgsl_struct
*info
);
821 static void mgsl_isr_misc( struct mgsl_struct
*info
);
822 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
);
823 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
);
825 typedef void (*isr_dispatch_func
)(struct mgsl_struct
*);
827 static isr_dispatch_func UscIsrTable
[7] =
832 mgsl_isr_transmit_data
,
833 mgsl_isr_transmit_status
,
834 mgsl_isr_receive_data
,
835 mgsl_isr_receive_status
839 * ioctl call handlers
841 static int tiocmget(struct tty_struct
*tty
, struct file
*file
);
842 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
843 unsigned int set
, unsigned int clear
);
844 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount
845 __user
*user_icount
);
846 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
);
847 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
);
848 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
);
849 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
);
850 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
);
851 static int mgsl_txabort(struct mgsl_struct
* info
);
852 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
);
853 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
*mask
);
854 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
);
856 /* set non-zero on successful registration with PCI subsystem */
857 static int pci_registered
;
860 * Global linked list of SyncLink devices
862 static struct mgsl_struct
*mgsl_device_list
;
863 static int mgsl_device_count
;
866 * Set this param to non-zero to load eax with the
867 * .text section address and breakpoint on module load.
868 * This is useful for use with gdb and add-symbol-file command.
870 static int break_on_load
;
873 * Driver major number, defaults to zero to get auto
874 * assigned major number. May be forced as module parameter.
879 * Array of user specified options for ISA adapters.
881 static int io
[MAX_ISA_DEVICES
];
882 static int irq
[MAX_ISA_DEVICES
];
883 static int dma
[MAX_ISA_DEVICES
];
884 static int debug_level
;
885 static int maxframe
[MAX_TOTAL_DEVICES
];
886 static int dosyncppp
[MAX_TOTAL_DEVICES
];
887 static int txdmabufs
[MAX_TOTAL_DEVICES
];
888 static int txholdbufs
[MAX_TOTAL_DEVICES
];
890 module_param(break_on_load
, bool, 0);
891 module_param(ttymajor
, int, 0);
892 module_param_array(io
, int, NULL
, 0);
893 module_param_array(irq
, int, NULL
, 0);
894 module_param_array(dma
, int, NULL
, 0);
895 module_param(debug_level
, int, 0);
896 module_param_array(maxframe
, int, NULL
, 0);
897 module_param_array(dosyncppp
, int, NULL
, 0);
898 module_param_array(txdmabufs
, int, NULL
, 0);
899 module_param_array(txholdbufs
, int, NULL
, 0);
901 static char *driver_name
= "SyncLink serial driver";
902 static char *driver_version
= "$Revision: 4.38 $";
904 static int synclink_init_one (struct pci_dev
*dev
,
905 const struct pci_device_id
*ent
);
906 static void synclink_remove_one (struct pci_dev
*dev
);
908 static struct pci_device_id synclink_pci_tbl
[] = {
909 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_USC
, PCI_ANY_ID
, PCI_ANY_ID
, },
910 { PCI_VENDOR_ID_MICROGATE
, 0x0210, PCI_ANY_ID
, PCI_ANY_ID
, },
911 { 0, }, /* terminate list */
913 MODULE_DEVICE_TABLE(pci
, synclink_pci_tbl
);
915 MODULE_LICENSE("GPL");
917 static struct pci_driver synclink_pci_driver
= {
919 .id_table
= synclink_pci_tbl
,
920 .probe
= synclink_init_one
,
921 .remove
= __devexit_p(synclink_remove_one
),
924 static struct tty_driver
*serial_driver
;
926 /* number of characters left in xmit buffer before we ask for more */
927 #define WAKEUP_CHARS 256
930 static void mgsl_change_params(struct mgsl_struct
*info
);
931 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
);
934 * 1st function defined in .text section. Calling this function in
935 * init_module() followed by a breakpoint allows a remote debugger
936 * (gdb) to get the .text address for the add-symbol-file command.
937 * This allows remote debugging of dynamically loadable modules.
939 static void* mgsl_get_text_ptr(void)
941 return mgsl_get_text_ptr
;
945 * tmp_buf is used as a temporary buffer by mgsl_write. We need to
946 * lock it in case the COPY_FROM_USER blocks while swapping in a page,
947 * and some other program tries to do a serial write at the same time.
948 * Since the lock will only come under contention when the system is
949 * swapping and available memory is low, it makes sense to share one
950 * buffer across all the serial ioports, since it significantly saves
951 * memory if large numbers of serial ports are open.
953 static unsigned char *tmp_buf
;
954 static DECLARE_MUTEX(tmp_buf_sem
);
956 static inline int mgsl_paranoia_check(struct mgsl_struct
*info
,
957 char *name
, const char *routine
)
959 #ifdef MGSL_PARANOIA_CHECK
960 static const char *badmagic
=
961 "Warning: bad magic number for mgsl struct (%s) in %s\n";
962 static const char *badinfo
=
963 "Warning: null mgsl_struct for (%s) in %s\n";
966 printk(badinfo
, name
, routine
);
969 if (info
->magic
!= MGSL_MAGIC
) {
970 printk(badmagic
, name
, routine
);
981 * line discipline callback wrappers
983 * The wrappers maintain line discipline references
984 * while calling into the line discipline.
986 * ldisc_receive_buf - pass receive data to line discipline
989 static void ldisc_receive_buf(struct tty_struct
*tty
,
990 const __u8
*data
, char *flags
, int count
)
992 struct tty_ldisc
*ld
;
995 ld
= tty_ldisc_ref(tty
);
998 ld
->receive_buf(tty
, data
, flags
, count
);
1003 /* mgsl_stop() throttle (stop) transmitter
1005 * Arguments: tty pointer to tty info structure
1006 * Return Value: None
1008 static void mgsl_stop(struct tty_struct
*tty
)
1010 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
1011 unsigned long flags
;
1013 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_stop"))
1016 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1017 printk("mgsl_stop(%s)\n",info
->device_name
);
1019 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1020 if (info
->tx_enabled
)
1021 usc_stop_transmitter(info
);
1022 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1024 } /* end of mgsl_stop() */
1026 /* mgsl_start() release (start) transmitter
1028 * Arguments: tty pointer to tty info structure
1029 * Return Value: None
1031 static void mgsl_start(struct tty_struct
*tty
)
1033 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
1034 unsigned long flags
;
1036 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_start"))
1039 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1040 printk("mgsl_start(%s)\n",info
->device_name
);
1042 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1043 if (!info
->tx_enabled
)
1044 usc_start_transmitter(info
);
1045 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1047 } /* end of mgsl_start() */
1050 * Bottom half work queue access functions
1053 /* mgsl_bh_action() Return next bottom half action to perform.
1054 * Return Value: BH action code or 0 if nothing to do.
1056 static int mgsl_bh_action(struct mgsl_struct
*info
)
1058 unsigned long flags
;
1061 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1063 if (info
->pending_bh
& BH_RECEIVE
) {
1064 info
->pending_bh
&= ~BH_RECEIVE
;
1066 } else if (info
->pending_bh
& BH_TRANSMIT
) {
1067 info
->pending_bh
&= ~BH_TRANSMIT
;
1069 } else if (info
->pending_bh
& BH_STATUS
) {
1070 info
->pending_bh
&= ~BH_STATUS
;
1075 /* Mark BH routine as complete */
1076 info
->bh_running
= 0;
1077 info
->bh_requested
= 0;
1080 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1086 * Perform bottom half processing of work items queued by ISR.
1088 static void mgsl_bh_handler(void* Context
)
1090 struct mgsl_struct
*info
= (struct mgsl_struct
*)Context
;
1096 if ( debug_level
>= DEBUG_LEVEL_BH
)
1097 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1098 __FILE__
,__LINE__
,info
->device_name
);
1100 info
->bh_running
= 1;
1102 while((action
= mgsl_bh_action(info
)) != 0) {
1104 /* Process work item */
1105 if ( debug_level
>= DEBUG_LEVEL_BH
)
1106 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1107 __FILE__
,__LINE__
,action
);
1112 mgsl_bh_receive(info
);
1115 mgsl_bh_transmit(info
);
1118 mgsl_bh_status(info
);
1121 /* unknown work item ID */
1122 printk("Unknown work item ID=%08X!\n", action
);
1127 if ( debug_level
>= DEBUG_LEVEL_BH
)
1128 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1129 __FILE__
,__LINE__
,info
->device_name
);
1132 static void mgsl_bh_receive(struct mgsl_struct
*info
)
1134 int (*get_rx_frame
)(struct mgsl_struct
*info
) =
1135 (info
->params
.mode
== MGSL_MODE_HDLC
? mgsl_get_rx_frame
: mgsl_get_raw_rx_frame
);
1137 if ( debug_level
>= DEBUG_LEVEL_BH
)
1138 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1139 __FILE__
,__LINE__
,info
->device_name
);
1143 if (info
->rx_rcc_underrun
) {
1144 unsigned long flags
;
1145 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1146 usc_start_receiver(info
);
1147 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1150 } while(get_rx_frame(info
));
1153 static void mgsl_bh_transmit(struct mgsl_struct
*info
)
1155 struct tty_struct
*tty
= info
->tty
;
1156 unsigned long flags
;
1158 if ( debug_level
>= DEBUG_LEVEL_BH
)
1159 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1160 __FILE__
,__LINE__
,info
->device_name
);
1164 wake_up_interruptible(&tty
->write_wait
);
1167 /* if transmitter idle and loopmode_send_done_requested
1168 * then start echoing RxD to TxD
1170 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1171 if ( !info
->tx_active
&& info
->loopmode_send_done_requested
)
1172 usc_loopmode_send_done( info
);
1173 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1176 static void mgsl_bh_status(struct mgsl_struct
*info
)
1178 if ( debug_level
>= DEBUG_LEVEL_BH
)
1179 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1180 __FILE__
,__LINE__
,info
->device_name
);
1182 info
->ri_chkcount
= 0;
1183 info
->dsr_chkcount
= 0;
1184 info
->dcd_chkcount
= 0;
1185 info
->cts_chkcount
= 0;
1188 /* mgsl_isr_receive_status()
1190 * Service a receive status interrupt. The type of status
1191 * interrupt is indicated by the state of the RCSR.
1192 * This is only used for HDLC mode.
1194 * Arguments: info pointer to device instance data
1195 * Return Value: None
1197 static void mgsl_isr_receive_status( struct mgsl_struct
*info
)
1199 u16 status
= usc_InReg( info
, RCSR
);
1201 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1202 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1203 __FILE__
,__LINE__
,status
);
1205 if ( (status
& RXSTATUS_ABORT_RECEIVED
) &&
1206 info
->loopmode_insert_requested
&&
1207 usc_loopmode_active(info
) )
1209 ++info
->icount
.rxabort
;
1210 info
->loopmode_insert_requested
= FALSE
;
1212 /* clear CMR:13 to start echoing RxD to TxD */
1213 info
->cmr_value
&= ~BIT13
;
1214 usc_OutReg(info
, CMR
, info
->cmr_value
);
1216 /* disable received abort irq (no longer required) */
1217 usc_OutReg(info
, RICR
,
1218 (usc_InReg(info
, RICR
) & ~RXSTATUS_ABORT_RECEIVED
));
1221 if (status
& (RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
)) {
1222 if (status
& RXSTATUS_EXITED_HUNT
)
1223 info
->icount
.exithunt
++;
1224 if (status
& RXSTATUS_IDLE_RECEIVED
)
1225 info
->icount
.rxidle
++;
1226 wake_up_interruptible(&info
->event_wait_q
);
1229 if (status
& RXSTATUS_OVERRUN
){
1230 info
->icount
.rxover
++;
1231 usc_process_rxoverrun_sync( info
);
1234 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
1235 usc_UnlatchRxstatusBits( info
, status
);
1237 } /* end of mgsl_isr_receive_status() */
1239 /* mgsl_isr_transmit_status()
1241 * Service a transmit status interrupt
1242 * HDLC mode :end of transmit frame
1243 * Async mode:all data is sent
1244 * transmit status is indicated by bits in the TCSR.
1246 * Arguments: info pointer to device instance data
1247 * Return Value: None
1249 static void mgsl_isr_transmit_status( struct mgsl_struct
*info
)
1251 u16 status
= usc_InReg( info
, TCSR
);
1253 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1254 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1255 __FILE__
,__LINE__
,status
);
1257 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
1258 usc_UnlatchTxstatusBits( info
, status
);
1260 if ( status
& (TXSTATUS_UNDERRUN
| TXSTATUS_ABORT_SENT
) )
1262 /* finished sending HDLC abort. This may leave */
1263 /* the TxFifo with data from the aborted frame */
1264 /* so purge the TxFifo. Also shutdown the DMA */
1265 /* channel in case there is data remaining in */
1266 /* the DMA buffer */
1267 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
1268 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
1271 if ( status
& TXSTATUS_EOF_SENT
)
1272 info
->icount
.txok
++;
1273 else if ( status
& TXSTATUS_UNDERRUN
)
1274 info
->icount
.txunder
++;
1275 else if ( status
& TXSTATUS_ABORT_SENT
)
1276 info
->icount
.txabort
++;
1278 info
->icount
.txunder
++;
1280 info
->tx_active
= 0;
1281 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1282 del_timer(&info
->tx_timer
);
1284 if ( info
->drop_rts_on_tx_done
) {
1285 usc_get_serial_signals( info
);
1286 if ( info
->serial_signals
& SerialSignal_RTS
) {
1287 info
->serial_signals
&= ~SerialSignal_RTS
;
1288 usc_set_serial_signals( info
);
1290 info
->drop_rts_on_tx_done
= 0;
1295 hdlcdev_tx_done(info
);
1299 if (info
->tty
->stopped
|| info
->tty
->hw_stopped
) {
1300 usc_stop_transmitter(info
);
1303 info
->pending_bh
|= BH_TRANSMIT
;
1306 } /* end of mgsl_isr_transmit_status() */
1308 /* mgsl_isr_io_pin()
1310 * Service an Input/Output pin interrupt. The type of
1311 * interrupt is indicated by bits in the MISR
1313 * Arguments: info pointer to device instance data
1314 * Return Value: None
1316 static void mgsl_isr_io_pin( struct mgsl_struct
*info
)
1318 struct mgsl_icount
*icount
;
1319 u16 status
= usc_InReg( info
, MISR
);
1321 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1322 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1323 __FILE__
,__LINE__
,status
);
1325 usc_ClearIrqPendingBits( info
, IO_PIN
);
1326 usc_UnlatchIostatusBits( info
, status
);
1328 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
1329 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
1330 icount
= &info
->icount
;
1331 /* update input line counters */
1332 if (status
& MISCSTATUS_RI_LATCHED
) {
1333 if ((info
->ri_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1334 usc_DisablestatusIrqs(info
,SICR_RI
);
1336 if ( status
& MISCSTATUS_RI
)
1337 info
->input_signal_events
.ri_up
++;
1339 info
->input_signal_events
.ri_down
++;
1341 if (status
& MISCSTATUS_DSR_LATCHED
) {
1342 if ((info
->dsr_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1343 usc_DisablestatusIrqs(info
,SICR_DSR
);
1345 if ( status
& MISCSTATUS_DSR
)
1346 info
->input_signal_events
.dsr_up
++;
1348 info
->input_signal_events
.dsr_down
++;
1350 if (status
& MISCSTATUS_DCD_LATCHED
) {
1351 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1352 usc_DisablestatusIrqs(info
,SICR_DCD
);
1354 if (status
& MISCSTATUS_DCD
) {
1355 info
->input_signal_events
.dcd_up
++;
1357 info
->input_signal_events
.dcd_down
++;
1360 hdlc_set_carrier(status
& MISCSTATUS_DCD
, info
->netdev
);
1363 if (status
& MISCSTATUS_CTS_LATCHED
)
1365 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1366 usc_DisablestatusIrqs(info
,SICR_CTS
);
1368 if ( status
& MISCSTATUS_CTS
)
1369 info
->input_signal_events
.cts_up
++;
1371 info
->input_signal_events
.cts_down
++;
1373 wake_up_interruptible(&info
->status_event_wait_q
);
1374 wake_up_interruptible(&info
->event_wait_q
);
1376 if ( (info
->flags
& ASYNC_CHECK_CD
) &&
1377 (status
& MISCSTATUS_DCD_LATCHED
) ) {
1378 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1379 printk("%s CD now %s...", info
->device_name
,
1380 (status
& MISCSTATUS_DCD
) ? "on" : "off");
1381 if (status
& MISCSTATUS_DCD
)
1382 wake_up_interruptible(&info
->open_wait
);
1384 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1385 printk("doing serial hangup...");
1387 tty_hangup(info
->tty
);
1391 if ( (info
->flags
& ASYNC_CTS_FLOW
) &&
1392 (status
& MISCSTATUS_CTS_LATCHED
) ) {
1393 if (info
->tty
->hw_stopped
) {
1394 if (status
& MISCSTATUS_CTS
) {
1395 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1396 printk("CTS tx start...");
1398 info
->tty
->hw_stopped
= 0;
1399 usc_start_transmitter(info
);
1400 info
->pending_bh
|= BH_TRANSMIT
;
1404 if (!(status
& MISCSTATUS_CTS
)) {
1405 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1406 printk("CTS tx stop...");
1408 info
->tty
->hw_stopped
= 1;
1409 usc_stop_transmitter(info
);
1415 info
->pending_bh
|= BH_STATUS
;
1417 /* for diagnostics set IRQ flag */
1418 if ( status
& MISCSTATUS_TXC_LATCHED
){
1419 usc_OutReg( info
, SICR
,
1420 (unsigned short)(usc_InReg(info
,SICR
) & ~(SICR_TXC_ACTIVE
+SICR_TXC_INACTIVE
)) );
1421 usc_UnlatchIostatusBits( info
, MISCSTATUS_TXC_LATCHED
);
1422 info
->irq_occurred
= 1;
1425 } /* end of mgsl_isr_io_pin() */
1427 /* mgsl_isr_transmit_data()
1429 * Service a transmit data interrupt (async mode only).
1431 * Arguments: info pointer to device instance data
1432 * Return Value: None
1434 static void mgsl_isr_transmit_data( struct mgsl_struct
*info
)
1436 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1437 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1438 __FILE__
,__LINE__
,info
->xmit_cnt
);
1440 usc_ClearIrqPendingBits( info
, TRANSMIT_DATA
);
1442 if (info
->tty
->stopped
|| info
->tty
->hw_stopped
) {
1443 usc_stop_transmitter(info
);
1447 if ( info
->xmit_cnt
)
1448 usc_load_txfifo( info
);
1450 info
->tx_active
= 0;
1452 if (info
->xmit_cnt
< WAKEUP_CHARS
)
1453 info
->pending_bh
|= BH_TRANSMIT
;
1455 } /* end of mgsl_isr_transmit_data() */
1457 /* mgsl_isr_receive_data()
1459 * Service a receive data interrupt. This occurs
1460 * when operating in asynchronous interrupt transfer mode.
1461 * The receive data FIFO is flushed to the receive data buffers.
1463 * Arguments: info pointer to device instance data
1464 * Return Value: None
1466 static void mgsl_isr_receive_data( struct mgsl_struct
*info
)
1471 unsigned char DataByte
;
1472 struct tty_struct
*tty
= info
->tty
;
1473 struct mgsl_icount
*icount
= &info
->icount
;
1475 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1476 printk("%s(%d):mgsl_isr_receive_data\n",
1479 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
);
1481 /* select FIFO status for RICR readback */
1482 usc_RCmd( info
, RCmd_SelectRicrRxFifostatus
);
1484 /* clear the Wordstatus bit so that status readback */
1485 /* only reflects the status of this byte */
1486 usc_OutReg( info
, RICR
+LSBONLY
, (u16
)(usc_InReg(info
, RICR
+LSBONLY
) & ~BIT3
));
1488 /* flush the receive FIFO */
1490 while( (Fifocount
= (usc_InReg(info
,RICR
) >> 8)) ) {
1493 /* read one byte from RxFIFO */
1494 outw( (inw(info
->io_base
+ CCAR
) & 0x0780) | (RDR
+LSBONLY
),
1495 info
->io_base
+ CCAR
);
1496 DataByte
= inb( info
->io_base
+ CCAR
);
1498 /* get the status of the received byte */
1499 status
= usc_InReg(info
, RCSR
);
1500 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1501 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) )
1502 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
1507 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1508 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) ) {
1509 printk("rxerr=%04X\n",status
);
1510 /* update error statistics */
1511 if ( status
& RXSTATUS_BREAK_RECEIVED
) {
1512 status
&= ~(RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
);
1514 } else if (status
& RXSTATUS_PARITY_ERROR
)
1516 else if (status
& RXSTATUS_FRAMING_ERROR
)
1518 else if (status
& RXSTATUS_OVERRUN
) {
1519 /* must issue purge fifo cmd before */
1520 /* 16C32 accepts more receive chars */
1521 usc_RTCmd(info
,RTCmd_PurgeRxFifo
);
1525 /* discard char if tty control flags say so */
1526 if (status
& info
->ignore_status_mask
)
1529 status
&= info
->read_status_mask
;
1531 if (status
& RXSTATUS_BREAK_RECEIVED
) {
1533 if (info
->flags
& ASYNC_SAK
)
1535 } else if (status
& RXSTATUS_PARITY_ERROR
)
1537 else if (status
& RXSTATUS_FRAMING_ERROR
)
1539 } /* end of if (error) */
1540 tty_insert_flip_char(tty
, DataByte
, flag
);
1541 if (status
& RXSTATUS_OVERRUN
) {
1542 /* Overrun is special, since it's
1543 * reported immediately, and doesn't
1544 * affect the current character
1546 work
+= tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
1550 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
1551 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1552 __FILE__
,__LINE__
,icount
->rx
,icount
->brk
,
1553 icount
->parity
,icount
->frame
,icount
->overrun
);
1557 tty_flip_buffer_push(tty
);
1562 * Service a miscellaneos interrupt source.
1564 * Arguments: info pointer to device extension (instance data)
1565 * Return Value: None
1567 static void mgsl_isr_misc( struct mgsl_struct
*info
)
1569 u16 status
= usc_InReg( info
, MISR
);
1571 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1572 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1573 __FILE__
,__LINE__
,status
);
1575 if ((status
& MISCSTATUS_RCC_UNDERRUN
) &&
1576 (info
->params
.mode
== MGSL_MODE_HDLC
)) {
1578 /* turn off receiver and rx DMA */
1579 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
1580 usc_DmaCmd(info
, DmaCmd_ResetRxChannel
);
1581 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
1582 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1583 usc_DisableInterrupts(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
1585 /* schedule BH handler to restart receiver */
1586 info
->pending_bh
|= BH_RECEIVE
;
1587 info
->rx_rcc_underrun
= 1;
1590 usc_ClearIrqPendingBits( info
, MISC
);
1591 usc_UnlatchMiscstatusBits( info
, status
);
1593 } /* end of mgsl_isr_misc() */
1597 * Services undefined interrupt vectors from the
1598 * USC. (hence this function SHOULD never be called)
1600 * Arguments: info pointer to device extension (instance data)
1601 * Return Value: None
1603 static void mgsl_isr_null( struct mgsl_struct
*info
)
1606 } /* end of mgsl_isr_null() */
1608 /* mgsl_isr_receive_dma()
1610 * Service a receive DMA channel interrupt.
1611 * For this driver there are two sources of receive DMA interrupts
1612 * as identified in the Receive DMA mode Register (RDMR):
1614 * BIT3 EOA/EOL End of List, all receive buffers in receive
1615 * buffer list have been filled (no more free buffers
1616 * available). The DMA controller has shut down.
1618 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1619 * DMA buffer is terminated in response to completion
1620 * of a good frame or a frame with errors. The status
1621 * of the frame is stored in the buffer entry in the
1622 * list of receive buffer entries.
1624 * Arguments: info pointer to device instance data
1625 * Return Value: None
1627 static void mgsl_isr_receive_dma( struct mgsl_struct
*info
)
1631 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1632 usc_OutDmaReg( info
, CDIR
, BIT9
+BIT1
);
1634 /* Read the receive DMA status to identify interrupt type. */
1635 /* This also clears the status bits. */
1636 status
= usc_InDmaReg( info
, RDMR
);
1638 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1639 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1640 __FILE__
,__LINE__
,info
->device_name
,status
);
1642 info
->pending_bh
|= BH_RECEIVE
;
1644 if ( status
& BIT3
) {
1645 info
->rx_overflow
= 1;
1646 info
->icount
.buf_overrun
++;
1649 } /* end of mgsl_isr_receive_dma() */
1651 /* mgsl_isr_transmit_dma()
1653 * This function services a transmit DMA channel interrupt.
1655 * For this driver there is one source of transmit DMA interrupts
1656 * as identified in the Transmit DMA Mode Register (TDMR):
1658 * BIT2 EOB End of Buffer. This interrupt occurs when a
1659 * transmit DMA buffer has been emptied.
1661 * The driver maintains enough transmit DMA buffers to hold at least
1662 * one max frame size transmit frame. When operating in a buffered
1663 * transmit mode, there may be enough transmit DMA buffers to hold at
1664 * least two or more max frame size frames. On an EOB condition,
1665 * determine if there are any queued transmit buffers and copy into
1666 * transmit DMA buffers if we have room.
1668 * Arguments: info pointer to device instance data
1669 * Return Value: None
1671 static void mgsl_isr_transmit_dma( struct mgsl_struct
*info
)
1675 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1676 usc_OutDmaReg(info
, CDIR
, BIT8
+BIT0
);
1678 /* Read the transmit DMA status to identify interrupt type. */
1679 /* This also clears the status bits. */
1681 status
= usc_InDmaReg( info
, TDMR
);
1683 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1684 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1685 __FILE__
,__LINE__
,info
->device_name
,status
);
1687 if ( status
& BIT2
) {
1688 --info
->tx_dma_buffers_used
;
1690 /* if there are transmit frames queued,
1691 * try to load the next one
1693 if ( load_next_tx_holding_buffer(info
) ) {
1694 /* if call returns non-zero value, we have
1695 * at least one free tx holding buffer
1697 info
->pending_bh
|= BH_TRANSMIT
;
1701 } /* end of mgsl_isr_transmit_dma() */
1705 * Interrupt service routine entry point.
1709 * irq interrupt number that caused interrupt
1710 * dev_id device ID supplied during interrupt registration
1711 * regs interrupted processor context
1713 * Return Value: None
1715 static irqreturn_t
mgsl_interrupt(int irq
, void *dev_id
, struct pt_regs
* regs
)
1717 struct mgsl_struct
* info
;
1721 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1722 printk("%s(%d):mgsl_interrupt(%d)entry.\n",
1723 __FILE__
,__LINE__
,irq
);
1725 info
= (struct mgsl_struct
*)dev_id
;
1729 spin_lock(&info
->irq_spinlock
);
1732 /* Read the interrupt vectors from hardware. */
1733 UscVector
= usc_InReg(info
, IVR
) >> 9;
1734 DmaVector
= usc_InDmaReg(info
, DIVR
);
1736 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1737 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1738 __FILE__
,__LINE__
,info
->device_name
,UscVector
,DmaVector
);
1740 if ( !UscVector
&& !DmaVector
)
1743 /* Dispatch interrupt vector */
1745 (*UscIsrTable
[UscVector
])(info
);
1746 else if ( (DmaVector
&(BIT10
|BIT9
)) == BIT10
)
1747 mgsl_isr_transmit_dma(info
);
1749 mgsl_isr_receive_dma(info
);
1751 if ( info
->isr_overflow
) {
1752 printk(KERN_ERR
"%s(%d):%s isr overflow irq=%d\n",
1753 __FILE__
,__LINE__
,info
->device_name
, irq
);
1754 usc_DisableMasterIrqBit(info
);
1755 usc_DisableDmaInterrupts(info
,DICR_MASTER
);
1760 /* Request bottom half processing if there's something
1761 * for it to do and the bh is not already running
1764 if ( info
->pending_bh
&& !info
->bh_running
&& !info
->bh_requested
) {
1765 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1766 printk("%s(%d):%s queueing bh task.\n",
1767 __FILE__
,__LINE__
,info
->device_name
);
1768 schedule_work(&info
->task
);
1769 info
->bh_requested
= 1;
1772 spin_unlock(&info
->irq_spinlock
);
1774 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1775 printk("%s(%d):mgsl_interrupt(%d)exit.\n",
1776 __FILE__
,__LINE__
,irq
);
1778 } /* end of mgsl_interrupt() */
1782 * Initialize and start device.
1784 * Arguments: info pointer to device instance data
1785 * Return Value: 0 if success, otherwise error code
1787 static int startup(struct mgsl_struct
* info
)
1791 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1792 printk("%s(%d):mgsl_startup(%s)\n",__FILE__
,__LINE__
,info
->device_name
);
1794 if (info
->flags
& ASYNC_INITIALIZED
)
1797 if (!info
->xmit_buf
) {
1798 /* allocate a page of memory for a transmit buffer */
1799 info
->xmit_buf
= (unsigned char *)get_zeroed_page(GFP_KERNEL
);
1800 if (!info
->xmit_buf
) {
1801 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
1802 __FILE__
,__LINE__
,info
->device_name
);
1807 info
->pending_bh
= 0;
1809 memset(&info
->icount
, 0, sizeof(info
->icount
));
1811 init_timer(&info
->tx_timer
);
1812 info
->tx_timer
.data
= (unsigned long)info
;
1813 info
->tx_timer
.function
= mgsl_tx_timeout
;
1815 /* Allocate and claim adapter resources */
1816 retval
= mgsl_claim_resources(info
);
1818 /* perform existence check and diagnostics */
1820 retval
= mgsl_adapter_test(info
);
1823 if (capable(CAP_SYS_ADMIN
) && info
->tty
)
1824 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1825 mgsl_release_resources(info
);
1829 /* program hardware for current parameters */
1830 mgsl_change_params(info
);
1833 clear_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1835 info
->flags
|= ASYNC_INITIALIZED
;
1839 } /* end of startup() */
1843 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1845 * Arguments: info pointer to device instance data
1846 * Return Value: None
1848 static void shutdown(struct mgsl_struct
* info
)
1850 unsigned long flags
;
1852 if (!(info
->flags
& ASYNC_INITIALIZED
))
1855 if (debug_level
>= DEBUG_LEVEL_INFO
)
1856 printk("%s(%d):mgsl_shutdown(%s)\n",
1857 __FILE__
,__LINE__
, info
->device_name
);
1859 /* clear status wait queue because status changes */
1860 /* can't happen after shutting down the hardware */
1861 wake_up_interruptible(&info
->status_event_wait_q
);
1862 wake_up_interruptible(&info
->event_wait_q
);
1864 del_timer(&info
->tx_timer
);
1866 if (info
->xmit_buf
) {
1867 free_page((unsigned long) info
->xmit_buf
);
1868 info
->xmit_buf
= NULL
;
1871 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1872 usc_DisableMasterIrqBit(info
);
1873 usc_stop_receiver(info
);
1874 usc_stop_transmitter(info
);
1875 usc_DisableInterrupts(info
,RECEIVE_DATA
+ RECEIVE_STATUS
+
1876 TRANSMIT_DATA
+ TRANSMIT_STATUS
+ IO_PIN
+ MISC
);
1877 usc_DisableDmaInterrupts(info
,DICR_MASTER
+ DICR_TRANSMIT
+ DICR_RECEIVE
);
1879 /* Disable DMAEN (Port 7, Bit 14) */
1880 /* This disconnects the DMA request signal from the ISA bus */
1881 /* on the ISA adapter. This has no effect for the PCI adapter */
1882 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) | BIT14
));
1884 /* Disable INTEN (Port 6, Bit12) */
1885 /* This disconnects the IRQ request signal to the ISA bus */
1886 /* on the ISA adapter. This has no effect for the PCI adapter */
1887 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) | BIT12
));
1889 if (!info
->tty
|| info
->tty
->termios
->c_cflag
& HUPCL
) {
1890 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
1891 usc_set_serial_signals(info
);
1894 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1896 mgsl_release_resources(info
);
1899 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1901 info
->flags
&= ~ASYNC_INITIALIZED
;
1903 } /* end of shutdown() */
1905 static void mgsl_program_hw(struct mgsl_struct
*info
)
1907 unsigned long flags
;
1909 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1911 usc_stop_receiver(info
);
1912 usc_stop_transmitter(info
);
1913 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1915 if (info
->params
.mode
== MGSL_MODE_HDLC
||
1916 info
->params
.mode
== MGSL_MODE_RAW
||
1918 usc_set_sync_mode(info
);
1920 usc_set_async_mode(info
);
1922 usc_set_serial_signals(info
);
1924 info
->dcd_chkcount
= 0;
1925 info
->cts_chkcount
= 0;
1926 info
->ri_chkcount
= 0;
1927 info
->dsr_chkcount
= 0;
1929 usc_EnableStatusIrqs(info
,SICR_CTS
+SICR_DSR
+SICR_DCD
+SICR_RI
);
1930 usc_EnableInterrupts(info
, IO_PIN
);
1931 usc_get_serial_signals(info
);
1933 if (info
->netcount
|| info
->tty
->termios
->c_cflag
& CREAD
)
1934 usc_start_receiver(info
);
1936 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1939 /* Reconfigure adapter based on new parameters
1941 static void mgsl_change_params(struct mgsl_struct
*info
)
1946 if (!info
->tty
|| !info
->tty
->termios
)
1949 if (debug_level
>= DEBUG_LEVEL_INFO
)
1950 printk("%s(%d):mgsl_change_params(%s)\n",
1951 __FILE__
,__LINE__
, info
->device_name
);
1953 cflag
= info
->tty
->termios
->c_cflag
;
1955 /* if B0 rate (hangup) specified then negate DTR and RTS */
1956 /* otherwise assert DTR and RTS */
1958 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1960 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
1962 /* byte size and parity */
1964 switch (cflag
& CSIZE
) {
1965 case CS5
: info
->params
.data_bits
= 5; break;
1966 case CS6
: info
->params
.data_bits
= 6; break;
1967 case CS7
: info
->params
.data_bits
= 7; break;
1968 case CS8
: info
->params
.data_bits
= 8; break;
1969 /* Never happens, but GCC is too dumb to figure it out */
1970 default: info
->params
.data_bits
= 7; break;
1974 info
->params
.stop_bits
= 2;
1976 info
->params
.stop_bits
= 1;
1978 info
->params
.parity
= ASYNC_PARITY_NONE
;
1979 if (cflag
& PARENB
) {
1981 info
->params
.parity
= ASYNC_PARITY_ODD
;
1983 info
->params
.parity
= ASYNC_PARITY_EVEN
;
1986 info
->params
.parity
= ASYNC_PARITY_SPACE
;
1990 /* calculate number of jiffies to transmit a full
1991 * FIFO (32 bytes) at specified data rate
1993 bits_per_char
= info
->params
.data_bits
+
1994 info
->params
.stop_bits
+ 1;
1996 /* if port data rate is set to 460800 or less then
1997 * allow tty settings to override, otherwise keep the
1998 * current data rate.
2000 if (info
->params
.data_rate
<= 460800)
2001 info
->params
.data_rate
= tty_get_baud_rate(info
->tty
);
2003 if ( info
->params
.data_rate
) {
2004 info
->timeout
= (32*HZ
*bits_per_char
) /
2005 info
->params
.data_rate
;
2007 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
2009 if (cflag
& CRTSCTS
)
2010 info
->flags
|= ASYNC_CTS_FLOW
;
2012 info
->flags
&= ~ASYNC_CTS_FLOW
;
2015 info
->flags
&= ~ASYNC_CHECK_CD
;
2017 info
->flags
|= ASYNC_CHECK_CD
;
2019 /* process tty input control flags */
2021 info
->read_status_mask
= RXSTATUS_OVERRUN
;
2022 if (I_INPCK(info
->tty
))
2023 info
->read_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
2024 if (I_BRKINT(info
->tty
) || I_PARMRK(info
->tty
))
2025 info
->read_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
2027 if (I_IGNPAR(info
->tty
))
2028 info
->ignore_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
2029 if (I_IGNBRK(info
->tty
)) {
2030 info
->ignore_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
2031 /* If ignoring parity and break indicators, ignore
2032 * overruns too. (For real raw support).
2034 if (I_IGNPAR(info
->tty
))
2035 info
->ignore_status_mask
|= RXSTATUS_OVERRUN
;
2038 mgsl_program_hw(info
);
2040 } /* end of mgsl_change_params() */
2044 * Add a character to the transmit buffer.
2046 * Arguments: tty pointer to tty information structure
2047 * ch character to add to transmit buffer
2049 * Return Value: None
2051 static void mgsl_put_char(struct tty_struct
*tty
, unsigned char ch
)
2053 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2054 unsigned long flags
;
2056 if ( debug_level
>= DEBUG_LEVEL_INFO
) {
2057 printk( "%s(%d):mgsl_put_char(%d) on %s\n",
2058 __FILE__
,__LINE__
,ch
,info
->device_name
);
2061 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_put_char"))
2064 if (!tty
|| !info
->xmit_buf
)
2067 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2069 if ( (info
->params
.mode
== MGSL_MODE_ASYNC
) || !info
->tx_active
) {
2071 if (info
->xmit_cnt
< SERIAL_XMIT_SIZE
- 1) {
2072 info
->xmit_buf
[info
->xmit_head
++] = ch
;
2073 info
->xmit_head
&= SERIAL_XMIT_SIZE
-1;
2078 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2080 } /* end of mgsl_put_char() */
2082 /* mgsl_flush_chars()
2084 * Enable transmitter so remaining characters in the
2085 * transmit buffer are sent.
2087 * Arguments: tty pointer to tty information structure
2088 * Return Value: None
2090 static void mgsl_flush_chars(struct tty_struct
*tty
)
2092 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2093 unsigned long flags
;
2095 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2096 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2097 __FILE__
,__LINE__
,info
->device_name
,info
->xmit_cnt
);
2099 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_chars"))
2102 if (info
->xmit_cnt
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
2106 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2107 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2108 __FILE__
,__LINE__
,info
->device_name
);
2110 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2112 if (!info
->tx_active
) {
2113 if ( (info
->params
.mode
== MGSL_MODE_HDLC
||
2114 info
->params
.mode
== MGSL_MODE_RAW
) && info
->xmit_cnt
) {
2115 /* operating in synchronous (frame oriented) mode */
2116 /* copy data from circular xmit_buf to */
2117 /* transmit DMA buffer. */
2118 mgsl_load_tx_dma_buffer(info
,
2119 info
->xmit_buf
,info
->xmit_cnt
);
2121 usc_start_transmitter(info
);
2124 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2126 } /* end of mgsl_flush_chars() */
2130 * Send a block of data
2134 * tty pointer to tty information structure
2135 * buf pointer to buffer containing send data
2136 * count size of send data in bytes
2138 * Return Value: number of characters written
2140 static int mgsl_write(struct tty_struct
* tty
,
2141 const unsigned char *buf
, int count
)
2144 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2145 unsigned long flags
;
2147 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2148 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2149 __FILE__
,__LINE__
,info
->device_name
,count
);
2151 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write"))
2154 if (!tty
|| !info
->xmit_buf
|| !tmp_buf
)
2157 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2158 info
->params
.mode
== MGSL_MODE_RAW
) {
2159 /* operating in synchronous (frame oriented) mode */
2160 /* operating in synchronous (frame oriented) mode */
2161 if (info
->tx_active
) {
2163 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
2167 /* transmitter is actively sending data -
2168 * if we have multiple transmit dma and
2169 * holding buffers, attempt to queue this
2170 * frame for transmission at a later time.
2172 if (info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
2173 /* no tx holding buffers available */
2178 /* queue transmit frame request */
2180 save_tx_buffer_request(info
,buf
,count
);
2182 /* if we have sufficient tx dma buffers,
2183 * load the next buffered tx request
2185 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2186 load_next_tx_holding_buffer(info
);
2187 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2191 /* if operating in HDLC LoopMode and the adapter */
2192 /* has yet to be inserted into the loop, we can't */
2195 if ( (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) &&
2196 !usc_loopmode_active(info
) )
2202 if ( info
->xmit_cnt
) {
2203 /* Send accumulated from send_char() calls */
2204 /* as frame and wait before accepting more data. */
2207 /* copy data from circular xmit_buf to */
2208 /* transmit DMA buffer. */
2209 mgsl_load_tx_dma_buffer(info
,
2210 info
->xmit_buf
,info
->xmit_cnt
);
2211 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2212 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2213 __FILE__
,__LINE__
,info
->device_name
);
2215 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2216 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2217 __FILE__
,__LINE__
,info
->device_name
);
2219 info
->xmit_cnt
= count
;
2220 mgsl_load_tx_dma_buffer(info
,buf
,count
);
2224 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2225 c
= min_t(int, count
,
2226 min(SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1,
2227 SERIAL_XMIT_SIZE
- info
->xmit_head
));
2229 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2232 memcpy(info
->xmit_buf
+ info
->xmit_head
, buf
, c
);
2233 info
->xmit_head
= ((info
->xmit_head
+ c
) &
2234 (SERIAL_XMIT_SIZE
-1));
2235 info
->xmit_cnt
+= c
;
2236 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2243 if (info
->xmit_cnt
&& !tty
->stopped
&& !tty
->hw_stopped
) {
2244 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2245 if (!info
->tx_active
)
2246 usc_start_transmitter(info
);
2247 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2250 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2251 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2252 __FILE__
,__LINE__
,info
->device_name
,ret
);
2256 } /* end of mgsl_write() */
2258 /* mgsl_write_room()
2260 * Return the count of free bytes in transmit buffer
2262 * Arguments: tty pointer to tty info structure
2263 * Return Value: None
2265 static int mgsl_write_room(struct tty_struct
*tty
)
2267 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2270 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_write_room"))
2272 ret
= SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1;
2276 if (debug_level
>= DEBUG_LEVEL_INFO
)
2277 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2278 __FILE__
,__LINE__
, info
->device_name
,ret
);
2280 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2281 info
->params
.mode
== MGSL_MODE_RAW
) {
2282 /* operating in synchronous (frame oriented) mode */
2283 if ( info
->tx_active
)
2286 return HDLC_MAX_FRAME_SIZE
;
2291 } /* end of mgsl_write_room() */
2293 /* mgsl_chars_in_buffer()
2295 * Return the count of bytes in transmit buffer
2297 * Arguments: tty pointer to tty info structure
2298 * Return Value: None
2300 static int mgsl_chars_in_buffer(struct tty_struct
*tty
)
2302 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2304 if (debug_level
>= DEBUG_LEVEL_INFO
)
2305 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2306 __FILE__
,__LINE__
, info
->device_name
);
2308 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_chars_in_buffer"))
2311 if (debug_level
>= DEBUG_LEVEL_INFO
)
2312 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2313 __FILE__
,__LINE__
, info
->device_name
,info
->xmit_cnt
);
2315 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
2316 info
->params
.mode
== MGSL_MODE_RAW
) {
2317 /* operating in synchronous (frame oriented) mode */
2318 if ( info
->tx_active
)
2319 return info
->max_frame_size
;
2324 return info
->xmit_cnt
;
2325 } /* end of mgsl_chars_in_buffer() */
2327 /* mgsl_flush_buffer()
2329 * Discard all data in the send buffer
2331 * Arguments: tty pointer to tty info structure
2332 * Return Value: None
2334 static void mgsl_flush_buffer(struct tty_struct
*tty
)
2336 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2337 unsigned long flags
;
2339 if (debug_level
>= DEBUG_LEVEL_INFO
)
2340 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2341 __FILE__
,__LINE__
, info
->device_name
);
2343 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_flush_buffer"))
2346 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2347 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
2348 del_timer(&info
->tx_timer
);
2349 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2351 wake_up_interruptible(&tty
->write_wait
);
2355 /* mgsl_send_xchar()
2357 * Send a high-priority XON/XOFF character
2359 * Arguments: tty pointer to tty info structure
2360 * ch character to send
2361 * Return Value: None
2363 static void mgsl_send_xchar(struct tty_struct
*tty
, char ch
)
2365 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2366 unsigned long flags
;
2368 if (debug_level
>= DEBUG_LEVEL_INFO
)
2369 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2370 __FILE__
,__LINE__
, info
->device_name
, ch
);
2372 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_send_xchar"))
2377 /* Make sure transmit interrupts are on */
2378 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2379 if (!info
->tx_enabled
)
2380 usc_start_transmitter(info
);
2381 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2383 } /* end of mgsl_send_xchar() */
2387 * Signal remote device to throttle send data (our receive data)
2389 * Arguments: tty pointer to tty info structure
2390 * Return Value: None
2392 static void mgsl_throttle(struct tty_struct
* tty
)
2394 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2395 unsigned long flags
;
2397 if (debug_level
>= DEBUG_LEVEL_INFO
)
2398 printk("%s(%d):mgsl_throttle(%s) entry\n",
2399 __FILE__
,__LINE__
, info
->device_name
);
2401 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_throttle"))
2405 mgsl_send_xchar(tty
, STOP_CHAR(tty
));
2407 if (tty
->termios
->c_cflag
& CRTSCTS
) {
2408 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2409 info
->serial_signals
&= ~SerialSignal_RTS
;
2410 usc_set_serial_signals(info
);
2411 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2413 } /* end of mgsl_throttle() */
2415 /* mgsl_unthrottle()
2417 * Signal remote device to stop throttling send data (our receive data)
2419 * Arguments: tty pointer to tty info structure
2420 * Return Value: None
2422 static void mgsl_unthrottle(struct tty_struct
* tty
)
2424 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2425 unsigned long flags
;
2427 if (debug_level
>= DEBUG_LEVEL_INFO
)
2428 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2429 __FILE__
,__LINE__
, info
->device_name
);
2431 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_unthrottle"))
2438 mgsl_send_xchar(tty
, START_CHAR(tty
));
2441 if (tty
->termios
->c_cflag
& CRTSCTS
) {
2442 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2443 info
->serial_signals
|= SerialSignal_RTS
;
2444 usc_set_serial_signals(info
);
2445 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2448 } /* end of mgsl_unthrottle() */
2452 * get the current serial parameters information
2454 * Arguments: info pointer to device instance data
2455 * user_icount pointer to buffer to hold returned stats
2457 * Return Value: 0 if success, otherwise error code
2459 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount __user
*user_icount
)
2463 if (debug_level
>= DEBUG_LEVEL_INFO
)
2464 printk("%s(%d):mgsl_get_params(%s)\n",
2465 __FILE__
,__LINE__
, info
->device_name
);
2468 memset(&info
->icount
, 0, sizeof(info
->icount
));
2470 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2477 } /* end of mgsl_get_stats() */
2479 /* mgsl_get_params()
2481 * get the current serial parameters information
2483 * Arguments: info pointer to device instance data
2484 * user_params pointer to buffer to hold returned params
2486 * Return Value: 0 if success, otherwise error code
2488 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*user_params
)
2491 if (debug_level
>= DEBUG_LEVEL_INFO
)
2492 printk("%s(%d):mgsl_get_params(%s)\n",
2493 __FILE__
,__LINE__
, info
->device_name
);
2495 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2497 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2498 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2499 __FILE__
,__LINE__
,info
->device_name
);
2505 } /* end of mgsl_get_params() */
2507 /* mgsl_set_params()
2509 * set the serial parameters
2513 * info pointer to device instance data
2514 * new_params user buffer containing new serial params
2516 * Return Value: 0 if success, otherwise error code
2518 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS __user
*new_params
)
2520 unsigned long flags
;
2521 MGSL_PARAMS tmp_params
;
2524 if (debug_level
>= DEBUG_LEVEL_INFO
)
2525 printk("%s(%d):mgsl_set_params %s\n", __FILE__
,__LINE__
,
2526 info
->device_name
);
2527 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2529 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2530 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2531 __FILE__
,__LINE__
,info
->device_name
);
2535 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2536 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2537 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2539 mgsl_change_params(info
);
2543 } /* end of mgsl_set_params() */
2545 /* mgsl_get_txidle()
2547 * get the current transmit idle mode
2549 * Arguments: info pointer to device instance data
2550 * idle_mode pointer to buffer to hold returned idle mode
2552 * Return Value: 0 if success, otherwise error code
2554 static int mgsl_get_txidle(struct mgsl_struct
* info
, int __user
*idle_mode
)
2558 if (debug_level
>= DEBUG_LEVEL_INFO
)
2559 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2560 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
2562 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
2564 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2565 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2566 __FILE__
,__LINE__
,info
->device_name
);
2572 } /* end of mgsl_get_txidle() */
2574 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2576 * Arguments: info pointer to device instance data
2577 * idle_mode new idle mode
2579 * Return Value: 0 if success, otherwise error code
2581 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
)
2583 unsigned long flags
;
2585 if (debug_level
>= DEBUG_LEVEL_INFO
)
2586 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__
,__LINE__
,
2587 info
->device_name
, idle_mode
);
2589 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2590 info
->idle_mode
= idle_mode
;
2591 usc_set_txidle( info
);
2592 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2595 } /* end of mgsl_set_txidle() */
2599 * enable or disable the transmitter
2603 * info pointer to device instance data
2604 * enable 1 = enable, 0 = disable
2606 * Return Value: 0 if success, otherwise error code
2608 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
)
2610 unsigned long flags
;
2612 if (debug_level
>= DEBUG_LEVEL_INFO
)
2613 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__
,__LINE__
,
2614 info
->device_name
, enable
);
2616 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2618 if ( !info
->tx_enabled
) {
2620 usc_start_transmitter(info
);
2621 /*--------------------------------------------------
2622 * if HDLC/SDLC Loop mode, attempt to insert the
2623 * station in the 'loop' by setting CMR:13. Upon
2624 * receipt of the next GoAhead (RxAbort) sequence,
2625 * the OnLoop indicator (CCSR:7) should go active
2626 * to indicate that we are on the loop
2627 *--------------------------------------------------*/
2628 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2629 usc_loopmode_insert_request( info
);
2632 if ( info
->tx_enabled
)
2633 usc_stop_transmitter(info
);
2635 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2638 } /* end of mgsl_txenable() */
2640 /* mgsl_txabort() abort send HDLC frame
2642 * Arguments: info pointer to device instance data
2643 * Return Value: 0 if success, otherwise error code
2645 static int mgsl_txabort(struct mgsl_struct
* info
)
2647 unsigned long flags
;
2649 if (debug_level
>= DEBUG_LEVEL_INFO
)
2650 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__
,__LINE__
,
2653 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2654 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
)
2656 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2657 usc_loopmode_cancel_transmit( info
);
2659 usc_TCmd(info
,TCmd_SendAbort
);
2661 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2664 } /* end of mgsl_txabort() */
2666 /* mgsl_rxenable() enable or disable the receiver
2668 * Arguments: info pointer to device instance data
2669 * enable 1 = enable, 0 = disable
2670 * Return Value: 0 if success, otherwise error code
2672 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
)
2674 unsigned long flags
;
2676 if (debug_level
>= DEBUG_LEVEL_INFO
)
2677 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__
,__LINE__
,
2678 info
->device_name
, enable
);
2680 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2682 if ( !info
->rx_enabled
)
2683 usc_start_receiver(info
);
2685 if ( info
->rx_enabled
)
2686 usc_stop_receiver(info
);
2688 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2691 } /* end of mgsl_rxenable() */
2693 /* mgsl_wait_event() wait for specified event to occur
2695 * Arguments: info pointer to device instance data
2696 * mask pointer to bitmask of events to wait for
2697 * Return Value: 0 if successful and bit mask updated with
2698 * of events triggerred,
2699 * otherwise error code
2701 static int mgsl_wait_event(struct mgsl_struct
* info
, int __user
* mask_ptr
)
2703 unsigned long flags
;
2706 struct mgsl_icount cprev
, cnow
;
2709 struct _input_signal_events oldsigs
, newsigs
;
2710 DECLARE_WAITQUEUE(wait
, current
);
2712 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
2717 if (debug_level
>= DEBUG_LEVEL_INFO
)
2718 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__
,__LINE__
,
2719 info
->device_name
, mask
);
2721 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2723 /* return immediately if state matches requested events */
2724 usc_get_serial_signals(info
);
2725 s
= info
->serial_signals
;
2727 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
2728 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
2729 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
2730 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
2732 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2736 /* save current irq counts */
2737 cprev
= info
->icount
;
2738 oldsigs
= info
->input_signal_events
;
2740 /* enable hunt and idle irqs if needed */
2741 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2742 u16 oldreg
= usc_InReg(info
,RICR
);
2743 u16 newreg
= oldreg
+
2744 (mask
& MgslEvent_ExitHuntMode
? RXSTATUS_EXITED_HUNT
:0) +
2745 (mask
& MgslEvent_IdleReceived
? RXSTATUS_IDLE_RECEIVED
:0);
2746 if (oldreg
!= newreg
)
2747 usc_OutReg(info
, RICR
, newreg
);
2750 set_current_state(TASK_INTERRUPTIBLE
);
2751 add_wait_queue(&info
->event_wait_q
, &wait
);
2753 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2758 if (signal_pending(current
)) {
2763 /* get current irq counts */
2764 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2765 cnow
= info
->icount
;
2766 newsigs
= info
->input_signal_events
;
2767 set_current_state(TASK_INTERRUPTIBLE
);
2768 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2770 /* if no change, wait aborted for some reason */
2771 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
2772 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
2773 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
2774 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
2775 newsigs
.cts_up
== oldsigs
.cts_up
&&
2776 newsigs
.cts_down
== oldsigs
.cts_down
&&
2777 newsigs
.ri_up
== oldsigs
.ri_up
&&
2778 newsigs
.ri_down
== oldsigs
.ri_down
&&
2779 cnow
.exithunt
== cprev
.exithunt
&&
2780 cnow
.rxidle
== cprev
.rxidle
) {
2786 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
2787 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
2788 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
2789 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
2790 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
2791 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
2792 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
2793 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
2794 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
2795 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
2803 remove_wait_queue(&info
->event_wait_q
, &wait
);
2804 set_current_state(TASK_RUNNING
);
2806 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2807 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2808 if (!waitqueue_active(&info
->event_wait_q
)) {
2809 /* disable enable exit hunt mode/idle rcvd IRQs */
2810 usc_OutReg(info
, RICR
, usc_InReg(info
,RICR
) &
2811 ~(RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
));
2813 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2817 PUT_USER(rc
, events
, mask_ptr
);
2821 } /* end of mgsl_wait_event() */
2823 static int modem_input_wait(struct mgsl_struct
*info
,int arg
)
2825 unsigned long flags
;
2827 struct mgsl_icount cprev
, cnow
;
2828 DECLARE_WAITQUEUE(wait
, current
);
2830 /* save current irq counts */
2831 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2832 cprev
= info
->icount
;
2833 add_wait_queue(&info
->status_event_wait_q
, &wait
);
2834 set_current_state(TASK_INTERRUPTIBLE
);
2835 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2839 if (signal_pending(current
)) {
2844 /* get new irq counts */
2845 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2846 cnow
= info
->icount
;
2847 set_current_state(TASK_INTERRUPTIBLE
);
2848 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2850 /* if no change, wait aborted for some reason */
2851 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
2852 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
2857 /* check for change in caller specified modem input */
2858 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
2859 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
2860 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
2861 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
2868 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
2869 set_current_state(TASK_RUNNING
);
2873 /* return the state of the serial control and status signals
2875 static int tiocmget(struct tty_struct
*tty
, struct file
*file
)
2877 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2878 unsigned int result
;
2879 unsigned long flags
;
2881 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2882 usc_get_serial_signals(info
);
2883 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2885 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
2886 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
2887 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
2888 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
2889 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
2890 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
2892 if (debug_level
>= DEBUG_LEVEL_INFO
)
2893 printk("%s(%d):%s tiocmget() value=%08X\n",
2894 __FILE__
,__LINE__
, info
->device_name
, result
);
2898 /* set modem control signals (DTR/RTS)
2900 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
2901 unsigned int set
, unsigned int clear
)
2903 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2904 unsigned long flags
;
2906 if (debug_level
>= DEBUG_LEVEL_INFO
)
2907 printk("%s(%d):%s tiocmset(%x,%x)\n",
2908 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
2910 if (set
& TIOCM_RTS
)
2911 info
->serial_signals
|= SerialSignal_RTS
;
2912 if (set
& TIOCM_DTR
)
2913 info
->serial_signals
|= SerialSignal_DTR
;
2914 if (clear
& TIOCM_RTS
)
2915 info
->serial_signals
&= ~SerialSignal_RTS
;
2916 if (clear
& TIOCM_DTR
)
2917 info
->serial_signals
&= ~SerialSignal_DTR
;
2919 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2920 usc_set_serial_signals(info
);
2921 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2926 /* mgsl_break() Set or clear transmit break condition
2928 * Arguments: tty pointer to tty instance data
2929 * break_state -1=set break condition, 0=clear
2930 * Return Value: None
2932 static void mgsl_break(struct tty_struct
*tty
, int break_state
)
2934 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
2935 unsigned long flags
;
2937 if (debug_level
>= DEBUG_LEVEL_INFO
)
2938 printk("%s(%d):mgsl_break(%s,%d)\n",
2939 __FILE__
,__LINE__
, info
->device_name
, break_state
);
2941 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_break"))
2944 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2945 if (break_state
== -1)
2946 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) | BIT7
));
2948 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) & ~BIT7
));
2949 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2951 } /* end of mgsl_break() */
2953 /* mgsl_ioctl() Service an IOCTL request
2957 * tty pointer to tty instance data
2958 * file pointer to associated file object for device
2959 * cmd IOCTL command code
2960 * arg command argument/context
2962 * Return Value: 0 if success, otherwise error code
2964 static int mgsl_ioctl(struct tty_struct
*tty
, struct file
* file
,
2965 unsigned int cmd
, unsigned long arg
)
2967 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
2969 if (debug_level
>= DEBUG_LEVEL_INFO
)
2970 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__
,__LINE__
,
2971 info
->device_name
, cmd
);
2973 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_ioctl"))
2976 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
2977 (cmd
!= TIOCMIWAIT
) && (cmd
!= TIOCGICOUNT
)) {
2978 if (tty
->flags
& (1 << TTY_IO_ERROR
))
2982 return mgsl_ioctl_common(info
, cmd
, arg
);
2985 static int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
)
2988 struct mgsl_icount cnow
; /* kernel counter temps */
2989 void __user
*argp
= (void __user
*)arg
;
2990 struct serial_icounter_struct __user
*p_cuser
; /* user space */
2991 unsigned long flags
;
2994 case MGSL_IOCGPARAMS
:
2995 return mgsl_get_params(info
, argp
);
2996 case MGSL_IOCSPARAMS
:
2997 return mgsl_set_params(info
, argp
);
2998 case MGSL_IOCGTXIDLE
:
2999 return mgsl_get_txidle(info
, argp
);
3000 case MGSL_IOCSTXIDLE
:
3001 return mgsl_set_txidle(info
,(int)arg
);
3002 case MGSL_IOCTXENABLE
:
3003 return mgsl_txenable(info
,(int)arg
);
3004 case MGSL_IOCRXENABLE
:
3005 return mgsl_rxenable(info
,(int)arg
);
3006 case MGSL_IOCTXABORT
:
3007 return mgsl_txabort(info
);
3008 case MGSL_IOCGSTATS
:
3009 return mgsl_get_stats(info
, argp
);
3010 case MGSL_IOCWAITEVENT
:
3011 return mgsl_wait_event(info
, argp
);
3012 case MGSL_IOCLOOPTXDONE
:
3013 return mgsl_loopmode_send_done(info
);
3014 /* Wait for modem input (DCD,RI,DSR,CTS) change
3015 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3018 return modem_input_wait(info
,(int)arg
);
3021 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
3022 * Return: write counters to the user passed counter struct
3023 * NB: both 1->0 and 0->1 transitions are counted except for
3024 * RI where only 0->1 is counted.
3027 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3028 cnow
= info
->icount
;
3029 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3031 PUT_USER(error
,cnow
.cts
, &p_cuser
->cts
);
3032 if (error
) return error
;
3033 PUT_USER(error
,cnow
.dsr
, &p_cuser
->dsr
);
3034 if (error
) return error
;
3035 PUT_USER(error
,cnow
.rng
, &p_cuser
->rng
);
3036 if (error
) return error
;
3037 PUT_USER(error
,cnow
.dcd
, &p_cuser
->dcd
);
3038 if (error
) return error
;
3039 PUT_USER(error
,cnow
.rx
, &p_cuser
->rx
);
3040 if (error
) return error
;
3041 PUT_USER(error
,cnow
.tx
, &p_cuser
->tx
);
3042 if (error
) return error
;
3043 PUT_USER(error
,cnow
.frame
, &p_cuser
->frame
);
3044 if (error
) return error
;
3045 PUT_USER(error
,cnow
.overrun
, &p_cuser
->overrun
);
3046 if (error
) return error
;
3047 PUT_USER(error
,cnow
.parity
, &p_cuser
->parity
);
3048 if (error
) return error
;
3049 PUT_USER(error
,cnow
.brk
, &p_cuser
->brk
);
3050 if (error
) return error
;
3051 PUT_USER(error
,cnow
.buf_overrun
, &p_cuser
->buf_overrun
);
3052 if (error
) return error
;
3055 return -ENOIOCTLCMD
;
3060 /* mgsl_set_termios()
3062 * Set new termios settings
3066 * tty pointer to tty structure
3067 * termios pointer to buffer to hold returned old termios
3069 * Return Value: None
3071 static void mgsl_set_termios(struct tty_struct
*tty
, struct termios
*old_termios
)
3073 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
3074 unsigned long flags
;
3076 if (debug_level
>= DEBUG_LEVEL_INFO
)
3077 printk("%s(%d):mgsl_set_termios %s\n", __FILE__
,__LINE__
,
3078 tty
->driver
->name
);
3080 /* just return if nothing has changed */
3081 if ((tty
->termios
->c_cflag
== old_termios
->c_cflag
)
3082 && (RELEVANT_IFLAG(tty
->termios
->c_iflag
)
3083 == RELEVANT_IFLAG(old_termios
->c_iflag
)))
3086 mgsl_change_params(info
);
3088 /* Handle transition to B0 status */
3089 if (old_termios
->c_cflag
& CBAUD
&&
3090 !(tty
->termios
->c_cflag
& CBAUD
)) {
3091 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
3092 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3093 usc_set_serial_signals(info
);
3094 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3097 /* Handle transition away from B0 status */
3098 if (!(old_termios
->c_cflag
& CBAUD
) &&
3099 tty
->termios
->c_cflag
& CBAUD
) {
3100 info
->serial_signals
|= SerialSignal_DTR
;
3101 if (!(tty
->termios
->c_cflag
& CRTSCTS
) ||
3102 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
3103 info
->serial_signals
|= SerialSignal_RTS
;
3105 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3106 usc_set_serial_signals(info
);
3107 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3110 /* Handle turning off CRTSCTS */
3111 if (old_termios
->c_cflag
& CRTSCTS
&&
3112 !(tty
->termios
->c_cflag
& CRTSCTS
)) {
3113 tty
->hw_stopped
= 0;
3117 } /* end of mgsl_set_termios() */
3121 * Called when port is closed. Wait for remaining data to be
3122 * sent. Disable port and free resources.
3126 * tty pointer to open tty structure
3127 * filp pointer to open file object
3129 * Return Value: None
3131 static void mgsl_close(struct tty_struct
*tty
, struct file
* filp
)
3133 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3135 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_close"))
3138 if (debug_level
>= DEBUG_LEVEL_INFO
)
3139 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3140 __FILE__
,__LINE__
, info
->device_name
, info
->count
);
3145 if (tty_hung_up_p(filp
))
3148 if ((tty
->count
== 1) && (info
->count
!= 1)) {
3150 * tty->count is 1 and the tty structure will be freed.
3151 * info->count should be one in this case.
3152 * if it's not, correct it so that the port is shutdown.
3154 printk("mgsl_close: bad refcount; tty->count is 1, "
3155 "info->count is %d\n", info
->count
);
3161 /* if at least one open remaining, leave hardware active */
3165 info
->flags
|= ASYNC_CLOSING
;
3167 /* set tty->closing to notify line discipline to
3168 * only process XON/XOFF characters. Only the N_TTY
3169 * discipline appears to use this (ppp does not).
3173 /* wait for transmit data to clear all layers */
3175 if (info
->closing_wait
!= ASYNC_CLOSING_WAIT_NONE
) {
3176 if (debug_level
>= DEBUG_LEVEL_INFO
)
3177 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3178 __FILE__
,__LINE__
, info
->device_name
);
3179 tty_wait_until_sent(tty
, info
->closing_wait
);
3182 if (info
->flags
& ASYNC_INITIALIZED
)
3183 mgsl_wait_until_sent(tty
, info
->timeout
);
3185 if (tty
->driver
->flush_buffer
)
3186 tty
->driver
->flush_buffer(tty
);
3188 tty_ldisc_flush(tty
);
3195 if (info
->blocked_open
) {
3196 if (info
->close_delay
) {
3197 msleep_interruptible(jiffies_to_msecs(info
->close_delay
));
3199 wake_up_interruptible(&info
->open_wait
);
3202 info
->flags
&= ~(ASYNC_NORMAL_ACTIVE
|ASYNC_CLOSING
);
3204 wake_up_interruptible(&info
->close_wait
);
3207 if (debug_level
>= DEBUG_LEVEL_INFO
)
3208 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__
,__LINE__
,
3209 tty
->driver
->name
, info
->count
);
3211 } /* end of mgsl_close() */
3213 /* mgsl_wait_until_sent()
3215 * Wait until the transmitter is empty.
3219 * tty pointer to tty info structure
3220 * timeout time to wait for send completion
3222 * Return Value: None
3224 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
)
3226 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3227 unsigned long orig_jiffies
, char_time
;
3232 if (debug_level
>= DEBUG_LEVEL_INFO
)
3233 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3234 __FILE__
,__LINE__
, info
->device_name
);
3236 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_wait_until_sent"))
3239 if (!(info
->flags
& ASYNC_INITIALIZED
))
3242 orig_jiffies
= jiffies
;
3244 /* Set check interval to 1/5 of estimated time to
3245 * send a character, and make it at least 1. The check
3246 * interval should also be less than the timeout.
3247 * Note: use tight timings here to satisfy the NIST-PCTS.
3250 if ( info
->params
.data_rate
) {
3251 char_time
= info
->timeout
/(32 * 5);
3258 char_time
= min_t(unsigned long, char_time
, timeout
);
3260 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
3261 info
->params
.mode
== MGSL_MODE_RAW
) {
3262 while (info
->tx_active
) {
3263 msleep_interruptible(jiffies_to_msecs(char_time
));
3264 if (signal_pending(current
))
3266 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3270 while (!(usc_InReg(info
,TCSR
) & TXSTATUS_ALL_SENT
) &&
3272 msleep_interruptible(jiffies_to_msecs(char_time
));
3273 if (signal_pending(current
))
3275 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
3281 if (debug_level
>= DEBUG_LEVEL_INFO
)
3282 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3283 __FILE__
,__LINE__
, info
->device_name
);
3285 } /* end of mgsl_wait_until_sent() */
3289 * Called by tty_hangup() when a hangup is signaled.
3290 * This is the same as to closing all open files for the port.
3292 * Arguments: tty pointer to associated tty object
3293 * Return Value: None
3295 static void mgsl_hangup(struct tty_struct
*tty
)
3297 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3299 if (debug_level
>= DEBUG_LEVEL_INFO
)
3300 printk("%s(%d):mgsl_hangup(%s)\n",
3301 __FILE__
,__LINE__
, info
->device_name
);
3303 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_hangup"))
3306 mgsl_flush_buffer(tty
);
3310 info
->flags
&= ~ASYNC_NORMAL_ACTIVE
;
3313 wake_up_interruptible(&info
->open_wait
);
3315 } /* end of mgsl_hangup() */
3317 /* block_til_ready()
3319 * Block the current process until the specified port
3320 * is ready to be opened.
3324 * tty pointer to tty info structure
3325 * filp pointer to open file object
3326 * info pointer to device instance data
3328 * Return Value: 0 if success, otherwise error code
3330 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,
3331 struct mgsl_struct
*info
)
3333 DECLARE_WAITQUEUE(wait
, current
);
3335 int do_clocal
= 0, extra_count
= 0;
3336 unsigned long flags
;
3338 if (debug_level
>= DEBUG_LEVEL_INFO
)
3339 printk("%s(%d):block_til_ready on %s\n",
3340 __FILE__
,__LINE__
, tty
->driver
->name
);
3342 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3343 /* nonblock mode is set or port is not enabled */
3344 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3348 if (tty
->termios
->c_cflag
& CLOCAL
)
3351 /* Wait for carrier detect and the line to become
3352 * free (i.e., not in use by the callout). While we are in
3353 * this loop, info->count is dropped by one, so that
3354 * mgsl_close() knows when to free things. We restore it upon
3355 * exit, either normal or abnormal.
3359 add_wait_queue(&info
->open_wait
, &wait
);
3361 if (debug_level
>= DEBUG_LEVEL_INFO
)
3362 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3363 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3365 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
3366 if (!tty_hung_up_p(filp
)) {
3370 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
3371 info
->blocked_open
++;
3374 if (tty
->termios
->c_cflag
& CBAUD
) {
3375 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3376 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3377 usc_set_serial_signals(info
);
3378 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3381 set_current_state(TASK_INTERRUPTIBLE
);
3383 if (tty_hung_up_p(filp
) || !(info
->flags
& ASYNC_INITIALIZED
)){
3384 retval
= (info
->flags
& ASYNC_HUP_NOTIFY
) ?
3385 -EAGAIN
: -ERESTARTSYS
;
3389 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3390 usc_get_serial_signals(info
);
3391 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3393 if (!(info
->flags
& ASYNC_CLOSING
) &&
3394 (do_clocal
|| (info
->serial_signals
& SerialSignal_DCD
)) ) {
3398 if (signal_pending(current
)) {
3399 retval
= -ERESTARTSYS
;
3403 if (debug_level
>= DEBUG_LEVEL_INFO
)
3404 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3405 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3410 set_current_state(TASK_RUNNING
);
3411 remove_wait_queue(&info
->open_wait
, &wait
);
3415 info
->blocked_open
--;
3417 if (debug_level
>= DEBUG_LEVEL_INFO
)
3418 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3419 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3422 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3426 } /* end of block_til_ready() */
3430 * Called when a port is opened. Init and enable port.
3431 * Perform serial-specific initialization for the tty structure.
3433 * Arguments: tty pointer to tty info structure
3434 * filp associated file pointer
3436 * Return Value: 0 if success, otherwise error code
3438 static int mgsl_open(struct tty_struct
*tty
, struct file
* filp
)
3440 struct mgsl_struct
*info
;
3443 unsigned long flags
;
3445 /* verify range of specified line number */
3447 if ((line
< 0) || (line
>= mgsl_device_count
)) {
3448 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3449 __FILE__
,__LINE__
,line
);
3453 /* find the info structure for the specified line */
3454 info
= mgsl_device_list
;
3455 while(info
&& info
->line
!= line
)
3456 info
= info
->next_device
;
3457 if (mgsl_paranoia_check(info
, tty
->name
, "mgsl_open"))
3460 tty
->driver_data
= info
;
3463 if (debug_level
>= DEBUG_LEVEL_INFO
)
3464 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3465 __FILE__
,__LINE__
,tty
->driver
->name
, info
->count
);
3467 /* If port is closing, signal caller to try again */
3468 if (tty_hung_up_p(filp
) || info
->flags
& ASYNC_CLOSING
){
3469 if (info
->flags
& ASYNC_CLOSING
)
3470 interruptible_sleep_on(&info
->close_wait
);
3471 retval
= ((info
->flags
& ASYNC_HUP_NOTIFY
) ?
3472 -EAGAIN
: -ERESTARTSYS
);
3477 page
= get_zeroed_page(GFP_KERNEL
);
3485 tmp_buf
= (unsigned char *) page
;
3488 info
->tty
->low_latency
= (info
->flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
3490 spin_lock_irqsave(&info
->netlock
, flags
);
3491 if (info
->netcount
) {
3493 spin_unlock_irqrestore(&info
->netlock
, flags
);
3497 spin_unlock_irqrestore(&info
->netlock
, flags
);
3499 if (info
->count
== 1) {
3500 /* 1st open on this device, init hardware */
3501 retval
= startup(info
);
3506 retval
= block_til_ready(tty
, filp
, info
);
3508 if (debug_level
>= DEBUG_LEVEL_INFO
)
3509 printk("%s(%d):block_til_ready(%s) returned %d\n",
3510 __FILE__
,__LINE__
, info
->device_name
, retval
);
3514 if (debug_level
>= DEBUG_LEVEL_INFO
)
3515 printk("%s(%d):mgsl_open(%s) success\n",
3516 __FILE__
,__LINE__
, info
->device_name
);
3521 if (tty
->count
== 1)
3522 info
->tty
= NULL
; /* tty layer will release tty struct */
3529 } /* end of mgsl_open() */
3532 * /proc fs routines....
3535 static inline int line_info(char *buf
, struct mgsl_struct
*info
)
3539 unsigned long flags
;
3541 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3542 ret
= sprintf(buf
, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3543 info
->device_name
, info
->io_base
, info
->irq_level
,
3544 info
->phys_memory_base
, info
->phys_lcr_base
);
3546 ret
= sprintf(buf
, "%s:(E)ISA io:%04X irq:%d dma:%d",
3547 info
->device_name
, info
->io_base
,
3548 info
->irq_level
, info
->dma_level
);
3551 /* output current serial signal states */
3552 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3553 usc_get_serial_signals(info
);
3554 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3558 if (info
->serial_signals
& SerialSignal_RTS
)
3559 strcat(stat_buf
, "|RTS");
3560 if (info
->serial_signals
& SerialSignal_CTS
)
3561 strcat(stat_buf
, "|CTS");
3562 if (info
->serial_signals
& SerialSignal_DTR
)
3563 strcat(stat_buf
, "|DTR");
3564 if (info
->serial_signals
& SerialSignal_DSR
)
3565 strcat(stat_buf
, "|DSR");
3566 if (info
->serial_signals
& SerialSignal_DCD
)
3567 strcat(stat_buf
, "|CD");
3568 if (info
->serial_signals
& SerialSignal_RI
)
3569 strcat(stat_buf
, "|RI");
3571 if (info
->params
.mode
== MGSL_MODE_HDLC
||
3572 info
->params
.mode
== MGSL_MODE_RAW
) {
3573 ret
+= sprintf(buf
+ret
, " HDLC txok:%d rxok:%d",
3574 info
->icount
.txok
, info
->icount
.rxok
);
3575 if (info
->icount
.txunder
)
3576 ret
+= sprintf(buf
+ret
, " txunder:%d", info
->icount
.txunder
);
3577 if (info
->icount
.txabort
)
3578 ret
+= sprintf(buf
+ret
, " txabort:%d", info
->icount
.txabort
);
3579 if (info
->icount
.rxshort
)
3580 ret
+= sprintf(buf
+ret
, " rxshort:%d", info
->icount
.rxshort
);
3581 if (info
->icount
.rxlong
)
3582 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxlong
);
3583 if (info
->icount
.rxover
)
3584 ret
+= sprintf(buf
+ret
, " rxover:%d", info
->icount
.rxover
);
3585 if (info
->icount
.rxcrc
)
3586 ret
+= sprintf(buf
+ret
, " rxcrc:%d", info
->icount
.rxcrc
);
3588 ret
+= sprintf(buf
+ret
, " ASYNC tx:%d rx:%d",
3589 info
->icount
.tx
, info
->icount
.rx
);
3590 if (info
->icount
.frame
)
3591 ret
+= sprintf(buf
+ret
, " fe:%d", info
->icount
.frame
);
3592 if (info
->icount
.parity
)
3593 ret
+= sprintf(buf
+ret
, " pe:%d", info
->icount
.parity
);
3594 if (info
->icount
.brk
)
3595 ret
+= sprintf(buf
+ret
, " brk:%d", info
->icount
.brk
);
3596 if (info
->icount
.overrun
)
3597 ret
+= sprintf(buf
+ret
, " oe:%d", info
->icount
.overrun
);
3600 /* Append serial signal status to end */
3601 ret
+= sprintf(buf
+ret
, " %s\n", stat_buf
+1);
3603 ret
+= sprintf(buf
+ret
, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3604 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
3607 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3609 u16 Tcsr
= usc_InReg( info
, TCSR
);
3610 u16 Tdmr
= usc_InDmaReg( info
, TDMR
);
3611 u16 Ticr
= usc_InReg( info
, TICR
);
3612 u16 Rscr
= usc_InReg( info
, RCSR
);
3613 u16 Rdmr
= usc_InDmaReg( info
, RDMR
);
3614 u16 Ricr
= usc_InReg( info
, RICR
);
3615 u16 Icr
= usc_InReg( info
, ICR
);
3616 u16 Dccr
= usc_InReg( info
, DCCR
);
3617 u16 Tmr
= usc_InReg( info
, TMR
);
3618 u16 Tccr
= usc_InReg( info
, TCCR
);
3619 u16 Ccar
= inw( info
->io_base
+ CCAR
);
3620 ret
+= sprintf(buf
+ret
, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3621 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3622 Tcsr
,Tdmr
,Ticr
,Rscr
,Rdmr
,Ricr
,Icr
,Dccr
,Tmr
,Tccr
,Ccar
);
3624 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3628 } /* end of line_info() */
3632 * Called to print information about devices
3635 * page page of memory to hold returned info
3644 static int mgsl_read_proc(char *page
, char **start
, off_t off
, int count
,
3645 int *eof
, void *data
)
3649 struct mgsl_struct
*info
;
3651 len
+= sprintf(page
, "synclink driver:%s\n", driver_version
);
3653 info
= mgsl_device_list
;
3655 l
= line_info(page
+ len
, info
);
3657 if (len
+begin
> off
+count
)
3659 if (len
+begin
< off
) {
3663 info
= info
->next_device
;
3668 if (off
>= len
+begin
)
3670 *start
= page
+ (off
-begin
);
3671 return ((count
< begin
+len
-off
) ? count
: begin
+len
-off
);
3673 } /* end of mgsl_read_proc() */
3675 /* mgsl_allocate_dma_buffers()
3677 * Allocate and format DMA buffers (ISA adapter)
3678 * or format shared memory buffers (PCI adapter).
3680 * Arguments: info pointer to device instance data
3681 * Return Value: 0 if success, otherwise error
3683 static int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
)
3685 unsigned short BuffersPerFrame
;
3687 info
->last_mem_alloc
= 0;
3689 /* Calculate the number of DMA buffers necessary to hold the */
3690 /* largest allowable frame size. Note: If the max frame size is */
3691 /* not an even multiple of the DMA buffer size then we need to */
3692 /* round the buffer count per frame up one. */
3694 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/DMABUFFERSIZE
);
3695 if ( info
->max_frame_size
% DMABUFFERSIZE
)
3698 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3700 * The PCI adapter has 256KBytes of shared memory to use.
3701 * This is 64 PAGE_SIZE buffers.
3703 * The first page is used for padding at this time so the
3704 * buffer list does not begin at offset 0 of the PCI
3705 * adapter's shared memory.
3707 * The 2nd page is used for the buffer list. A 4K buffer
3708 * list can hold 128 DMA_BUFFER structures at 32 bytes
3711 * This leaves 62 4K pages.
3713 * The next N pages are used for transmit frame(s). We
3714 * reserve enough 4K page blocks to hold the required
3715 * number of transmit dma buffers (num_tx_dma_buffers),
3716 * each of MaxFrameSize size.
3718 * Of the remaining pages (62-N), determine how many can
3719 * be used to receive full MaxFrameSize inbound frames
3721 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3722 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3724 /* Calculate the number of PAGE_SIZE buffers needed for */
3725 /* receive and transmit DMA buffers. */
3728 /* Calculate the number of DMA buffers necessary to */
3729 /* hold 7 max size receive frames and one max size transmit frame. */
3730 /* The receive buffer count is bumped by one so we avoid an */
3731 /* End of List condition if all receive buffers are used when */
3732 /* using linked list DMA buffers. */
3734 info
->tx_buffer_count
= info
->num_tx_dma_buffers
* BuffersPerFrame
;
3735 info
->rx_buffer_count
= (BuffersPerFrame
* MAXRXFRAMES
) + 6;
3738 * limit total TxBuffers & RxBuffers to 62 4K total
3739 * (ala PCI Allocation)
3742 if ( (info
->tx_buffer_count
+ info
->rx_buffer_count
) > 62 )
3743 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3747 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3748 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3749 __FILE__
,__LINE__
, info
->tx_buffer_count
,info
->rx_buffer_count
);
3751 if ( mgsl_alloc_buffer_list_memory( info
) < 0 ||
3752 mgsl_alloc_frame_memory(info
, info
->rx_buffer_list
, info
->rx_buffer_count
) < 0 ||
3753 mgsl_alloc_frame_memory(info
, info
->tx_buffer_list
, info
->tx_buffer_count
) < 0 ||
3754 mgsl_alloc_intermediate_rxbuffer_memory(info
) < 0 ||
3755 mgsl_alloc_intermediate_txbuffer_memory(info
) < 0 ) {
3756 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__
,__LINE__
);
3760 mgsl_reset_rx_dma_buffers( info
);
3761 mgsl_reset_tx_dma_buffers( info
);
3765 } /* end of mgsl_allocate_dma_buffers() */
3768 * mgsl_alloc_buffer_list_memory()
3770 * Allocate a common DMA buffer for use as the
3771 * receive and transmit buffer lists.
3773 * A buffer list is a set of buffer entries where each entry contains
3774 * a pointer to an actual buffer and a pointer to the next buffer entry
3775 * (plus some other info about the buffer).
3777 * The buffer entries for a list are built to form a circular list so
3778 * that when the entire list has been traversed you start back at the
3781 * This function allocates memory for just the buffer entries.
3782 * The links (pointer to next entry) are filled in with the physical
3783 * address of the next entry so the adapter can navigate the list
3784 * using bus master DMA. The pointers to the actual buffers are filled
3785 * out later when the actual buffers are allocated.
3787 * Arguments: info pointer to device instance data
3788 * Return Value: 0 if success, otherwise error
3790 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct
*info
)
3794 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3795 /* PCI adapter uses shared memory. */
3796 info
->buffer_list
= info
->memory_base
+ info
->last_mem_alloc
;
3797 info
->buffer_list_phys
= info
->last_mem_alloc
;
3798 info
->last_mem_alloc
+= BUFFERLISTSIZE
;
3800 /* ISA adapter uses system memory. */
3801 /* The buffer lists are allocated as a common buffer that both */
3802 /* the processor and adapter can access. This allows the driver to */
3803 /* inspect portions of the buffer while other portions are being */
3804 /* updated by the adapter using Bus Master DMA. */
3806 info
->buffer_list
= dma_alloc_coherent(NULL
, BUFFERLISTSIZE
, &info
->buffer_list_dma_addr
, GFP_KERNEL
);
3807 if (info
->buffer_list
== NULL
)
3809 info
->buffer_list_phys
= (u32
)(info
->buffer_list_dma_addr
);
3812 /* We got the memory for the buffer entry lists. */
3813 /* Initialize the memory block to all zeros. */
3814 memset( info
->buffer_list
, 0, BUFFERLISTSIZE
);
3816 /* Save virtual address pointers to the receive and */
3817 /* transmit buffer lists. (Receive 1st). These pointers will */
3818 /* be used by the processor to access the lists. */
3819 info
->rx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3820 info
->tx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3821 info
->tx_buffer_list
+= info
->rx_buffer_count
;
3824 * Build the links for the buffer entry lists such that
3825 * two circular lists are built. (Transmit and Receive).
3827 * Note: the links are physical addresses
3828 * which are read by the adapter to determine the next
3829 * buffer entry to use.
3832 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
3833 /* calculate and store physical address of this buffer entry */
3834 info
->rx_buffer_list
[i
].phys_entry
=
3835 info
->buffer_list_phys
+ (i
* sizeof(DMABUFFERENTRY
));
3837 /* calculate and store physical address of */
3838 /* next entry in cirular list of entries */
3840 info
->rx_buffer_list
[i
].link
= info
->buffer_list_phys
;
3842 if ( i
< info
->rx_buffer_count
- 1 )
3843 info
->rx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3846 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
3847 /* calculate and store physical address of this buffer entry */
3848 info
->tx_buffer_list
[i
].phys_entry
= info
->buffer_list_phys
+
3849 ((info
->rx_buffer_count
+ i
) * sizeof(DMABUFFERENTRY
));
3851 /* calculate and store physical address of */
3852 /* next entry in cirular list of entries */
3854 info
->tx_buffer_list
[i
].link
= info
->buffer_list_phys
+
3855 info
->rx_buffer_count
* sizeof(DMABUFFERENTRY
);
3857 if ( i
< info
->tx_buffer_count
- 1 )
3858 info
->tx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3863 } /* end of mgsl_alloc_buffer_list_memory() */
3865 /* Free DMA buffers allocated for use as the
3866 * receive and transmit buffer lists.
3869 * The data transfer buffers associated with the buffer list
3870 * MUST be freed before freeing the buffer list itself because
3871 * the buffer list contains the information necessary to free
3872 * the individual buffers!
3874 static void mgsl_free_buffer_list_memory( struct mgsl_struct
*info
)
3876 if (info
->buffer_list
&& info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3877 dma_free_coherent(NULL
, BUFFERLISTSIZE
, info
->buffer_list
, info
->buffer_list_dma_addr
);
3879 info
->buffer_list
= NULL
;
3880 info
->rx_buffer_list
= NULL
;
3881 info
->tx_buffer_list
= NULL
;
3883 } /* end of mgsl_free_buffer_list_memory() */
3886 * mgsl_alloc_frame_memory()
3888 * Allocate the frame DMA buffers used by the specified buffer list.
3889 * Each DMA buffer will be one memory page in size. This is necessary
3890 * because memory can fragment enough that it may be impossible
3895 * info pointer to device instance data
3896 * BufferList pointer to list of buffer entries
3897 * Buffercount count of buffer entries in buffer list
3899 * Return Value: 0 if success, otherwise -ENOMEM
3901 static int mgsl_alloc_frame_memory(struct mgsl_struct
*info
,DMABUFFERENTRY
*BufferList
,int Buffercount
)
3906 /* Allocate page sized buffers for the receive buffer list */
3908 for ( i
= 0; i
< Buffercount
; i
++ ) {
3909 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3910 /* PCI adapter uses shared memory buffers. */
3911 BufferList
[i
].virt_addr
= info
->memory_base
+ info
->last_mem_alloc
;
3912 phys_addr
= info
->last_mem_alloc
;
3913 info
->last_mem_alloc
+= DMABUFFERSIZE
;
3915 /* ISA adapter uses system memory. */
3916 BufferList
[i
].virt_addr
= dma_alloc_coherent(NULL
, DMABUFFERSIZE
, &BufferList
[i
].dma_addr
, GFP_KERNEL
);
3917 if (BufferList
[i
].virt_addr
== NULL
)
3919 phys_addr
= (u32
)(BufferList
[i
].dma_addr
);
3921 BufferList
[i
].phys_addr
= phys_addr
;
3926 } /* end of mgsl_alloc_frame_memory() */
3929 * mgsl_free_frame_memory()
3931 * Free the buffers associated with
3932 * each buffer entry of a buffer list.
3936 * info pointer to device instance data
3937 * BufferList pointer to list of buffer entries
3938 * Buffercount count of buffer entries in buffer list
3940 * Return Value: None
3942 static void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
, int Buffercount
)
3947 for ( i
= 0 ; i
< Buffercount
; i
++ ) {
3948 if ( BufferList
[i
].virt_addr
) {
3949 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3950 dma_free_coherent(NULL
, DMABUFFERSIZE
, BufferList
[i
].virt_addr
, BufferList
[i
].dma_addr
);
3951 BufferList
[i
].virt_addr
= NULL
;
3956 } /* end of mgsl_free_frame_memory() */
3958 /* mgsl_free_dma_buffers()
3962 * Arguments: info pointer to device instance data
3963 * Return Value: None
3965 static void mgsl_free_dma_buffers( struct mgsl_struct
*info
)
3967 mgsl_free_frame_memory( info
, info
->rx_buffer_list
, info
->rx_buffer_count
);
3968 mgsl_free_frame_memory( info
, info
->tx_buffer_list
, info
->tx_buffer_count
);
3969 mgsl_free_buffer_list_memory( info
);
3971 } /* end of mgsl_free_dma_buffers() */
3975 * mgsl_alloc_intermediate_rxbuffer_memory()
3977 * Allocate a buffer large enough to hold max_frame_size. This buffer
3978 * is used to pass an assembled frame to the line discipline.
3982 * info pointer to device instance data
3984 * Return Value: 0 if success, otherwise -ENOMEM
3986 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
3988 info
->intermediate_rxbuffer
= kmalloc(info
->max_frame_size
, GFP_KERNEL
| GFP_DMA
);
3989 if ( info
->intermediate_rxbuffer
== NULL
)
3994 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
3997 * mgsl_free_intermediate_rxbuffer_memory()
4002 * info pointer to device instance data
4004 * Return Value: None
4006 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
4008 kfree(info
->intermediate_rxbuffer
);
4009 info
->intermediate_rxbuffer
= NULL
;
4011 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
4014 * mgsl_alloc_intermediate_txbuffer_memory()
4016 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
4017 * This buffer is used to load transmit frames into the adapter's dma transfer
4018 * buffers when there is sufficient space.
4022 * info pointer to device instance data
4024 * Return Value: 0 if success, otherwise -ENOMEM
4026 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
4030 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4031 printk("%s %s(%d) allocating %d tx holding buffers\n",
4032 info
->device_name
, __FILE__
,__LINE__
,info
->num_tx_holding_buffers
);
4034 memset(info
->tx_holding_buffers
,0,sizeof(info
->tx_holding_buffers
));
4036 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
4037 info
->tx_holding_buffers
[i
].buffer
=
4038 kmalloc(info
->max_frame_size
, GFP_KERNEL
);
4039 if ( info
->tx_holding_buffers
[i
].buffer
== NULL
)
4045 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
4048 * mgsl_free_intermediate_txbuffer_memory()
4053 * info pointer to device instance data
4055 * Return Value: None
4057 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct
*info
)
4061 for ( i
=0; i
<info
->num_tx_holding_buffers
; ++i
) {
4062 kfree(info
->tx_holding_buffers
[i
].buffer
);
4063 info
->tx_holding_buffers
[i
].buffer
= NULL
;
4066 info
->get_tx_holding_index
= 0;
4067 info
->put_tx_holding_index
= 0;
4068 info
->tx_holding_count
= 0;
4070 } /* end of mgsl_free_intermediate_txbuffer_memory() */
4074 * load_next_tx_holding_buffer()
4076 * attempts to load the next buffered tx request into the
4081 * info pointer to device instance data
4083 * Return Value: 1 if next buffered tx request loaded
4084 * into adapter's tx dma buffer,
4087 static int load_next_tx_holding_buffer(struct mgsl_struct
*info
)
4091 if ( info
->tx_holding_count
) {
4092 /* determine if we have enough tx dma buffers
4093 * to accommodate the next tx frame
4095 struct tx_holding_buffer
*ptx
=
4096 &info
->tx_holding_buffers
[info
->get_tx_holding_index
];
4097 int num_free
= num_free_tx_dma_buffers(info
);
4098 int num_needed
= ptx
->buffer_size
/ DMABUFFERSIZE
;
4099 if ( ptx
->buffer_size
% DMABUFFERSIZE
)
4102 if (num_needed
<= num_free
) {
4103 info
->xmit_cnt
= ptx
->buffer_size
;
4104 mgsl_load_tx_dma_buffer(info
,ptx
->buffer
,ptx
->buffer_size
);
4106 --info
->tx_holding_count
;
4107 if ( ++info
->get_tx_holding_index
>= info
->num_tx_holding_buffers
)
4108 info
->get_tx_holding_index
=0;
4110 /* restart transmit timer */
4111 mod_timer(&info
->tx_timer
, jiffies
+ msecs_to_jiffies(5000));
4121 * save_tx_buffer_request()
4123 * attempt to store transmit frame request for later transmission
4127 * info pointer to device instance data
4128 * Buffer pointer to buffer containing frame to load
4129 * BufferSize size in bytes of frame in Buffer
4131 * Return Value: 1 if able to store, 0 otherwise
4133 static int save_tx_buffer_request(struct mgsl_struct
*info
,const char *Buffer
, unsigned int BufferSize
)
4135 struct tx_holding_buffer
*ptx
;
4137 if ( info
->tx_holding_count
>= info
->num_tx_holding_buffers
) {
4138 return 0; /* all buffers in use */
4141 ptx
= &info
->tx_holding_buffers
[info
->put_tx_holding_index
];
4142 ptx
->buffer_size
= BufferSize
;
4143 memcpy( ptx
->buffer
, Buffer
, BufferSize
);
4145 ++info
->tx_holding_count
;
4146 if ( ++info
->put_tx_holding_index
>= info
->num_tx_holding_buffers
)
4147 info
->put_tx_holding_index
=0;
4152 static int mgsl_claim_resources(struct mgsl_struct
*info
)
4154 if (request_region(info
->io_base
,info
->io_addr_size
,"synclink") == NULL
) {
4155 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4156 __FILE__
,__LINE__
,info
->device_name
, info
->io_base
);
4159 info
->io_addr_requested
= 1;
4161 if ( request_irq(info
->irq_level
,mgsl_interrupt
,info
->irq_flags
,
4162 info
->device_name
, info
) < 0 ) {
4163 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4164 __FILE__
,__LINE__
,info
->device_name
, info
->irq_level
);
4167 info
->irq_requested
= 1;
4169 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4170 if (request_mem_region(info
->phys_memory_base
,0x40000,"synclink") == NULL
) {
4171 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4172 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4175 info
->shared_mem_requested
= 1;
4176 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclink") == NULL
) {
4177 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4178 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
+ info
->lcr_offset
);
4181 info
->lcr_mem_requested
= 1;
4183 info
->memory_base
= ioremap(info
->phys_memory_base
,0x40000);
4184 if (!info
->memory_base
) {
4185 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4186 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4190 if ( !mgsl_memory_test(info
) ) {
4191 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4192 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4196 info
->lcr_base
= ioremap(info
->phys_lcr_base
,PAGE_SIZE
) + info
->lcr_offset
;
4197 if (!info
->lcr_base
) {
4198 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4199 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
4204 /* claim DMA channel */
4206 if (request_dma(info
->dma_level
,info
->device_name
) < 0){
4207 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4208 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4209 mgsl_release_resources( info
);
4212 info
->dma_requested
= 1;
4214 /* ISA adapter uses bus master DMA */
4215 set_dma_mode(info
->dma_level
,DMA_MODE_CASCADE
);
4216 enable_dma(info
->dma_level
);
4219 if ( mgsl_allocate_dma_buffers(info
) < 0 ) {
4220 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4221 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4227 mgsl_release_resources(info
);
4230 } /* end of mgsl_claim_resources() */
4232 static void mgsl_release_resources(struct mgsl_struct
*info
)
4234 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4235 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4236 __FILE__
,__LINE__
,info
->device_name
);
4238 if ( info
->irq_requested
) {
4239 free_irq(info
->irq_level
, info
);
4240 info
->irq_requested
= 0;
4242 if ( info
->dma_requested
) {
4243 disable_dma(info
->dma_level
);
4244 free_dma(info
->dma_level
);
4245 info
->dma_requested
= 0;
4247 mgsl_free_dma_buffers(info
);
4248 mgsl_free_intermediate_rxbuffer_memory(info
);
4249 mgsl_free_intermediate_txbuffer_memory(info
);
4251 if ( info
->io_addr_requested
) {
4252 release_region(info
->io_base
,info
->io_addr_size
);
4253 info
->io_addr_requested
= 0;
4255 if ( info
->shared_mem_requested
) {
4256 release_mem_region(info
->phys_memory_base
,0x40000);
4257 info
->shared_mem_requested
= 0;
4259 if ( info
->lcr_mem_requested
) {
4260 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
4261 info
->lcr_mem_requested
= 0;
4263 if (info
->memory_base
){
4264 iounmap(info
->memory_base
);
4265 info
->memory_base
= NULL
;
4267 if (info
->lcr_base
){
4268 iounmap(info
->lcr_base
- info
->lcr_offset
);
4269 info
->lcr_base
= NULL
;
4272 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4273 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4274 __FILE__
,__LINE__
,info
->device_name
);
4276 } /* end of mgsl_release_resources() */
4278 /* mgsl_add_device()
4280 * Add the specified device instance data structure to the
4281 * global linked list of devices and increment the device count.
4283 * Arguments: info pointer to device instance data
4284 * Return Value: None
4286 static void mgsl_add_device( struct mgsl_struct
*info
)
4288 info
->next_device
= NULL
;
4289 info
->line
= mgsl_device_count
;
4290 sprintf(info
->device_name
,"ttySL%d",info
->line
);
4292 if (info
->line
< MAX_TOTAL_DEVICES
) {
4293 if (maxframe
[info
->line
])
4294 info
->max_frame_size
= maxframe
[info
->line
];
4295 info
->dosyncppp
= dosyncppp
[info
->line
];
4297 if (txdmabufs
[info
->line
]) {
4298 info
->num_tx_dma_buffers
= txdmabufs
[info
->line
];
4299 if (info
->num_tx_dma_buffers
< 1)
4300 info
->num_tx_dma_buffers
= 1;
4303 if (txholdbufs
[info
->line
]) {
4304 info
->num_tx_holding_buffers
= txholdbufs
[info
->line
];
4305 if (info
->num_tx_holding_buffers
< 1)
4306 info
->num_tx_holding_buffers
= 1;
4307 else if (info
->num_tx_holding_buffers
> MAX_TX_HOLDING_BUFFERS
)
4308 info
->num_tx_holding_buffers
= MAX_TX_HOLDING_BUFFERS
;
4312 mgsl_device_count
++;
4314 if ( !mgsl_device_list
)
4315 mgsl_device_list
= info
;
4317 struct mgsl_struct
*current_dev
= mgsl_device_list
;
4318 while( current_dev
->next_device
)
4319 current_dev
= current_dev
->next_device
;
4320 current_dev
->next_device
= info
;
4323 if ( info
->max_frame_size
< 4096 )
4324 info
->max_frame_size
= 4096;
4325 else if ( info
->max_frame_size
> 65535 )
4326 info
->max_frame_size
= 65535;
4328 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4329 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4330 info
->hw_version
+ 1, info
->device_name
, info
->io_base
, info
->irq_level
,
4331 info
->phys_memory_base
, info
->phys_lcr_base
,
4332 info
->max_frame_size
);
4334 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4335 info
->device_name
, info
->io_base
, info
->irq_level
, info
->dma_level
,
4336 info
->max_frame_size
);
4343 } /* end of mgsl_add_device() */
4345 /* mgsl_allocate_device()
4347 * Allocate and initialize a device instance structure
4350 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4352 static struct mgsl_struct
* mgsl_allocate_device(void)
4354 struct mgsl_struct
*info
;
4356 info
= (struct mgsl_struct
*)kmalloc(sizeof(struct mgsl_struct
),
4360 printk("Error can't allocate device instance data\n");
4362 memset(info
, 0, sizeof(struct mgsl_struct
));
4363 info
->magic
= MGSL_MAGIC
;
4364 INIT_WORK(&info
->task
, mgsl_bh_handler
, info
);
4365 info
->max_frame_size
= 4096;
4366 info
->close_delay
= 5*HZ
/10;
4367 info
->closing_wait
= 30*HZ
;
4368 init_waitqueue_head(&info
->open_wait
);
4369 init_waitqueue_head(&info
->close_wait
);
4370 init_waitqueue_head(&info
->status_event_wait_q
);
4371 init_waitqueue_head(&info
->event_wait_q
);
4372 spin_lock_init(&info
->irq_spinlock
);
4373 spin_lock_init(&info
->netlock
);
4374 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
4375 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
4376 info
->num_tx_dma_buffers
= 1;
4377 info
->num_tx_holding_buffers
= 0;
4382 } /* end of mgsl_allocate_device()*/
4384 static struct tty_operations mgsl_ops
= {
4386 .close
= mgsl_close
,
4387 .write
= mgsl_write
,
4388 .put_char
= mgsl_put_char
,
4389 .flush_chars
= mgsl_flush_chars
,
4390 .write_room
= mgsl_write_room
,
4391 .chars_in_buffer
= mgsl_chars_in_buffer
,
4392 .flush_buffer
= mgsl_flush_buffer
,
4393 .ioctl
= mgsl_ioctl
,
4394 .throttle
= mgsl_throttle
,
4395 .unthrottle
= mgsl_unthrottle
,
4396 .send_xchar
= mgsl_send_xchar
,
4397 .break_ctl
= mgsl_break
,
4398 .wait_until_sent
= mgsl_wait_until_sent
,
4399 .read_proc
= mgsl_read_proc
,
4400 .set_termios
= mgsl_set_termios
,
4402 .start
= mgsl_start
,
4403 .hangup
= mgsl_hangup
,
4404 .tiocmget
= tiocmget
,
4405 .tiocmset
= tiocmset
,
4409 * perform tty device initialization
4411 static int mgsl_init_tty(void)
4415 serial_driver
= alloc_tty_driver(128);
4419 serial_driver
->owner
= THIS_MODULE
;
4420 serial_driver
->driver_name
= "synclink";
4421 serial_driver
->name
= "ttySL";
4422 serial_driver
->major
= ttymajor
;
4423 serial_driver
->minor_start
= 64;
4424 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4425 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4426 serial_driver
->init_termios
= tty_std_termios
;
4427 serial_driver
->init_termios
.c_cflag
=
4428 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4429 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4430 tty_set_operations(serial_driver
, &mgsl_ops
);
4431 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4432 printk("%s(%d):Couldn't register serial driver\n",
4434 put_tty_driver(serial_driver
);
4435 serial_driver
= NULL
;
4439 printk("%s %s, tty major#%d\n",
4440 driver_name
, driver_version
,
4441 serial_driver
->major
);
4445 /* enumerate user specified ISA adapters
4447 static void mgsl_enum_isa_devices(void)
4449 struct mgsl_struct
*info
;
4452 /* Check for user specified ISA devices */
4454 for (i
=0 ;(i
< MAX_ISA_DEVICES
) && io
[i
] && irq
[i
]; i
++){
4455 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4456 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4457 io
[i
], irq
[i
], dma
[i
] );
4459 info
= mgsl_allocate_device();
4461 /* error allocating device instance data */
4462 if ( debug_level
>= DEBUG_LEVEL_ERROR
)
4463 printk( "can't allocate device instance data.\n");
4467 /* Copy user configuration info to device instance data */
4468 info
->io_base
= (unsigned int)io
[i
];
4469 info
->irq_level
= (unsigned int)irq
[i
];
4470 info
->irq_level
= irq_canonicalize(info
->irq_level
);
4471 info
->dma_level
= (unsigned int)dma
[i
];
4472 info
->bus_type
= MGSL_BUS_TYPE_ISA
;
4473 info
->io_addr_size
= 16;
4474 info
->irq_flags
= 0;
4476 mgsl_add_device( info
);
4480 static void synclink_cleanup(void)
4483 struct mgsl_struct
*info
;
4484 struct mgsl_struct
*tmp
;
4486 printk("Unloading %s: %s\n", driver_name
, driver_version
);
4488 if (serial_driver
) {
4489 if ((rc
= tty_unregister_driver(serial_driver
)))
4490 printk("%s(%d) failed to unregister tty driver err=%d\n",
4491 __FILE__
,__LINE__
,rc
);
4492 put_tty_driver(serial_driver
);
4495 info
= mgsl_device_list
;
4500 mgsl_release_resources(info
);
4502 info
= info
->next_device
;
4507 free_page((unsigned long) tmp_buf
);
4512 pci_unregister_driver(&synclink_pci_driver
);
4515 static int __init
synclink_init(void)
4519 if (break_on_load
) {
4520 mgsl_get_text_ptr();
4524 printk("%s %s\n", driver_name
, driver_version
);
4526 mgsl_enum_isa_devices();
4527 if ((rc
= pci_register_driver(&synclink_pci_driver
)) < 0)
4528 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4532 if ((rc
= mgsl_init_tty()) < 0)
4542 static void __exit
synclink_exit(void)
4547 module_init(synclink_init
);
4548 module_exit(synclink_exit
);
4553 * Issue a USC Receive/Transmit command to the
4554 * Channel Command/Address Register (CCAR).
4558 * The command is encoded in the most significant 5 bits <15..11>
4559 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4560 * and Bits <6..0> must be written as zeros.
4564 * info pointer to device information structure
4565 * Cmd command mask (use symbolic macros)
4571 static void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
)
4573 /* output command to CCAR in bits <15..11> */
4574 /* preserve bits <10..7>, bits <6..0> must be zero */
4576 outw( Cmd
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4578 /* Read to flush write to CCAR */
4579 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4580 inw( info
->io_base
+ CCAR
);
4582 } /* end of usc_RTCmd() */
4587 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4591 * info pointer to device information structure
4592 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4598 static void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
)
4600 /* write command mask to DCAR */
4601 outw( Cmd
+ info
->mbre_bit
, info
->io_base
);
4603 /* Read to flush write to DCAR */
4604 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4605 inw( info
->io_base
);
4607 } /* end of usc_DmaCmd() */
4612 * Write a 16-bit value to a USC DMA register
4616 * info pointer to device info structure
4617 * RegAddr register address (number) for write
4618 * RegValue 16-bit value to write to register
4625 static void usc_OutDmaReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4627 /* Note: The DCAR is located at the adapter base address */
4628 /* Note: must preserve state of BIT8 in DCAR */
4630 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4631 outw( RegValue
, info
->io_base
);
4633 /* Read to flush write to DCAR */
4634 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4635 inw( info
->io_base
);
4637 } /* end of usc_OutDmaReg() */
4642 * Read a 16-bit value from a DMA register
4646 * info pointer to device info structure
4647 * RegAddr register address (number) to read from
4651 * The 16-bit value read from register
4654 static u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 RegAddr
)
4656 /* Note: The DCAR is located at the adapter base address */
4657 /* Note: must preserve state of BIT8 in DCAR */
4659 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4660 return inw( info
->io_base
);
4662 } /* end of usc_InDmaReg() */
4668 * Write a 16-bit value to a USC serial channel register
4672 * info pointer to device info structure
4673 * RegAddr register address (number) to write to
4674 * RegValue 16-bit value to write to register
4681 static void usc_OutReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4683 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4684 outw( RegValue
, info
->io_base
+ CCAR
);
4686 /* Read to flush write to CCAR */
4687 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4688 inw( info
->io_base
+ CCAR
);
4690 } /* end of usc_OutReg() */
4695 * Reads a 16-bit value from a USC serial channel register
4699 * info pointer to device extension
4700 * RegAddr register address (number) to read from
4704 * 16-bit value read from register
4706 static u16
usc_InReg( struct mgsl_struct
*info
, u16 RegAddr
)
4708 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4709 return inw( info
->io_base
+ CCAR
);
4711 } /* end of usc_InReg() */
4713 /* usc_set_sdlc_mode()
4715 * Set up the adapter for SDLC DMA communications.
4717 * Arguments: info pointer to device instance data
4718 * Return Value: NONE
4720 static void usc_set_sdlc_mode( struct mgsl_struct
*info
)
4726 * determine if the IUSC on the adapter is pre-SL1660. If
4727 * not, take advantage of the UnderWait feature of more
4728 * modern chips. If an underrun occurs and this bit is set,
4729 * the transmitter will idle the programmed idle pattern
4730 * until the driver has time to service the underrun. Otherwise,
4731 * the dma controller may get the cycles previously requested
4732 * and begin transmitting queued tx data.
4734 usc_OutReg(info
,TMCR
,0x1f);
4735 RegValue
=usc_InReg(info
,TMDR
);
4736 if ( RegValue
== IUSC_PRE_SL1660
)
4742 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
4745 ** Channel Mode Register (CMR)
4747 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4748 ** <13> 0 0 = Transmit Disabled (initially)
4749 ** <12> 0 1 = Consecutive Idles share common 0
4750 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4751 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4752 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4754 ** 1000 1110 0000 0110 = 0x8e06
4758 /*--------------------------------------------------
4759 * ignore user options for UnderRun Actions and
4761 *--------------------------------------------------*/
4765 /* Channel mode Register (CMR)
4767 * <15..14> 00 Tx Sub modes, Underrun Action
4768 * <13> 0 1 = Send Preamble before opening flag
4769 * <12> 0 1 = Consecutive Idles share common 0
4770 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4771 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4772 * <3..0> 0110 Receiver mode = HDLC/SDLC
4774 * 0000 0110 0000 0110 = 0x0606
4776 if (info
->params
.mode
== MGSL_MODE_RAW
) {
4777 RegValue
= 0x0001; /* Set Receive mode = external sync */
4779 usc_OutReg( info
, IOCR
, /* Set IOCR DCD is RxSync Detect Input */
4780 (unsigned short)((usc_InReg(info
, IOCR
) & ~(BIT13
|BIT12
)) | BIT12
));
4784 * CMR <15> 0 Don't send CRC on Tx Underrun
4785 * CMR <14> x undefined
4786 * CMR <13> 0 Send preamble before openning sync
4787 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4790 * CMR <11-8) 0100 MonoSync
4792 * 0x00 0100 xxxx xxxx 04xx
4800 if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_ABORT15
)
4802 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_FLAG
)
4804 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_CRC
)
4805 RegValue
|= BIT15
+ BIT14
;
4808 if ( info
->params
.preamble
!= HDLC_PREAMBLE_PATTERN_NONE
)
4812 if ( info
->params
.mode
== MGSL_MODE_HDLC
&&
4813 (info
->params
.flags
& HDLC_FLAG_SHARE_ZERO
) )
4816 if ( info
->params
.addr_filter
!= 0xff )
4818 /* set up receive address filtering */
4819 usc_OutReg( info
, RSR
, info
->params
.addr_filter
);
4823 usc_OutReg( info
, CMR
, RegValue
);
4824 info
->cmr_value
= RegValue
;
4826 /* Receiver mode Register (RMR)
4828 * <15..13> 000 encoding
4829 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4830 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4831 * <9> 0 1 = Include Receive chars in CRC
4832 * <8> 1 1 = Use Abort/PE bit as abort indicator
4833 * <7..6> 00 Even parity
4834 * <5> 0 parity disabled
4835 * <4..2> 000 Receive Char Length = 8 bits
4836 * <1..0> 00 Disable Receiver
4838 * 0000 0101 0000 0000 = 0x0500
4843 switch ( info
->params
.encoding
) {
4844 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4845 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4846 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4847 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4848 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4849 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4850 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4853 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4855 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4856 RegValue
|= ( BIT12
| BIT10
| BIT9
);
4858 usc_OutReg( info
, RMR
, RegValue
);
4860 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4861 /* When an opening flag of an SDLC frame is recognized the */
4862 /* Receive Character count (RCC) is loaded with the value in */
4863 /* RCLR. The RCC is decremented for each received byte. The */
4864 /* value of RCC is stored after the closing flag of the frame */
4865 /* allowing the frame size to be computed. */
4867 usc_OutReg( info
, RCLR
, RCLRVALUE
);
4869 usc_RCmd( info
, RCmd_SelectRicrdma_level
);
4871 /* Receive Interrupt Control Register (RICR)
4873 * <15..8> ? RxFIFO DMA Request Level
4874 * <7> 0 Exited Hunt IA (Interrupt Arm)
4875 * <6> 0 Idle Received IA
4876 * <5> 0 Break/Abort IA
4878 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4880 * <1> 1 Rx Overrun IA
4881 * <0> 0 Select TC0 value for readback
4883 * 0000 0000 0000 1000 = 0x000a
4886 /* Carry over the Exit Hunt and Idle Received bits */
4887 /* in case they have been armed by usc_ArmEvents. */
4889 RegValue
= usc_InReg( info
, RICR
) & 0xc0;
4891 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4892 usc_OutReg( info
, RICR
, (u16
)(0x030a | RegValue
) );
4894 usc_OutReg( info
, RICR
, (u16
)(0x140a | RegValue
) );
4896 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4898 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
4899 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
4901 /* Transmit mode Register (TMR)
4903 * <15..13> 000 encoding
4904 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4905 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4906 * <9> 0 1 = Tx CRC Enabled
4907 * <8> 0 1 = Append CRC to end of transmit frame
4908 * <7..6> 00 Transmit parity Even
4909 * <5> 0 Transmit parity Disabled
4910 * <4..2> 000 Tx Char Length = 8 bits
4911 * <1..0> 00 Disable Transmitter
4913 * 0000 0100 0000 0000 = 0x0400
4918 switch ( info
->params
.encoding
) {
4919 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4920 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4921 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4922 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4923 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4924 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4925 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4928 if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_16_CCITT
)
4929 RegValue
|= BIT9
+ BIT8
;
4930 else if ( (info
->params
.crc_type
& HDLC_CRC_MASK
) == HDLC_CRC_32_CCITT
)
4931 RegValue
|= ( BIT12
| BIT10
| BIT9
| BIT8
);
4933 usc_OutReg( info
, TMR
, RegValue
);
4935 usc_set_txidle( info
);
4938 usc_TCmd( info
, TCmd_SelectTicrdma_level
);
4940 /* Transmit Interrupt Control Register (TICR)
4942 * <15..8> ? Transmit FIFO DMA Level
4943 * <7> 0 Present IA (Interrupt Arm)
4944 * <6> 0 Idle Sent IA
4945 * <5> 1 Abort Sent IA
4946 * <4> 1 EOF/EOM Sent IA
4948 * <2> 1 1 = Wait for SW Trigger to Start Frame
4949 * <1> 1 Tx Underrun IA
4950 * <0> 0 TC0 constant on read back
4952 * 0000 0000 0011 0110 = 0x0036
4955 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4956 usc_OutReg( info
, TICR
, 0x0736 );
4958 usc_OutReg( info
, TICR
, 0x1436 );
4960 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
4961 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
4964 ** Transmit Command/Status Register (TCSR)
4966 ** <15..12> 0000 TCmd
4967 ** <11> 0/1 UnderWait
4968 ** <10..08> 000 TxIdle
4972 ** <4> x EOF/EOM Sent
4978 ** 0000 0000 0000 0000 = 0x0000
4980 info
->tcsr_value
= 0;
4983 info
->tcsr_value
|= TCSR_UNDERWAIT
;
4985 usc_OutReg( info
, TCSR
, info
->tcsr_value
);
4987 /* Clock mode Control Register (CMCR)
4989 * <15..14> 00 counter 1 Source = Disabled
4990 * <13..12> 00 counter 0 Source = Disabled
4991 * <11..10> 11 BRG1 Input is TxC Pin
4992 * <9..8> 11 BRG0 Input is TxC Pin
4993 * <7..6> 01 DPLL Input is BRG1 Output
4994 * <5..3> XXX TxCLK comes from Port 0
4995 * <2..0> XXX RxCLK comes from Port 1
4997 * 0000 1111 0111 0111 = 0x0f77
5002 if ( info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
5003 RegValue
|= 0x0003; /* RxCLK from DPLL */
5004 else if ( info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
5005 RegValue
|= 0x0004; /* RxCLK from BRG0 */
5006 else if ( info
->params
.flags
& HDLC_FLAG_RXC_TXCPIN
)
5007 RegValue
|= 0x0006; /* RxCLK from TXC Input */
5009 RegValue
|= 0x0007; /* RxCLK from Port1 */
5011 if ( info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
5012 RegValue
|= 0x0018; /* TxCLK from DPLL */
5013 else if ( info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
5014 RegValue
|= 0x0020; /* TxCLK from BRG0 */
5015 else if ( info
->params
.flags
& HDLC_FLAG_TXC_RXCPIN
)
5016 RegValue
|= 0x0038; /* RxCLK from TXC Input */
5018 RegValue
|= 0x0030; /* TxCLK from Port0 */
5020 usc_OutReg( info
, CMCR
, RegValue
);
5023 /* Hardware Configuration Register (HCR)
5025 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
5026 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
5027 * <12> 0 CVOK:0=report code violation in biphase
5028 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
5029 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
5030 * <7..6> 00 reserved
5031 * <5> 0 BRG1 mode:0=continuous,1=single cycle
5033 * <3..2> 00 reserved
5034 * <1> 0 BRG0 mode:0=continuous,1=single cycle
5040 if ( info
->params
.flags
& (HDLC_FLAG_RXC_DPLL
+ HDLC_FLAG_TXC_DPLL
) ) {
5045 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
5046 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5048 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5049 XtalSpeed
= 11059200;
5051 XtalSpeed
= 14745600;
5053 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
5057 else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
5064 /* Tc = (Xtal/Speed) - 1 */
5065 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5066 /* then rounding up gives a more precise time constant. Instead */
5067 /* of rounding up and then subtracting 1 we just don't subtract */
5068 /* the one in this case. */
5070 /*--------------------------------------------------
5071 * ejz: for DPLL mode, application should use the
5072 * same clock speed as the partner system, even
5073 * though clocking is derived from the input RxData.
5074 * In case the user uses a 0 for the clock speed,
5075 * default to 0xffffffff and don't try to divide by
5077 *--------------------------------------------------*/
5078 if ( info
->params
.clock_speed
)
5080 Tc
= (u16
)((XtalSpeed
/DpllDivisor
)/info
->params
.clock_speed
);
5081 if ( !((((XtalSpeed
/DpllDivisor
) % info
->params
.clock_speed
) * 2)
5082 / info
->params
.clock_speed
) )
5089 /* Write 16-bit Time Constant for BRG1 */
5090 usc_OutReg( info
, TC1R
, Tc
);
5092 RegValue
|= BIT4
; /* enable BRG1 */
5094 switch ( info
->params
.encoding
) {
5095 case HDLC_ENCODING_NRZ
:
5096 case HDLC_ENCODING_NRZB
:
5097 case HDLC_ENCODING_NRZI_MARK
:
5098 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT8
; break;
5099 case HDLC_ENCODING_BIPHASE_MARK
:
5100 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT9
; break;
5101 case HDLC_ENCODING_BIPHASE_LEVEL
:
5102 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT9
+ BIT8
; break;
5106 usc_OutReg( info
, HCR
, RegValue
);
5109 /* Channel Control/status Register (CCSR)
5111 * <15> X RCC FIFO Overflow status (RO)
5112 * <14> X RCC FIFO Not Empty status (RO)
5113 * <13> 0 1 = Clear RCC FIFO (WO)
5114 * <12> X DPLL Sync (RW)
5115 * <11> X DPLL 2 Missed Clocks status (RO)
5116 * <10> X DPLL 1 Missed Clock status (RO)
5117 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5118 * <7> X SDLC Loop On status (RO)
5119 * <6> X SDLC Loop Send status (RO)
5120 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5121 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5122 * <1..0> 00 reserved
5124 * 0000 0000 0010 0000 = 0x0020
5127 usc_OutReg( info
, CCSR
, 0x1020 );
5130 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
) {
5131 usc_OutReg( info
, SICR
,
5132 (u16
)(usc_InReg(info
,SICR
) | SICR_CTS_INACTIVE
) );
5136 /* enable Master Interrupt Enable bit (MIE) */
5137 usc_EnableMasterIrqBit( info
);
5139 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
+ RECEIVE_DATA
+
5140 TRANSMIT_STATUS
+ TRANSMIT_DATA
+ MISC
);
5142 /* arm RCC underflow interrupt */
5143 usc_OutReg(info
, SICR
, (u16
)(usc_InReg(info
,SICR
) | BIT3
));
5144 usc_EnableInterrupts(info
, MISC
);
5147 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5148 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5149 info
->mbre_bit
= BIT8
;
5150 outw( BIT8
, info
->io_base
); /* set Master Bus Enable (DCAR) */
5152 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
5153 /* Enable DMAEN (Port 7, Bit 14) */
5154 /* This connects the DMA request signal to the ISA bus */
5155 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) & ~BIT14
));
5158 /* DMA Control Register (DCR)
5160 * <15..14> 10 Priority mode = Alternating Tx/Rx
5161 * 01 Rx has priority
5162 * 00 Tx has priority
5164 * <13> 1 Enable Priority Preempt per DCR<15..14>
5165 * (WARNING DCR<11..10> must be 00 when this is 1)
5166 * 0 Choose activate channel per DCR<11..10>
5168 * <12> 0 Little Endian for Array/List
5169 * <11..10> 00 Both Channels can use each bus grant
5170 * <9..6> 0000 reserved
5171 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5172 * <4> 0 1 = drive D/C and S/D pins
5173 * <3> 1 1 = Add one wait state to all DMA cycles.
5174 * <2> 0 1 = Strobe /UAS on every transfer.
5175 * <1..0> 11 Addr incrementing only affects LS24 bits
5177 * 0110 0000 0000 1011 = 0x600b
5180 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5181 /* PCI adapter does not need DMA wait state */
5182 usc_OutDmaReg( info
, DCR
, 0xa00b );
5185 usc_OutDmaReg( info
, DCR
, 0x800b );
5188 /* Receive DMA mode Register (RDMR)
5190 * <15..14> 11 DMA mode = Linked List Buffer mode
5191 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5192 * <12> 1 Clear count of List Entry after fetching
5193 * <11..10> 00 Address mode = Increment
5194 * <9> 1 Terminate Buffer on RxBound
5195 * <8> 0 Bus Width = 16bits
5196 * <7..0> ? status Bits (write as 0s)
5198 * 1111 0010 0000 0000 = 0xf200
5201 usc_OutDmaReg( info
, RDMR
, 0xf200 );
5204 /* Transmit DMA mode Register (TDMR)
5206 * <15..14> 11 DMA mode = Linked List Buffer mode
5207 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5208 * <12> 1 Clear count of List Entry after fetching
5209 * <11..10> 00 Address mode = Increment
5210 * <9> 1 Terminate Buffer on end of frame
5211 * <8> 0 Bus Width = 16bits
5212 * <7..0> ? status Bits (Read Only so write as 0)
5214 * 1111 0010 0000 0000 = 0xf200
5217 usc_OutDmaReg( info
, TDMR
, 0xf200 );
5220 /* DMA Interrupt Control Register (DICR)
5222 * <15> 1 DMA Interrupt Enable
5223 * <14> 0 1 = Disable IEO from USC
5224 * <13> 0 1 = Don't provide vector during IntAck
5225 * <12> 1 1 = Include status in Vector
5226 * <10..2> 0 reserved, Must be 0s
5227 * <1> 0 1 = Rx DMA Interrupt Enabled
5228 * <0> 0 1 = Tx DMA Interrupt Enabled
5230 * 1001 0000 0000 0000 = 0x9000
5233 usc_OutDmaReg( info
, DICR
, 0x9000 );
5235 usc_InDmaReg( info
, RDMR
); /* clear pending receive DMA IRQ bits */
5236 usc_InDmaReg( info
, TDMR
); /* clear pending transmit DMA IRQ bits */
5237 usc_OutDmaReg( info
, CDIR
, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5239 /* Channel Control Register (CCR)
5241 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5242 * <13> 0 Trigger Tx on SW Command Disabled
5243 * <12> 0 Flag Preamble Disabled
5244 * <11..10> 00 Preamble Length
5245 * <9..8> 00 Preamble Pattern
5246 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5247 * <5> 0 Trigger Rx on SW Command Disabled
5250 * 1000 0000 1000 0000 = 0x8080
5255 switch ( info
->params
.preamble_length
) {
5256 case HDLC_PREAMBLE_LENGTH_16BITS
: RegValue
|= BIT10
; break;
5257 case HDLC_PREAMBLE_LENGTH_32BITS
: RegValue
|= BIT11
; break;
5258 case HDLC_PREAMBLE_LENGTH_64BITS
: RegValue
|= BIT11
+ BIT10
; break;
5261 switch ( info
->params
.preamble
) {
5262 case HDLC_PREAMBLE_PATTERN_FLAGS
: RegValue
|= BIT8
+ BIT12
; break;
5263 case HDLC_PREAMBLE_PATTERN_ONES
: RegValue
|= BIT8
; break;
5264 case HDLC_PREAMBLE_PATTERN_10
: RegValue
|= BIT9
; break;
5265 case HDLC_PREAMBLE_PATTERN_01
: RegValue
|= BIT9
+ BIT8
; break;
5268 usc_OutReg( info
, CCR
, RegValue
);
5272 * Burst/Dwell Control Register
5274 * <15..8> 0x20 Maximum number of transfers per bus grant
5275 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5278 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5279 /* don't limit bus occupancy on PCI adapter */
5280 usc_OutDmaReg( info
, BDCR
, 0x0000 );
5283 usc_OutDmaReg( info
, BDCR
, 0x2000 );
5285 usc_stop_transmitter(info
);
5286 usc_stop_receiver(info
);
5288 } /* end of usc_set_sdlc_mode() */
5290 /* usc_enable_loopback()
5292 * Set the 16C32 for internal loopback mode.
5293 * The TxCLK and RxCLK signals are generated from the BRG0 and
5294 * the TxD is looped back to the RxD internally.
5296 * Arguments: info pointer to device instance data
5297 * enable 1 = enable loopback, 0 = disable
5298 * Return Value: None
5300 static void usc_enable_loopback(struct mgsl_struct
*info
, int enable
)
5303 /* blank external TXD output */
5304 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) | (BIT7
+BIT6
));
5306 /* Clock mode Control Register (CMCR)
5308 * <15..14> 00 counter 1 Disabled
5309 * <13..12> 00 counter 0 Disabled
5310 * <11..10> 11 BRG1 Input is TxC Pin
5311 * <9..8> 11 BRG0 Input is TxC Pin
5312 * <7..6> 01 DPLL Input is BRG1 Output
5313 * <5..3> 100 TxCLK comes from BRG0
5314 * <2..0> 100 RxCLK comes from BRG0
5316 * 0000 1111 0110 0100 = 0x0f64
5319 usc_OutReg( info
, CMCR
, 0x0f64 );
5321 /* Write 16-bit Time Constant for BRG0 */
5322 /* use clock speed if available, otherwise use 8 for diagnostics */
5323 if (info
->params
.clock_speed
) {
5324 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5325 usc_OutReg(info
, TC0R
, (u16
)((11059200/info
->params
.clock_speed
)-1));
5327 usc_OutReg(info
, TC0R
, (u16
)((14745600/info
->params
.clock_speed
)-1));
5329 usc_OutReg(info
, TC0R
, (u16
)8);
5331 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5332 mode = Continuous Set Bit 0 to enable BRG0. */
5333 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5335 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5336 usc_OutReg(info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004));
5338 /* set Internal Data loopback mode */
5339 info
->loopback_bits
= 0x300;
5340 outw( 0x0300, info
->io_base
+ CCAR
);
5342 /* enable external TXD output */
5343 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) & ~(BIT7
+BIT6
));
5345 /* clear Internal Data loopback mode */
5346 info
->loopback_bits
= 0;
5347 outw( 0,info
->io_base
+ CCAR
);
5350 } /* end of usc_enable_loopback() */
5352 /* usc_enable_aux_clock()
5354 * Enabled the AUX clock output at the specified frequency.
5358 * info pointer to device extension
5359 * data_rate data rate of clock in bits per second
5360 * A data rate of 0 disables the AUX clock.
5362 * Return Value: None
5364 static void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 data_rate
)
5370 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5371 XtalSpeed
= 11059200;
5373 XtalSpeed
= 14745600;
5376 /* Tc = (Xtal/Speed) - 1 */
5377 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5378 /* then rounding up gives a more precise time constant. Instead */
5379 /* of rounding up and then subtracting 1 we just don't subtract */
5380 /* the one in this case. */
5383 Tc
= (u16
)(XtalSpeed
/data_rate
);
5384 if ( !(((XtalSpeed
% data_rate
) * 2) / data_rate
) )
5387 /* Write 16-bit Time Constant for BRG0 */
5388 usc_OutReg( info
, TC0R
, Tc
);
5391 * Hardware Configuration Register (HCR)
5392 * Clear Bit 1, BRG0 mode = Continuous
5393 * Set Bit 0 to enable BRG0.
5396 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5398 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5399 usc_OutReg( info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
5401 /* data rate == 0 so turn off BRG0 */
5402 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
5405 } /* end of usc_enable_aux_clock() */
5409 * usc_process_rxoverrun_sync()
5411 * This function processes a receive overrun by resetting the
5412 * receive DMA buffers and issuing a Purge Rx FIFO command
5413 * to allow the receiver to continue receiving.
5417 * info pointer to device extension
5419 * Return Value: None
5421 static void usc_process_rxoverrun_sync( struct mgsl_struct
*info
)
5425 int frame_start_index
;
5426 int start_of_frame_found
= FALSE
;
5427 int end_of_frame_found
= FALSE
;
5428 int reprogram_dma
= FALSE
;
5430 DMABUFFERENTRY
*buffer_list
= info
->rx_buffer_list
;
5433 usc_DmaCmd( info
, DmaCmd_PauseRxChannel
);
5434 usc_RCmd( info
, RCmd_EnterHuntmode
);
5435 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5437 /* CurrentRxBuffer points to the 1st buffer of the next */
5438 /* possibly available receive frame. */
5440 frame_start_index
= start_index
= end_index
= info
->current_rx_buffer
;
5442 /* Search for an unfinished string of buffers. This means */
5443 /* that a receive frame started (at least one buffer with */
5444 /* count set to zero) but there is no terminiting buffer */
5445 /* (status set to non-zero). */
5447 while( !buffer_list
[end_index
].count
)
5449 /* Count field has been reset to zero by 16C32. */
5450 /* This buffer is currently in use. */
5452 if ( !start_of_frame_found
)
5454 start_of_frame_found
= TRUE
;
5455 frame_start_index
= end_index
;
5456 end_of_frame_found
= FALSE
;
5459 if ( buffer_list
[end_index
].status
)
5461 /* Status field has been set by 16C32. */
5462 /* This is the last buffer of a received frame. */
5464 /* We want to leave the buffers for this frame intact. */
5465 /* Move on to next possible frame. */
5467 start_of_frame_found
= FALSE
;
5468 end_of_frame_found
= TRUE
;
5471 /* advance to next buffer entry in linked list */
5473 if ( end_index
== info
->rx_buffer_count
)
5476 if ( start_index
== end_index
)
5478 /* The entire list has been searched with all Counts == 0 and */
5479 /* all Status == 0. The receive buffers are */
5480 /* completely screwed, reset all receive buffers! */
5481 mgsl_reset_rx_dma_buffers( info
);
5482 frame_start_index
= 0;
5483 start_of_frame_found
= FALSE
;
5484 reprogram_dma
= TRUE
;
5489 if ( start_of_frame_found
&& !end_of_frame_found
)
5491 /* There is an unfinished string of receive DMA buffers */
5492 /* as a result of the receiver overrun. */
5494 /* Reset the buffers for the unfinished frame */
5495 /* and reprogram the receive DMA controller to start */
5496 /* at the 1st buffer of unfinished frame. */
5498 start_index
= frame_start_index
;
5502 *((unsigned long *)&(info
->rx_buffer_list
[start_index
++].count
)) = DMABUFFERSIZE
;
5504 /* Adjust index for wrap around. */
5505 if ( start_index
== info
->rx_buffer_count
)
5508 } while( start_index
!= end_index
);
5510 reprogram_dma
= TRUE
;
5513 if ( reprogram_dma
)
5515 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
5516 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5517 usc_UnlatchRxstatusBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5519 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5521 /* This empties the receive FIFO and loads the RCC with RCLR */
5522 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5524 /* program 16C32 with physical address of 1st DMA buffer entry */
5525 phys_addr
= info
->rx_buffer_list
[frame_start_index
].phys_entry
;
5526 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5527 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5529 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5530 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5531 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5533 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5534 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5536 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5537 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5538 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5539 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5540 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5542 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5546 /* This empties the receive FIFO and loads the RCC with RCLR */
5547 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5548 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5551 } /* end of usc_process_rxoverrun_sync() */
5553 /* usc_stop_receiver()
5555 * Disable USC receiver
5557 * Arguments: info pointer to device instance data
5558 * Return Value: None
5560 static void usc_stop_receiver( struct mgsl_struct
*info
)
5562 if (debug_level
>= DEBUG_LEVEL_ISR
)
5563 printk("%s(%d):usc_stop_receiver(%s)\n",
5564 __FILE__
,__LINE__
, info
->device_name
);
5566 /* Disable receive DMA channel. */
5567 /* This also disables receive DMA channel interrupts */
5568 usc_DmaCmd( info
, DmaCmd_ResetRxChannel
);
5570 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5571 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5572 usc_DisableInterrupts( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5574 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5576 /* This empties the receive FIFO and loads the RCC with RCLR */
5577 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5578 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5580 info
->rx_enabled
= 0;
5581 info
->rx_overflow
= 0;
5582 info
->rx_rcc_underrun
= 0;
5584 } /* end of stop_receiver() */
5586 /* usc_start_receiver()
5588 * Enable the USC receiver
5590 * Arguments: info pointer to device instance data
5591 * Return Value: None
5593 static void usc_start_receiver( struct mgsl_struct
*info
)
5597 if (debug_level
>= DEBUG_LEVEL_ISR
)
5598 printk("%s(%d):usc_start_receiver(%s)\n",
5599 __FILE__
,__LINE__
, info
->device_name
);
5601 mgsl_reset_rx_dma_buffers( info
);
5602 usc_stop_receiver( info
);
5604 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5605 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5607 if ( info
->params
.mode
== MGSL_MODE_HDLC
||
5608 info
->params
.mode
== MGSL_MODE_RAW
) {
5609 /* DMA mode Transfers */
5610 /* Program the DMA controller. */
5611 /* Enable the DMA controller end of buffer interrupt. */
5613 /* program 16C32 with physical address of 1st DMA buffer entry */
5614 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
5615 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5616 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5618 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5619 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5620 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5622 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5623 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5625 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5626 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5627 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5628 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5629 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5631 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5633 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
5634 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5635 usc_EnableInterrupts(info
, RECEIVE_DATA
);
5637 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5638 usc_RCmd( info
, RCmd_EnterHuntmode
);
5640 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5643 usc_OutReg( info
, CCSR
, 0x1020 );
5645 info
->rx_enabled
= 1;
5647 } /* end of usc_start_receiver() */
5649 /* usc_start_transmitter()
5651 * Enable the USC transmitter and send a transmit frame if
5652 * one is loaded in the DMA buffers.
5654 * Arguments: info pointer to device instance data
5655 * Return Value: None
5657 static void usc_start_transmitter( struct mgsl_struct
*info
)
5660 unsigned int FrameSize
;
5662 if (debug_level
>= DEBUG_LEVEL_ISR
)
5663 printk("%s(%d):usc_start_transmitter(%s)\n",
5664 __FILE__
,__LINE__
, info
->device_name
);
5666 if ( info
->xmit_cnt
) {
5668 /* If auto RTS enabled and RTS is inactive, then assert */
5669 /* RTS and set a flag indicating that the driver should */
5670 /* negate RTS when the transmission completes. */
5672 info
->drop_rts_on_tx_done
= 0;
5674 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
5675 usc_get_serial_signals( info
);
5676 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
5677 info
->serial_signals
|= SerialSignal_RTS
;
5678 usc_set_serial_signals( info
);
5679 info
->drop_rts_on_tx_done
= 1;
5684 if ( info
->params
.mode
== MGSL_MODE_ASYNC
) {
5685 if ( !info
->tx_active
) {
5686 usc_UnlatchTxstatusBits(info
, TXSTATUS_ALL
);
5687 usc_ClearIrqPendingBits(info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5688 usc_EnableInterrupts(info
, TRANSMIT_DATA
);
5689 usc_load_txfifo(info
);
5692 /* Disable transmit DMA controller while programming. */
5693 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5695 /* Transmit DMA buffer is loaded, so program USC */
5696 /* to send the frame contained in the buffers. */
5698 FrameSize
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
;
5700 /* if operating in Raw sync mode, reset the rcc component
5701 * of the tx dma buffer entry, otherwise, the serial controller
5702 * will send a closing sync char after this count.
5704 if ( info
->params
.mode
== MGSL_MODE_RAW
)
5705 info
->tx_buffer_list
[info
->start_tx_dma_buffer
].rcc
= 0;
5707 /* Program the Transmit Character Length Register (TCLR) */
5708 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5709 usc_OutReg( info
, TCLR
, (u16
)FrameSize
);
5711 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5713 /* Program the address of the 1st DMA Buffer Entry in linked list */
5714 phys_addr
= info
->tx_buffer_list
[info
->start_tx_dma_buffer
].phys_entry
;
5715 usc_OutDmaReg( info
, NTARL
, (u16
)phys_addr
);
5716 usc_OutDmaReg( info
, NTARU
, (u16
)(phys_addr
>> 16) );
5718 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5719 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
5720 usc_EnableInterrupts( info
, TRANSMIT_STATUS
);
5722 if ( info
->params
.mode
== MGSL_MODE_RAW
&&
5723 info
->num_tx_dma_buffers
> 1 ) {
5724 /* When running external sync mode, attempt to 'stream' transmit */
5725 /* by filling tx dma buffers as they become available. To do this */
5726 /* we need to enable Tx DMA EOB Status interrupts : */
5728 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5729 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5731 usc_OutDmaReg( info
, TDIAR
, BIT2
|BIT3
);
5732 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT0
) );
5735 /* Initialize Transmit DMA Channel */
5736 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
5738 usc_TCmd( info
, TCmd_SendFrame
);
5740 info
->tx_timer
.expires
= jiffies
+ msecs_to_jiffies(5000);
5741 add_timer(&info
->tx_timer
);
5743 info
->tx_active
= 1;
5746 if ( !info
->tx_enabled
) {
5747 info
->tx_enabled
= 1;
5748 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
5749 usc_EnableTransmitter(info
,ENABLE_AUTO_CTS
);
5751 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
5754 } /* end of usc_start_transmitter() */
5756 /* usc_stop_transmitter()
5758 * Stops the transmitter and DMA
5760 * Arguments: info pointer to device isntance data
5761 * Return Value: None
5763 static void usc_stop_transmitter( struct mgsl_struct
*info
)
5765 if (debug_level
>= DEBUG_LEVEL_ISR
)
5766 printk("%s(%d):usc_stop_transmitter(%s)\n",
5767 __FILE__
,__LINE__
, info
->device_name
);
5769 del_timer(&info
->tx_timer
);
5771 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5772 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5773 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5775 usc_EnableTransmitter(info
,DISABLE_UNCONDITIONAL
);
5776 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5777 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5779 info
->tx_enabled
= 0;
5780 info
->tx_active
= 0;
5782 } /* end of usc_stop_transmitter() */
5784 /* usc_load_txfifo()
5786 * Fill the transmit FIFO until the FIFO is full or
5787 * there is no more data to load.
5789 * Arguments: info pointer to device extension (instance data)
5790 * Return Value: None
5792 static void usc_load_txfifo( struct mgsl_struct
*info
)
5797 if ( !info
->xmit_cnt
&& !info
->x_char
)
5800 /* Select transmit FIFO status readback in TICR */
5801 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
5803 /* load the Transmit FIFO until FIFOs full or all data sent */
5805 while( (Fifocount
= usc_InReg(info
, TICR
) >> 8) && info
->xmit_cnt
) {
5806 /* there is more space in the transmit FIFO and */
5807 /* there is more data in transmit buffer */
5809 if ( (info
->xmit_cnt
> 1) && (Fifocount
> 1) && !info
->x_char
) {
5810 /* write a 16-bit word from transmit buffer to 16C32 */
5812 TwoBytes
[0] = info
->xmit_buf
[info
->xmit_tail
++];
5813 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5814 TwoBytes
[1] = info
->xmit_buf
[info
->xmit_tail
++];
5815 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5817 outw( *((u16
*)TwoBytes
), info
->io_base
+ DATAREG
);
5819 info
->xmit_cnt
-= 2;
5820 info
->icount
.tx
+= 2;
5822 /* only 1 byte left to transmit or 1 FIFO slot left */
5824 outw( (inw( info
->io_base
+ CCAR
) & 0x0780) | (TDR
+LSBONLY
),
5825 info
->io_base
+ CCAR
);
5828 /* transmit pending high priority char */
5829 outw( info
->x_char
,info
->io_base
+ CCAR
);
5832 outw( info
->xmit_buf
[info
->xmit_tail
++],info
->io_base
+ CCAR
);
5833 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5840 } /* end of usc_load_txfifo() */
5844 * Reset the adapter to a known state and prepare it for further use.
5846 * Arguments: info pointer to device instance data
5847 * Return Value: None
5849 static void usc_reset( struct mgsl_struct
*info
)
5851 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5855 /* Set BIT30 of Misc Control Register */
5856 /* (Local Control Register 0x50) to force reset of USC. */
5858 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5859 u32
*LCR0BRDR
= (u32
*)(info
->lcr_base
+ 0x28);
5861 info
->misc_ctrl_value
|= BIT30
;
5862 *MiscCtrl
= info
->misc_ctrl_value
;
5865 * Force at least 170ns delay before clearing
5866 * reset bit. Each read from LCR takes at least
5867 * 30ns so 10 times for 300ns to be safe.
5870 readval
= *MiscCtrl
;
5872 info
->misc_ctrl_value
&= ~BIT30
;
5873 *MiscCtrl
= info
->misc_ctrl_value
;
5875 *LCR0BRDR
= BUS_DESCRIPTOR(
5876 1, // Write Strobe Hold (0-3)
5877 2, // Write Strobe Delay (0-3)
5878 2, // Read Strobe Delay (0-3)
5879 0, // NWDD (Write data-data) (0-3)
5880 4, // NWAD (Write Addr-data) (0-31)
5881 0, // NXDA (Read/Write Data-Addr) (0-3)
5882 0, // NRDD (Read Data-Data) (0-3)
5883 5 // NRAD (Read Addr-Data) (0-31)
5887 outb( 0,info
->io_base
+ 8 );
5891 info
->loopback_bits
= 0;
5892 info
->usc_idle_mode
= 0;
5895 * Program the Bus Configuration Register (BCR)
5897 * <15> 0 Don't use separate address
5898 * <14..6> 0 reserved
5899 * <5..4> 00 IAckmode = Default, don't care
5900 * <3> 1 Bus Request Totem Pole output
5901 * <2> 1 Use 16 Bit data bus
5902 * <1> 0 IRQ Totem Pole output
5903 * <0> 0 Don't Shift Right Addr
5905 * 0000 0000 0000 1100 = 0x000c
5907 * By writing to io_base + SDPIN the Wait/Ack pin is
5908 * programmed to work as a Wait pin.
5911 outw( 0x000c,info
->io_base
+ SDPIN
);
5914 outw( 0,info
->io_base
);
5915 outw( 0,info
->io_base
+ CCAR
);
5917 /* select little endian byte ordering */
5918 usc_RTCmd( info
, RTCmd_SelectLittleEndian
);
5921 /* Port Control Register (PCR)
5923 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5924 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5925 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5926 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5927 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5928 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5929 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5930 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5932 * 1111 0000 1111 0101 = 0xf0f5
5935 usc_OutReg( info
, PCR
, 0xf0f5 );
5939 * Input/Output Control Register
5941 * <15..14> 00 CTS is active low input
5942 * <13..12> 00 DCD is active low input
5943 * <11..10> 00 TxREQ pin is input (DSR)
5944 * <9..8> 00 RxREQ pin is input (RI)
5945 * <7..6> 00 TxD is output (Transmit Data)
5946 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5947 * <2..0> 100 RxC is Output (drive with BRG0)
5949 * 0000 0000 0000 0100 = 0x0004
5952 usc_OutReg( info
, IOCR
, 0x0004 );
5954 } /* end of usc_reset() */
5956 /* usc_set_async_mode()
5958 * Program adapter for asynchronous communications.
5960 * Arguments: info pointer to device instance data
5961 * Return Value: None
5963 static void usc_set_async_mode( struct mgsl_struct
*info
)
5967 /* disable interrupts while programming USC */
5968 usc_DisableMasterIrqBit( info
);
5970 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5971 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5973 usc_loopback_frame( info
);
5975 /* Channel mode Register (CMR)
5977 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5978 * <13..12> 00 00 = 16X Clock
5979 * <11..8> 0000 Transmitter mode = Asynchronous
5980 * <7..6> 00 reserved?
5981 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5982 * <3..0> 0000 Receiver mode = Asynchronous
5984 * 0000 0000 0000 0000 = 0x0
5988 if ( info
->params
.stop_bits
!= 1 )
5990 usc_OutReg( info
, CMR
, RegValue
);
5993 /* Receiver mode Register (RMR)
5995 * <15..13> 000 encoding = None
5996 * <12..08> 00000 reserved (Sync Only)
5997 * <7..6> 00 Even parity
5998 * <5> 0 parity disabled
5999 * <4..2> 000 Receive Char Length = 8 bits
6000 * <1..0> 00 Disable Receiver
6002 * 0000 0000 0000 0000 = 0x0
6007 if ( info
->params
.data_bits
!= 8 )
6008 RegValue
|= BIT4
+BIT3
+BIT2
;
6010 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
6012 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
6016 usc_OutReg( info
, RMR
, RegValue
);
6019 /* Set IRQ trigger level */
6021 usc_RCmd( info
, RCmd_SelectRicrIntLevel
);
6024 /* Receive Interrupt Control Register (RICR)
6026 * <15..8> ? RxFIFO IRQ Request Level
6028 * Note: For async mode the receive FIFO level must be set
6029 * to 0 to aviod the situation where the FIFO contains fewer bytes
6030 * than the trigger level and no more data is expected.
6032 * <7> 0 Exited Hunt IA (Interrupt Arm)
6033 * <6> 0 Idle Received IA
6034 * <5> 0 Break/Abort IA
6036 * <3> 0 Queued status reflects oldest byte in FIFO
6038 * <1> 0 Rx Overrun IA
6039 * <0> 0 Select TC0 value for readback
6041 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
6044 usc_OutReg( info
, RICR
, 0x0000 );
6046 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
6047 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
6050 /* Transmit mode Register (TMR)
6052 * <15..13> 000 encoding = None
6053 * <12..08> 00000 reserved (Sync Only)
6054 * <7..6> 00 Transmit parity Even
6055 * <5> 0 Transmit parity Disabled
6056 * <4..2> 000 Tx Char Length = 8 bits
6057 * <1..0> 00 Disable Transmitter
6059 * 0000 0000 0000 0000 = 0x0
6064 if ( info
->params
.data_bits
!= 8 )
6065 RegValue
|= BIT4
+BIT3
+BIT2
;
6067 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
6069 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
6073 usc_OutReg( info
, TMR
, RegValue
);
6075 usc_set_txidle( info
);
6078 /* Set IRQ trigger level */
6080 usc_TCmd( info
, TCmd_SelectTicrIntLevel
);
6083 /* Transmit Interrupt Control Register (TICR)
6085 * <15..8> ? Transmit FIFO IRQ Level
6086 * <7> 0 Present IA (Interrupt Arm)
6087 * <6> 1 Idle Sent IA
6088 * <5> 0 Abort Sent IA
6089 * <4> 0 EOF/EOM Sent IA
6091 * <2> 0 1 = Wait for SW Trigger to Start Frame
6092 * <1> 0 Tx Underrun IA
6093 * <0> 0 TC0 constant on read back
6095 * 0000 0000 0100 0000 = 0x0040
6098 usc_OutReg( info
, TICR
, 0x1f40 );
6100 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
6101 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
6103 usc_enable_async_clock( info
, info
->params
.data_rate
);
6106 /* Channel Control/status Register (CCSR)
6108 * <15> X RCC FIFO Overflow status (RO)
6109 * <14> X RCC FIFO Not Empty status (RO)
6110 * <13> 0 1 = Clear RCC FIFO (WO)
6111 * <12> X DPLL in Sync status (RO)
6112 * <11> X DPLL 2 Missed Clocks status (RO)
6113 * <10> X DPLL 1 Missed Clock status (RO)
6114 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6115 * <7> X SDLC Loop On status (RO)
6116 * <6> X SDLC Loop Send status (RO)
6117 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6118 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6119 * <1..0> 00 reserved
6121 * 0000 0000 0010 0000 = 0x0020
6124 usc_OutReg( info
, CCSR
, 0x0020 );
6126 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6127 RECEIVE_DATA
+ RECEIVE_STATUS
);
6129 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
6130 RECEIVE_DATA
+ RECEIVE_STATUS
);
6132 usc_EnableMasterIrqBit( info
);
6134 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6135 /* Enable INTEN (Port 6, Bit12) */
6136 /* This connects the IRQ request signal to the ISA bus */
6137 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6140 if (info
->params
.loopback
) {
6141 info
->loopback_bits
= 0x300;
6142 outw(0x0300, info
->io_base
+ CCAR
);
6145 } /* end of usc_set_async_mode() */
6147 /* usc_loopback_frame()
6149 * Loop back a small (2 byte) dummy SDLC frame.
6150 * Interrupts and DMA are NOT used. The purpose of this is to
6151 * clear any 'stale' status info left over from running in async mode.
6153 * The 16C32 shows the strange behaviour of marking the 1st
6154 * received SDLC frame with a CRC error even when there is no
6155 * CRC error. To get around this a small dummy from of 2 bytes
6156 * is looped back when switching from async to sync mode.
6158 * Arguments: info pointer to device instance data
6159 * Return Value: None
6161 static void usc_loopback_frame( struct mgsl_struct
*info
)
6164 unsigned long oldmode
= info
->params
.mode
;
6166 info
->params
.mode
= MGSL_MODE_HDLC
;
6168 usc_DisableMasterIrqBit( info
);
6170 usc_set_sdlc_mode( info
);
6171 usc_enable_loopback( info
, 1 );
6173 /* Write 16-bit Time Constant for BRG0 */
6174 usc_OutReg( info
, TC0R
, 0 );
6176 /* Channel Control Register (CCR)
6178 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6179 * <13> 0 Trigger Tx on SW Command Disabled
6180 * <12> 0 Flag Preamble Disabled
6181 * <11..10> 00 Preamble Length = 8-Bits
6182 * <9..8> 01 Preamble Pattern = flags
6183 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6184 * <5> 0 Trigger Rx on SW Command Disabled
6187 * 0000 0001 0000 0000 = 0x0100
6190 usc_OutReg( info
, CCR
, 0x0100 );
6192 /* SETUP RECEIVER */
6193 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
6194 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
6196 /* SETUP TRANSMITTER */
6197 /* Program the Transmit Character Length Register (TCLR) */
6198 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6199 usc_OutReg( info
, TCLR
, 2 );
6200 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
6202 /* unlatch Tx status bits, and start transmit channel. */
6203 usc_UnlatchTxstatusBits(info
,TXSTATUS_ALL
);
6204 outw(0,info
->io_base
+ DATAREG
);
6206 /* ENABLE TRANSMITTER */
6207 usc_TCmd( info
, TCmd_SendFrame
);
6208 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
6210 /* WAIT FOR RECEIVE COMPLETE */
6211 for (i
=0 ; i
<1000 ; i
++)
6212 if (usc_InReg( info
, RCSR
) & (BIT8
+ BIT4
+ BIT3
+ BIT1
))
6215 /* clear Internal Data loopback mode */
6216 usc_enable_loopback(info
, 0);
6218 usc_EnableMasterIrqBit(info
);
6220 info
->params
.mode
= oldmode
;
6222 } /* end of usc_loopback_frame() */
6224 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6226 * Arguments: info pointer to adapter info structure
6227 * Return Value: None
6229 static void usc_set_sync_mode( struct mgsl_struct
*info
)
6231 usc_loopback_frame( info
);
6232 usc_set_sdlc_mode( info
);
6234 if (info
->bus_type
== MGSL_BUS_TYPE_ISA
) {
6235 /* Enable INTEN (Port 6, Bit12) */
6236 /* This connects the IRQ request signal to the ISA bus */
6237 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6240 usc_enable_aux_clock(info
, info
->params
.clock_speed
);
6242 if (info
->params
.loopback
)
6243 usc_enable_loopback(info
,1);
6245 } /* end of mgsl_set_sync_mode() */
6247 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6249 * Arguments: info pointer to device instance data
6250 * Return Value: None
6252 static void usc_set_txidle( struct mgsl_struct
*info
)
6254 u16 usc_idle_mode
= IDLEMODE_FLAGS
;
6256 /* Map API idle mode to USC register bits */
6258 switch( info
->idle_mode
){
6259 case HDLC_TXIDLE_FLAGS
: usc_idle_mode
= IDLEMODE_FLAGS
; break;
6260 case HDLC_TXIDLE_ALT_ZEROS_ONES
: usc_idle_mode
= IDLEMODE_ALT_ONE_ZERO
; break;
6261 case HDLC_TXIDLE_ZEROS
: usc_idle_mode
= IDLEMODE_ZERO
; break;
6262 case HDLC_TXIDLE_ONES
: usc_idle_mode
= IDLEMODE_ONE
; break;
6263 case HDLC_TXIDLE_ALT_MARK_SPACE
: usc_idle_mode
= IDLEMODE_ALT_MARK_SPACE
; break;
6264 case HDLC_TXIDLE_SPACE
: usc_idle_mode
= IDLEMODE_SPACE
; break;
6265 case HDLC_TXIDLE_MARK
: usc_idle_mode
= IDLEMODE_MARK
; break;
6268 info
->usc_idle_mode
= usc_idle_mode
;
6269 //usc_OutReg(info, TCSR, usc_idle_mode);
6270 info
->tcsr_value
&= ~IDLEMODE_MASK
; /* clear idle mode bits */
6271 info
->tcsr_value
+= usc_idle_mode
;
6272 usc_OutReg(info
, TCSR
, info
->tcsr_value
);
6275 * if SyncLink WAN adapter is running in external sync mode, the
6276 * transmitter has been set to Monosync in order to try to mimic
6277 * a true raw outbound bit stream. Monosync still sends an open/close
6278 * sync char at the start/end of a frame. Try to match those sync
6279 * patterns to the idle mode set here
6281 if ( info
->params
.mode
== MGSL_MODE_RAW
) {
6282 unsigned char syncpat
= 0;
6283 switch( info
->idle_mode
) {
6284 case HDLC_TXIDLE_FLAGS
:
6287 case HDLC_TXIDLE_ALT_ZEROS_ONES
:
6290 case HDLC_TXIDLE_ZEROS
:
6291 case HDLC_TXIDLE_SPACE
:
6294 case HDLC_TXIDLE_ONES
:
6295 case HDLC_TXIDLE_MARK
:
6298 case HDLC_TXIDLE_ALT_MARK_SPACE
:
6303 usc_SetTransmitSyncChars(info
,syncpat
,syncpat
);
6306 } /* end of usc_set_txidle() */
6308 /* usc_get_serial_signals()
6310 * Query the adapter for the state of the V24 status (input) signals.
6312 * Arguments: info pointer to device instance data
6313 * Return Value: None
6315 static void usc_get_serial_signals( struct mgsl_struct
*info
)
6319 /* clear all serial signals except DTR and RTS */
6320 info
->serial_signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
6322 /* Read the Misc Interrupt status Register (MISR) to get */
6323 /* the V24 status signals. */
6325 status
= usc_InReg( info
, MISR
);
6327 /* set serial signal bits to reflect MISR */
6329 if ( status
& MISCSTATUS_CTS
)
6330 info
->serial_signals
|= SerialSignal_CTS
;
6332 if ( status
& MISCSTATUS_DCD
)
6333 info
->serial_signals
|= SerialSignal_DCD
;
6335 if ( status
& MISCSTATUS_RI
)
6336 info
->serial_signals
|= SerialSignal_RI
;
6338 if ( status
& MISCSTATUS_DSR
)
6339 info
->serial_signals
|= SerialSignal_DSR
;
6341 } /* end of usc_get_serial_signals() */
6343 /* usc_set_serial_signals()
6345 * Set the state of DTR and RTS based on contents of
6346 * serial_signals member of device extension.
6348 * Arguments: info pointer to device instance data
6349 * Return Value: None
6351 static void usc_set_serial_signals( struct mgsl_struct
*info
)
6354 unsigned char V24Out
= info
->serial_signals
;
6356 /* get the current value of the Port Control Register (PCR) */
6358 Control
= usc_InReg( info
, PCR
);
6360 if ( V24Out
& SerialSignal_RTS
)
6365 if ( V24Out
& SerialSignal_DTR
)
6370 usc_OutReg( info
, PCR
, Control
);
6372 } /* end of usc_set_serial_signals() */
6374 /* usc_enable_async_clock()
6376 * Enable the async clock at the specified frequency.
6378 * Arguments: info pointer to device instance data
6379 * data_rate data rate of clock in bps
6380 * 0 disables the AUX clock.
6381 * Return Value: None
6383 static void usc_enable_async_clock( struct mgsl_struct
*info
, u32 data_rate
)
6387 * Clock mode Control Register (CMCR)
6389 * <15..14> 00 counter 1 Disabled
6390 * <13..12> 00 counter 0 Disabled
6391 * <11..10> 11 BRG1 Input is TxC Pin
6392 * <9..8> 11 BRG0 Input is TxC Pin
6393 * <7..6> 01 DPLL Input is BRG1 Output
6394 * <5..3> 100 TxCLK comes from BRG0
6395 * <2..0> 100 RxCLK comes from BRG0
6397 * 0000 1111 0110 0100 = 0x0f64
6400 usc_OutReg( info
, CMCR
, 0x0f64 );
6404 * Write 16-bit Time Constant for BRG0
6405 * Time Constant = (ClkSpeed / data_rate) - 1
6406 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6409 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6410 usc_OutReg( info
, TC0R
, (u16
)((691200/data_rate
) - 1) );
6412 usc_OutReg( info
, TC0R
, (u16
)((921600/data_rate
) - 1) );
6416 * Hardware Configuration Register (HCR)
6417 * Clear Bit 1, BRG0 mode = Continuous
6418 * Set Bit 0 to enable BRG0.
6421 usc_OutReg( info
, HCR
,
6422 (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
6425 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6427 usc_OutReg( info
, IOCR
,
6428 (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
6430 /* data rate == 0 so turn off BRG0 */
6431 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
6434 } /* end of usc_enable_async_clock() */
6437 * Buffer Structures:
6439 * Normal memory access uses virtual addresses that can make discontiguous
6440 * physical memory pages appear to be contiguous in the virtual address
6441 * space (the processors memory mapping handles the conversions).
6443 * DMA transfers require physically contiguous memory. This is because
6444 * the DMA system controller and DMA bus masters deal with memory using
6445 * only physical addresses.
6447 * This causes a problem under Windows NT when large DMA buffers are
6448 * needed. Fragmentation of the nonpaged pool prevents allocations of
6449 * physically contiguous buffers larger than the PAGE_SIZE.
6451 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6452 * allows DMA transfers to physically discontiguous buffers. Information
6453 * about each data transfer buffer is contained in a memory structure
6454 * called a 'buffer entry'. A list of buffer entries is maintained
6455 * to track and control the use of the data transfer buffers.
6457 * To support this strategy we will allocate sufficient PAGE_SIZE
6458 * contiguous memory buffers to allow for the total required buffer
6461 * The 16C32 accesses the list of buffer entries using Bus Master
6462 * DMA. Control information is read from the buffer entries by the
6463 * 16C32 to control data transfers. status information is written to
6464 * the buffer entries by the 16C32 to indicate the status of completed
6467 * The CPU writes control information to the buffer entries to control
6468 * the 16C32 and reads status information from the buffer entries to
6469 * determine information about received and transmitted frames.
6471 * Because the CPU and 16C32 (adapter) both need simultaneous access
6472 * to the buffer entries, the buffer entry memory is allocated with
6473 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6474 * entry list to PAGE_SIZE.
6476 * The actual data buffers on the other hand will only be accessed
6477 * by the CPU or the adapter but not by both simultaneously. This allows
6478 * Scatter/Gather packet based DMA procedures for using physically
6479 * discontiguous pages.
6483 * mgsl_reset_tx_dma_buffers()
6485 * Set the count for all transmit buffers to 0 to indicate the
6486 * buffer is available for use and set the current buffer to the
6487 * first buffer. This effectively makes all buffers free and
6488 * discards any data in buffers.
6490 * Arguments: info pointer to device instance data
6491 * Return Value: None
6493 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct
*info
)
6497 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
6498 *((unsigned long *)&(info
->tx_buffer_list
[i
].count
)) = 0;
6501 info
->current_tx_buffer
= 0;
6502 info
->start_tx_dma_buffer
= 0;
6503 info
->tx_dma_buffers_used
= 0;
6505 info
->get_tx_holding_index
= 0;
6506 info
->put_tx_holding_index
= 0;
6507 info
->tx_holding_count
= 0;
6509 } /* end of mgsl_reset_tx_dma_buffers() */
6512 * num_free_tx_dma_buffers()
6514 * returns the number of free tx dma buffers available
6516 * Arguments: info pointer to device instance data
6517 * Return Value: number of free tx dma buffers
6519 static int num_free_tx_dma_buffers(struct mgsl_struct
*info
)
6521 return info
->tx_buffer_count
- info
->tx_dma_buffers_used
;
6525 * mgsl_reset_rx_dma_buffers()
6527 * Set the count for all receive buffers to DMABUFFERSIZE
6528 * and set the current buffer to the first buffer. This effectively
6529 * makes all buffers free and discards any data in buffers.
6531 * Arguments: info pointer to device instance data
6532 * Return Value: None
6534 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
)
6538 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
6539 *((unsigned long *)&(info
->rx_buffer_list
[i
].count
)) = DMABUFFERSIZE
;
6540 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6541 // info->rx_buffer_list[i].status = 0;
6544 info
->current_rx_buffer
= 0;
6546 } /* end of mgsl_reset_rx_dma_buffers() */
6549 * mgsl_free_rx_frame_buffers()
6551 * Free the receive buffers used by a received SDLC
6552 * frame such that the buffers can be reused.
6556 * info pointer to device instance data
6557 * StartIndex index of 1st receive buffer of frame
6558 * EndIndex index of last receive buffer of frame
6560 * Return Value: None
6562 static void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
)
6565 DMABUFFERENTRY
*pBufEntry
;
6568 /* Starting with 1st buffer entry of the frame clear the status */
6569 /* field and set the count field to DMA Buffer Size. */
6574 pBufEntry
= &(info
->rx_buffer_list
[Index
]);
6576 if ( Index
== EndIndex
) {
6577 /* This is the last buffer of the frame! */
6581 /* reset current buffer for reuse */
6582 // pBufEntry->status = 0;
6583 // pBufEntry->count = DMABUFFERSIZE;
6584 *((unsigned long *)&(pBufEntry
->count
)) = DMABUFFERSIZE
;
6586 /* advance to next buffer entry in linked list */
6588 if ( Index
== info
->rx_buffer_count
)
6592 /* set current buffer to next buffer after last buffer of frame */
6593 info
->current_rx_buffer
= Index
;
6595 } /* end of free_rx_frame_buffers() */
6597 /* mgsl_get_rx_frame()
6599 * This function attempts to return a received SDLC frame from the
6600 * receive DMA buffers. Only frames received without errors are returned.
6602 * Arguments: info pointer to device extension
6603 * Return Value: 1 if frame returned, otherwise 0
6605 static int mgsl_get_rx_frame(struct mgsl_struct
*info
)
6607 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
6608 unsigned short status
;
6609 DMABUFFERENTRY
*pBufEntry
;
6610 unsigned int framesize
= 0;
6612 unsigned long flags
;
6613 struct tty_struct
*tty
= info
->tty
;
6614 int return_frame
= 0;
6617 * current_rx_buffer points to the 1st buffer of the next available
6618 * receive frame. To find the last buffer of the frame look for
6619 * a non-zero status field in the buffer entries. (The status
6620 * field is set by the 16C32 after completing a receive frame.
6623 StartIndex
= EndIndex
= info
->current_rx_buffer
;
6625 while( !info
->rx_buffer_list
[EndIndex
].status
) {
6627 * If the count field of the buffer entry is non-zero then
6628 * this buffer has not been used. (The 16C32 clears the count
6629 * field when it starts using the buffer.) If an unused buffer
6630 * is encountered then there are no frames available.
6633 if ( info
->rx_buffer_list
[EndIndex
].count
)
6636 /* advance to next buffer entry in linked list */
6638 if ( EndIndex
== info
->rx_buffer_count
)
6641 /* if entire list searched then no frame available */
6642 if ( EndIndex
== StartIndex
) {
6643 /* If this occurs then something bad happened,
6644 * all buffers have been 'used' but none mark
6645 * the end of a frame. Reset buffers and receiver.
6648 if ( info
->rx_enabled
){
6649 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6650 usc_start_receiver(info
);
6651 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6658 /* check status of receive frame */
6660 status
= info
->rx_buffer_list
[EndIndex
].status
;
6662 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6663 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6664 if ( status
& RXSTATUS_SHORT_FRAME
)
6665 info
->icount
.rxshort
++;
6666 else if ( status
& RXSTATUS_ABORT
)
6667 info
->icount
.rxabort
++;
6668 else if ( status
& RXSTATUS_OVERRUN
)
6669 info
->icount
.rxover
++;
6671 info
->icount
.rxcrc
++;
6672 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
)
6678 struct net_device_stats
*stats
= hdlc_stats(info
->netdev
);
6680 stats
->rx_frame_errors
++;
6686 if ( return_frame
) {
6687 /* receive frame has no errors, get frame size.
6688 * The frame size is the starting value of the RCC (which was
6689 * set to 0xffff) minus the ending value of the RCC (decremented
6690 * once for each receive character) minus 2 for the 16-bit CRC.
6693 framesize
= RCLRVALUE
- info
->rx_buffer_list
[EndIndex
].rcc
;
6695 /* adjust frame size for CRC if any */
6696 if ( info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
6698 else if ( info
->params
.crc_type
== HDLC_CRC_32_CCITT
)
6702 if ( debug_level
>= DEBUG_LEVEL_BH
)
6703 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6704 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6706 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6707 mgsl_trace_block(info
,info
->rx_buffer_list
[StartIndex
].virt_addr
,
6708 min_t(int, framesize
, DMABUFFERSIZE
),0);
6711 if ( ( (info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) &&
6712 ((framesize
+1) > info
->max_frame_size
) ) ||
6713 (framesize
> info
->max_frame_size
) )
6714 info
->icount
.rxlong
++;
6716 /* copy dma buffer(s) to contiguous intermediate buffer */
6717 int copy_count
= framesize
;
6718 int index
= StartIndex
;
6719 unsigned char *ptmp
= info
->intermediate_rxbuffer
;
6721 if ( !(status
& RXSTATUS_CRC_ERROR
))
6722 info
->icount
.rxok
++;
6726 if ( copy_count
> DMABUFFERSIZE
)
6727 partial_count
= DMABUFFERSIZE
;
6729 partial_count
= copy_count
;
6731 pBufEntry
= &(info
->rx_buffer_list
[index
]);
6732 memcpy( ptmp
, pBufEntry
->virt_addr
, partial_count
);
6733 ptmp
+= partial_count
;
6734 copy_count
-= partial_count
;
6736 if ( ++index
== info
->rx_buffer_count
)
6740 if ( info
->params
.crc_type
& HDLC_CRC_RETURN_EX
) {
6742 *ptmp
= (status
& RXSTATUS_CRC_ERROR
?
6746 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6747 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6748 __FILE__
,__LINE__
,info
->device_name
,
6754 hdlcdev_rx(info
,info
->intermediate_rxbuffer
,framesize
);
6757 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6760 /* Free the buffers used by this frame. */
6761 mgsl_free_rx_frame_buffers( info
, StartIndex
, EndIndex
);
6767 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6768 /* The receiver needs to restarted because of
6769 * a receive overflow (buffer or FIFO). If the
6770 * receive buffers are now empty, then restart receiver.
6773 if ( !info
->rx_buffer_list
[EndIndex
].status
&&
6774 info
->rx_buffer_list
[EndIndex
].count
) {
6775 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6776 usc_start_receiver(info
);
6777 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6783 } /* end of mgsl_get_rx_frame() */
6785 /* mgsl_get_raw_rx_frame()
6787 * This function attempts to return a received frame from the
6788 * receive DMA buffers when running in external loop mode. In this mode,
6789 * we will return at most one DMABUFFERSIZE frame to the application.
6790 * The USC receiver is triggering off of DCD going active to start a new
6791 * frame, and DCD going inactive to terminate the frame (similar to
6792 * processing a closing flag character).
6794 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6795 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6796 * status field and the RCC field will indicate the length of the
6797 * entire received frame. We take this RCC field and get the modulus
6798 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6799 * last Rx DMA buffer and return that last portion of the frame.
6801 * Arguments: info pointer to device extension
6802 * Return Value: 1 if frame returned, otherwise 0
6804 static int mgsl_get_raw_rx_frame(struct mgsl_struct
*info
)
6806 unsigned int CurrentIndex
, NextIndex
;
6807 unsigned short status
;
6808 DMABUFFERENTRY
*pBufEntry
;
6809 unsigned int framesize
= 0;
6811 unsigned long flags
;
6812 struct tty_struct
*tty
= info
->tty
;
6815 * current_rx_buffer points to the 1st buffer of the next available
6816 * receive frame. The status field is set by the 16C32 after
6817 * completing a receive frame. If the status field of this buffer
6818 * is zero, either the USC is still filling this buffer or this
6819 * is one of a series of buffers making up a received frame.
6821 * If the count field of this buffer is zero, the USC is either
6822 * using this buffer or has used this buffer. Look at the count
6823 * field of the next buffer. If that next buffer's count is
6824 * non-zero, the USC is still actively using the current buffer.
6825 * Otherwise, if the next buffer's count field is zero, the
6826 * current buffer is complete and the USC is using the next
6829 CurrentIndex
= NextIndex
= info
->current_rx_buffer
;
6831 if ( NextIndex
== info
->rx_buffer_count
)
6834 if ( info
->rx_buffer_list
[CurrentIndex
].status
!= 0 ||
6835 (info
->rx_buffer_list
[CurrentIndex
].count
== 0 &&
6836 info
->rx_buffer_list
[NextIndex
].count
== 0)) {
6838 * Either the status field of this dma buffer is non-zero
6839 * (indicating the last buffer of a receive frame) or the next
6840 * buffer is marked as in use -- implying this buffer is complete
6841 * and an intermediate buffer for this received frame.
6844 status
= info
->rx_buffer_list
[CurrentIndex
].status
;
6846 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6847 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6848 if ( status
& RXSTATUS_SHORT_FRAME
)
6849 info
->icount
.rxshort
++;
6850 else if ( status
& RXSTATUS_ABORT
)
6851 info
->icount
.rxabort
++;
6852 else if ( status
& RXSTATUS_OVERRUN
)
6853 info
->icount
.rxover
++;
6855 info
->icount
.rxcrc
++;
6859 * A receive frame is available, get frame size and status.
6861 * The frame size is the starting value of the RCC (which was
6862 * set to 0xffff) minus the ending value of the RCC (decremented
6863 * once for each receive character) minus 2 or 4 for the 16-bit
6866 * If the status field is zero, this is an intermediate buffer.
6869 * If the DMA Buffer Entry's Status field is non-zero, the
6870 * receive operation completed normally (ie: DCD dropped). The
6871 * RCC field is valid and holds the received frame size.
6872 * It is possible that the RCC field will be zero on a DMA buffer
6873 * entry with a non-zero status. This can occur if the total
6874 * frame size (number of bytes between the time DCD goes active
6875 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6876 * case the 16C32 has underrun on the RCC count and appears to
6877 * stop updating this counter to let us know the actual received
6878 * frame size. If this happens (non-zero status and zero RCC),
6879 * simply return the entire RxDMA Buffer
6883 * In the event that the final RxDMA Buffer is
6884 * terminated with a non-zero status and the RCC
6885 * field is zero, we interpret this as the RCC
6886 * having underflowed (received frame > 65535 bytes).
6888 * Signal the event to the user by passing back
6889 * a status of RxStatus_CrcError returning the full
6890 * buffer and let the app figure out what data is
6893 if ( info
->rx_buffer_list
[CurrentIndex
].rcc
)
6894 framesize
= RCLRVALUE
- info
->rx_buffer_list
[CurrentIndex
].rcc
;
6896 framesize
= DMABUFFERSIZE
;
6899 framesize
= DMABUFFERSIZE
;
6902 if ( framesize
> DMABUFFERSIZE
) {
6904 * if running in raw sync mode, ISR handler for
6905 * End Of Buffer events terminates all buffers at 4K.
6906 * If this frame size is said to be >4K, get the
6907 * actual number of bytes of the frame in this buffer.
6909 framesize
= framesize
% DMABUFFERSIZE
;
6913 if ( debug_level
>= DEBUG_LEVEL_BH
)
6914 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6915 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6917 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6918 mgsl_trace_block(info
,info
->rx_buffer_list
[CurrentIndex
].virt_addr
,
6919 min_t(int, framesize
, DMABUFFERSIZE
),0);
6922 /* copy dma buffer(s) to contiguous intermediate buffer */
6923 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6925 pBufEntry
= &(info
->rx_buffer_list
[CurrentIndex
]);
6926 memcpy( info
->intermediate_rxbuffer
, pBufEntry
->virt_addr
, framesize
);
6927 info
->icount
.rxok
++;
6929 ldisc_receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6932 /* Free the buffers used by this frame. */
6933 mgsl_free_rx_frame_buffers( info
, CurrentIndex
, CurrentIndex
);
6939 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6940 /* The receiver needs to restarted because of
6941 * a receive overflow (buffer or FIFO). If the
6942 * receive buffers are now empty, then restart receiver.
6945 if ( !info
->rx_buffer_list
[CurrentIndex
].status
&&
6946 info
->rx_buffer_list
[CurrentIndex
].count
) {
6947 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6948 usc_start_receiver(info
);
6949 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6955 } /* end of mgsl_get_raw_rx_frame() */
6957 /* mgsl_load_tx_dma_buffer()
6959 * Load the transmit DMA buffer with the specified data.
6963 * info pointer to device extension
6964 * Buffer pointer to buffer containing frame to load
6965 * BufferSize size in bytes of frame in Buffer
6967 * Return Value: None
6969 static void mgsl_load_tx_dma_buffer(struct mgsl_struct
*info
,
6970 const char *Buffer
, unsigned int BufferSize
)
6972 unsigned short Copycount
;
6974 DMABUFFERENTRY
*pBufEntry
;
6976 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6977 mgsl_trace_block(info
,Buffer
, min_t(int, BufferSize
, DMABUFFERSIZE
), 1);
6979 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
6980 /* set CMR:13 to start transmit when
6981 * next GoAhead (abort) is received
6983 info
->cmr_value
|= BIT13
;
6986 /* begin loading the frame in the next available tx dma
6987 * buffer, remember it's starting location for setting
6988 * up tx dma operation
6990 i
= info
->current_tx_buffer
;
6991 info
->start_tx_dma_buffer
= i
;
6993 /* Setup the status and RCC (Frame Size) fields of the 1st */
6994 /* buffer entry in the transmit DMA buffer list. */
6996 info
->tx_buffer_list
[i
].status
= info
->cmr_value
& 0xf000;
6997 info
->tx_buffer_list
[i
].rcc
= BufferSize
;
6998 info
->tx_buffer_list
[i
].count
= BufferSize
;
7000 /* Copy frame data from 1st source buffer to the DMA buffers. */
7001 /* The frame data may span multiple DMA buffers. */
7003 while( BufferSize
){
7004 /* Get a pointer to next DMA buffer entry. */
7005 pBufEntry
= &info
->tx_buffer_list
[i
++];
7007 if ( i
== info
->tx_buffer_count
)
7010 /* Calculate the number of bytes that can be copied from */
7011 /* the source buffer to this DMA buffer. */
7012 if ( BufferSize
> DMABUFFERSIZE
)
7013 Copycount
= DMABUFFERSIZE
;
7015 Copycount
= BufferSize
;
7017 /* Actually copy data from source buffer to DMA buffer. */
7018 /* Also set the data count for this individual DMA buffer. */
7019 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
7020 mgsl_load_pci_memory(pBufEntry
->virt_addr
, Buffer
,Copycount
);
7022 memcpy(pBufEntry
->virt_addr
, Buffer
, Copycount
);
7024 pBufEntry
->count
= Copycount
;
7026 /* Advance source pointer and reduce remaining data count. */
7027 Buffer
+= Copycount
;
7028 BufferSize
-= Copycount
;
7030 ++info
->tx_dma_buffers_used
;
7033 /* remember next available tx dma buffer */
7034 info
->current_tx_buffer
= i
;
7036 } /* end of mgsl_load_tx_dma_buffer() */
7039 * mgsl_register_test()
7041 * Performs a register test of the 16C32.
7043 * Arguments: info pointer to device instance data
7044 * Return Value: TRUE if test passed, otherwise FALSE
7046 static BOOLEAN
mgsl_register_test( struct mgsl_struct
*info
)
7048 static unsigned short BitPatterns
[] =
7049 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
7050 static unsigned int Patterncount
= ARRAY_SIZE(BitPatterns
);
7053 unsigned long flags
;
7055 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7058 /* Verify the reset state of some registers. */
7060 if ( (usc_InReg( info
, SICR
) != 0) ||
7061 (usc_InReg( info
, IVR
) != 0) ||
7062 (usc_InDmaReg( info
, DIVR
) != 0) ){
7067 /* Write bit patterns to various registers but do it out of */
7068 /* sync, then read back and verify values. */
7070 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7071 usc_OutReg( info
, TC0R
, BitPatterns
[i
] );
7072 usc_OutReg( info
, TC1R
, BitPatterns
[(i
+1)%Patterncount
] );
7073 usc_OutReg( info
, TCLR
, BitPatterns
[(i
+2)%Patterncount
] );
7074 usc_OutReg( info
, RCLR
, BitPatterns
[(i
+3)%Patterncount
] );
7075 usc_OutReg( info
, RSR
, BitPatterns
[(i
+4)%Patterncount
] );
7076 usc_OutDmaReg( info
, TBCR
, BitPatterns
[(i
+5)%Patterncount
] );
7078 if ( (usc_InReg( info
, TC0R
) != BitPatterns
[i
]) ||
7079 (usc_InReg( info
, TC1R
) != BitPatterns
[(i
+1)%Patterncount
]) ||
7080 (usc_InReg( info
, TCLR
) != BitPatterns
[(i
+2)%Patterncount
]) ||
7081 (usc_InReg( info
, RCLR
) != BitPatterns
[(i
+3)%Patterncount
]) ||
7082 (usc_InReg( info
, RSR
) != BitPatterns
[(i
+4)%Patterncount
]) ||
7083 (usc_InDmaReg( info
, TBCR
) != BitPatterns
[(i
+5)%Patterncount
]) ){
7091 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7095 } /* end of mgsl_register_test() */
7097 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7099 * Arguments: info pointer to device instance data
7100 * Return Value: TRUE if test passed, otherwise FALSE
7102 static BOOLEAN
mgsl_irq_test( struct mgsl_struct
*info
)
7104 unsigned long EndTime
;
7105 unsigned long flags
;
7107 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7111 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7112 * The ISR sets irq_occurred to 1.
7115 info
->irq_occurred
= FALSE
;
7117 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7118 /* Enable INTEN (Port 6, Bit12) */
7119 /* This connects the IRQ request signal to the ISA bus */
7120 /* on the ISA adapter. This has no effect for the PCI adapter */
7121 usc_OutReg( info
, PCR
, (unsigned short)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
) );
7123 usc_EnableMasterIrqBit(info
);
7124 usc_EnableInterrupts(info
, IO_PIN
);
7125 usc_ClearIrqPendingBits(info
, IO_PIN
);
7127 usc_UnlatchIostatusBits(info
, MISCSTATUS_TXC_LATCHED
);
7128 usc_EnableStatusIrqs(info
, SICR_TXC_ACTIVE
+ SICR_TXC_INACTIVE
);
7130 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7133 while( EndTime
-- && !info
->irq_occurred
) {
7134 msleep_interruptible(10);
7137 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7139 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7141 if ( !info
->irq_occurred
)
7146 } /* end of mgsl_irq_test() */
7150 * Perform a DMA test of the 16C32. A small frame is
7151 * transmitted via DMA from a transmit buffer to a receive buffer
7152 * using single buffer DMA mode.
7154 * Arguments: info pointer to device instance data
7155 * Return Value: TRUE if test passed, otherwise FALSE
7157 static BOOLEAN
mgsl_dma_test( struct mgsl_struct
*info
)
7159 unsigned short FifoLevel
;
7160 unsigned long phys_addr
;
7161 unsigned int FrameSize
;
7165 unsigned short status
=0;
7166 unsigned long EndTime
;
7167 unsigned long flags
;
7168 MGSL_PARAMS tmp_params
;
7170 /* save current port options */
7171 memcpy(&tmp_params
,&info
->params
,sizeof(MGSL_PARAMS
));
7172 /* load default port options */
7173 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
7175 #define TESTFRAMESIZE 40
7177 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7179 /* setup 16C32 for SDLC DMA transfer mode */
7182 usc_set_sdlc_mode(info
);
7183 usc_enable_loopback(info
,1);
7185 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7186 * field of the buffer entry after fetching buffer address. This
7187 * way we can detect a DMA failure for a DMA read (which should be
7188 * non-destructive to system memory) before we try and write to
7189 * memory (where a failure could corrupt system memory).
7192 /* Receive DMA mode Register (RDMR)
7194 * <15..14> 11 DMA mode = Linked List Buffer mode
7195 * <13> 1 RSBinA/L = store Rx status Block in List entry
7196 * <12> 0 1 = Clear count of List Entry after fetching
7197 * <11..10> 00 Address mode = Increment
7198 * <9> 1 Terminate Buffer on RxBound
7199 * <8> 0 Bus Width = 16bits
7200 * <7..0> ? status Bits (write as 0s)
7202 * 1110 0010 0000 0000 = 0xe200
7205 usc_OutDmaReg( info
, RDMR
, 0xe200 );
7207 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7210 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7212 FrameSize
= TESTFRAMESIZE
;
7214 /* setup 1st transmit buffer entry: */
7215 /* with frame size and transmit control word */
7217 info
->tx_buffer_list
[0].count
= FrameSize
;
7218 info
->tx_buffer_list
[0].rcc
= FrameSize
;
7219 info
->tx_buffer_list
[0].status
= 0x4000;
7221 /* build a transmit frame in 1st transmit DMA buffer */
7223 TmpPtr
= info
->tx_buffer_list
[0].virt_addr
;
7224 for (i
= 0; i
< FrameSize
; i
++ )
7227 /* setup 1st receive buffer entry: */
7228 /* clear status, set max receive buffer size */
7230 info
->rx_buffer_list
[0].status
= 0;
7231 info
->rx_buffer_list
[0].count
= FrameSize
+ 4;
7233 /* zero out the 1st receive buffer */
7235 memset( info
->rx_buffer_list
[0].virt_addr
, 0, FrameSize
+ 4 );
7237 /* Set count field of next buffer entries to prevent */
7238 /* 16C32 from using buffers after the 1st one. */
7240 info
->tx_buffer_list
[1].count
= 0;
7241 info
->rx_buffer_list
[1].count
= 0;
7244 /***************************/
7245 /* Program 16C32 receiver. */
7246 /***************************/
7248 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7250 /* setup DMA transfers */
7251 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
7253 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7254 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
7255 usc_OutDmaReg( info
, NRARL
, (unsigned short)phys_addr
);
7256 usc_OutDmaReg( info
, NRARU
, (unsigned short)(phys_addr
>> 16) );
7258 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7259 usc_InDmaReg( info
, RDMR
);
7260 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
7262 /* Enable Receiver (RMR <1..0> = 10) */
7263 usc_OutReg( info
, RMR
, (unsigned short)((usc_InReg(info
, RMR
) & 0xfffc) | 0x0002) );
7265 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7268 /*************************************************************/
7269 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7270 /*************************************************************/
7272 /* Wait 100ms for interrupt. */
7273 EndTime
= jiffies
+ msecs_to_jiffies(100);
7276 if (time_after(jiffies
, EndTime
)) {
7281 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7282 status
= usc_InDmaReg( info
, RDMR
);
7283 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7285 if ( !(status
& BIT4
) && (status
& BIT5
) ) {
7286 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7287 /* BUSY (BIT 5) is active (channel still active). */
7288 /* This means the buffer entry read has completed. */
7294 /******************************/
7295 /* Program 16C32 transmitter. */
7296 /******************************/
7298 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7300 /* Program the Transmit Character Length Register (TCLR) */
7301 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7303 usc_OutReg( info
, TCLR
, (unsigned short)info
->tx_buffer_list
[0].count
);
7304 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7306 /* Program the address of the 1st DMA Buffer Entry in linked list */
7308 phys_addr
= info
->tx_buffer_list
[0].phys_entry
;
7309 usc_OutDmaReg( info
, NTARL
, (unsigned short)phys_addr
);
7310 usc_OutDmaReg( info
, NTARU
, (unsigned short)(phys_addr
>> 16) );
7312 /* unlatch Tx status bits, and start transmit channel. */
7314 usc_OutReg( info
, TCSR
, (unsigned short)(( usc_InReg(info
, TCSR
) & 0x0f00) | 0xfa) );
7315 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
7317 /* wait for DMA controller to fill transmit FIFO */
7319 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
7321 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7324 /**********************************/
7325 /* WAIT FOR TRANSMIT FIFO TO FILL */
7326 /**********************************/
7329 EndTime
= jiffies
+ msecs_to_jiffies(100);
7332 if (time_after(jiffies
, EndTime
)) {
7337 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7338 FifoLevel
= usc_InReg(info
, TICR
) >> 8;
7339 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7341 if ( FifoLevel
< 16 )
7344 if ( FrameSize
< 32 ) {
7345 /* This frame is smaller than the entire transmit FIFO */
7346 /* so wait for the entire frame to be loaded. */
7347 if ( FifoLevel
<= (32 - FrameSize
) )
7355 /* Enable 16C32 transmitter. */
7357 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7359 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7360 usc_TCmd( info
, TCmd_SendFrame
);
7361 usc_OutReg( info
, TMR
, (unsigned short)((usc_InReg(info
, TMR
) & 0xfffc) | 0x0002) );
7363 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7366 /******************************/
7367 /* WAIT FOR TRANSMIT COMPLETE */
7368 /******************************/
7371 EndTime
= jiffies
+ msecs_to_jiffies(100);
7373 /* While timer not expired wait for transmit complete */
7375 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7376 status
= usc_InReg( info
, TCSR
);
7377 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7379 while ( !(status
& (BIT6
+BIT5
+BIT4
+BIT2
+BIT1
)) ) {
7380 if (time_after(jiffies
, EndTime
)) {
7385 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7386 status
= usc_InReg( info
, TCSR
);
7387 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7393 /* CHECK FOR TRANSMIT ERRORS */
7394 if ( status
& (BIT5
+ BIT1
) )
7399 /* WAIT FOR RECEIVE COMPLETE */
7402 EndTime
= jiffies
+ msecs_to_jiffies(100);
7404 /* Wait for 16C32 to write receive status to buffer entry. */
7405 status
=info
->rx_buffer_list
[0].status
;
7406 while ( status
== 0 ) {
7407 if (time_after(jiffies
, EndTime
)) {
7411 status
=info
->rx_buffer_list
[0].status
;
7417 /* CHECK FOR RECEIVE ERRORS */
7418 status
= info
->rx_buffer_list
[0].status
;
7420 if ( status
& (BIT8
+ BIT3
+ BIT1
) ) {
7421 /* receive error has occurred */
7424 if ( memcmp( info
->tx_buffer_list
[0].virt_addr
,
7425 info
->rx_buffer_list
[0].virt_addr
, FrameSize
) ){
7431 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7433 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7435 /* restore current port options */
7436 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
7440 } /* end of mgsl_dma_test() */
7442 /* mgsl_adapter_test()
7444 * Perform the register, IRQ, and DMA tests for the 16C32.
7446 * Arguments: info pointer to device instance data
7447 * Return Value: 0 if success, otherwise -ENODEV
7449 static int mgsl_adapter_test( struct mgsl_struct
*info
)
7451 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7452 printk( "%s(%d):Testing device %s\n",
7453 __FILE__
,__LINE__
,info
->device_name
);
7455 if ( !mgsl_register_test( info
) ) {
7456 info
->init_error
= DiagStatus_AddressFailure
;
7457 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7458 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->io_base
) );
7462 if ( !mgsl_irq_test( info
) ) {
7463 info
->init_error
= DiagStatus_IrqFailure
;
7464 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7465 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
7469 if ( !mgsl_dma_test( info
) ) {
7470 info
->init_error
= DiagStatus_DmaFailure
;
7471 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7472 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->dma_level
) );
7476 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7477 printk( "%s(%d):device %s passed diagnostics\n",
7478 __FILE__
,__LINE__
,info
->device_name
);
7482 } /* end of mgsl_adapter_test() */
7484 /* mgsl_memory_test()
7486 * Test the shared memory on a PCI adapter.
7488 * Arguments: info pointer to device instance data
7489 * Return Value: TRUE if test passed, otherwise FALSE
7491 static BOOLEAN
mgsl_memory_test( struct mgsl_struct
*info
)
7493 static unsigned long BitPatterns
[] =
7494 { 0x0, 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7495 unsigned long Patterncount
= ARRAY_SIZE(BitPatterns
);
7497 unsigned long TestLimit
= SHARED_MEM_ADDRESS_SIZE
/sizeof(unsigned long);
7498 unsigned long * TestAddr
;
7500 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
7503 TestAddr
= (unsigned long *)info
->memory_base
;
7505 /* Test data lines with test pattern at one location. */
7507 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7508 *TestAddr
= BitPatterns
[i
];
7509 if ( *TestAddr
!= BitPatterns
[i
] )
7513 /* Test address lines with incrementing pattern over */
7514 /* entire address range. */
7516 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7521 TestAddr
= (unsigned long *)info
->memory_base
;
7523 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7524 if ( *TestAddr
!= i
* 4 )
7529 memset( info
->memory_base
, 0, SHARED_MEM_ADDRESS_SIZE
);
7533 } /* End Of mgsl_memory_test() */
7536 /* mgsl_load_pci_memory()
7538 * Load a large block of data into the PCI shared memory.
7539 * Use this instead of memcpy() or memmove() to move data
7540 * into the PCI shared memory.
7544 * This function prevents the PCI9050 interface chip from hogging
7545 * the adapter local bus, which can starve the 16C32 by preventing
7546 * 16C32 bus master cycles.
7548 * The PCI9050 documentation says that the 9050 will always release
7549 * control of the local bus after completing the current read
7550 * or write operation.
7552 * It appears that as long as the PCI9050 write FIFO is full, the
7553 * PCI9050 treats all of the writes as a single burst transaction
7554 * and will not release the bus. This causes DMA latency problems
7555 * at high speeds when copying large data blocks to the shared
7558 * This function in effect, breaks the a large shared memory write
7559 * into multiple transations by interleaving a shared memory read
7560 * which will flush the write FIFO and 'complete' the write
7561 * transation. This allows any pending DMA request to gain control
7562 * of the local bus in a timely fasion.
7566 * TargetPtr pointer to target address in PCI shared memory
7567 * SourcePtr pointer to source buffer for data
7568 * count count in bytes of data to copy
7570 * Return Value: None
7572 static void mgsl_load_pci_memory( char* TargetPtr
, const char* SourcePtr
,
7573 unsigned short count
)
7575 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7576 #define PCI_LOAD_INTERVAL 64
7578 unsigned short Intervalcount
= count
/ PCI_LOAD_INTERVAL
;
7579 unsigned short Index
;
7580 unsigned long Dummy
;
7582 for ( Index
= 0 ; Index
< Intervalcount
; Index
++ )
7584 memcpy(TargetPtr
, SourcePtr
, PCI_LOAD_INTERVAL
);
7585 Dummy
= *((volatile unsigned long *)TargetPtr
);
7586 TargetPtr
+= PCI_LOAD_INTERVAL
;
7587 SourcePtr
+= PCI_LOAD_INTERVAL
;
7590 memcpy( TargetPtr
, SourcePtr
, count
% PCI_LOAD_INTERVAL
);
7592 } /* End Of mgsl_load_pci_memory() */
7594 static void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
)
7599 printk("%s tx data:\n",info
->device_name
);
7601 printk("%s rx data:\n",info
->device_name
);
7609 for(i
=0;i
<linecount
;i
++)
7610 printk("%02X ",(unsigned char)data
[i
]);
7613 for(i
=0;i
<linecount
;i
++) {
7614 if (data
[i
]>=040 && data
[i
]<=0176)
7615 printk("%c",data
[i
]);
7624 } /* end of mgsl_trace_block() */
7626 /* mgsl_tx_timeout()
7628 * called when HDLC frame times out
7629 * update stats and do tx completion processing
7631 * Arguments: context pointer to device instance data
7632 * Return Value: None
7634 static void mgsl_tx_timeout(unsigned long context
)
7636 struct mgsl_struct
*info
= (struct mgsl_struct
*)context
;
7637 unsigned long flags
;
7639 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7640 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7641 __FILE__
,__LINE__
,info
->device_name
);
7642 if(info
->tx_active
&&
7643 (info
->params
.mode
== MGSL_MODE_HDLC
||
7644 info
->params
.mode
== MGSL_MODE_RAW
) ) {
7645 info
->icount
.txtimeout
++;
7647 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7648 info
->tx_active
= 0;
7649 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
7651 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
7652 usc_loopmode_cancel_transmit( info
);
7654 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7658 hdlcdev_tx_done(info
);
7661 mgsl_bh_transmit(info
);
7663 } /* end of mgsl_tx_timeout() */
7665 /* signal that there are no more frames to send, so that
7666 * line is 'released' by echoing RxD to TxD when current
7667 * transmission is complete (or immediately if no tx in progress).
7669 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
)
7671 unsigned long flags
;
7673 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7674 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
7675 if (info
->tx_active
)
7676 info
->loopmode_send_done_requested
= TRUE
;
7678 usc_loopmode_send_done(info
);
7680 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7685 /* release the line by echoing RxD to TxD
7686 * upon completion of a transmit frame
7688 static void usc_loopmode_send_done( struct mgsl_struct
* info
)
7690 info
->loopmode_send_done_requested
= FALSE
;
7691 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7692 info
->cmr_value
&= ~BIT13
;
7693 usc_OutReg(info
, CMR
, info
->cmr_value
);
7696 /* abort a transmit in progress while in HDLC LoopMode
7698 static void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
)
7700 /* reset tx dma channel and purge TxFifo */
7701 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7702 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
7703 usc_loopmode_send_done( info
);
7706 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7707 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7708 * we must clear CMR:13 to begin repeating TxData to RxData
7710 static void usc_loopmode_insert_request( struct mgsl_struct
* info
)
7712 info
->loopmode_insert_requested
= TRUE
;
7714 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7715 * begin repeating TxData on RxData (complete insertion)
7717 usc_OutReg( info
, RICR
,
7718 (usc_InReg( info
, RICR
) | RXSTATUS_ABORT_RECEIVED
) );
7720 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7721 info
->cmr_value
|= BIT13
;
7722 usc_OutReg(info
, CMR
, info
->cmr_value
);
7725 /* return 1 if station is inserted into the loop, otherwise 0
7727 static int usc_loopmode_active( struct mgsl_struct
* info
)
7729 return usc_InReg( info
, CCSR
) & BIT7
? 1 : 0 ;
7735 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7736 * set encoding and frame check sequence (FCS) options
7738 * dev pointer to network device structure
7739 * encoding serial encoding setting
7740 * parity FCS setting
7742 * returns 0 if success, otherwise error code
7744 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
7745 unsigned short parity
)
7747 struct mgsl_struct
*info
= dev_to_port(dev
);
7748 unsigned char new_encoding
;
7749 unsigned short new_crctype
;
7751 /* return error if TTY interface open */
7757 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
7758 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
7759 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
7760 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
7761 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
7762 default: return -EINVAL
;
7767 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
7768 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
7769 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
7770 default: return -EINVAL
;
7773 info
->params
.encoding
= new_encoding
;
7774 info
->params
.crc_type
= new_crctype
;;
7776 /* if network interface up, reprogram hardware */
7778 mgsl_program_hw(info
);
7784 * called by generic HDLC layer to send frame
7786 * skb socket buffer containing HDLC frame
7787 * dev pointer to network device structure
7789 * returns 0 if success, otherwise error code
7791 static int hdlcdev_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
7793 struct mgsl_struct
*info
= dev_to_port(dev
);
7794 struct net_device_stats
*stats
= hdlc_stats(dev
);
7795 unsigned long flags
;
7797 if (debug_level
>= DEBUG_LEVEL_INFO
)
7798 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
7800 /* stop sending until this frame completes */
7801 netif_stop_queue(dev
);
7803 /* copy data to device buffers */
7804 info
->xmit_cnt
= skb
->len
;
7805 mgsl_load_tx_dma_buffer(info
, skb
->data
, skb
->len
);
7807 /* update network statistics */
7808 stats
->tx_packets
++;
7809 stats
->tx_bytes
+= skb
->len
;
7811 /* done with socket buffer, so free it */
7814 /* save start time for transmit timeout detection */
7815 dev
->trans_start
= jiffies
;
7817 /* start hardware transmitter if necessary */
7818 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7819 if (!info
->tx_active
)
7820 usc_start_transmitter(info
);
7821 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7827 * called by network layer when interface enabled
7828 * claim resources and initialize hardware
7830 * dev pointer to network device structure
7832 * returns 0 if success, otherwise error code
7834 static int hdlcdev_open(struct net_device
*dev
)
7836 struct mgsl_struct
*info
= dev_to_port(dev
);
7838 unsigned long flags
;
7840 if (debug_level
>= DEBUG_LEVEL_INFO
)
7841 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
7843 /* generic HDLC layer open processing */
7844 if ((rc
= hdlc_open(dev
)))
7847 /* arbitrate between network and tty opens */
7848 spin_lock_irqsave(&info
->netlock
, flags
);
7849 if (info
->count
!= 0 || info
->netcount
!= 0) {
7850 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
7851 spin_unlock_irqrestore(&info
->netlock
, flags
);
7855 spin_unlock_irqrestore(&info
->netlock
, flags
);
7857 /* claim resources and init adapter */
7858 if ((rc
= startup(info
)) != 0) {
7859 spin_lock_irqsave(&info
->netlock
, flags
);
7861 spin_unlock_irqrestore(&info
->netlock
, flags
);
7865 /* assert DTR and RTS, apply hardware settings */
7866 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
7867 mgsl_program_hw(info
);
7869 /* enable network layer transmit */
7870 dev
->trans_start
= jiffies
;
7871 netif_start_queue(dev
);
7873 /* inform generic HDLC layer of current DCD status */
7874 spin_lock_irqsave(&info
->irq_spinlock
, flags
);
7875 usc_get_serial_signals(info
);
7876 spin_unlock_irqrestore(&info
->irq_spinlock
, flags
);
7877 hdlc_set_carrier(info
->serial_signals
& SerialSignal_DCD
, dev
);
7883 * called by network layer when interface is disabled
7884 * shutdown hardware and release resources
7886 * dev pointer to network device structure
7888 * returns 0 if success, otherwise error code
7890 static int hdlcdev_close(struct net_device
*dev
)
7892 struct mgsl_struct
*info
= dev_to_port(dev
);
7893 unsigned long flags
;
7895 if (debug_level
>= DEBUG_LEVEL_INFO
)
7896 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
7898 netif_stop_queue(dev
);
7900 /* shutdown adapter and release resources */
7905 spin_lock_irqsave(&info
->netlock
, flags
);
7907 spin_unlock_irqrestore(&info
->netlock
, flags
);
7913 * called by network layer to process IOCTL call to network device
7915 * dev pointer to network device structure
7916 * ifr pointer to network interface request structure
7917 * cmd IOCTL command code
7919 * returns 0 if success, otherwise error code
7921 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7923 const size_t size
= sizeof(sync_serial_settings
);
7924 sync_serial_settings new_line
;
7925 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
7926 struct mgsl_struct
*info
= dev_to_port(dev
);
7929 if (debug_level
>= DEBUG_LEVEL_INFO
)
7930 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
7932 /* return error if TTY interface open */
7936 if (cmd
!= SIOCWANDEV
)
7937 return hdlc_ioctl(dev
, ifr
, cmd
);
7939 switch(ifr
->ifr_settings
.type
) {
7940 case IF_GET_IFACE
: /* return current sync_serial_settings */
7942 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
7943 if (ifr
->ifr_settings
.size
< size
) {
7944 ifr
->ifr_settings
.size
= size
; /* data size wanted */
7948 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7949 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7950 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7951 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7954 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
7955 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
7956 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
7957 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
7958 default: new_line
.clock_type
= CLOCK_DEFAULT
;
7961 new_line
.clock_rate
= info
->params
.clock_speed
;
7962 new_line
.loopback
= info
->params
.loopback
? 1:0;
7964 if (copy_to_user(line
, &new_line
, size
))
7968 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
7970 if(!capable(CAP_NET_ADMIN
))
7972 if (copy_from_user(&new_line
, line
, size
))
7975 switch (new_line
.clock_type
)
7977 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
7978 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
7979 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
7980 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
7981 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
7982 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7983 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7984 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7985 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
7986 default: return -EINVAL
;
7989 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
7992 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
7993 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
7994 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
7995 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
7996 info
->params
.flags
|= flags
;
7998 info
->params
.loopback
= new_line
.loopback
;
8000 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
8001 info
->params
.clock_speed
= new_line
.clock_rate
;
8003 info
->params
.clock_speed
= 0;
8005 /* if network interface up, reprogram hardware */
8007 mgsl_program_hw(info
);
8011 return hdlc_ioctl(dev
, ifr
, cmd
);
8016 * called by network layer when transmit timeout is detected
8018 * dev pointer to network device structure
8020 static void hdlcdev_tx_timeout(struct net_device
*dev
)
8022 struct mgsl_struct
*info
= dev_to_port(dev
);
8023 struct net_device_stats
*stats
= hdlc_stats(dev
);
8024 unsigned long flags
;
8026 if (debug_level
>= DEBUG_LEVEL_INFO
)
8027 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
8030 stats
->tx_aborted_errors
++;
8032 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
8033 usc_stop_transmitter(info
);
8034 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
8036 netif_wake_queue(dev
);
8040 * called by device driver when transmit completes
8041 * reenable network layer transmit if stopped
8043 * info pointer to device instance information
8045 static void hdlcdev_tx_done(struct mgsl_struct
*info
)
8047 if (netif_queue_stopped(info
->netdev
))
8048 netif_wake_queue(info
->netdev
);
8052 * called by device driver when frame received
8053 * pass frame to network layer
8055 * info pointer to device instance information
8056 * buf pointer to buffer contianing frame data
8057 * size count of data bytes in buf
8059 static void hdlcdev_rx(struct mgsl_struct
*info
, char *buf
, int size
)
8061 struct sk_buff
*skb
= dev_alloc_skb(size
);
8062 struct net_device
*dev
= info
->netdev
;
8063 struct net_device_stats
*stats
= hdlc_stats(dev
);
8065 if (debug_level
>= DEBUG_LEVEL_INFO
)
8066 printk("hdlcdev_rx(%s)\n",dev
->name
);
8069 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n", dev
->name
);
8070 stats
->rx_dropped
++;
8074 memcpy(skb_put(skb
, size
),buf
,size
);
8076 skb
->protocol
= hdlc_type_trans(skb
, info
->netdev
);
8078 stats
->rx_packets
++;
8079 stats
->rx_bytes
+= size
;
8083 info
->netdev
->last_rx
= jiffies
;
8087 * called by device driver when adding device instance
8088 * do generic HDLC initialization
8090 * info pointer to device instance information
8092 * returns 0 if success, otherwise error code
8094 static int hdlcdev_init(struct mgsl_struct
*info
)
8097 struct net_device
*dev
;
8100 /* allocate and initialize network and HDLC layer objects */
8102 if (!(dev
= alloc_hdlcdev(info
))) {
8103 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
8107 /* for network layer reporting purposes only */
8108 dev
->base_addr
= info
->io_base
;
8109 dev
->irq
= info
->irq_level
;
8110 dev
->dma
= info
->dma_level
;
8112 /* network layer callbacks and settings */
8113 dev
->do_ioctl
= hdlcdev_ioctl
;
8114 dev
->open
= hdlcdev_open
;
8115 dev
->stop
= hdlcdev_close
;
8116 dev
->tx_timeout
= hdlcdev_tx_timeout
;
8117 dev
->watchdog_timeo
= 10*HZ
;
8118 dev
->tx_queue_len
= 50;
8120 /* generic HDLC layer callbacks and settings */
8121 hdlc
= dev_to_hdlc(dev
);
8122 hdlc
->attach
= hdlcdev_attach
;
8123 hdlc
->xmit
= hdlcdev_xmit
;
8125 /* register objects with HDLC layer */
8126 if ((rc
= register_hdlc_device(dev
))) {
8127 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
8137 * called by device driver when removing device instance
8138 * do generic HDLC cleanup
8140 * info pointer to device instance information
8142 static void hdlcdev_exit(struct mgsl_struct
*info
)
8144 unregister_hdlc_device(info
->netdev
);
8145 free_netdev(info
->netdev
);
8146 info
->netdev
= NULL
;
8149 #endif /* CONFIG_HDLC */
8152 static int __devinit
synclink_init_one (struct pci_dev
*dev
,
8153 const struct pci_device_id
*ent
)
8155 struct mgsl_struct
*info
;
8157 if (pci_enable_device(dev
)) {
8158 printk("error enabling pci device %p\n", dev
);
8162 if (!(info
= mgsl_allocate_device())) {
8163 printk("can't allocate device instance data.\n");
8167 /* Copy user configuration info to device instance data */
8169 info
->io_base
= pci_resource_start(dev
, 2);
8170 info
->irq_level
= dev
->irq
;
8171 info
->phys_memory_base
= pci_resource_start(dev
, 3);
8173 /* Because veremap only works on page boundaries we must map
8174 * a larger area than is actually implemented for the LCR
8175 * memory range. We map a full page starting at the page boundary.
8177 info
->phys_lcr_base
= pci_resource_start(dev
, 0);
8178 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
8179 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
8181 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
8182 info
->io_addr_size
= 8;
8183 info
->irq_flags
= SA_SHIRQ
;
8185 if (dev
->device
== 0x0210) {
8186 /* Version 1 PCI9030 based universal PCI adapter */
8187 info
->misc_ctrl_value
= 0x007c4080;
8188 info
->hw_version
= 1;
8190 /* Version 0 PCI9050 based 5V PCI adapter
8191 * A PCI9050 bug prevents reading LCR registers if
8192 * LCR base address bit 7 is set. Maintain shadow
8193 * value so we can write to LCR misc control reg.
8195 info
->misc_ctrl_value
= 0x087e4546;
8196 info
->hw_version
= 0;
8199 mgsl_add_device(info
);
8204 static void __devexit
synclink_remove_one (struct pci_dev
*dev
)