2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
7 * written by Paul Fulghum for Microgate Corporation
10 * Microgate and SyncLink are trademarks of Microgate Corporation
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30 # define BREAKPOINT() asm(" int $3");
32 # define BREAKPOINT() { }
35 #define MAX_DEVICES 12
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
53 #include <linux/slab.h>
54 #include <linux/netdevice.h>
55 #include <linux/vmalloc.h>
56 #include <linux/init.h>
57 #include <linux/delay.h>
58 #include <linux/ioctl.h>
60 #include <asm/system.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
74 #define SYNCLINK_GENERIC_HDLC 0
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
82 #include <asm/uaccess.h>
84 static MGSL_PARAMS default_params
= {
85 MGSL_MODE_HDLC
, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE
/* unsigned char parity; */
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
108 #define BUFFERLISTSIZE 4096
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
113 u16 next
; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr
; /* lower 16 bits of buffer addr */
115 u8 buf_base
; /* upper 8 bits of buffer addr */
117 u16 length
; /* length of buffer */
118 u8 status
; /* status of buffer */
120 } SCADESC
, *PSCADESC
;
122 typedef struct _SCADESC_EX
124 /* device driver bookkeeping section */
125 char *virt_addr
; /* virtual address of data buffer */
126 u16 phys_entry
; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX
, *PSCADESC_EX
;
129 /* The queue of BH actions to be performed */
132 #define BH_TRANSMIT 2
135 #define IO_PIN_SHUTDOWN_LIMIT 100
137 struct _input_signal_events
{
149 * Device instance data structure
151 typedef struct _synclinkmp_info
{
152 void *if_ptr
; /* General purpose pointer (used by SPPP) */
155 int count
; /* count of opens */
157 unsigned short close_delay
;
158 unsigned short closing_wait
; /* time to wait before closing */
160 struct mgsl_icount icount
;
162 struct tty_struct
*tty
;
164 int x_char
; /* xon/xoff character */
165 int blocked_open
; /* # of blocked opens */
166 u16 read_status_mask1
; /* break detection (SR1 indications) */
167 u16 read_status_mask2
; /* parity/framing/overun (SR2 indications) */
168 unsigned char ignore_status_mask1
; /* break detection (SR1 indications) */
169 unsigned char ignore_status_mask2
; /* parity/framing/overun (SR2 indications) */
170 unsigned char *tx_buf
;
175 wait_queue_head_t open_wait
;
176 wait_queue_head_t close_wait
;
178 wait_queue_head_t status_event_wait_q
;
179 wait_queue_head_t event_wait_q
;
180 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
181 struct _synclinkmp_info
*next_device
; /* device list link */
182 struct timer_list status_timer
; /* input signal status check timer */
184 spinlock_t lock
; /* spinlock for synchronizing with ISR */
185 struct work_struct task
; /* task structure for scheduling bh */
187 u32 max_frame_size
; /* as set by device config */
191 bool bh_running
; /* Protection from multiple */
195 int dcd_chkcount
; /* check counts to prevent */
196 int cts_chkcount
; /* too many IRQs if a signal */
197 int dsr_chkcount
; /* is floating */
200 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
201 unsigned long buffer_list_phys
;
203 unsigned int rx_buf_count
; /* count of total allocated Rx buffers */
204 SCADESC
*rx_buf_list
; /* list of receive buffer entries */
205 SCADESC_EX rx_buf_list_ex
[SCAMAXDESC
]; /* list of receive buffer entries */
206 unsigned int current_rx_buf
;
208 unsigned int tx_buf_count
; /* count of total allocated Tx buffers */
209 SCADESC
*tx_buf_list
; /* list of transmit buffer entries */
210 SCADESC_EX tx_buf_list_ex
[SCAMAXDESC
]; /* list of transmit buffer entries */
211 unsigned int last_tx_buf
;
213 unsigned char *tmp_rx_buf
;
214 unsigned int tmp_rx_buf_count
;
223 unsigned char ie0_value
;
224 unsigned char ie1_value
;
225 unsigned char ie2_value
;
226 unsigned char ctrlreg_value
;
227 unsigned char old_signals
;
229 char device_name
[25]; /* device instance name */
235 struct _synclinkmp_info
*port_array
[SCA_MAX_PORTS
];
237 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
239 unsigned int irq_level
; /* interrupt level */
240 unsigned long irq_flags
;
241 bool irq_requested
; /* true if IRQ requested */
243 MGSL_PARAMS params
; /* communications parameters */
245 unsigned char serial_signals
; /* current serial signal states */
247 bool irq_occurred
; /* for diagnostics use */
248 unsigned int init_error
; /* Initialization startup error */
251 unsigned char* memory_base
; /* shared memory address (PCI only) */
252 u32 phys_memory_base
;
253 int shared_mem_requested
;
255 unsigned char* sca_base
; /* HD64570 SCA Memory address */
258 bool sca_base_requested
;
260 unsigned char* lcr_base
; /* local config registers (PCI only) */
263 int lcr_mem_requested
;
265 unsigned char* statctrl_base
; /* status/control register memory */
266 u32 phys_statctrl_base
;
268 bool sca_statctrl_requested
;
271 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
272 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
273 bool drop_rts_on_tx_done
;
275 struct _input_signal_events input_signal_events
;
277 /* SPPP/Cisco HDLC device parts */
282 #if SYNCLINK_GENERIC_HDLC
283 struct net_device
*netdev
;
288 #define MGSL_MAGIC 0x5401
291 * define serial signal status change macros
293 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
294 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
295 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
296 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
298 /* Common Register macros */
317 /* MSCI Register macros */
347 /* Timer Register Macros */
357 /* DMA Controller Register macros */
388 /* combine with timer or DMA register address */
396 /* SCA Command Codes */
399 #define TXENABLE 0x02
400 #define TXDISABLE 0x03
401 #define TXCRCINIT 0x04
402 #define TXCRCEXCL 0x05
406 #define TXBUFCLR 0x09
408 #define RXENABLE 0x12
409 #define RXDISABLE 0x13
410 #define RXCRCINIT 0x14
411 #define RXREJECT 0x15
412 #define SEARCHMP 0x16
413 #define RXCRCEXCL 0x17
414 #define RXCRCCALC 0x18
418 /* DMA command codes */
420 #define FEICLEAR 0x02
454 * Global linked list of SyncLink devices
456 static SLMP_INFO
*synclinkmp_device_list
= NULL
;
457 static int synclinkmp_adapter_count
= -1;
458 static int synclinkmp_device_count
= 0;
461 * Set this param to non-zero to load eax with the
462 * .text section address and breakpoint on module load.
463 * This is useful for use with gdb and add-symbol-file command.
465 static int break_on_load
=0;
468 * Driver major number, defaults to zero to get auto
469 * assigned major number. May be forced as module parameter.
471 static int ttymajor
=0;
474 * Array of user specified options for ISA adapters.
476 static int debug_level
= 0;
477 static int maxframe
[MAX_DEVICES
] = {0,};
478 static int dosyncppp
[MAX_DEVICES
] = {0,};
480 module_param(break_on_load
, bool, 0);
481 module_param(ttymajor
, int, 0);
482 module_param(debug_level
, int, 0);
483 module_param_array(maxframe
, int, NULL
, 0);
484 module_param_array(dosyncppp
, int, NULL
, 0);
486 static char *driver_name
= "SyncLink MultiPort driver";
487 static char *driver_version
= "$Revision: 4.38 $";
489 static int synclinkmp_init_one(struct pci_dev
*dev
,const struct pci_device_id
*ent
);
490 static void synclinkmp_remove_one(struct pci_dev
*dev
);
492 static struct pci_device_id synclinkmp_pci_tbl
[] = {
493 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_SCA
, PCI_ANY_ID
, PCI_ANY_ID
, },
494 { 0, }, /* terminate list */
496 MODULE_DEVICE_TABLE(pci
, synclinkmp_pci_tbl
);
498 MODULE_LICENSE("GPL");
500 static struct pci_driver synclinkmp_pci_driver
= {
501 .name
= "synclinkmp",
502 .id_table
= synclinkmp_pci_tbl
,
503 .probe
= synclinkmp_init_one
,
504 .remove
= __devexit_p(synclinkmp_remove_one
),
508 static struct tty_driver
*serial_driver
;
510 /* number of characters left in xmit buffer before we ask for more */
511 #define WAKEUP_CHARS 256
516 static int open(struct tty_struct
*tty
, struct file
* filp
);
517 static void close(struct tty_struct
*tty
, struct file
* filp
);
518 static void hangup(struct tty_struct
*tty
);
519 static void set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
);
521 static int write(struct tty_struct
*tty
, const unsigned char *buf
, int count
);
522 static void put_char(struct tty_struct
*tty
, unsigned char ch
);
523 static void send_xchar(struct tty_struct
*tty
, char ch
);
524 static void wait_until_sent(struct tty_struct
*tty
, int timeout
);
525 static int write_room(struct tty_struct
*tty
);
526 static void flush_chars(struct tty_struct
*tty
);
527 static void flush_buffer(struct tty_struct
*tty
);
528 static void tx_hold(struct tty_struct
*tty
);
529 static void tx_release(struct tty_struct
*tty
);
531 static int ioctl(struct tty_struct
*tty
, struct file
*file
, unsigned int cmd
, unsigned long arg
);
532 static int read_proc(char *page
, char **start
, off_t off
, int count
,int *eof
, void *data
);
533 static int chars_in_buffer(struct tty_struct
*tty
);
534 static void throttle(struct tty_struct
* tty
);
535 static void unthrottle(struct tty_struct
* tty
);
536 static void set_break(struct tty_struct
*tty
, int break_state
);
538 #if SYNCLINK_GENERIC_HDLC
539 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
540 static void hdlcdev_tx_done(SLMP_INFO
*info
);
541 static void hdlcdev_rx(SLMP_INFO
*info
, char *buf
, int size
);
542 static int hdlcdev_init(SLMP_INFO
*info
);
543 static void hdlcdev_exit(SLMP_INFO
*info
);
548 static int get_stats(SLMP_INFO
*info
, struct mgsl_icount __user
*user_icount
);
549 static int get_params(SLMP_INFO
*info
, MGSL_PARAMS __user
*params
);
550 static int set_params(SLMP_INFO
*info
, MGSL_PARAMS __user
*params
);
551 static int get_txidle(SLMP_INFO
*info
, int __user
*idle_mode
);
552 static int set_txidle(SLMP_INFO
*info
, int idle_mode
);
553 static int tx_enable(SLMP_INFO
*info
, int enable
);
554 static int tx_abort(SLMP_INFO
*info
);
555 static int rx_enable(SLMP_INFO
*info
, int enable
);
556 static int modem_input_wait(SLMP_INFO
*info
,int arg
);
557 static int wait_mgsl_event(SLMP_INFO
*info
, int __user
*mask_ptr
);
558 static int tiocmget(struct tty_struct
*tty
, struct file
*file
);
559 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
560 unsigned int set
, unsigned int clear
);
561 static void set_break(struct tty_struct
*tty
, int break_state
);
563 static void add_device(SLMP_INFO
*info
);
564 static void device_init(int adapter_num
, struct pci_dev
*pdev
);
565 static int claim_resources(SLMP_INFO
*info
);
566 static void release_resources(SLMP_INFO
*info
);
568 static int startup(SLMP_INFO
*info
);
569 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,SLMP_INFO
*info
);
570 static void shutdown(SLMP_INFO
*info
);
571 static void program_hw(SLMP_INFO
*info
);
572 static void change_params(SLMP_INFO
*info
);
574 static bool init_adapter(SLMP_INFO
*info
);
575 static bool register_test(SLMP_INFO
*info
);
576 static bool irq_test(SLMP_INFO
*info
);
577 static bool loopback_test(SLMP_INFO
*info
);
578 static int adapter_test(SLMP_INFO
*info
);
579 static bool memory_test(SLMP_INFO
*info
);
581 static void reset_adapter(SLMP_INFO
*info
);
582 static void reset_port(SLMP_INFO
*info
);
583 static void async_mode(SLMP_INFO
*info
);
584 static void hdlc_mode(SLMP_INFO
*info
);
586 static void rx_stop(SLMP_INFO
*info
);
587 static void rx_start(SLMP_INFO
*info
);
588 static void rx_reset_buffers(SLMP_INFO
*info
);
589 static void rx_free_frame_buffers(SLMP_INFO
*info
, unsigned int first
, unsigned int last
);
590 static bool rx_get_frame(SLMP_INFO
*info
);
592 static void tx_start(SLMP_INFO
*info
);
593 static void tx_stop(SLMP_INFO
*info
);
594 static void tx_load_fifo(SLMP_INFO
*info
);
595 static void tx_set_idle(SLMP_INFO
*info
);
596 static void tx_load_dma_buffer(SLMP_INFO
*info
, const char *buf
, unsigned int count
);
598 static void get_signals(SLMP_INFO
*info
);
599 static void set_signals(SLMP_INFO
*info
);
600 static void enable_loopback(SLMP_INFO
*info
, int enable
);
601 static void set_rate(SLMP_INFO
*info
, u32 data_rate
);
603 static int bh_action(SLMP_INFO
*info
);
604 static void bh_handler(struct work_struct
*work
);
605 static void bh_receive(SLMP_INFO
*info
);
606 static void bh_transmit(SLMP_INFO
*info
);
607 static void bh_status(SLMP_INFO
*info
);
608 static void isr_timer(SLMP_INFO
*info
);
609 static void isr_rxint(SLMP_INFO
*info
);
610 static void isr_rxrdy(SLMP_INFO
*info
);
611 static void isr_txint(SLMP_INFO
*info
);
612 static void isr_txrdy(SLMP_INFO
*info
);
613 static void isr_rxdmaok(SLMP_INFO
*info
);
614 static void isr_rxdmaerror(SLMP_INFO
*info
);
615 static void isr_txdmaok(SLMP_INFO
*info
);
616 static void isr_txdmaerror(SLMP_INFO
*info
);
617 static void isr_io_pin(SLMP_INFO
*info
, u16 status
);
619 static int alloc_dma_bufs(SLMP_INFO
*info
);
620 static void free_dma_bufs(SLMP_INFO
*info
);
621 static int alloc_buf_list(SLMP_INFO
*info
);
622 static int alloc_frame_bufs(SLMP_INFO
*info
, SCADESC
*list
, SCADESC_EX
*list_ex
,int count
);
623 static int alloc_tmp_rx_buf(SLMP_INFO
*info
);
624 static void free_tmp_rx_buf(SLMP_INFO
*info
);
626 static void load_pci_memory(SLMP_INFO
*info
, char* dest
, const char* src
, unsigned short count
);
627 static void trace_block(SLMP_INFO
*info
, const char* data
, int count
, int xmit
);
628 static void tx_timeout(unsigned long context
);
629 static void status_timeout(unsigned long context
);
631 static unsigned char read_reg(SLMP_INFO
*info
, unsigned char addr
);
632 static void write_reg(SLMP_INFO
*info
, unsigned char addr
, unsigned char val
);
633 static u16
read_reg16(SLMP_INFO
*info
, unsigned char addr
);
634 static void write_reg16(SLMP_INFO
*info
, unsigned char addr
, u16 val
);
635 static unsigned char read_status_reg(SLMP_INFO
* info
);
636 static void write_control_reg(SLMP_INFO
* info
);
639 static unsigned char rx_active_fifo_level
= 16; // rx request FIFO activation level in bytes
640 static unsigned char tx_active_fifo_level
= 16; // tx request FIFO activation level in bytes
641 static unsigned char tx_negate_fifo_level
= 32; // tx request FIFO negation level in bytes
643 static u32 misc_ctrl_value
= 0x007e4040;
644 static u32 lcr1_brdr_value
= 0x00800028;
646 static u32 read_ahead_count
= 8;
648 /* DPCR, DMA Priority Control
650 * 07..05 Not used, must be 0
651 * 04 BRC, bus release condition: 0=all transfers complete
652 * 1=release after 1 xfer on all channels
653 * 03 CCC, channel change condition: 0=every cycle
654 * 1=after each channel completes all xfers
655 * 02..00 PR<2..0>, priority 100=round robin
659 static unsigned char dma_priority
= 0x04;
661 // Number of bytes that can be written to shared RAM
662 // in a single write operation
663 static u32 sca_pci_load_interval
= 64;
666 * 1st function defined in .text section. Calling this function in
667 * init_module() followed by a breakpoint allows a remote debugger
668 * (gdb) to get the .text address for the add-symbol-file command.
669 * This allows remote debugging of dynamically loadable modules.
671 static void* synclinkmp_get_text_ptr(void);
672 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr
;}
674 static inline int sanity_check(SLMP_INFO
*info
,
675 char *name
, const char *routine
)
678 static const char *badmagic
=
679 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
680 static const char *badinfo
=
681 "Warning: null synclinkmp_struct for (%s) in %s\n";
684 printk(badinfo
, name
, routine
);
687 if (info
->magic
!= MGSL_MAGIC
) {
688 printk(badmagic
, name
, routine
);
699 * line discipline callback wrappers
701 * The wrappers maintain line discipline references
702 * while calling into the line discipline.
704 * ldisc_receive_buf - pass receive data to line discipline
707 static void ldisc_receive_buf(struct tty_struct
*tty
,
708 const __u8
*data
, char *flags
, int count
)
710 struct tty_ldisc
*ld
;
713 ld
= tty_ldisc_ref(tty
);
716 ld
->receive_buf(tty
, data
, flags
, count
);
723 /* Called when a port is opened. Init and enable port.
725 static int open(struct tty_struct
*tty
, struct file
*filp
)
732 if ((line
< 0) || (line
>= synclinkmp_device_count
)) {
733 printk("%s(%d): open with invalid line #%d.\n",
734 __FILE__
,__LINE__
,line
);
738 info
= synclinkmp_device_list
;
739 while(info
&& info
->line
!= line
)
740 info
= info
->next_device
;
741 if (sanity_check(info
, tty
->name
, "open"))
743 if ( info
->init_error
) {
744 printk("%s(%d):%s device is not allocated, init error=%d\n",
745 __FILE__
,__LINE__
,info
->device_name
,info
->init_error
);
749 tty
->driver_data
= info
;
752 if (debug_level
>= DEBUG_LEVEL_INFO
)
753 printk("%s(%d):%s open(), old ref count = %d\n",
754 __FILE__
,__LINE__
,tty
->driver
->name
, info
->count
);
756 /* If port is closing, signal caller to try again */
757 if (tty_hung_up_p(filp
) || info
->flags
& ASYNC_CLOSING
){
758 if (info
->flags
& ASYNC_CLOSING
)
759 interruptible_sleep_on(&info
->close_wait
);
760 retval
= ((info
->flags
& ASYNC_HUP_NOTIFY
) ?
761 -EAGAIN
: -ERESTARTSYS
);
765 info
->tty
->low_latency
= (info
->flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
767 spin_lock_irqsave(&info
->netlock
, flags
);
768 if (info
->netcount
) {
770 spin_unlock_irqrestore(&info
->netlock
, flags
);
774 spin_unlock_irqrestore(&info
->netlock
, flags
);
776 if (info
->count
== 1) {
777 /* 1st open on this device, init hardware */
778 retval
= startup(info
);
783 retval
= block_til_ready(tty
, filp
, info
);
785 if (debug_level
>= DEBUG_LEVEL_INFO
)
786 printk("%s(%d):%s block_til_ready() returned %d\n",
787 __FILE__
,__LINE__
, info
->device_name
, retval
);
791 if (debug_level
>= DEBUG_LEVEL_INFO
)
792 printk("%s(%d):%s open() success\n",
793 __FILE__
,__LINE__
, info
->device_name
);
799 info
->tty
= NULL
; /* tty layer will release tty struct */
807 /* Called when port is closed. Wait for remaining data to be
808 * sent. Disable port and free resources.
810 static void close(struct tty_struct
*tty
, struct file
*filp
)
812 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
814 if (sanity_check(info
, tty
->name
, "close"))
817 if (debug_level
>= DEBUG_LEVEL_INFO
)
818 printk("%s(%d):%s close() entry, count=%d\n",
819 __FILE__
,__LINE__
, info
->device_name
, info
->count
);
824 if (tty_hung_up_p(filp
))
827 if ((tty
->count
== 1) && (info
->count
!= 1)) {
829 * tty->count is 1 and the tty structure will be freed.
830 * info->count should be one in this case.
831 * if it's not, correct it so that the port is shutdown.
833 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
834 "info->count is %d\n",
835 __FILE__
,__LINE__
, info
->device_name
, info
->count
);
841 /* if at least one open remaining, leave hardware active */
845 info
->flags
|= ASYNC_CLOSING
;
847 /* set tty->closing to notify line discipline to
848 * only process XON/XOFF characters. Only the N_TTY
849 * discipline appears to use this (ppp does not).
853 /* wait for transmit data to clear all layers */
855 if (info
->closing_wait
!= ASYNC_CLOSING_WAIT_NONE
) {
856 if (debug_level
>= DEBUG_LEVEL_INFO
)
857 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
858 __FILE__
,__LINE__
, info
->device_name
);
859 tty_wait_until_sent(tty
, info
->closing_wait
);
862 if (info
->flags
& ASYNC_INITIALIZED
)
863 wait_until_sent(tty
, info
->timeout
);
867 tty_ldisc_flush(tty
);
874 if (info
->blocked_open
) {
875 if (info
->close_delay
) {
876 msleep_interruptible(jiffies_to_msecs(info
->close_delay
));
878 wake_up_interruptible(&info
->open_wait
);
881 info
->flags
&= ~(ASYNC_NORMAL_ACTIVE
|ASYNC_CLOSING
);
883 wake_up_interruptible(&info
->close_wait
);
886 if (debug_level
>= DEBUG_LEVEL_INFO
)
887 printk("%s(%d):%s close() exit, count=%d\n", __FILE__
,__LINE__
,
888 tty
->driver
->name
, info
->count
);
891 /* Called by tty_hangup() when a hangup is signaled.
892 * This is the same as closing all open descriptors for the port.
894 static void hangup(struct tty_struct
*tty
)
896 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
898 if (debug_level
>= DEBUG_LEVEL_INFO
)
899 printk("%s(%d):%s hangup()\n",
900 __FILE__
,__LINE__
, info
->device_name
);
902 if (sanity_check(info
, tty
->name
, "hangup"))
909 info
->flags
&= ~ASYNC_NORMAL_ACTIVE
;
912 wake_up_interruptible(&info
->open_wait
);
915 /* Set new termios settings
917 static void set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
)
919 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
922 if (debug_level
>= DEBUG_LEVEL_INFO
)
923 printk("%s(%d):%s set_termios()\n", __FILE__
,__LINE__
,
928 /* Handle transition to B0 status */
929 if (old_termios
->c_cflag
& CBAUD
&&
930 !(tty
->termios
->c_cflag
& CBAUD
)) {
931 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
932 spin_lock_irqsave(&info
->lock
,flags
);
934 spin_unlock_irqrestore(&info
->lock
,flags
);
937 /* Handle transition away from B0 status */
938 if (!(old_termios
->c_cflag
& CBAUD
) &&
939 tty
->termios
->c_cflag
& CBAUD
) {
940 info
->serial_signals
|= SerialSignal_DTR
;
941 if (!(tty
->termios
->c_cflag
& CRTSCTS
) ||
942 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
943 info
->serial_signals
|= SerialSignal_RTS
;
945 spin_lock_irqsave(&info
->lock
,flags
);
947 spin_unlock_irqrestore(&info
->lock
,flags
);
950 /* Handle turning off CRTSCTS */
951 if (old_termios
->c_cflag
& CRTSCTS
&&
952 !(tty
->termios
->c_cflag
& CRTSCTS
)) {
958 /* Send a block of data
962 * tty pointer to tty information structure
963 * buf pointer to buffer containing send data
964 * count size of send data in bytes
966 * Return Value: number of characters written
968 static int write(struct tty_struct
*tty
,
969 const unsigned char *buf
, int count
)
972 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
975 if (debug_level
>= DEBUG_LEVEL_INFO
)
976 printk("%s(%d):%s write() count=%d\n",
977 __FILE__
,__LINE__
,info
->device_name
,count
);
979 if (sanity_check(info
, tty
->name
, "write"))
985 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
986 if (count
> info
->max_frame_size
) {
992 if (info
->tx_count
) {
993 /* send accumulated data from send_char() calls */
994 /* as frame and wait before accepting more data. */
995 tx_load_dma_buffer(info
, info
->tx_buf
, info
->tx_count
);
998 ret
= info
->tx_count
= count
;
999 tx_load_dma_buffer(info
, buf
, count
);
1004 c
= min_t(int, count
,
1005 min(info
->max_frame_size
- info
->tx_count
- 1,
1006 info
->max_frame_size
- info
->tx_put
));
1010 memcpy(info
->tx_buf
+ info
->tx_put
, buf
, c
);
1012 spin_lock_irqsave(&info
->lock
,flags
);
1014 if (info
->tx_put
>= info
->max_frame_size
)
1015 info
->tx_put
-= info
->max_frame_size
;
1016 info
->tx_count
+= c
;
1017 spin_unlock_irqrestore(&info
->lock
,flags
);
1024 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1026 ret
= info
->tx_count
= 0;
1029 tx_load_dma_buffer(info
, info
->tx_buf
, info
->tx_count
);
1032 if (info
->tx_count
&& !tty
->stopped
&& !tty
->hw_stopped
) {
1033 spin_lock_irqsave(&info
->lock
,flags
);
1034 if (!info
->tx_active
)
1036 spin_unlock_irqrestore(&info
->lock
,flags
);
1040 if (debug_level
>= DEBUG_LEVEL_INFO
)
1041 printk( "%s(%d):%s write() returning=%d\n",
1042 __FILE__
,__LINE__
,info
->device_name
,ret
);
1046 /* Add a character to the transmit buffer.
1048 static void put_char(struct tty_struct
*tty
, unsigned char ch
)
1050 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1051 unsigned long flags
;
1053 if ( debug_level
>= DEBUG_LEVEL_INFO
) {
1054 printk( "%s(%d):%s put_char(%d)\n",
1055 __FILE__
,__LINE__
,info
->device_name
,ch
);
1058 if (sanity_check(info
, tty
->name
, "put_char"))
1064 spin_lock_irqsave(&info
->lock
,flags
);
1066 if ( (info
->params
.mode
!= MGSL_MODE_HDLC
) ||
1067 !info
->tx_active
) {
1069 if (info
->tx_count
< info
->max_frame_size
- 1) {
1070 info
->tx_buf
[info
->tx_put
++] = ch
;
1071 if (info
->tx_put
>= info
->max_frame_size
)
1072 info
->tx_put
-= info
->max_frame_size
;
1077 spin_unlock_irqrestore(&info
->lock
,flags
);
1080 /* Send a high-priority XON/XOFF character
1082 static void send_xchar(struct tty_struct
*tty
, char ch
)
1084 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1085 unsigned long flags
;
1087 if (debug_level
>= DEBUG_LEVEL_INFO
)
1088 printk("%s(%d):%s send_xchar(%d)\n",
1089 __FILE__
,__LINE__
, info
->device_name
, ch
);
1091 if (sanity_check(info
, tty
->name
, "send_xchar"))
1096 /* Make sure transmit interrupts are on */
1097 spin_lock_irqsave(&info
->lock
,flags
);
1098 if (!info
->tx_enabled
)
1100 spin_unlock_irqrestore(&info
->lock
,flags
);
1104 /* Wait until the transmitter is empty.
1106 static void wait_until_sent(struct tty_struct
*tty
, int timeout
)
1108 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
1109 unsigned long orig_jiffies
, char_time
;
1114 if (debug_level
>= DEBUG_LEVEL_INFO
)
1115 printk("%s(%d):%s wait_until_sent() entry\n",
1116 __FILE__
,__LINE__
, info
->device_name
);
1118 if (sanity_check(info
, tty
->name
, "wait_until_sent"))
1123 if (!(info
->flags
& ASYNC_INITIALIZED
))
1126 orig_jiffies
= jiffies
;
1128 /* Set check interval to 1/5 of estimated time to
1129 * send a character, and make it at least 1. The check
1130 * interval should also be less than the timeout.
1131 * Note: use tight timings here to satisfy the NIST-PCTS.
1134 if ( info
->params
.data_rate
) {
1135 char_time
= info
->timeout
/(32 * 5);
1142 char_time
= min_t(unsigned long, char_time
, timeout
);
1144 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
1145 while (info
->tx_active
) {
1146 msleep_interruptible(jiffies_to_msecs(char_time
));
1147 if (signal_pending(current
))
1149 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
1153 //TODO: determine if there is something similar to USC16C32
1154 // TXSTATUS_ALL_SENT status
1155 while ( info
->tx_active
&& info
->tx_enabled
) {
1156 msleep_interruptible(jiffies_to_msecs(char_time
));
1157 if (signal_pending(current
))
1159 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
1166 if (debug_level
>= DEBUG_LEVEL_INFO
)
1167 printk("%s(%d):%s wait_until_sent() exit\n",
1168 __FILE__
,__LINE__
, info
->device_name
);
1171 /* Return the count of free bytes in transmit buffer
1173 static int write_room(struct tty_struct
*tty
)
1175 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1178 if (sanity_check(info
, tty
->name
, "write_room"))
1182 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1183 ret
= (info
->tx_active
) ? 0 : HDLC_MAX_FRAME_SIZE
;
1185 ret
= info
->max_frame_size
- info
->tx_count
- 1;
1191 if (debug_level
>= DEBUG_LEVEL_INFO
)
1192 printk("%s(%d):%s write_room()=%d\n",
1193 __FILE__
, __LINE__
, info
->device_name
, ret
);
1198 /* enable transmitter and send remaining buffered characters
1200 static void flush_chars(struct tty_struct
*tty
)
1202 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1203 unsigned long flags
;
1205 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1206 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1207 __FILE__
,__LINE__
,info
->device_name
,info
->tx_count
);
1209 if (sanity_check(info
, tty
->name
, "flush_chars"))
1212 if (info
->tx_count
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
1216 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1217 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1218 __FILE__
,__LINE__
,info
->device_name
);
1220 spin_lock_irqsave(&info
->lock
,flags
);
1222 if (!info
->tx_active
) {
1223 if ( (info
->params
.mode
== MGSL_MODE_HDLC
) &&
1225 /* operating in synchronous (frame oriented) mode */
1226 /* copy data from circular tx_buf to */
1227 /* transmit DMA buffer. */
1228 tx_load_dma_buffer(info
,
1229 info
->tx_buf
,info
->tx_count
);
1234 spin_unlock_irqrestore(&info
->lock
,flags
);
1237 /* Discard all data in the send buffer
1239 static void flush_buffer(struct tty_struct
*tty
)
1241 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1242 unsigned long flags
;
1244 if (debug_level
>= DEBUG_LEVEL_INFO
)
1245 printk("%s(%d):%s flush_buffer() entry\n",
1246 __FILE__
,__LINE__
, info
->device_name
);
1248 if (sanity_check(info
, tty
->name
, "flush_buffer"))
1251 spin_lock_irqsave(&info
->lock
,flags
);
1252 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
1253 del_timer(&info
->tx_timer
);
1254 spin_unlock_irqrestore(&info
->lock
,flags
);
1259 /* throttle (stop) transmitter
1261 static void tx_hold(struct tty_struct
*tty
)
1263 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1264 unsigned long flags
;
1266 if (sanity_check(info
, tty
->name
, "tx_hold"))
1269 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1270 printk("%s(%d):%s tx_hold()\n",
1271 __FILE__
,__LINE__
,info
->device_name
);
1273 spin_lock_irqsave(&info
->lock
,flags
);
1274 if (info
->tx_enabled
)
1276 spin_unlock_irqrestore(&info
->lock
,flags
);
1279 /* release (start) transmitter
1281 static void tx_release(struct tty_struct
*tty
)
1283 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1284 unsigned long flags
;
1286 if (sanity_check(info
, tty
->name
, "tx_release"))
1289 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1290 printk("%s(%d):%s tx_release()\n",
1291 __FILE__
,__LINE__
,info
->device_name
);
1293 spin_lock_irqsave(&info
->lock
,flags
);
1294 if (!info
->tx_enabled
)
1296 spin_unlock_irqrestore(&info
->lock
,flags
);
1299 /* Service an IOCTL request
1303 * tty pointer to tty instance data
1304 * file pointer to associated file object for device
1305 * cmd IOCTL command code
1306 * arg command argument/context
1308 * Return Value: 0 if success, otherwise error code
1310 static int do_ioctl(struct tty_struct
*tty
, struct file
*file
,
1311 unsigned int cmd
, unsigned long arg
)
1313 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1315 struct mgsl_icount cnow
; /* kernel counter temps */
1316 struct serial_icounter_struct __user
*p_cuser
; /* user space */
1317 unsigned long flags
;
1318 void __user
*argp
= (void __user
*)arg
;
1320 if (debug_level
>= DEBUG_LEVEL_INFO
)
1321 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__
,__LINE__
,
1322 info
->device_name
, cmd
);
1324 if (sanity_check(info
, tty
->name
, "ioctl"))
1327 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
1328 (cmd
!= TIOCMIWAIT
) && (cmd
!= TIOCGICOUNT
)) {
1329 if (tty
->flags
& (1 << TTY_IO_ERROR
))
1334 case MGSL_IOCGPARAMS
:
1335 return get_params(info
, argp
);
1336 case MGSL_IOCSPARAMS
:
1337 return set_params(info
, argp
);
1338 case MGSL_IOCGTXIDLE
:
1339 return get_txidle(info
, argp
);
1340 case MGSL_IOCSTXIDLE
:
1341 return set_txidle(info
, (int)arg
);
1342 case MGSL_IOCTXENABLE
:
1343 return tx_enable(info
, (int)arg
);
1344 case MGSL_IOCRXENABLE
:
1345 return rx_enable(info
, (int)arg
);
1346 case MGSL_IOCTXABORT
:
1347 return tx_abort(info
);
1348 case MGSL_IOCGSTATS
:
1349 return get_stats(info
, argp
);
1350 case MGSL_IOCWAITEVENT
:
1351 return wait_mgsl_event(info
, argp
);
1352 case MGSL_IOCLOOPTXDONE
:
1353 return 0; // TODO: Not supported, need to document
1354 /* Wait for modem input (DCD,RI,DSR,CTS) change
1355 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1358 return modem_input_wait(info
,(int)arg
);
1361 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1362 * Return: write counters to the user passed counter struct
1363 * NB: both 1->0 and 0->1 transitions are counted except for
1364 * RI where only 0->1 is counted.
1367 spin_lock_irqsave(&info
->lock
,flags
);
1368 cnow
= info
->icount
;
1369 spin_unlock_irqrestore(&info
->lock
,flags
);
1371 PUT_USER(error
,cnow
.cts
, &p_cuser
->cts
);
1372 if (error
) return error
;
1373 PUT_USER(error
,cnow
.dsr
, &p_cuser
->dsr
);
1374 if (error
) return error
;
1375 PUT_USER(error
,cnow
.rng
, &p_cuser
->rng
);
1376 if (error
) return error
;
1377 PUT_USER(error
,cnow
.dcd
, &p_cuser
->dcd
);
1378 if (error
) return error
;
1379 PUT_USER(error
,cnow
.rx
, &p_cuser
->rx
);
1380 if (error
) return error
;
1381 PUT_USER(error
,cnow
.tx
, &p_cuser
->tx
);
1382 if (error
) return error
;
1383 PUT_USER(error
,cnow
.frame
, &p_cuser
->frame
);
1384 if (error
) return error
;
1385 PUT_USER(error
,cnow
.overrun
, &p_cuser
->overrun
);
1386 if (error
) return error
;
1387 PUT_USER(error
,cnow
.parity
, &p_cuser
->parity
);
1388 if (error
) return error
;
1389 PUT_USER(error
,cnow
.brk
, &p_cuser
->brk
);
1390 if (error
) return error
;
1391 PUT_USER(error
,cnow
.buf_overrun
, &p_cuser
->buf_overrun
);
1392 if (error
) return error
;
1395 return -ENOIOCTLCMD
;
1400 static int ioctl(struct tty_struct
*tty
, struct file
*file
,
1401 unsigned int cmd
, unsigned long arg
)
1405 ret
= do_ioctl(tty
, file
, cmd
, arg
);
1411 * /proc fs routines....
1414 static inline int line_info(char *buf
, SLMP_INFO
*info
)
1418 unsigned long flags
;
1420 ret
= sprintf(buf
, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1421 "\tIRQ=%d MaxFrameSize=%u\n",
1423 info
->phys_sca_base
,
1424 info
->phys_memory_base
,
1425 info
->phys_statctrl_base
,
1426 info
->phys_lcr_base
,
1428 info
->max_frame_size
);
1430 /* output current serial signal states */
1431 spin_lock_irqsave(&info
->lock
,flags
);
1433 spin_unlock_irqrestore(&info
->lock
,flags
);
1437 if (info
->serial_signals
& SerialSignal_RTS
)
1438 strcat(stat_buf
, "|RTS");
1439 if (info
->serial_signals
& SerialSignal_CTS
)
1440 strcat(stat_buf
, "|CTS");
1441 if (info
->serial_signals
& SerialSignal_DTR
)
1442 strcat(stat_buf
, "|DTR");
1443 if (info
->serial_signals
& SerialSignal_DSR
)
1444 strcat(stat_buf
, "|DSR");
1445 if (info
->serial_signals
& SerialSignal_DCD
)
1446 strcat(stat_buf
, "|CD");
1447 if (info
->serial_signals
& SerialSignal_RI
)
1448 strcat(stat_buf
, "|RI");
1450 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1451 ret
+= sprintf(buf
+ret
, "\tHDLC txok:%d rxok:%d",
1452 info
->icount
.txok
, info
->icount
.rxok
);
1453 if (info
->icount
.txunder
)
1454 ret
+= sprintf(buf
+ret
, " txunder:%d", info
->icount
.txunder
);
1455 if (info
->icount
.txabort
)
1456 ret
+= sprintf(buf
+ret
, " txabort:%d", info
->icount
.txabort
);
1457 if (info
->icount
.rxshort
)
1458 ret
+= sprintf(buf
+ret
, " rxshort:%d", info
->icount
.rxshort
);
1459 if (info
->icount
.rxlong
)
1460 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxlong
);
1461 if (info
->icount
.rxover
)
1462 ret
+= sprintf(buf
+ret
, " rxover:%d", info
->icount
.rxover
);
1463 if (info
->icount
.rxcrc
)
1464 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxcrc
);
1466 ret
+= sprintf(buf
+ret
, "\tASYNC tx:%d rx:%d",
1467 info
->icount
.tx
, info
->icount
.rx
);
1468 if (info
->icount
.frame
)
1469 ret
+= sprintf(buf
+ret
, " fe:%d", info
->icount
.frame
);
1470 if (info
->icount
.parity
)
1471 ret
+= sprintf(buf
+ret
, " pe:%d", info
->icount
.parity
);
1472 if (info
->icount
.brk
)
1473 ret
+= sprintf(buf
+ret
, " brk:%d", info
->icount
.brk
);
1474 if (info
->icount
.overrun
)
1475 ret
+= sprintf(buf
+ret
, " oe:%d", info
->icount
.overrun
);
1478 /* Append serial signal status to end */
1479 ret
+= sprintf(buf
+ret
, " %s\n", stat_buf
+1);
1481 ret
+= sprintf(buf
+ret
, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1482 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
1488 /* Called to print information about devices
1490 static int read_proc(char *page
, char **start
, off_t off
, int count
,
1491 int *eof
, void *data
)
1497 len
+= sprintf(page
, "synclinkmp driver:%s\n", driver_version
);
1499 info
= synclinkmp_device_list
;
1501 l
= line_info(page
+ len
, info
);
1503 if (len
+begin
> off
+count
)
1505 if (len
+begin
< off
) {
1509 info
= info
->next_device
;
1514 if (off
>= len
+begin
)
1516 *start
= page
+ (off
-begin
);
1517 return ((count
< begin
+len
-off
) ? count
: begin
+len
-off
);
1520 /* Return the count of bytes in transmit buffer
1522 static int chars_in_buffer(struct tty_struct
*tty
)
1524 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1526 if (sanity_check(info
, tty
->name
, "chars_in_buffer"))
1529 if (debug_level
>= DEBUG_LEVEL_INFO
)
1530 printk("%s(%d):%s chars_in_buffer()=%d\n",
1531 __FILE__
, __LINE__
, info
->device_name
, info
->tx_count
);
1533 return info
->tx_count
;
1536 /* Signal remote device to throttle send data (our receive data)
1538 static void throttle(struct tty_struct
* tty
)
1540 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1541 unsigned long flags
;
1543 if (debug_level
>= DEBUG_LEVEL_INFO
)
1544 printk("%s(%d):%s throttle() entry\n",
1545 __FILE__
,__LINE__
, info
->device_name
);
1547 if (sanity_check(info
, tty
->name
, "throttle"))
1551 send_xchar(tty
, STOP_CHAR(tty
));
1553 if (tty
->termios
->c_cflag
& CRTSCTS
) {
1554 spin_lock_irqsave(&info
->lock
,flags
);
1555 info
->serial_signals
&= ~SerialSignal_RTS
;
1557 spin_unlock_irqrestore(&info
->lock
,flags
);
1561 /* Signal remote device to stop throttling send data (our receive data)
1563 static void unthrottle(struct tty_struct
* tty
)
1565 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1566 unsigned long flags
;
1568 if (debug_level
>= DEBUG_LEVEL_INFO
)
1569 printk("%s(%d):%s unthrottle() entry\n",
1570 __FILE__
,__LINE__
, info
->device_name
);
1572 if (sanity_check(info
, tty
->name
, "unthrottle"))
1579 send_xchar(tty
, START_CHAR(tty
));
1582 if (tty
->termios
->c_cflag
& CRTSCTS
) {
1583 spin_lock_irqsave(&info
->lock
,flags
);
1584 info
->serial_signals
|= SerialSignal_RTS
;
1586 spin_unlock_irqrestore(&info
->lock
,flags
);
1590 /* set or clear transmit break condition
1591 * break_state -1=set break condition, 0=clear
1593 static void set_break(struct tty_struct
*tty
, int break_state
)
1595 unsigned char RegValue
;
1596 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
1597 unsigned long flags
;
1599 if (debug_level
>= DEBUG_LEVEL_INFO
)
1600 printk("%s(%d):%s set_break(%d)\n",
1601 __FILE__
,__LINE__
, info
->device_name
, break_state
);
1603 if (sanity_check(info
, tty
->name
, "set_break"))
1606 spin_lock_irqsave(&info
->lock
,flags
);
1607 RegValue
= read_reg(info
, CTL
);
1608 if (break_state
== -1)
1612 write_reg(info
, CTL
, RegValue
);
1613 spin_unlock_irqrestore(&info
->lock
,flags
);
1616 #if SYNCLINK_GENERIC_HDLC
1619 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1620 * set encoding and frame check sequence (FCS) options
1622 * dev pointer to network device structure
1623 * encoding serial encoding setting
1624 * parity FCS setting
1626 * returns 0 if success, otherwise error code
1628 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
1629 unsigned short parity
)
1631 SLMP_INFO
*info
= dev_to_port(dev
);
1632 unsigned char new_encoding
;
1633 unsigned short new_crctype
;
1635 /* return error if TTY interface open */
1641 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
1642 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
1643 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
1644 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
1645 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
1646 default: return -EINVAL
;
1651 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
1652 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
1653 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
1654 default: return -EINVAL
;
1657 info
->params
.encoding
= new_encoding
;
1658 info
->params
.crc_type
= new_crctype
;
1660 /* if network interface up, reprogram hardware */
1668 * called by generic HDLC layer to send frame
1670 * skb socket buffer containing HDLC frame
1671 * dev pointer to network device structure
1673 * returns 0 if success, otherwise error code
1675 static int hdlcdev_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1677 SLMP_INFO
*info
= dev_to_port(dev
);
1678 struct net_device_stats
*stats
= hdlc_stats(dev
);
1679 unsigned long flags
;
1681 if (debug_level
>= DEBUG_LEVEL_INFO
)
1682 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
1684 /* stop sending until this frame completes */
1685 netif_stop_queue(dev
);
1687 /* copy data to device buffers */
1688 info
->tx_count
= skb
->len
;
1689 tx_load_dma_buffer(info
, skb
->data
, skb
->len
);
1691 /* update network statistics */
1692 stats
->tx_packets
++;
1693 stats
->tx_bytes
+= skb
->len
;
1695 /* done with socket buffer, so free it */
1698 /* save start time for transmit timeout detection */
1699 dev
->trans_start
= jiffies
;
1701 /* start hardware transmitter if necessary */
1702 spin_lock_irqsave(&info
->lock
,flags
);
1703 if (!info
->tx_active
)
1705 spin_unlock_irqrestore(&info
->lock
,flags
);
1711 * called by network layer when interface enabled
1712 * claim resources and initialize hardware
1714 * dev pointer to network device structure
1716 * returns 0 if success, otherwise error code
1718 static int hdlcdev_open(struct net_device
*dev
)
1720 SLMP_INFO
*info
= dev_to_port(dev
);
1722 unsigned long flags
;
1724 if (debug_level
>= DEBUG_LEVEL_INFO
)
1725 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
1727 /* generic HDLC layer open processing */
1728 if ((rc
= hdlc_open(dev
)))
1731 /* arbitrate between network and tty opens */
1732 spin_lock_irqsave(&info
->netlock
, flags
);
1733 if (info
->count
!= 0 || info
->netcount
!= 0) {
1734 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
1735 spin_unlock_irqrestore(&info
->netlock
, flags
);
1739 spin_unlock_irqrestore(&info
->netlock
, flags
);
1741 /* claim resources and init adapter */
1742 if ((rc
= startup(info
)) != 0) {
1743 spin_lock_irqsave(&info
->netlock
, flags
);
1745 spin_unlock_irqrestore(&info
->netlock
, flags
);
1749 /* assert DTR and RTS, apply hardware settings */
1750 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1753 /* enable network layer transmit */
1754 dev
->trans_start
= jiffies
;
1755 netif_start_queue(dev
);
1757 /* inform generic HDLC layer of current DCD status */
1758 spin_lock_irqsave(&info
->lock
, flags
);
1760 spin_unlock_irqrestore(&info
->lock
, flags
);
1761 if (info
->serial_signals
& SerialSignal_DCD
)
1762 netif_carrier_on(dev
);
1764 netif_carrier_off(dev
);
1769 * called by network layer when interface is disabled
1770 * shutdown hardware and release resources
1772 * dev pointer to network device structure
1774 * returns 0 if success, otherwise error code
1776 static int hdlcdev_close(struct net_device
*dev
)
1778 SLMP_INFO
*info
= dev_to_port(dev
);
1779 unsigned long flags
;
1781 if (debug_level
>= DEBUG_LEVEL_INFO
)
1782 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
1784 netif_stop_queue(dev
);
1786 /* shutdown adapter and release resources */
1791 spin_lock_irqsave(&info
->netlock
, flags
);
1793 spin_unlock_irqrestore(&info
->netlock
, flags
);
1799 * called by network layer to process IOCTL call to network device
1801 * dev pointer to network device structure
1802 * ifr pointer to network interface request structure
1803 * cmd IOCTL command code
1805 * returns 0 if success, otherwise error code
1807 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1809 const size_t size
= sizeof(sync_serial_settings
);
1810 sync_serial_settings new_line
;
1811 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
1812 SLMP_INFO
*info
= dev_to_port(dev
);
1815 if (debug_level
>= DEBUG_LEVEL_INFO
)
1816 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
1818 /* return error if TTY interface open */
1822 if (cmd
!= SIOCWANDEV
)
1823 return hdlc_ioctl(dev
, ifr
, cmd
);
1825 switch(ifr
->ifr_settings
.type
) {
1826 case IF_GET_IFACE
: /* return current sync_serial_settings */
1828 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
1829 if (ifr
->ifr_settings
.size
< size
) {
1830 ifr
->ifr_settings
.size
= size
; /* data size wanted */
1834 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1835 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1836 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1837 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1840 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
1841 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
1842 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
1843 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
1844 default: new_line
.clock_type
= CLOCK_DEFAULT
;
1847 new_line
.clock_rate
= info
->params
.clock_speed
;
1848 new_line
.loopback
= info
->params
.loopback
? 1:0;
1850 if (copy_to_user(line
, &new_line
, size
))
1854 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
1856 if(!capable(CAP_NET_ADMIN
))
1858 if (copy_from_user(&new_line
, line
, size
))
1861 switch (new_line
.clock_type
)
1863 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
1864 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
1865 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
1866 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
1867 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
1868 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1869 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1870 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1871 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
1872 default: return -EINVAL
;
1875 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
1878 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1879 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1880 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1881 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1882 info
->params
.flags
|= flags
;
1884 info
->params
.loopback
= new_line
.loopback
;
1886 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
1887 info
->params
.clock_speed
= new_line
.clock_rate
;
1889 info
->params
.clock_speed
= 0;
1891 /* if network interface up, reprogram hardware */
1897 return hdlc_ioctl(dev
, ifr
, cmd
);
1902 * called by network layer when transmit timeout is detected
1904 * dev pointer to network device structure
1906 static void hdlcdev_tx_timeout(struct net_device
*dev
)
1908 SLMP_INFO
*info
= dev_to_port(dev
);
1909 struct net_device_stats
*stats
= hdlc_stats(dev
);
1910 unsigned long flags
;
1912 if (debug_level
>= DEBUG_LEVEL_INFO
)
1913 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
1916 stats
->tx_aborted_errors
++;
1918 spin_lock_irqsave(&info
->lock
,flags
);
1920 spin_unlock_irqrestore(&info
->lock
,flags
);
1922 netif_wake_queue(dev
);
1926 * called by device driver when transmit completes
1927 * reenable network layer transmit if stopped
1929 * info pointer to device instance information
1931 static void hdlcdev_tx_done(SLMP_INFO
*info
)
1933 if (netif_queue_stopped(info
->netdev
))
1934 netif_wake_queue(info
->netdev
);
1938 * called by device driver when frame received
1939 * pass frame to network layer
1941 * info pointer to device instance information
1942 * buf pointer to buffer contianing frame data
1943 * size count of data bytes in buf
1945 static void hdlcdev_rx(SLMP_INFO
*info
, char *buf
, int size
)
1947 struct sk_buff
*skb
= dev_alloc_skb(size
);
1948 struct net_device
*dev
= info
->netdev
;
1949 struct net_device_stats
*stats
= hdlc_stats(dev
);
1951 if (debug_level
>= DEBUG_LEVEL_INFO
)
1952 printk("hdlcdev_rx(%s)\n",dev
->name
);
1955 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n", dev
->name
);
1956 stats
->rx_dropped
++;
1960 memcpy(skb_put(skb
, size
),buf
,size
);
1962 skb
->protocol
= hdlc_type_trans(skb
, info
->netdev
);
1964 stats
->rx_packets
++;
1965 stats
->rx_bytes
+= size
;
1969 info
->netdev
->last_rx
= jiffies
;
1973 * called by device driver when adding device instance
1974 * do generic HDLC initialization
1976 * info pointer to device instance information
1978 * returns 0 if success, otherwise error code
1980 static int hdlcdev_init(SLMP_INFO
*info
)
1983 struct net_device
*dev
;
1986 /* allocate and initialize network and HDLC layer objects */
1988 if (!(dev
= alloc_hdlcdev(info
))) {
1989 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
1993 /* for network layer reporting purposes only */
1994 dev
->mem_start
= info
->phys_sca_base
;
1995 dev
->mem_end
= info
->phys_sca_base
+ SCA_BASE_SIZE
- 1;
1996 dev
->irq
= info
->irq_level
;
1998 /* network layer callbacks and settings */
1999 dev
->do_ioctl
= hdlcdev_ioctl
;
2000 dev
->open
= hdlcdev_open
;
2001 dev
->stop
= hdlcdev_close
;
2002 dev
->tx_timeout
= hdlcdev_tx_timeout
;
2003 dev
->watchdog_timeo
= 10*HZ
;
2004 dev
->tx_queue_len
= 50;
2006 /* generic HDLC layer callbacks and settings */
2007 hdlc
= dev_to_hdlc(dev
);
2008 hdlc
->attach
= hdlcdev_attach
;
2009 hdlc
->xmit
= hdlcdev_xmit
;
2011 /* register objects with HDLC layer */
2012 if ((rc
= register_hdlc_device(dev
))) {
2013 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
2023 * called by device driver when removing device instance
2024 * do generic HDLC cleanup
2026 * info pointer to device instance information
2028 static void hdlcdev_exit(SLMP_INFO
*info
)
2030 unregister_hdlc_device(info
->netdev
);
2031 free_netdev(info
->netdev
);
2032 info
->netdev
= NULL
;
2035 #endif /* CONFIG_HDLC */
2038 /* Return next bottom half action to perform.
2039 * Return Value: BH action code or 0 if nothing to do.
2041 static int bh_action(SLMP_INFO
*info
)
2043 unsigned long flags
;
2046 spin_lock_irqsave(&info
->lock
,flags
);
2048 if (info
->pending_bh
& BH_RECEIVE
) {
2049 info
->pending_bh
&= ~BH_RECEIVE
;
2051 } else if (info
->pending_bh
& BH_TRANSMIT
) {
2052 info
->pending_bh
&= ~BH_TRANSMIT
;
2054 } else if (info
->pending_bh
& BH_STATUS
) {
2055 info
->pending_bh
&= ~BH_STATUS
;
2060 /* Mark BH routine as complete */
2061 info
->bh_running
= false;
2062 info
->bh_requested
= false;
2065 spin_unlock_irqrestore(&info
->lock
,flags
);
2070 /* Perform bottom half processing of work items queued by ISR.
2072 static void bh_handler(struct work_struct
*work
)
2074 SLMP_INFO
*info
= container_of(work
, SLMP_INFO
, task
);
2080 if ( debug_level
>= DEBUG_LEVEL_BH
)
2081 printk( "%s(%d):%s bh_handler() entry\n",
2082 __FILE__
,__LINE__
,info
->device_name
);
2084 info
->bh_running
= true;
2086 while((action
= bh_action(info
)) != 0) {
2088 /* Process work item */
2089 if ( debug_level
>= DEBUG_LEVEL_BH
)
2090 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2091 __FILE__
,__LINE__
,info
->device_name
, action
);
2105 /* unknown work item ID */
2106 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2107 __FILE__
,__LINE__
,info
->device_name
,action
);
2112 if ( debug_level
>= DEBUG_LEVEL_BH
)
2113 printk( "%s(%d):%s bh_handler() exit\n",
2114 __FILE__
,__LINE__
,info
->device_name
);
2117 static void bh_receive(SLMP_INFO
*info
)
2119 if ( debug_level
>= DEBUG_LEVEL_BH
)
2120 printk( "%s(%d):%s bh_receive()\n",
2121 __FILE__
,__LINE__
,info
->device_name
);
2123 while( rx_get_frame(info
) );
2126 static void bh_transmit(SLMP_INFO
*info
)
2128 struct tty_struct
*tty
= info
->tty
;
2130 if ( debug_level
>= DEBUG_LEVEL_BH
)
2131 printk( "%s(%d):%s bh_transmit() entry\n",
2132 __FILE__
,__LINE__
,info
->device_name
);
2138 static void bh_status(SLMP_INFO
*info
)
2140 if ( debug_level
>= DEBUG_LEVEL_BH
)
2141 printk( "%s(%d):%s bh_status() entry\n",
2142 __FILE__
,__LINE__
,info
->device_name
);
2144 info
->ri_chkcount
= 0;
2145 info
->dsr_chkcount
= 0;
2146 info
->dcd_chkcount
= 0;
2147 info
->cts_chkcount
= 0;
2150 static void isr_timer(SLMP_INFO
* info
)
2152 unsigned char timer
= (info
->port_num
& 1) ? TIMER2
: TIMER0
;
2154 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2155 write_reg(info
, IER2
, 0);
2157 /* TMCS, Timer Control/Status Register
2159 * 07 CMF, Compare match flag (read only) 1=match
2160 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2161 * 05 Reserved, must be 0
2162 * 04 TME, Timer Enable
2163 * 03..00 Reserved, must be 0
2167 write_reg(info
, (unsigned char)(timer
+ TMCS
), 0);
2169 info
->irq_occurred
= true;
2171 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2172 printk("%s(%d):%s isr_timer()\n",
2173 __FILE__
,__LINE__
,info
->device_name
);
2176 static void isr_rxint(SLMP_INFO
* info
)
2178 struct tty_struct
*tty
= info
->tty
;
2179 struct mgsl_icount
*icount
= &info
->icount
;
2180 unsigned char status
= read_reg(info
, SR1
) & info
->ie1_value
& (FLGD
+ IDLD
+ CDCD
+ BRKD
);
2181 unsigned char status2
= read_reg(info
, SR2
) & info
->ie2_value
& OVRN
;
2183 /* clear status bits */
2185 write_reg(info
, SR1
, status
);
2188 write_reg(info
, SR2
, status2
);
2190 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2191 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2192 __FILE__
,__LINE__
,info
->device_name
,status
,status2
);
2194 if (info
->params
.mode
== MGSL_MODE_ASYNC
) {
2195 if (status
& BRKD
) {
2198 /* process break detection if tty control
2199 * is not set to ignore it
2202 if (!(status
& info
->ignore_status_mask1
)) {
2203 if (info
->read_status_mask1
& BRKD
) {
2204 tty_insert_flip_char(tty
, 0, TTY_BREAK
);
2205 if (info
->flags
& ASYNC_SAK
)
2213 if (status
& (FLGD
|IDLD
)) {
2215 info
->icount
.exithunt
++;
2216 else if (status
& IDLD
)
2217 info
->icount
.rxidle
++;
2218 wake_up_interruptible(&info
->event_wait_q
);
2222 if (status
& CDCD
) {
2223 /* simulate a common modem status change interrupt
2226 get_signals( info
);
2228 MISCSTATUS_DCD_LATCHED
|(info
->serial_signals
&SerialSignal_DCD
));
2233 * handle async rx data interrupts
2235 static void isr_rxrdy(SLMP_INFO
* info
)
2238 unsigned char DataByte
;
2239 struct tty_struct
*tty
= info
->tty
;
2240 struct mgsl_icount
*icount
= &info
->icount
;
2242 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2243 printk("%s(%d):%s isr_rxrdy\n",
2244 __FILE__
,__LINE__
,info
->device_name
);
2246 while((status
= read_reg(info
,CST0
)) & BIT0
)
2250 DataByte
= read_reg(info
,TRB
);
2254 if ( status
& (PE
+ FRME
+ OVRN
) ) {
2255 printk("%s(%d):%s rxerr=%04X\n",
2256 __FILE__
,__LINE__
,info
->device_name
,status
);
2258 /* update error statistics */
2261 else if (status
& FRME
)
2263 else if (status
& OVRN
)
2266 /* discard char if tty control flags say so */
2267 if (status
& info
->ignore_status_mask2
)
2270 status
&= info
->read_status_mask2
;
2275 else if (status
& FRME
)
2277 if (status
& OVRN
) {
2278 /* Overrun is special, since it's
2279 * reported immediately, and doesn't
2280 * affect the current character
2285 } /* end of if (error) */
2288 tty_insert_flip_char(tty
, DataByte
, flag
);
2290 tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
2294 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
2295 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2296 __FILE__
,__LINE__
,info
->device_name
,
2297 icount
->rx
,icount
->brk
,icount
->parity
,
2298 icount
->frame
,icount
->overrun
);
2302 tty_flip_buffer_push(tty
);
2305 static void isr_txeom(SLMP_INFO
* info
, unsigned char status
)
2307 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2308 printk("%s(%d):%s isr_txeom status=%02x\n",
2309 __FILE__
,__LINE__
,info
->device_name
,status
);
2311 write_reg(info
, TXDMA
+ DIR, 0x00); /* disable Tx DMA IRQs */
2312 write_reg(info
, TXDMA
+ DSR
, 0xc0); /* clear IRQs and disable DMA */
2313 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
2315 if (status
& UDRN
) {
2316 write_reg(info
, CMD
, TXRESET
);
2317 write_reg(info
, CMD
, TXENABLE
);
2319 write_reg(info
, CMD
, TXBUFCLR
);
2321 /* disable and clear tx interrupts */
2322 info
->ie0_value
&= ~TXRDYE
;
2323 info
->ie1_value
&= ~(IDLE
+ UDRN
);
2324 write_reg16(info
, IE0
, (unsigned short)((info
->ie1_value
<< 8) + info
->ie0_value
));
2325 write_reg(info
, SR1
, (unsigned char)(UDRN
+ IDLE
));
2327 if ( info
->tx_active
) {
2328 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
2330 info
->icount
.txunder
++;
2331 else if (status
& IDLE
)
2332 info
->icount
.txok
++;
2335 info
->tx_active
= false;
2336 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
2338 del_timer(&info
->tx_timer
);
2340 if (info
->params
.mode
!= MGSL_MODE_ASYNC
&& info
->drop_rts_on_tx_done
) {
2341 info
->serial_signals
&= ~SerialSignal_RTS
;
2342 info
->drop_rts_on_tx_done
= false;
2346 #if SYNCLINK_GENERIC_HDLC
2348 hdlcdev_tx_done(info
);
2352 if (info
->tty
&& (info
->tty
->stopped
|| info
->tty
->hw_stopped
)) {
2356 info
->pending_bh
|= BH_TRANSMIT
;
2363 * handle tx status interrupts
2365 static void isr_txint(SLMP_INFO
* info
)
2367 unsigned char status
= read_reg(info
, SR1
) & info
->ie1_value
& (UDRN
+ IDLE
+ CCTS
);
2369 /* clear status bits */
2370 write_reg(info
, SR1
, status
);
2372 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2373 printk("%s(%d):%s isr_txint status=%02x\n",
2374 __FILE__
,__LINE__
,info
->device_name
,status
);
2376 if (status
& (UDRN
+ IDLE
))
2377 isr_txeom(info
, status
);
2379 if (status
& CCTS
) {
2380 /* simulate a common modem status change interrupt
2383 get_signals( info
);
2385 MISCSTATUS_CTS_LATCHED
|(info
->serial_signals
&SerialSignal_CTS
));
2391 * handle async tx data interrupts
2393 static void isr_txrdy(SLMP_INFO
* info
)
2395 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2396 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2397 __FILE__
,__LINE__
,info
->device_name
,info
->tx_count
);
2399 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
2400 /* disable TXRDY IRQ, enable IDLE IRQ */
2401 info
->ie0_value
&= ~TXRDYE
;
2402 info
->ie1_value
|= IDLE
;
2403 write_reg16(info
, IE0
, (unsigned short)((info
->ie1_value
<< 8) + info
->ie0_value
));
2407 if (info
->tty
&& (info
->tty
->stopped
|| info
->tty
->hw_stopped
)) {
2412 if ( info
->tx_count
)
2413 tx_load_fifo( info
);
2415 info
->tx_active
= false;
2416 info
->ie0_value
&= ~TXRDYE
;
2417 write_reg(info
, IE0
, info
->ie0_value
);
2420 if (info
->tx_count
< WAKEUP_CHARS
)
2421 info
->pending_bh
|= BH_TRANSMIT
;
2424 static void isr_rxdmaok(SLMP_INFO
* info
)
2426 /* BIT7 = EOT (end of transfer)
2427 * BIT6 = EOM (end of message/frame)
2429 unsigned char status
= read_reg(info
,RXDMA
+ DSR
) & 0xc0;
2431 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2432 write_reg(info
, RXDMA
+ DSR
, (unsigned char)(status
| 1));
2434 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2435 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2436 __FILE__
,__LINE__
,info
->device_name
,status
);
2438 info
->pending_bh
|= BH_RECEIVE
;
2441 static void isr_rxdmaerror(SLMP_INFO
* info
)
2443 /* BIT5 = BOF (buffer overflow)
2444 * BIT4 = COF (counter overflow)
2446 unsigned char status
= read_reg(info
,RXDMA
+ DSR
) & 0x30;
2448 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2449 write_reg(info
, RXDMA
+ DSR
, (unsigned char)(status
| 1));
2451 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2452 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2453 __FILE__
,__LINE__
,info
->device_name
,status
);
2455 info
->rx_overflow
= true;
2456 info
->pending_bh
|= BH_RECEIVE
;
2459 static void isr_txdmaok(SLMP_INFO
* info
)
2461 unsigned char status_reg1
= read_reg(info
, SR1
);
2463 write_reg(info
, TXDMA
+ DIR, 0x00); /* disable Tx DMA IRQs */
2464 write_reg(info
, TXDMA
+ DSR
, 0xc0); /* clear IRQs and disable DMA */
2465 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
2467 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2468 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2469 __FILE__
,__LINE__
,info
->device_name
,status_reg1
);
2471 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2472 write_reg16(info
, TRC0
, 0);
2473 info
->ie0_value
|= TXRDYE
;
2474 write_reg(info
, IE0
, info
->ie0_value
);
2477 static void isr_txdmaerror(SLMP_INFO
* info
)
2479 /* BIT5 = BOF (buffer overflow)
2480 * BIT4 = COF (counter overflow)
2482 unsigned char status
= read_reg(info
,TXDMA
+ DSR
) & 0x30;
2484 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2485 write_reg(info
, TXDMA
+ DSR
, (unsigned char)(status
| 1));
2487 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2488 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2489 __FILE__
,__LINE__
,info
->device_name
,status
);
2492 /* handle input serial signal changes
2494 static void isr_io_pin( SLMP_INFO
*info
, u16 status
)
2496 struct mgsl_icount
*icount
;
2498 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2499 printk("%s(%d):isr_io_pin status=%04X\n",
2500 __FILE__
,__LINE__
,status
);
2502 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
2503 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
2504 icount
= &info
->icount
;
2505 /* update input line counters */
2506 if (status
& MISCSTATUS_RI_LATCHED
) {
2508 if ( status
& SerialSignal_RI
)
2509 info
->input_signal_events
.ri_up
++;
2511 info
->input_signal_events
.ri_down
++;
2513 if (status
& MISCSTATUS_DSR_LATCHED
) {
2515 if ( status
& SerialSignal_DSR
)
2516 info
->input_signal_events
.dsr_up
++;
2518 info
->input_signal_events
.dsr_down
++;
2520 if (status
& MISCSTATUS_DCD_LATCHED
) {
2521 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
) {
2522 info
->ie1_value
&= ~CDCD
;
2523 write_reg(info
, IE1
, info
->ie1_value
);
2526 if (status
& SerialSignal_DCD
) {
2527 info
->input_signal_events
.dcd_up
++;
2529 info
->input_signal_events
.dcd_down
++;
2530 #if SYNCLINK_GENERIC_HDLC
2531 if (info
->netcount
) {
2532 if (status
& SerialSignal_DCD
)
2533 netif_carrier_on(info
->netdev
);
2535 netif_carrier_off(info
->netdev
);
2539 if (status
& MISCSTATUS_CTS_LATCHED
)
2541 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
) {
2542 info
->ie1_value
&= ~CCTS
;
2543 write_reg(info
, IE1
, info
->ie1_value
);
2546 if ( status
& SerialSignal_CTS
)
2547 info
->input_signal_events
.cts_up
++;
2549 info
->input_signal_events
.cts_down
++;
2551 wake_up_interruptible(&info
->status_event_wait_q
);
2552 wake_up_interruptible(&info
->event_wait_q
);
2554 if ( (info
->flags
& ASYNC_CHECK_CD
) &&
2555 (status
& MISCSTATUS_DCD_LATCHED
) ) {
2556 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2557 printk("%s CD now %s...", info
->device_name
,
2558 (status
& SerialSignal_DCD
) ? "on" : "off");
2559 if (status
& SerialSignal_DCD
)
2560 wake_up_interruptible(&info
->open_wait
);
2562 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2563 printk("doing serial hangup...");
2565 tty_hangup(info
->tty
);
2569 if ( (info
->flags
& ASYNC_CTS_FLOW
) &&
2570 (status
& MISCSTATUS_CTS_LATCHED
) ) {
2572 if (info
->tty
->hw_stopped
) {
2573 if (status
& SerialSignal_CTS
) {
2574 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2575 printk("CTS tx start...");
2576 info
->tty
->hw_stopped
= 0;
2578 info
->pending_bh
|= BH_TRANSMIT
;
2582 if (!(status
& SerialSignal_CTS
)) {
2583 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2584 printk("CTS tx stop...");
2585 info
->tty
->hw_stopped
= 1;
2593 info
->pending_bh
|= BH_STATUS
;
2596 /* Interrupt service routine entry point.
2599 * irq interrupt number that caused interrupt
2600 * dev_id device ID supplied during interrupt registration
2601 * regs interrupted processor context
2603 static irqreturn_t
synclinkmp_interrupt(int dummy
, void *dev_id
)
2605 SLMP_INFO
*info
= dev_id
;
2606 unsigned char status
, status0
, status1
=0;
2607 unsigned char dmastatus
, dmastatus0
, dmastatus1
=0;
2608 unsigned char timerstatus0
, timerstatus1
=0;
2609 unsigned char shift
;
2613 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2614 printk(KERN_DEBUG
"%s(%d): synclinkmp_interrupt(%d)entry.\n",
2615 __FILE__
, __LINE__
, info
->irq_level
);
2617 spin_lock(&info
->lock
);
2621 /* get status for SCA0 (ports 0-1) */
2622 tmp
= read_reg16(info
, ISR0
); /* get ISR0 and ISR1 in one read */
2623 status0
= (unsigned char)tmp
;
2624 dmastatus0
= (unsigned char)(tmp
>>8);
2625 timerstatus0
= read_reg(info
, ISR2
);
2627 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2628 printk(KERN_DEBUG
"%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2629 __FILE__
, __LINE__
, info
->device_name
,
2630 status0
, dmastatus0
, timerstatus0
);
2632 if (info
->port_count
== 4) {
2633 /* get status for SCA1 (ports 2-3) */
2634 tmp
= read_reg16(info
->port_array
[2], ISR0
);
2635 status1
= (unsigned char)tmp
;
2636 dmastatus1
= (unsigned char)(tmp
>>8);
2637 timerstatus1
= read_reg(info
->port_array
[2], ISR2
);
2639 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2640 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2641 __FILE__
,__LINE__
,info
->device_name
,
2642 status1
,dmastatus1
,timerstatus1
);
2645 if (!status0
&& !dmastatus0
&& !timerstatus0
&&
2646 !status1
&& !dmastatus1
&& !timerstatus1
)
2649 for(i
=0; i
< info
->port_count
; i
++) {
2650 if (info
->port_array
[i
] == NULL
)
2654 dmastatus
= dmastatus0
;
2657 dmastatus
= dmastatus1
;
2660 shift
= i
& 1 ? 4 :0;
2662 if (status
& BIT0
<< shift
)
2663 isr_rxrdy(info
->port_array
[i
]);
2664 if (status
& BIT1
<< shift
)
2665 isr_txrdy(info
->port_array
[i
]);
2666 if (status
& BIT2
<< shift
)
2667 isr_rxint(info
->port_array
[i
]);
2668 if (status
& BIT3
<< shift
)
2669 isr_txint(info
->port_array
[i
]);
2671 if (dmastatus
& BIT0
<< shift
)
2672 isr_rxdmaerror(info
->port_array
[i
]);
2673 if (dmastatus
& BIT1
<< shift
)
2674 isr_rxdmaok(info
->port_array
[i
]);
2675 if (dmastatus
& BIT2
<< shift
)
2676 isr_txdmaerror(info
->port_array
[i
]);
2677 if (dmastatus
& BIT3
<< shift
)
2678 isr_txdmaok(info
->port_array
[i
]);
2681 if (timerstatus0
& (BIT5
| BIT4
))
2682 isr_timer(info
->port_array
[0]);
2683 if (timerstatus0
& (BIT7
| BIT6
))
2684 isr_timer(info
->port_array
[1]);
2685 if (timerstatus1
& (BIT5
| BIT4
))
2686 isr_timer(info
->port_array
[2]);
2687 if (timerstatus1
& (BIT7
| BIT6
))
2688 isr_timer(info
->port_array
[3]);
2691 for(i
=0; i
< info
->port_count
; i
++) {
2692 SLMP_INFO
* port
= info
->port_array
[i
];
2694 /* Request bottom half processing if there's something
2695 * for it to do and the bh is not already running.
2697 * Note: startup adapter diags require interrupts.
2698 * do not request bottom half processing if the
2699 * device is not open in a normal mode.
2701 if ( port
&& (port
->count
|| port
->netcount
) &&
2702 port
->pending_bh
&& !port
->bh_running
&&
2703 !port
->bh_requested
) {
2704 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2705 printk("%s(%d):%s queueing bh task.\n",
2706 __FILE__
,__LINE__
,port
->device_name
);
2707 schedule_work(&port
->task
);
2708 port
->bh_requested
= true;
2712 spin_unlock(&info
->lock
);
2714 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2715 printk(KERN_DEBUG
"%s(%d):synclinkmp_interrupt(%d)exit.\n",
2716 __FILE__
, __LINE__
, info
->irq_level
);
2720 /* Initialize and start device.
2722 static int startup(SLMP_INFO
* info
)
2724 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2725 printk("%s(%d):%s tx_releaseup()\n",__FILE__
,__LINE__
,info
->device_name
);
2727 if (info
->flags
& ASYNC_INITIALIZED
)
2730 if (!info
->tx_buf
) {
2731 info
->tx_buf
= kmalloc(info
->max_frame_size
, GFP_KERNEL
);
2732 if (!info
->tx_buf
) {
2733 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
2734 __FILE__
,__LINE__
,info
->device_name
);
2739 info
->pending_bh
= 0;
2741 memset(&info
->icount
, 0, sizeof(info
->icount
));
2743 /* program hardware for current parameters */
2746 change_params(info
);
2748 mod_timer(&info
->status_timer
, jiffies
+ msecs_to_jiffies(10));
2751 clear_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
2753 info
->flags
|= ASYNC_INITIALIZED
;
2758 /* Called by close() and hangup() to shutdown hardware
2760 static void shutdown(SLMP_INFO
* info
)
2762 unsigned long flags
;
2764 if (!(info
->flags
& ASYNC_INITIALIZED
))
2767 if (debug_level
>= DEBUG_LEVEL_INFO
)
2768 printk("%s(%d):%s synclinkmp_shutdown()\n",
2769 __FILE__
,__LINE__
, info
->device_name
);
2771 /* clear status wait queue because status changes */
2772 /* can't happen after shutting down the hardware */
2773 wake_up_interruptible(&info
->status_event_wait_q
);
2774 wake_up_interruptible(&info
->event_wait_q
);
2776 del_timer(&info
->tx_timer
);
2777 del_timer(&info
->status_timer
);
2779 kfree(info
->tx_buf
);
2780 info
->tx_buf
= NULL
;
2782 spin_lock_irqsave(&info
->lock
,flags
);
2786 if (!info
->tty
|| info
->tty
->termios
->c_cflag
& HUPCL
) {
2787 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
2791 spin_unlock_irqrestore(&info
->lock
,flags
);
2794 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
2796 info
->flags
&= ~ASYNC_INITIALIZED
;
2799 static void program_hw(SLMP_INFO
*info
)
2801 unsigned long flags
;
2803 spin_lock_irqsave(&info
->lock
,flags
);
2808 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
2810 if (info
->params
.mode
== MGSL_MODE_HDLC
|| info
->netcount
)
2817 info
->dcd_chkcount
= 0;
2818 info
->cts_chkcount
= 0;
2819 info
->ri_chkcount
= 0;
2820 info
->dsr_chkcount
= 0;
2822 info
->ie1_value
|= (CDCD
|CCTS
);
2823 write_reg(info
, IE1
, info
->ie1_value
);
2827 if (info
->netcount
|| (info
->tty
&& info
->tty
->termios
->c_cflag
& CREAD
) )
2830 spin_unlock_irqrestore(&info
->lock
,flags
);
2833 /* Reconfigure adapter based on new parameters
2835 static void change_params(SLMP_INFO
*info
)
2840 if (!info
->tty
|| !info
->tty
->termios
)
2843 if (debug_level
>= DEBUG_LEVEL_INFO
)
2844 printk("%s(%d):%s change_params()\n",
2845 __FILE__
,__LINE__
, info
->device_name
);
2847 cflag
= info
->tty
->termios
->c_cflag
;
2849 /* if B0 rate (hangup) specified then negate DTR and RTS */
2850 /* otherwise assert DTR and RTS */
2852 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
2854 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
2856 /* byte size and parity */
2858 switch (cflag
& CSIZE
) {
2859 case CS5
: info
->params
.data_bits
= 5; break;
2860 case CS6
: info
->params
.data_bits
= 6; break;
2861 case CS7
: info
->params
.data_bits
= 7; break;
2862 case CS8
: info
->params
.data_bits
= 8; break;
2863 /* Never happens, but GCC is too dumb to figure it out */
2864 default: info
->params
.data_bits
= 7; break;
2868 info
->params
.stop_bits
= 2;
2870 info
->params
.stop_bits
= 1;
2872 info
->params
.parity
= ASYNC_PARITY_NONE
;
2873 if (cflag
& PARENB
) {
2875 info
->params
.parity
= ASYNC_PARITY_ODD
;
2877 info
->params
.parity
= ASYNC_PARITY_EVEN
;
2880 info
->params
.parity
= ASYNC_PARITY_SPACE
;
2884 /* calculate number of jiffies to transmit a full
2885 * FIFO (32 bytes) at specified data rate
2887 bits_per_char
= info
->params
.data_bits
+
2888 info
->params
.stop_bits
+ 1;
2890 /* if port data rate is set to 460800 or less then
2891 * allow tty settings to override, otherwise keep the
2892 * current data rate.
2894 if (info
->params
.data_rate
<= 460800) {
2895 info
->params
.data_rate
= tty_get_baud_rate(info
->tty
);
2898 if ( info
->params
.data_rate
) {
2899 info
->timeout
= (32*HZ
*bits_per_char
) /
2900 info
->params
.data_rate
;
2902 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
2904 if (cflag
& CRTSCTS
)
2905 info
->flags
|= ASYNC_CTS_FLOW
;
2907 info
->flags
&= ~ASYNC_CTS_FLOW
;
2910 info
->flags
&= ~ASYNC_CHECK_CD
;
2912 info
->flags
|= ASYNC_CHECK_CD
;
2914 /* process tty input control flags */
2916 info
->read_status_mask2
= OVRN
;
2917 if (I_INPCK(info
->tty
))
2918 info
->read_status_mask2
|= PE
| FRME
;
2919 if (I_BRKINT(info
->tty
) || I_PARMRK(info
->tty
))
2920 info
->read_status_mask1
|= BRKD
;
2921 if (I_IGNPAR(info
->tty
))
2922 info
->ignore_status_mask2
|= PE
| FRME
;
2923 if (I_IGNBRK(info
->tty
)) {
2924 info
->ignore_status_mask1
|= BRKD
;
2925 /* If ignoring parity and break indicators, ignore
2926 * overruns too. (For real raw support).
2928 if (I_IGNPAR(info
->tty
))
2929 info
->ignore_status_mask2
|= OVRN
;
2935 static int get_stats(SLMP_INFO
* info
, struct mgsl_icount __user
*user_icount
)
2939 if (debug_level
>= DEBUG_LEVEL_INFO
)
2940 printk("%s(%d):%s get_params()\n",
2941 __FILE__
,__LINE__
, info
->device_name
);
2944 memset(&info
->icount
, 0, sizeof(info
->icount
));
2946 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2954 static int get_params(SLMP_INFO
* info
, MGSL_PARAMS __user
*user_params
)
2957 if (debug_level
>= DEBUG_LEVEL_INFO
)
2958 printk("%s(%d):%s get_params()\n",
2959 __FILE__
,__LINE__
, info
->device_name
);
2961 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2963 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2964 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2965 __FILE__
,__LINE__
,info
->device_name
);
2972 static int set_params(SLMP_INFO
* info
, MGSL_PARAMS __user
*new_params
)
2974 unsigned long flags
;
2975 MGSL_PARAMS tmp_params
;
2978 if (debug_level
>= DEBUG_LEVEL_INFO
)
2979 printk("%s(%d):%s set_params\n",
2980 __FILE__
,__LINE__
,info
->device_name
);
2981 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2983 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2984 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2985 __FILE__
,__LINE__
,info
->device_name
);
2989 spin_lock_irqsave(&info
->lock
,flags
);
2990 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2991 spin_unlock_irqrestore(&info
->lock
,flags
);
2993 change_params(info
);
2998 static int get_txidle(SLMP_INFO
* info
, int __user
*idle_mode
)
3002 if (debug_level
>= DEBUG_LEVEL_INFO
)
3003 printk("%s(%d):%s get_txidle()=%d\n",
3004 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
3006 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
3008 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3009 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3010 __FILE__
,__LINE__
,info
->device_name
);
3017 static int set_txidle(SLMP_INFO
* info
, int idle_mode
)
3019 unsigned long flags
;
3021 if (debug_level
>= DEBUG_LEVEL_INFO
)
3022 printk("%s(%d):%s set_txidle(%d)\n",
3023 __FILE__
,__LINE__
,info
->device_name
, idle_mode
);
3025 spin_lock_irqsave(&info
->lock
,flags
);
3026 info
->idle_mode
= idle_mode
;
3027 tx_set_idle( info
);
3028 spin_unlock_irqrestore(&info
->lock
,flags
);
3032 static int tx_enable(SLMP_INFO
* info
, int enable
)
3034 unsigned long flags
;
3036 if (debug_level
>= DEBUG_LEVEL_INFO
)
3037 printk("%s(%d):%s tx_enable(%d)\n",
3038 __FILE__
,__LINE__
,info
->device_name
, enable
);
3040 spin_lock_irqsave(&info
->lock
,flags
);
3042 if ( !info
->tx_enabled
) {
3046 if ( info
->tx_enabled
)
3049 spin_unlock_irqrestore(&info
->lock
,flags
);
3053 /* abort send HDLC frame
3055 static int tx_abort(SLMP_INFO
* info
)
3057 unsigned long flags
;
3059 if (debug_level
>= DEBUG_LEVEL_INFO
)
3060 printk("%s(%d):%s tx_abort()\n",
3061 __FILE__
,__LINE__
,info
->device_name
);
3063 spin_lock_irqsave(&info
->lock
,flags
);
3064 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
3065 info
->ie1_value
&= ~UDRN
;
3066 info
->ie1_value
|= IDLE
;
3067 write_reg(info
, IE1
, info
->ie1_value
); /* disable tx status interrupts */
3068 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
)); /* clear pending */
3070 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
3071 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
3073 write_reg(info
, CMD
, TXABORT
);
3075 spin_unlock_irqrestore(&info
->lock
,flags
);
3079 static int rx_enable(SLMP_INFO
* info
, int enable
)
3081 unsigned long flags
;
3083 if (debug_level
>= DEBUG_LEVEL_INFO
)
3084 printk("%s(%d):%s rx_enable(%d)\n",
3085 __FILE__
,__LINE__
,info
->device_name
,enable
);
3087 spin_lock_irqsave(&info
->lock
,flags
);
3089 if ( !info
->rx_enabled
)
3092 if ( info
->rx_enabled
)
3095 spin_unlock_irqrestore(&info
->lock
,flags
);
3099 /* wait for specified event to occur
3101 static int wait_mgsl_event(SLMP_INFO
* info
, int __user
*mask_ptr
)
3103 unsigned long flags
;
3106 struct mgsl_icount cprev
, cnow
;
3109 struct _input_signal_events oldsigs
, newsigs
;
3110 DECLARE_WAITQUEUE(wait
, current
);
3112 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
3117 if (debug_level
>= DEBUG_LEVEL_INFO
)
3118 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3119 __FILE__
,__LINE__
,info
->device_name
,mask
);
3121 spin_lock_irqsave(&info
->lock
,flags
);
3123 /* return immediately if state matches requested events */
3125 s
= info
->serial_signals
;
3128 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
3129 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
3130 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
3131 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
3133 spin_unlock_irqrestore(&info
->lock
,flags
);
3137 /* save current irq counts */
3138 cprev
= info
->icount
;
3139 oldsigs
= info
->input_signal_events
;
3141 /* enable hunt and idle irqs if needed */
3142 if (mask
& (MgslEvent_ExitHuntMode
+MgslEvent_IdleReceived
)) {
3143 unsigned char oldval
= info
->ie1_value
;
3144 unsigned char newval
= oldval
+
3145 (mask
& MgslEvent_ExitHuntMode
? FLGD
:0) +
3146 (mask
& MgslEvent_IdleReceived
? IDLD
:0);
3147 if ( oldval
!= newval
) {
3148 info
->ie1_value
= newval
;
3149 write_reg(info
, IE1
, info
->ie1_value
);
3153 set_current_state(TASK_INTERRUPTIBLE
);
3154 add_wait_queue(&info
->event_wait_q
, &wait
);
3156 spin_unlock_irqrestore(&info
->lock
,flags
);
3160 if (signal_pending(current
)) {
3165 /* get current irq counts */
3166 spin_lock_irqsave(&info
->lock
,flags
);
3167 cnow
= info
->icount
;
3168 newsigs
= info
->input_signal_events
;
3169 set_current_state(TASK_INTERRUPTIBLE
);
3170 spin_unlock_irqrestore(&info
->lock
,flags
);
3172 /* if no change, wait aborted for some reason */
3173 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
3174 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
3175 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
3176 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
3177 newsigs
.cts_up
== oldsigs
.cts_up
&&
3178 newsigs
.cts_down
== oldsigs
.cts_down
&&
3179 newsigs
.ri_up
== oldsigs
.ri_up
&&
3180 newsigs
.ri_down
== oldsigs
.ri_down
&&
3181 cnow
.exithunt
== cprev
.exithunt
&&
3182 cnow
.rxidle
== cprev
.rxidle
) {
3188 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
3189 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
3190 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
3191 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
3192 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
3193 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
3194 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
3195 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
3196 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
3197 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
3205 remove_wait_queue(&info
->event_wait_q
, &wait
);
3206 set_current_state(TASK_RUNNING
);
3209 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
3210 spin_lock_irqsave(&info
->lock
,flags
);
3211 if (!waitqueue_active(&info
->event_wait_q
)) {
3212 /* disable enable exit hunt mode/idle rcvd IRQs */
3213 info
->ie1_value
&= ~(FLGD
|IDLD
);
3214 write_reg(info
, IE1
, info
->ie1_value
);
3216 spin_unlock_irqrestore(&info
->lock
,flags
);
3220 PUT_USER(rc
, events
, mask_ptr
);
3225 static int modem_input_wait(SLMP_INFO
*info
,int arg
)
3227 unsigned long flags
;
3229 struct mgsl_icount cprev
, cnow
;
3230 DECLARE_WAITQUEUE(wait
, current
);
3232 /* save current irq counts */
3233 spin_lock_irqsave(&info
->lock
,flags
);
3234 cprev
= info
->icount
;
3235 add_wait_queue(&info
->status_event_wait_q
, &wait
);
3236 set_current_state(TASK_INTERRUPTIBLE
);
3237 spin_unlock_irqrestore(&info
->lock
,flags
);
3241 if (signal_pending(current
)) {
3246 /* get new irq counts */
3247 spin_lock_irqsave(&info
->lock
,flags
);
3248 cnow
= info
->icount
;
3249 set_current_state(TASK_INTERRUPTIBLE
);
3250 spin_unlock_irqrestore(&info
->lock
,flags
);
3252 /* if no change, wait aborted for some reason */
3253 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
3254 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
3259 /* check for change in caller specified modem input */
3260 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
3261 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
3262 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
3263 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
3270 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
3271 set_current_state(TASK_RUNNING
);
3275 /* return the state of the serial control and status signals
3277 static int tiocmget(struct tty_struct
*tty
, struct file
*file
)
3279 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
3280 unsigned int result
;
3281 unsigned long flags
;
3283 spin_lock_irqsave(&info
->lock
,flags
);
3285 spin_unlock_irqrestore(&info
->lock
,flags
);
3287 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
3288 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
3289 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
3290 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
3291 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
3292 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
3294 if (debug_level
>= DEBUG_LEVEL_INFO
)
3295 printk("%s(%d):%s tiocmget() value=%08X\n",
3296 __FILE__
,__LINE__
, info
->device_name
, result
);
3300 /* set modem control signals (DTR/RTS)
3302 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
3303 unsigned int set
, unsigned int clear
)
3305 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
3306 unsigned long flags
;
3308 if (debug_level
>= DEBUG_LEVEL_INFO
)
3309 printk("%s(%d):%s tiocmset(%x,%x)\n",
3310 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
3312 if (set
& TIOCM_RTS
)
3313 info
->serial_signals
|= SerialSignal_RTS
;
3314 if (set
& TIOCM_DTR
)
3315 info
->serial_signals
|= SerialSignal_DTR
;
3316 if (clear
& TIOCM_RTS
)
3317 info
->serial_signals
&= ~SerialSignal_RTS
;
3318 if (clear
& TIOCM_DTR
)
3319 info
->serial_signals
&= ~SerialSignal_DTR
;
3321 spin_lock_irqsave(&info
->lock
,flags
);
3323 spin_unlock_irqrestore(&info
->lock
,flags
);
3330 /* Block the current process until the specified port is ready to open.
3332 static int block_til_ready(struct tty_struct
*tty
, struct file
*filp
,
3335 DECLARE_WAITQUEUE(wait
, current
);
3337 bool do_clocal
= false;
3338 bool extra_count
= false;
3339 unsigned long flags
;
3341 if (debug_level
>= DEBUG_LEVEL_INFO
)
3342 printk("%s(%d):%s block_til_ready()\n",
3343 __FILE__
,__LINE__
, tty
->driver
->name
);
3345 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3346 /* nonblock mode is set or port is not enabled */
3347 /* just verify that callout device is not active */
3348 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3352 if (tty
->termios
->c_cflag
& CLOCAL
)
3355 /* Wait for carrier detect and the line to become
3356 * free (i.e., not in use by the callout). While we are in
3357 * this loop, info->count is dropped by one, so that
3358 * close() knows when to free things. We restore it upon
3359 * exit, either normal or abnormal.
3363 add_wait_queue(&info
->open_wait
, &wait
);
3365 if (debug_level
>= DEBUG_LEVEL_INFO
)
3366 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3367 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3369 spin_lock_irqsave(&info
->lock
, flags
);
3370 if (!tty_hung_up_p(filp
)) {
3374 spin_unlock_irqrestore(&info
->lock
, flags
);
3375 info
->blocked_open
++;
3378 if ((tty
->termios
->c_cflag
& CBAUD
)) {
3379 spin_lock_irqsave(&info
->lock
,flags
);
3380 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3382 spin_unlock_irqrestore(&info
->lock
,flags
);
3385 set_current_state(TASK_INTERRUPTIBLE
);
3387 if (tty_hung_up_p(filp
) || !(info
->flags
& ASYNC_INITIALIZED
)){
3388 retval
= (info
->flags
& ASYNC_HUP_NOTIFY
) ?
3389 -EAGAIN
: -ERESTARTSYS
;
3393 spin_lock_irqsave(&info
->lock
,flags
);
3395 spin_unlock_irqrestore(&info
->lock
,flags
);
3397 if (!(info
->flags
& ASYNC_CLOSING
) &&
3398 (do_clocal
|| (info
->serial_signals
& SerialSignal_DCD
)) ) {
3402 if (signal_pending(current
)) {
3403 retval
= -ERESTARTSYS
;
3407 if (debug_level
>= DEBUG_LEVEL_INFO
)
3408 printk("%s(%d):%s block_til_ready() count=%d\n",
3409 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3414 set_current_state(TASK_RUNNING
);
3415 remove_wait_queue(&info
->open_wait
, &wait
);
3419 info
->blocked_open
--;
3421 if (debug_level
>= DEBUG_LEVEL_INFO
)
3422 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3423 __FILE__
,__LINE__
, tty
->driver
->name
, info
->count
);
3426 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3431 static int alloc_dma_bufs(SLMP_INFO
*info
)
3433 unsigned short BuffersPerFrame
;
3434 unsigned short BufferCount
;
3436 // Force allocation to start at 64K boundary for each port.
3437 // This is necessary because *all* buffer descriptors for a port
3438 // *must* be in the same 64K block. All descriptors on a port
3439 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3440 // into the CBP register.
3441 info
->port_array
[0]->last_mem_alloc
= (SCA_MEM_SIZE
/4) * info
->port_num
;
3443 /* Calculate the number of DMA buffers necessary to hold the */
3444 /* largest allowable frame size. Note: If the max frame size is */
3445 /* not an even multiple of the DMA buffer size then we need to */
3446 /* round the buffer count per frame up one. */
3448 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/SCABUFSIZE
);
3449 if ( info
->max_frame_size
% SCABUFSIZE
)
3452 /* calculate total number of data buffers (SCABUFSIZE) possible
3453 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3454 * for the descriptor list (BUFFERLISTSIZE).
3456 BufferCount
= (SCA_MEM_SIZE
/4 - BUFFERLISTSIZE
)/SCABUFSIZE
;
3458 /* limit number of buffers to maximum amount of descriptors */
3459 if (BufferCount
> BUFFERLISTSIZE
/sizeof(SCADESC
))
3460 BufferCount
= BUFFERLISTSIZE
/sizeof(SCADESC
);
3462 /* use enough buffers to transmit one max size frame */
3463 info
->tx_buf_count
= BuffersPerFrame
+ 1;
3465 /* never use more than half the available buffers for transmit */
3466 if (info
->tx_buf_count
> (BufferCount
/2))
3467 info
->tx_buf_count
= BufferCount
/2;
3469 if (info
->tx_buf_count
> SCAMAXDESC
)
3470 info
->tx_buf_count
= SCAMAXDESC
;
3472 /* use remaining buffers for receive */
3473 info
->rx_buf_count
= BufferCount
- info
->tx_buf_count
;
3475 if (info
->rx_buf_count
> SCAMAXDESC
)
3476 info
->rx_buf_count
= SCAMAXDESC
;
3478 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3479 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3480 __FILE__
,__LINE__
, info
->device_name
,
3481 info
->tx_buf_count
,info
->rx_buf_count
);
3483 if ( alloc_buf_list( info
) < 0 ||
3484 alloc_frame_bufs(info
,
3486 info
->rx_buf_list_ex
,
3487 info
->rx_buf_count
) < 0 ||
3488 alloc_frame_bufs(info
,
3490 info
->tx_buf_list_ex
,
3491 info
->tx_buf_count
) < 0 ||
3492 alloc_tmp_rx_buf(info
) < 0 ) {
3493 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3494 __FILE__
,__LINE__
, info
->device_name
);
3498 rx_reset_buffers( info
);
3503 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3505 static int alloc_buf_list(SLMP_INFO
*info
)
3509 /* build list in adapter shared memory */
3510 info
->buffer_list
= info
->memory_base
+ info
->port_array
[0]->last_mem_alloc
;
3511 info
->buffer_list_phys
= info
->port_array
[0]->last_mem_alloc
;
3512 info
->port_array
[0]->last_mem_alloc
+= BUFFERLISTSIZE
;
3514 memset(info
->buffer_list
, 0, BUFFERLISTSIZE
);
3516 /* Save virtual address pointers to the receive and */
3517 /* transmit buffer lists. (Receive 1st). These pointers will */
3518 /* be used by the processor to access the lists. */
3519 info
->rx_buf_list
= (SCADESC
*)info
->buffer_list
;
3521 info
->tx_buf_list
= (SCADESC
*)info
->buffer_list
;
3522 info
->tx_buf_list
+= info
->rx_buf_count
;
3524 /* Build links for circular buffer entry lists (tx and rx)
3526 * Note: links are physical addresses read by the SCA device
3527 * to determine the next buffer entry to use.
3530 for ( i
= 0; i
< info
->rx_buf_count
; i
++ ) {
3531 /* calculate and store physical address of this buffer entry */
3532 info
->rx_buf_list_ex
[i
].phys_entry
=
3533 info
->buffer_list_phys
+ (i
* sizeof(SCABUFSIZE
));
3535 /* calculate and store physical address of */
3536 /* next entry in cirular list of entries */
3537 info
->rx_buf_list
[i
].next
= info
->buffer_list_phys
;
3538 if ( i
< info
->rx_buf_count
- 1 )
3539 info
->rx_buf_list
[i
].next
+= (i
+ 1) * sizeof(SCADESC
);
3541 info
->rx_buf_list
[i
].length
= SCABUFSIZE
;
3544 for ( i
= 0; i
< info
->tx_buf_count
; i
++ ) {
3545 /* calculate and store physical address of this buffer entry */
3546 info
->tx_buf_list_ex
[i
].phys_entry
= info
->buffer_list_phys
+
3547 ((info
->rx_buf_count
+ i
) * sizeof(SCADESC
));
3549 /* calculate and store physical address of */
3550 /* next entry in cirular list of entries */
3552 info
->tx_buf_list
[i
].next
= info
->buffer_list_phys
+
3553 info
->rx_buf_count
* sizeof(SCADESC
);
3555 if ( i
< info
->tx_buf_count
- 1 )
3556 info
->tx_buf_list
[i
].next
+= (i
+ 1) * sizeof(SCADESC
);
3562 /* Allocate the frame DMA buffers used by the specified buffer list.
3564 static int alloc_frame_bufs(SLMP_INFO
*info
, SCADESC
*buf_list
,SCADESC_EX
*buf_list_ex
,int count
)
3567 unsigned long phys_addr
;
3569 for ( i
= 0; i
< count
; i
++ ) {
3570 buf_list_ex
[i
].virt_addr
= info
->memory_base
+ info
->port_array
[0]->last_mem_alloc
;
3571 phys_addr
= info
->port_array
[0]->last_mem_alloc
;
3572 info
->port_array
[0]->last_mem_alloc
+= SCABUFSIZE
;
3574 buf_list
[i
].buf_ptr
= (unsigned short)phys_addr
;
3575 buf_list
[i
].buf_base
= (unsigned char)(phys_addr
>> 16);
3581 static void free_dma_bufs(SLMP_INFO
*info
)
3583 info
->buffer_list
= NULL
;
3584 info
->rx_buf_list
= NULL
;
3585 info
->tx_buf_list
= NULL
;
3588 /* allocate buffer large enough to hold max_frame_size.
3589 * This buffer is used to pass an assembled frame to the line discipline.
3591 static int alloc_tmp_rx_buf(SLMP_INFO
*info
)
3593 info
->tmp_rx_buf
= kmalloc(info
->max_frame_size
, GFP_KERNEL
);
3594 if (info
->tmp_rx_buf
== NULL
)
3599 static void free_tmp_rx_buf(SLMP_INFO
*info
)
3601 kfree(info
->tmp_rx_buf
);
3602 info
->tmp_rx_buf
= NULL
;
3605 static int claim_resources(SLMP_INFO
*info
)
3607 if (request_mem_region(info
->phys_memory_base
,SCA_MEM_SIZE
,"synclinkmp") == NULL
) {
3608 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3609 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3610 info
->init_error
= DiagStatus_AddressConflict
;
3614 info
->shared_mem_requested
= true;
3616 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclinkmp") == NULL
) {
3617 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3618 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
3619 info
->init_error
= DiagStatus_AddressConflict
;
3623 info
->lcr_mem_requested
= true;
3625 if (request_mem_region(info
->phys_sca_base
+ info
->sca_offset
,SCA_BASE_SIZE
,"synclinkmp") == NULL
) {
3626 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3627 __FILE__
,__LINE__
,info
->device_name
, info
->phys_sca_base
);
3628 info
->init_error
= DiagStatus_AddressConflict
;
3632 info
->sca_base_requested
= true;
3634 if (request_mem_region(info
->phys_statctrl_base
+ info
->statctrl_offset
,SCA_REG_SIZE
,"synclinkmp") == NULL
) {
3635 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3636 __FILE__
,__LINE__
,info
->device_name
, info
->phys_statctrl_base
);
3637 info
->init_error
= DiagStatus_AddressConflict
;
3641 info
->sca_statctrl_requested
= true;
3643 info
->memory_base
= ioremap(info
->phys_memory_base
,SCA_MEM_SIZE
);
3644 if (!info
->memory_base
) {
3645 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3646 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3647 info
->init_error
= DiagStatus_CantAssignPciResources
;
3651 info
->lcr_base
= ioremap(info
->phys_lcr_base
,PAGE_SIZE
);
3652 if (!info
->lcr_base
) {
3653 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3654 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
3655 info
->init_error
= DiagStatus_CantAssignPciResources
;
3658 info
->lcr_base
+= info
->lcr_offset
;
3660 info
->sca_base
= ioremap(info
->phys_sca_base
,PAGE_SIZE
);
3661 if (!info
->sca_base
) {
3662 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3663 __FILE__
,__LINE__
,info
->device_name
, info
->phys_sca_base
);
3664 info
->init_error
= DiagStatus_CantAssignPciResources
;
3667 info
->sca_base
+= info
->sca_offset
;
3669 info
->statctrl_base
= ioremap(info
->phys_statctrl_base
,PAGE_SIZE
);
3670 if (!info
->statctrl_base
) {
3671 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3672 __FILE__
,__LINE__
,info
->device_name
, info
->phys_statctrl_base
);
3673 info
->init_error
= DiagStatus_CantAssignPciResources
;
3676 info
->statctrl_base
+= info
->statctrl_offset
;
3678 if ( !memory_test(info
) ) {
3679 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3680 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3681 info
->init_error
= DiagStatus_MemoryError
;
3688 release_resources( info
);
3692 static void release_resources(SLMP_INFO
*info
)
3694 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3695 printk( "%s(%d):%s release_resources() entry\n",
3696 __FILE__
,__LINE__
,info
->device_name
);
3698 if ( info
->irq_requested
) {
3699 free_irq(info
->irq_level
, info
);
3700 info
->irq_requested
= false;
3703 if ( info
->shared_mem_requested
) {
3704 release_mem_region(info
->phys_memory_base
,SCA_MEM_SIZE
);
3705 info
->shared_mem_requested
= false;
3707 if ( info
->lcr_mem_requested
) {
3708 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
3709 info
->lcr_mem_requested
= false;
3711 if ( info
->sca_base_requested
) {
3712 release_mem_region(info
->phys_sca_base
+ info
->sca_offset
,SCA_BASE_SIZE
);
3713 info
->sca_base_requested
= false;
3715 if ( info
->sca_statctrl_requested
) {
3716 release_mem_region(info
->phys_statctrl_base
+ info
->statctrl_offset
,SCA_REG_SIZE
);
3717 info
->sca_statctrl_requested
= false;
3720 if (info
->memory_base
){
3721 iounmap(info
->memory_base
);
3722 info
->memory_base
= NULL
;
3725 if (info
->sca_base
) {
3726 iounmap(info
->sca_base
- info
->sca_offset
);
3727 info
->sca_base
=NULL
;
3730 if (info
->statctrl_base
) {
3731 iounmap(info
->statctrl_base
- info
->statctrl_offset
);
3732 info
->statctrl_base
=NULL
;
3735 if (info
->lcr_base
){
3736 iounmap(info
->lcr_base
- info
->lcr_offset
);
3737 info
->lcr_base
= NULL
;
3740 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3741 printk( "%s(%d):%s release_resources() exit\n",
3742 __FILE__
,__LINE__
,info
->device_name
);
3745 /* Add the specified device instance data structure to the
3746 * global linked list of devices and increment the device count.
3748 static void add_device(SLMP_INFO
*info
)
3750 info
->next_device
= NULL
;
3751 info
->line
= synclinkmp_device_count
;
3752 sprintf(info
->device_name
,"ttySLM%dp%d",info
->adapter_num
,info
->port_num
);
3754 if (info
->line
< MAX_DEVICES
) {
3755 if (maxframe
[info
->line
])
3756 info
->max_frame_size
= maxframe
[info
->line
];
3757 info
->dosyncppp
= dosyncppp
[info
->line
];
3760 synclinkmp_device_count
++;
3762 if ( !synclinkmp_device_list
)
3763 synclinkmp_device_list
= info
;
3765 SLMP_INFO
*current_dev
= synclinkmp_device_list
;
3766 while( current_dev
->next_device
)
3767 current_dev
= current_dev
->next_device
;
3768 current_dev
->next_device
= info
;
3771 if ( info
->max_frame_size
< 4096 )
3772 info
->max_frame_size
= 4096;
3773 else if ( info
->max_frame_size
> 65535 )
3774 info
->max_frame_size
= 65535;
3776 printk( "SyncLink MultiPort %s: "
3777 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3779 info
->phys_sca_base
,
3780 info
->phys_memory_base
,
3781 info
->phys_statctrl_base
,
3782 info
->phys_lcr_base
,
3784 info
->max_frame_size
);
3786 #if SYNCLINK_GENERIC_HDLC
3791 /* Allocate and initialize a device instance structure
3793 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3795 static SLMP_INFO
*alloc_dev(int adapter_num
, int port_num
, struct pci_dev
*pdev
)
3799 info
= kzalloc(sizeof(SLMP_INFO
),
3803 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3804 __FILE__
,__LINE__
, adapter_num
, port_num
);
3806 info
->magic
= MGSL_MAGIC
;
3807 INIT_WORK(&info
->task
, bh_handler
);
3808 info
->max_frame_size
= 4096;
3809 info
->close_delay
= 5*HZ
/10;
3810 info
->closing_wait
= 30*HZ
;
3811 init_waitqueue_head(&info
->open_wait
);
3812 init_waitqueue_head(&info
->close_wait
);
3813 init_waitqueue_head(&info
->status_event_wait_q
);
3814 init_waitqueue_head(&info
->event_wait_q
);
3815 spin_lock_init(&info
->netlock
);
3816 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
3817 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
3818 info
->adapter_num
= adapter_num
;
3819 info
->port_num
= port_num
;
3821 /* Copy configuration info to device instance data */
3822 info
->irq_level
= pdev
->irq
;
3823 info
->phys_lcr_base
= pci_resource_start(pdev
,0);
3824 info
->phys_sca_base
= pci_resource_start(pdev
,2);
3825 info
->phys_memory_base
= pci_resource_start(pdev
,3);
3826 info
->phys_statctrl_base
= pci_resource_start(pdev
,4);
3828 /* Because veremap only works on page boundaries we must map
3829 * a larger area than is actually implemented for the LCR
3830 * memory range. We map a full page starting at the page boundary.
3832 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
3833 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
3835 info
->sca_offset
= info
->phys_sca_base
& (PAGE_SIZE
-1);
3836 info
->phys_sca_base
&= ~(PAGE_SIZE
-1);
3838 info
->statctrl_offset
= info
->phys_statctrl_base
& (PAGE_SIZE
-1);
3839 info
->phys_statctrl_base
&= ~(PAGE_SIZE
-1);
3841 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
3842 info
->irq_flags
= IRQF_SHARED
;
3844 setup_timer(&info
->tx_timer
, tx_timeout
, (unsigned long)info
);
3845 setup_timer(&info
->status_timer
, status_timeout
,
3846 (unsigned long)info
);
3848 /* Store the PCI9050 misc control register value because a flaw
3849 * in the PCI9050 prevents LCR registers from being read if
3850 * BIOS assigns an LCR base address with bit 7 set.
3852 * Only the misc control register is accessed for which only
3853 * write access is needed, so set an initial value and change
3854 * bits to the device instance data as we write the value
3855 * to the actual misc control register.
3857 info
->misc_ctrl_value
= 0x087e4546;
3859 /* initial port state is unknown - if startup errors
3860 * occur, init_error will be set to indicate the
3861 * problem. Once the port is fully initialized,
3862 * this value will be set to 0 to indicate the
3863 * port is available.
3865 info
->init_error
= -1;
3871 static void device_init(int adapter_num
, struct pci_dev
*pdev
)
3873 SLMP_INFO
*port_array
[SCA_MAX_PORTS
];
3876 /* allocate device instances for up to SCA_MAX_PORTS devices */
3877 for ( port
= 0; port
< SCA_MAX_PORTS
; ++port
) {
3878 port_array
[port
] = alloc_dev(adapter_num
,port
,pdev
);
3879 if( port_array
[port
] == NULL
) {
3880 for ( --port
; port
>= 0; --port
)
3881 kfree(port_array
[port
]);
3886 /* give copy of port_array to all ports and add to device list */
3887 for ( port
= 0; port
< SCA_MAX_PORTS
; ++port
) {
3888 memcpy(port_array
[port
]->port_array
,port_array
,sizeof(port_array
));
3889 add_device( port_array
[port
] );
3890 spin_lock_init(&port_array
[port
]->lock
);
3893 /* Allocate and claim adapter resources */
3894 if ( !claim_resources(port_array
[0]) ) {
3896 alloc_dma_bufs(port_array
[0]);
3898 /* copy resource information from first port to others */
3899 for ( port
= 1; port
< SCA_MAX_PORTS
; ++port
) {
3900 port_array
[port
]->lock
= port_array
[0]->lock
;
3901 port_array
[port
]->irq_level
= port_array
[0]->irq_level
;
3902 port_array
[port
]->memory_base
= port_array
[0]->memory_base
;
3903 port_array
[port
]->sca_base
= port_array
[0]->sca_base
;
3904 port_array
[port
]->statctrl_base
= port_array
[0]->statctrl_base
;
3905 port_array
[port
]->lcr_base
= port_array
[0]->lcr_base
;
3906 alloc_dma_bufs(port_array
[port
]);
3909 if ( request_irq(port_array
[0]->irq_level
,
3910 synclinkmp_interrupt
,
3911 port_array
[0]->irq_flags
,
3912 port_array
[0]->device_name
,
3913 port_array
[0]) < 0 ) {
3914 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3916 port_array
[0]->device_name
,
3917 port_array
[0]->irq_level
);
3920 port_array
[0]->irq_requested
= true;
3921 adapter_test(port_array
[0]);
3926 static const struct tty_operations ops
= {
3930 .put_char
= put_char
,
3931 .flush_chars
= flush_chars
,
3932 .write_room
= write_room
,
3933 .chars_in_buffer
= chars_in_buffer
,
3934 .flush_buffer
= flush_buffer
,
3936 .throttle
= throttle
,
3937 .unthrottle
= unthrottle
,
3938 .send_xchar
= send_xchar
,
3939 .break_ctl
= set_break
,
3940 .wait_until_sent
= wait_until_sent
,
3941 .read_proc
= read_proc
,
3942 .set_termios
= set_termios
,
3944 .start
= tx_release
,
3946 .tiocmget
= tiocmget
,
3947 .tiocmset
= tiocmset
,
3950 static void synclinkmp_cleanup(void)
3956 printk("Unloading %s %s\n", driver_name
, driver_version
);
3958 if (serial_driver
) {
3959 if ((rc
= tty_unregister_driver(serial_driver
)))
3960 printk("%s(%d) failed to unregister tty driver err=%d\n",
3961 __FILE__
,__LINE__
,rc
);
3962 put_tty_driver(serial_driver
);
3966 info
= synclinkmp_device_list
;
3969 info
= info
->next_device
;
3972 /* release devices */
3973 info
= synclinkmp_device_list
;
3975 #if SYNCLINK_GENERIC_HDLC
3978 free_dma_bufs(info
);
3979 free_tmp_rx_buf(info
);
3980 if ( info
->port_num
== 0 ) {
3982 write_reg(info
, LPR
, 1); /* set low power mode */
3983 release_resources(info
);
3986 info
= info
->next_device
;
3990 pci_unregister_driver(&synclinkmp_pci_driver
);
3993 /* Driver initialization entry point.
3996 static int __init
synclinkmp_init(void)
4000 if (break_on_load
) {
4001 synclinkmp_get_text_ptr();
4005 printk("%s %s\n", driver_name
, driver_version
);
4007 if ((rc
= pci_register_driver(&synclinkmp_pci_driver
)) < 0) {
4008 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4012 serial_driver
= alloc_tty_driver(128);
4013 if (!serial_driver
) {
4018 /* Initialize the tty_driver structure */
4020 serial_driver
->owner
= THIS_MODULE
;
4021 serial_driver
->driver_name
= "synclinkmp";
4022 serial_driver
->name
= "ttySLM";
4023 serial_driver
->major
= ttymajor
;
4024 serial_driver
->minor_start
= 64;
4025 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4026 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4027 serial_driver
->init_termios
= tty_std_termios
;
4028 serial_driver
->init_termios
.c_cflag
=
4029 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4030 serial_driver
->init_termios
.c_ispeed
= 9600;
4031 serial_driver
->init_termios
.c_ospeed
= 9600;
4032 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4033 tty_set_operations(serial_driver
, &ops
);
4034 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4035 printk("%s(%d):Couldn't register serial driver\n",
4037 put_tty_driver(serial_driver
);
4038 serial_driver
= NULL
;
4042 printk("%s %s, tty major#%d\n",
4043 driver_name
, driver_version
,
4044 serial_driver
->major
);
4049 synclinkmp_cleanup();
4053 static void __exit
synclinkmp_exit(void)
4055 synclinkmp_cleanup();
4058 module_init(synclinkmp_init
);
4059 module_exit(synclinkmp_exit
);
4061 /* Set the port for internal loopback mode.
4062 * The TxCLK and RxCLK signals are generated from the BRG and
4063 * the TxD is looped back to the RxD internally.
4065 static void enable_loopback(SLMP_INFO
*info
, int enable
)
4068 /* MD2 (Mode Register 2)
4069 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4071 write_reg(info
, MD2
, (unsigned char)(read_reg(info
, MD2
) | (BIT1
+ BIT0
)));
4073 /* degate external TxC clock source */
4074 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4075 write_control_reg(info
);
4077 /* RXS/TXS (Rx/Tx clock source)
4078 * 07 Reserved, must be 0
4079 * 06..04 Clock Source, 100=BRG
4080 * 03..00 Clock Divisor, 0000=1
4082 write_reg(info
, RXS
, 0x40);
4083 write_reg(info
, TXS
, 0x40);
4086 /* MD2 (Mode Register 2)
4087 * 01..00 CNCT<1..0> Channel connection, 0=normal
4089 write_reg(info
, MD2
, (unsigned char)(read_reg(info
, MD2
) & ~(BIT1
+ BIT0
)));
4091 /* RXS/TXS (Rx/Tx clock source)
4092 * 07 Reserved, must be 0
4093 * 06..04 Clock Source, 000=RxC/TxC Pin
4094 * 03..00 Clock Divisor, 0000=1
4096 write_reg(info
, RXS
, 0x00);
4097 write_reg(info
, TXS
, 0x00);
4100 /* set LinkSpeed if available, otherwise default to 2Mbps */
4101 if (info
->params
.clock_speed
)
4102 set_rate(info
, info
->params
.clock_speed
);
4104 set_rate(info
, 3686400);
4107 /* Set the baud rate register to the desired speed
4109 * data_rate data rate of clock in bits per second
4110 * A data rate of 0 disables the AUX clock.
4112 static void set_rate( SLMP_INFO
*info
, u32 data_rate
)
4115 unsigned char BRValue
;
4118 /* fBRG = fCLK/(TMC * 2^BR)
4120 if (data_rate
!= 0) {
4121 Divisor
= 14745600/data_rate
;
4128 if (TMCValue
!= 1 && TMCValue
!= 2) {
4129 /* BRValue of 0 provides 50/50 duty cycle *only* when
4130 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4137 /* while TMCValue is too big for TMC register, divide
4138 * by 2 and increment BR exponent.
4140 for(; TMCValue
> 256 && BRValue
< 10; BRValue
++)
4143 write_reg(info
, TXS
,
4144 (unsigned char)((read_reg(info
, TXS
) & 0xf0) | BRValue
));
4145 write_reg(info
, RXS
,
4146 (unsigned char)((read_reg(info
, RXS
) & 0xf0) | BRValue
));
4147 write_reg(info
, TMC
, (unsigned char)TMCValue
);
4150 write_reg(info
, TXS
,0);
4151 write_reg(info
, RXS
,0);
4152 write_reg(info
, TMC
, 0);
4158 static void rx_stop(SLMP_INFO
*info
)
4160 if (debug_level
>= DEBUG_LEVEL_ISR
)
4161 printk("%s(%d):%s rx_stop()\n",
4162 __FILE__
,__LINE__
, info
->device_name
);
4164 write_reg(info
, CMD
, RXRESET
);
4166 info
->ie0_value
&= ~RXRDYE
;
4167 write_reg(info
, IE0
, info
->ie0_value
); /* disable Rx data interrupts */
4169 write_reg(info
, RXDMA
+ DSR
, 0); /* disable Rx DMA */
4170 write_reg(info
, RXDMA
+ DCMD
, SWABORT
); /* reset/init Rx DMA */
4171 write_reg(info
, RXDMA
+ DIR, 0); /* disable Rx DMA interrupts */
4173 info
->rx_enabled
= false;
4174 info
->rx_overflow
= false;
4177 /* enable the receiver
4179 static void rx_start(SLMP_INFO
*info
)
4183 if (debug_level
>= DEBUG_LEVEL_ISR
)
4184 printk("%s(%d):%s rx_start()\n",
4185 __FILE__
,__LINE__
, info
->device_name
);
4187 write_reg(info
, CMD
, RXRESET
);
4189 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
4190 /* HDLC, disabe IRQ on rxdata */
4191 info
->ie0_value
&= ~RXRDYE
;
4192 write_reg(info
, IE0
, info
->ie0_value
);
4194 /* Reset all Rx DMA buffers and program rx dma */
4195 write_reg(info
, RXDMA
+ DSR
, 0); /* disable Rx DMA */
4196 write_reg(info
, RXDMA
+ DCMD
, SWABORT
); /* reset/init Rx DMA */
4198 for (i
= 0; i
< info
->rx_buf_count
; i
++) {
4199 info
->rx_buf_list
[i
].status
= 0xff;
4201 // throttle to 4 shared memory writes at a time to prevent
4202 // hogging local bus (keep latency time for DMA requests low).
4204 read_status_reg(info
);
4206 info
->current_rx_buf
= 0;
4208 /* set current/1st descriptor address */
4209 write_reg16(info
, RXDMA
+ CDA
,
4210 info
->rx_buf_list_ex
[0].phys_entry
);
4212 /* set new last rx descriptor address */
4213 write_reg16(info
, RXDMA
+ EDA
,
4214 info
->rx_buf_list_ex
[info
->rx_buf_count
- 1].phys_entry
);
4216 /* set buffer length (shared by all rx dma data buffers) */
4217 write_reg16(info
, RXDMA
+ BFL
, SCABUFSIZE
);
4219 write_reg(info
, RXDMA
+ DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4220 write_reg(info
, RXDMA
+ DSR
, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4222 /* async, enable IRQ on rxdata */
4223 info
->ie0_value
|= RXRDYE
;
4224 write_reg(info
, IE0
, info
->ie0_value
);
4227 write_reg(info
, CMD
, RXENABLE
);
4229 info
->rx_overflow
= false;
4230 info
->rx_enabled
= true;
4233 /* Enable the transmitter and send a transmit frame if
4234 * one is loaded in the DMA buffers.
4236 static void tx_start(SLMP_INFO
*info
)
4238 if (debug_level
>= DEBUG_LEVEL_ISR
)
4239 printk("%s(%d):%s tx_start() tx_count=%d\n",
4240 __FILE__
,__LINE__
, info
->device_name
,info
->tx_count
);
4242 if (!info
->tx_enabled
) {
4243 write_reg(info
, CMD
, TXRESET
);
4244 write_reg(info
, CMD
, TXENABLE
);
4245 info
->tx_enabled
= true;
4248 if ( info
->tx_count
) {
4250 /* If auto RTS enabled and RTS is inactive, then assert */
4251 /* RTS and set a flag indicating that the driver should */
4252 /* negate RTS when the transmission completes. */
4254 info
->drop_rts_on_tx_done
= false;
4256 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
4258 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
4259 get_signals( info
);
4260 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
4261 info
->serial_signals
|= SerialSignal_RTS
;
4262 set_signals( info
);
4263 info
->drop_rts_on_tx_done
= true;
4267 write_reg16(info
, TRC0
,
4268 (unsigned short)(((tx_negate_fifo_level
-1)<<8) + tx_active_fifo_level
));
4270 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
4271 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
4273 /* set TX CDA (current descriptor address) */
4274 write_reg16(info
, TXDMA
+ CDA
,
4275 info
->tx_buf_list_ex
[0].phys_entry
);
4277 /* set TX EDA (last descriptor address) */
4278 write_reg16(info
, TXDMA
+ EDA
,
4279 info
->tx_buf_list_ex
[info
->last_tx_buf
].phys_entry
);
4281 /* enable underrun IRQ */
4282 info
->ie1_value
&= ~IDLE
;
4283 info
->ie1_value
|= UDRN
;
4284 write_reg(info
, IE1
, info
->ie1_value
);
4285 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
));
4287 write_reg(info
, TXDMA
+ DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4288 write_reg(info
, TXDMA
+ DSR
, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4290 mod_timer(&info
->tx_timer
, jiffies
+
4291 msecs_to_jiffies(5000));
4295 /* async, enable IRQ on txdata */
4296 info
->ie0_value
|= TXRDYE
;
4297 write_reg(info
, IE0
, info
->ie0_value
);
4300 info
->tx_active
= true;
4304 /* stop the transmitter and DMA
4306 static void tx_stop( SLMP_INFO
*info
)
4308 if (debug_level
>= DEBUG_LEVEL_ISR
)
4309 printk("%s(%d):%s tx_stop()\n",
4310 __FILE__
,__LINE__
, info
->device_name
);
4312 del_timer(&info
->tx_timer
);
4314 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
4315 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
4317 write_reg(info
, CMD
, TXRESET
);
4319 info
->ie1_value
&= ~(UDRN
+ IDLE
);
4320 write_reg(info
, IE1
, info
->ie1_value
); /* disable tx status interrupts */
4321 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
)); /* clear pending */
4323 info
->ie0_value
&= ~TXRDYE
;
4324 write_reg(info
, IE0
, info
->ie0_value
); /* disable tx data interrupts */
4326 info
->tx_enabled
= false;
4327 info
->tx_active
= false;
4330 /* Fill the transmit FIFO until the FIFO is full or
4331 * there is no more data to load.
4333 static void tx_load_fifo(SLMP_INFO
*info
)
4337 /* do nothing is now tx data available and no XON/XOFF pending */
4339 if ( !info
->tx_count
&& !info
->x_char
)
4342 /* load the Transmit FIFO until FIFOs full or all data sent */
4344 while( info
->tx_count
&& (read_reg(info
,SR0
) & BIT1
) ) {
4346 /* there is more space in the transmit FIFO and */
4347 /* there is more data in transmit buffer */
4349 if ( (info
->tx_count
> 1) && !info
->x_char
) {
4351 TwoBytes
[0] = info
->tx_buf
[info
->tx_get
++];
4352 if (info
->tx_get
>= info
->max_frame_size
)
4353 info
->tx_get
-= info
->max_frame_size
;
4354 TwoBytes
[1] = info
->tx_buf
[info
->tx_get
++];
4355 if (info
->tx_get
>= info
->max_frame_size
)
4356 info
->tx_get
-= info
->max_frame_size
;
4358 write_reg16(info
, TRB
, *((u16
*)TwoBytes
));
4360 info
->tx_count
-= 2;
4361 info
->icount
.tx
+= 2;
4363 /* only 1 byte left to transmit or 1 FIFO slot left */
4366 /* transmit pending high priority char */
4367 write_reg(info
, TRB
, info
->x_char
);
4370 write_reg(info
, TRB
, info
->tx_buf
[info
->tx_get
++]);
4371 if (info
->tx_get
>= info
->max_frame_size
)
4372 info
->tx_get
-= info
->max_frame_size
;
4380 /* Reset a port to a known state
4382 static void reset_port(SLMP_INFO
*info
)
4384 if (info
->sca_base
) {
4389 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
4392 /* disable all port interrupts */
4393 info
->ie0_value
= 0;
4394 info
->ie1_value
= 0;
4395 info
->ie2_value
= 0;
4396 write_reg(info
, IE0
, info
->ie0_value
);
4397 write_reg(info
, IE1
, info
->ie1_value
);
4398 write_reg(info
, IE2
, info
->ie2_value
);
4400 write_reg(info
, CMD
, CHRESET
);
4404 /* Reset all the ports to a known state.
4406 static void reset_adapter(SLMP_INFO
*info
)
4410 for ( i
=0; i
< SCA_MAX_PORTS
; ++i
) {
4411 if (info
->port_array
[i
])
4412 reset_port(info
->port_array
[i
]);
4416 /* Program port for asynchronous communications.
4418 static void async_mode(SLMP_INFO
*info
)
4421 unsigned char RegValue
;
4426 /* MD0, Mode Register 0
4428 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4429 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4430 * 03 Reserved, must be 0
4431 * 02 CRCCC, CRC Calculation, 0=disabled
4432 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4437 if (info
->params
.stop_bits
!= 1)
4439 write_reg(info
, MD0
, RegValue
);
4441 /* MD1, Mode Register 1
4443 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4444 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4445 * 03..02 RXCHR<1..0>, rx char size
4446 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4451 switch (info
->params
.data_bits
) {
4452 case 7: RegValue
|= BIT4
+ BIT2
; break;
4453 case 6: RegValue
|= BIT5
+ BIT3
; break;
4454 case 5: RegValue
|= BIT5
+ BIT4
+ BIT3
+ BIT2
; break;
4456 if (info
->params
.parity
!= ASYNC_PARITY_NONE
) {
4458 if (info
->params
.parity
== ASYNC_PARITY_ODD
)
4461 write_reg(info
, MD1
, RegValue
);
4463 /* MD2, Mode Register 2
4465 * 07..02 Reserved, must be 0
4466 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4471 if (info
->params
.loopback
)
4472 RegValue
|= (BIT1
+ BIT0
);
4473 write_reg(info
, MD2
, RegValue
);
4475 /* RXS, Receive clock source
4477 * 07 Reserved, must be 0
4478 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4479 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4482 write_reg(info
, RXS
, RegValue
);
4484 /* TXS, Transmit clock source
4486 * 07 Reserved, must be 0
4487 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4488 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4491 write_reg(info
, TXS
, RegValue
);
4495 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4497 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4498 write_control_reg(info
);
4502 /* RRC Receive Ready Control 0
4504 * 07..05 Reserved, must be 0
4505 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4507 write_reg(info
, RRC
, 0x00);
4509 /* TRC0 Transmit Ready Control 0
4511 * 07..05 Reserved, must be 0
4512 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4514 write_reg(info
, TRC0
, 0x10);
4516 /* TRC1 Transmit Ready Control 1
4518 * 07..05 Reserved, must be 0
4519 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4521 write_reg(info
, TRC1
, 0x1e);
4523 /* CTL, MSCI control register
4525 * 07..06 Reserved, set to 0
4526 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4527 * 04 IDLC, idle control, 0=mark 1=idle register
4528 * 03 BRK, break, 0=off 1 =on (async)
4529 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4530 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4531 * 00 RTS, RTS output control, 0=active 1=inactive
4536 if (!(info
->serial_signals
& SerialSignal_RTS
))
4538 write_reg(info
, CTL
, RegValue
);
4540 /* enable status interrupts */
4541 info
->ie0_value
|= TXINTE
+ RXINTE
;
4542 write_reg(info
, IE0
, info
->ie0_value
);
4544 /* enable break detect interrupt */
4545 info
->ie1_value
= BRKD
;
4546 write_reg(info
, IE1
, info
->ie1_value
);
4548 /* enable rx overrun interrupt */
4549 info
->ie2_value
= OVRN
;
4550 write_reg(info
, IE2
, info
->ie2_value
);
4552 set_rate( info
, info
->params
.data_rate
* 16 );
4555 /* Program the SCA for HDLC communications.
4557 static void hdlc_mode(SLMP_INFO
*info
)
4559 unsigned char RegValue
;
4562 // Can't use DPLL because SCA outputs recovered clock on RxC when
4563 // DPLL mode selected. This causes output contention with RxC receiver.
4564 // Use of DPLL would require external hardware to disable RxC receiver
4565 // when DPLL mode selected.
4566 info
->params
.flags
&= ~(HDLC_FLAG_TXC_DPLL
+ HDLC_FLAG_RXC_DPLL
);
4568 /* disable DMA interrupts */
4569 write_reg(info
, TXDMA
+ DIR, 0);
4570 write_reg(info
, RXDMA
+ DIR, 0);
4572 /* MD0, Mode Register 0
4574 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4575 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4576 * 03 Reserved, must be 0
4577 * 02 CRCCC, CRC Calculation, 1=enabled
4578 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4579 * 00 CRC0, CRC initial value, 1 = all 1s
4584 if (info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
4586 if (info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
4588 if (info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
4589 RegValue
|= BIT2
+ BIT1
;
4590 write_reg(info
, MD0
, RegValue
);
4592 /* MD1, Mode Register 1
4594 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4595 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4596 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4597 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4602 write_reg(info
, MD1
, RegValue
);
4604 /* MD2, Mode Register 2
4606 * 07 NRZFM, 0=NRZ, 1=FM
4607 * 06..05 CODE<1..0> Encoding, 00=NRZ
4608 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4609 * 02 Reserved, must be 0
4610 * 01..00 CNCT<1..0> Channel connection, 0=normal
4615 switch(info
->params
.encoding
) {
4616 case HDLC_ENCODING_NRZI
: RegValue
|= BIT5
; break;
4617 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT7
+ BIT5
; break; /* aka FM1 */
4618 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT7
+ BIT6
; break; /* aka FM0 */
4619 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT7
; break; /* aka Manchester */
4621 case HDLC_ENCODING_NRZB
: /* not supported */
4622 case HDLC_ENCODING_NRZI_MARK
: /* not supported */
4623 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: /* not supported */
4626 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
4629 } else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
4635 write_reg(info
, MD2
, RegValue
);
4638 /* RXS, Receive clock source
4640 * 07 Reserved, must be 0
4641 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4642 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4645 if (info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4647 if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4648 RegValue
|= BIT6
+ BIT5
;
4649 write_reg(info
, RXS
, RegValue
);
4651 /* TXS, Transmit clock source
4653 * 07 Reserved, must be 0
4654 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4655 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4658 if (info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4660 if (info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4661 RegValue
|= BIT6
+ BIT5
;
4662 write_reg(info
, TXS
, RegValue
);
4664 if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4665 set_rate(info
, info
->params
.clock_speed
* DpllDivisor
);
4667 set_rate(info
, info
->params
.clock_speed
);
4669 /* GPDATA (General Purpose I/O Data Register)
4671 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4673 if (info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4674 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4676 info
->port_array
[0]->ctrlreg_value
&= ~(BIT0
<< (info
->port_num
* 2));
4677 write_control_reg(info
);
4679 /* RRC Receive Ready Control 0
4681 * 07..05 Reserved, must be 0
4682 * 04..00 RRC<4..0> Rx FIFO trigger active
4684 write_reg(info
, RRC
, rx_active_fifo_level
);
4686 /* TRC0 Transmit Ready Control 0
4688 * 07..05 Reserved, must be 0
4689 * 04..00 TRC<4..0> Tx FIFO trigger active
4691 write_reg(info
, TRC0
, tx_active_fifo_level
);
4693 /* TRC1 Transmit Ready Control 1
4695 * 07..05 Reserved, must be 0
4696 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4698 write_reg(info
, TRC1
, (unsigned char)(tx_negate_fifo_level
- 1));
4700 /* DMR, DMA Mode Register
4702 * 07..05 Reserved, must be 0
4703 * 04 TMOD, Transfer Mode: 1=chained-block
4704 * 03 Reserved, must be 0
4705 * 02 NF, Number of Frames: 1=multi-frame
4706 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4707 * 00 Reserved, must be 0
4711 write_reg(info
, TXDMA
+ DMR
, 0x14);
4712 write_reg(info
, RXDMA
+ DMR
, 0x14);
4714 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4715 write_reg(info
, RXDMA
+ CPB
,
4716 (unsigned char)(info
->buffer_list_phys
>> 16));
4718 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4719 write_reg(info
, TXDMA
+ CPB
,
4720 (unsigned char)(info
->buffer_list_phys
>> 16));
4722 /* enable status interrupts. other code enables/disables
4723 * the individual sources for these two interrupt classes.
4725 info
->ie0_value
|= TXINTE
+ RXINTE
;
4726 write_reg(info
, IE0
, info
->ie0_value
);
4728 /* CTL, MSCI control register
4730 * 07..06 Reserved, set to 0
4731 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4732 * 04 IDLC, idle control, 0=mark 1=idle register
4733 * 03 BRK, break, 0=off 1 =on (async)
4734 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4735 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4736 * 00 RTS, RTS output control, 0=active 1=inactive
4741 if (!(info
->serial_signals
& SerialSignal_RTS
))
4743 write_reg(info
, CTL
, RegValue
);
4745 /* preamble not supported ! */
4751 set_rate(info
, info
->params
.clock_speed
);
4753 if (info
->params
.loopback
)
4754 enable_loopback(info
,1);
4757 /* Set the transmit HDLC idle mode
4759 static void tx_set_idle(SLMP_INFO
*info
)
4761 unsigned char RegValue
= 0xff;
4763 /* Map API idle mode to SCA register bits */
4764 switch(info
->idle_mode
) {
4765 case HDLC_TXIDLE_FLAGS
: RegValue
= 0x7e; break;
4766 case HDLC_TXIDLE_ALT_ZEROS_ONES
: RegValue
= 0xaa; break;
4767 case HDLC_TXIDLE_ZEROS
: RegValue
= 0x00; break;
4768 case HDLC_TXIDLE_ONES
: RegValue
= 0xff; break;
4769 case HDLC_TXIDLE_ALT_MARK_SPACE
: RegValue
= 0xaa; break;
4770 case HDLC_TXIDLE_SPACE
: RegValue
= 0x00; break;
4771 case HDLC_TXIDLE_MARK
: RegValue
= 0xff; break;
4774 write_reg(info
, IDL
, RegValue
);
4777 /* Query the adapter for the state of the V24 status (input) signals.
4779 static void get_signals(SLMP_INFO
*info
)
4781 u16 status
= read_reg(info
, SR3
);
4782 u16 gpstatus
= read_status_reg(info
);
4785 /* clear all serial signals except DTR and RTS */
4786 info
->serial_signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
4788 /* set serial signal bits to reflect MISR */
4790 if (!(status
& BIT3
))
4791 info
->serial_signals
|= SerialSignal_CTS
;
4793 if ( !(status
& BIT2
))
4794 info
->serial_signals
|= SerialSignal_DCD
;
4796 testbit
= BIT1
<< (info
->port_num
* 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4797 if (!(gpstatus
& testbit
))
4798 info
->serial_signals
|= SerialSignal_RI
;
4800 testbit
= BIT0
<< (info
->port_num
* 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4801 if (!(gpstatus
& testbit
))
4802 info
->serial_signals
|= SerialSignal_DSR
;
4805 /* Set the state of DTR and RTS based on contents of
4806 * serial_signals member of device context.
4808 static void set_signals(SLMP_INFO
*info
)
4810 unsigned char RegValue
;
4813 RegValue
= read_reg(info
, CTL
);
4814 if (info
->serial_signals
& SerialSignal_RTS
)
4818 write_reg(info
, CTL
, RegValue
);
4820 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4821 EnableBit
= BIT1
<< (info
->port_num
*2);
4822 if (info
->serial_signals
& SerialSignal_DTR
)
4823 info
->port_array
[0]->ctrlreg_value
&= ~EnableBit
;
4825 info
->port_array
[0]->ctrlreg_value
|= EnableBit
;
4826 write_control_reg(info
);
4829 /*******************/
4830 /* DMA Buffer Code */
4831 /*******************/
4833 /* Set the count for all receive buffers to SCABUFSIZE
4834 * and set the current buffer to the first buffer. This effectively
4835 * makes all buffers free and discards any data in buffers.
4837 static void rx_reset_buffers(SLMP_INFO
*info
)
4839 rx_free_frame_buffers(info
, 0, info
->rx_buf_count
- 1);
4842 /* Free the buffers used by a received frame
4844 * info pointer to device instance data
4845 * first index of 1st receive buffer of frame
4846 * last index of last receive buffer of frame
4848 static void rx_free_frame_buffers(SLMP_INFO
*info
, unsigned int first
, unsigned int last
)
4853 /* reset current buffer for reuse */
4854 info
->rx_buf_list
[first
].status
= 0xff;
4856 if (first
== last
) {
4858 /* set new last rx descriptor address */
4859 write_reg16(info
, RXDMA
+ EDA
, info
->rx_buf_list_ex
[first
].phys_entry
);
4863 if (first
== info
->rx_buf_count
)
4867 /* set current buffer to next buffer after last buffer of frame */
4868 info
->current_rx_buf
= first
;
4871 /* Return a received frame from the receive DMA buffers.
4872 * Only frames received without errors are returned.
4874 * Return Value: true if frame returned, otherwise false
4876 static bool rx_get_frame(SLMP_INFO
*info
)
4878 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
4879 unsigned short status
;
4880 unsigned int framesize
= 0;
4881 bool ReturnCode
= false;
4882 unsigned long flags
;
4883 struct tty_struct
*tty
= info
->tty
;
4884 unsigned char addr_field
= 0xff;
4886 SCADESC_EX
*desc_ex
;
4889 /* assume no frame returned, set zero length */
4894 * current_rx_buf points to the 1st buffer of the next available
4895 * receive frame. To find the last buffer of the frame look for
4896 * a non-zero status field in the buffer entries. (The status
4897 * field is set by the 16C32 after completing a receive frame.
4899 StartIndex
= EndIndex
= info
->current_rx_buf
;
4902 desc
= &info
->rx_buf_list
[EndIndex
];
4903 desc_ex
= &info
->rx_buf_list_ex
[EndIndex
];
4905 if (desc
->status
== 0xff)
4906 goto Cleanup
; /* current desc still in use, no frames available */
4908 if (framesize
== 0 && info
->params
.addr_filter
!= 0xff)
4909 addr_field
= desc_ex
->virt_addr
[0];
4911 framesize
+= desc
->length
;
4913 /* Status != 0 means last buffer of frame */
4918 if (EndIndex
== info
->rx_buf_count
)
4921 if (EndIndex
== info
->current_rx_buf
) {
4922 /* all buffers have been 'used' but none mark */
4923 /* the end of a frame. Reset buffers and receiver. */
4924 if ( info
->rx_enabled
){
4925 spin_lock_irqsave(&info
->lock
,flags
);
4927 spin_unlock_irqrestore(&info
->lock
,flags
);
4934 /* check status of receive frame */
4936 /* frame status is byte stored after frame data
4938 * 7 EOM (end of msg), 1 = last buffer of frame
4939 * 6 Short Frame, 1 = short frame
4940 * 5 Abort, 1 = frame aborted
4941 * 4 Residue, 1 = last byte is partial
4942 * 3 Overrun, 1 = overrun occurred during frame reception
4943 * 2 CRC, 1 = CRC error detected
4946 status
= desc
->status
;
4948 /* ignore CRC bit if not using CRC (bit is undefined) */
4949 /* Note:CRC is not save to data buffer */
4950 if (info
->params
.crc_type
== HDLC_CRC_NONE
)
4953 if (framesize
== 0 ||
4954 (addr_field
!= 0xff && addr_field
!= info
->params
.addr_filter
)) {
4955 /* discard 0 byte frames, this seems to occur sometime
4956 * when remote is idling flags.
4958 rx_free_frame_buffers(info
, StartIndex
, EndIndex
);
4965 if (status
& (BIT6
+BIT5
+BIT3
+BIT2
)) {
4966 /* received frame has errors,
4967 * update counts and mark frame size as 0
4970 info
->icount
.rxshort
++;
4971 else if (status
& BIT5
)
4972 info
->icount
.rxabort
++;
4973 else if (status
& BIT3
)
4974 info
->icount
.rxover
++;
4976 info
->icount
.rxcrc
++;
4979 #if SYNCLINK_GENERIC_HDLC
4981 struct net_device_stats
*stats
= hdlc_stats(info
->netdev
);
4983 stats
->rx_frame_errors
++;
4988 if ( debug_level
>= DEBUG_LEVEL_BH
)
4989 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4990 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
4992 if ( debug_level
>= DEBUG_LEVEL_DATA
)
4993 trace_block(info
,info
->rx_buf_list_ex
[StartIndex
].virt_addr
,
4994 min_t(int, framesize
,SCABUFSIZE
),0);
4997 if (framesize
> info
->max_frame_size
)
4998 info
->icount
.rxlong
++;
5000 /* copy dma buffer(s) to contiguous intermediate buffer */
5001 int copy_count
= framesize
;
5002 int index
= StartIndex
;
5003 unsigned char *ptmp
= info
->tmp_rx_buf
;
5004 info
->tmp_rx_buf_count
= framesize
;
5006 info
->icount
.rxok
++;
5009 int partial_count
= min(copy_count
,SCABUFSIZE
);
5011 info
->rx_buf_list_ex
[index
].virt_addr
,
5013 ptmp
+= partial_count
;
5014 copy_count
-= partial_count
;
5016 if ( ++index
== info
->rx_buf_count
)
5020 #if SYNCLINK_GENERIC_HDLC
5022 hdlcdev_rx(info
,info
->tmp_rx_buf
,framesize
);
5025 ldisc_receive_buf(tty
,info
->tmp_rx_buf
,
5026 info
->flag_buf
, framesize
);
5029 /* Free the buffers used by this frame. */
5030 rx_free_frame_buffers( info
, StartIndex
, EndIndex
);
5035 if ( info
->rx_enabled
&& info
->rx_overflow
) {
5036 /* Receiver is enabled, but needs to restarted due to
5037 * rx buffer overflow. If buffers are empty, restart receiver.
5039 if (info
->rx_buf_list
[EndIndex
].status
== 0xff) {
5040 spin_lock_irqsave(&info
->lock
,flags
);
5042 spin_unlock_irqrestore(&info
->lock
,flags
);
5049 /* load the transmit DMA buffer with data
5051 static void tx_load_dma_buffer(SLMP_INFO
*info
, const char *buf
, unsigned int count
)
5053 unsigned short copy_count
;
5056 SCADESC_EX
*desc_ex
;
5058 if ( debug_level
>= DEBUG_LEVEL_DATA
)
5059 trace_block(info
,buf
, min_t(int, count
,SCABUFSIZE
), 1);
5061 /* Copy source buffer to one or more DMA buffers, starting with
5062 * the first transmit dma buffer.
5066 copy_count
= min_t(unsigned short,count
,SCABUFSIZE
);
5068 desc
= &info
->tx_buf_list
[i
];
5069 desc_ex
= &info
->tx_buf_list_ex
[i
];
5071 load_pci_memory(info
, desc_ex
->virt_addr
,buf
,copy_count
);
5073 desc
->length
= copy_count
;
5077 count
-= copy_count
;
5083 if (i
>= info
->tx_buf_count
)
5087 info
->tx_buf_list
[i
].status
= 0x81; /* set EOM and EOT status */
5088 info
->last_tx_buf
= ++i
;
5091 static bool register_test(SLMP_INFO
*info
)
5093 static unsigned char testval
[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5094 static unsigned int count
= ARRAY_SIZE(testval
);
5097 unsigned long flags
;
5099 spin_lock_irqsave(&info
->lock
,flags
);
5102 /* assume failure */
5103 info
->init_error
= DiagStatus_AddressFailure
;
5105 /* Write bit patterns to various registers but do it out of */
5106 /* sync, then read back and verify values. */
5108 for (i
= 0 ; i
< count
; i
++) {
5109 write_reg(info
, TMC
, testval
[i
]);
5110 write_reg(info
, IDL
, testval
[(i
+1)%count
]);
5111 write_reg(info
, SA0
, testval
[(i
+2)%count
]);
5112 write_reg(info
, SA1
, testval
[(i
+3)%count
]);
5114 if ( (read_reg(info
, TMC
) != testval
[i
]) ||
5115 (read_reg(info
, IDL
) != testval
[(i
+1)%count
]) ||
5116 (read_reg(info
, SA0
) != testval
[(i
+2)%count
]) ||
5117 (read_reg(info
, SA1
) != testval
[(i
+3)%count
]) )
5125 spin_unlock_irqrestore(&info
->lock
,flags
);
5130 static bool irq_test(SLMP_INFO
*info
)
5132 unsigned long timeout
;
5133 unsigned long flags
;
5135 unsigned char timer
= (info
->port_num
& 1) ? TIMER2
: TIMER0
;
5137 spin_lock_irqsave(&info
->lock
,flags
);
5140 /* assume failure */
5141 info
->init_error
= DiagStatus_IrqFailure
;
5142 info
->irq_occurred
= false;
5144 /* setup timer0 on SCA0 to interrupt */
5146 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5147 write_reg(info
, IER2
, (unsigned char)((info
->port_num
& 1) ? BIT6
: BIT4
));
5149 write_reg(info
, (unsigned char)(timer
+ TEPR
), 0); /* timer expand prescale */
5150 write_reg16(info
, (unsigned char)(timer
+ TCONR
), 1); /* timer constant */
5153 /* TMCS, Timer Control/Status Register
5155 * 07 CMF, Compare match flag (read only) 1=match
5156 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5157 * 05 Reserved, must be 0
5158 * 04 TME, Timer Enable
5159 * 03..00 Reserved, must be 0
5163 write_reg(info
, (unsigned char)(timer
+ TMCS
), 0x50);
5165 spin_unlock_irqrestore(&info
->lock
,flags
);
5168 while( timeout
-- && !info
->irq_occurred
) {
5169 msleep_interruptible(10);
5172 spin_lock_irqsave(&info
->lock
,flags
);
5174 spin_unlock_irqrestore(&info
->lock
,flags
);
5176 return info
->irq_occurred
;
5179 /* initialize individual SCA device (2 ports)
5181 static bool sca_init(SLMP_INFO
*info
)
5183 /* set wait controller to single mem partition (low), no wait states */
5184 write_reg(info
, PABR0
, 0); /* wait controller addr boundary 0 */
5185 write_reg(info
, PABR1
, 0); /* wait controller addr boundary 1 */
5186 write_reg(info
, WCRL
, 0); /* wait controller low range */
5187 write_reg(info
, WCRM
, 0); /* wait controller mid range */
5188 write_reg(info
, WCRH
, 0); /* wait controller high range */
5190 /* DPCR, DMA Priority Control
5192 * 07..05 Not used, must be 0
5193 * 04 BRC, bus release condition: 0=all transfers complete
5194 * 03 CCC, channel change condition: 0=every cycle
5195 * 02..00 PR<2..0>, priority 100=round robin
5199 write_reg(info
, DPCR
, dma_priority
);
5201 /* DMA Master Enable, BIT7: 1=enable all channels */
5202 write_reg(info
, DMER
, 0x80);
5204 /* enable all interrupt classes */
5205 write_reg(info
, IER0
, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5206 write_reg(info
, IER1
, 0xff); /* DMIB,DMIA (channels 0-3) */
5207 write_reg(info
, IER2
, 0xf0); /* TIRQ (timers 0-3) */
5209 /* ITCR, interrupt control register
5210 * 07 IPC, interrupt priority, 0=MSCI->DMA
5211 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5212 * 04 VOS, Vector Output, 0=unmodified vector
5213 * 03..00 Reserved, must be 0
5215 write_reg(info
, ITCR
, 0);
5220 /* initialize adapter hardware
5222 static bool init_adapter(SLMP_INFO
*info
)
5226 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5227 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5230 info
->misc_ctrl_value
|= BIT30
;
5231 *MiscCtrl
= info
->misc_ctrl_value
;
5234 * Force at least 170ns delay before clearing
5235 * reset bit. Each read from LCR takes at least
5236 * 30ns so 10 times for 300ns to be safe.
5239 readval
= *MiscCtrl
;
5241 info
->misc_ctrl_value
&= ~BIT30
;
5242 *MiscCtrl
= info
->misc_ctrl_value
;
5244 /* init control reg (all DTRs off, all clksel=input) */
5245 info
->ctrlreg_value
= 0xaa;
5246 write_control_reg(info
);
5249 volatile u32
*LCR1BRDR
= (u32
*)(info
->lcr_base
+ 0x2c);
5250 lcr1_brdr_value
&= ~(BIT5
+ BIT4
+ BIT3
);
5252 switch(read_ahead_count
)
5255 lcr1_brdr_value
|= BIT5
+ BIT4
+ BIT3
;
5258 lcr1_brdr_value
|= BIT5
+ BIT4
;
5261 lcr1_brdr_value
|= BIT5
+ BIT3
;
5264 lcr1_brdr_value
|= BIT5
;
5268 *LCR1BRDR
= lcr1_brdr_value
;
5269 *MiscCtrl
= misc_ctrl_value
;
5272 sca_init(info
->port_array
[0]);
5273 sca_init(info
->port_array
[2]);
5278 /* Loopback an HDLC frame to test the hardware
5279 * interrupt and DMA functions.
5281 static bool loopback_test(SLMP_INFO
*info
)
5283 #define TESTFRAMESIZE 20
5285 unsigned long timeout
;
5286 u16 count
= TESTFRAMESIZE
;
5287 unsigned char buf
[TESTFRAMESIZE
];
5289 unsigned long flags
;
5291 struct tty_struct
*oldtty
= info
->tty
;
5292 u32 speed
= info
->params
.clock_speed
;
5294 info
->params
.clock_speed
= 3686400;
5297 /* assume failure */
5298 info
->init_error
= DiagStatus_DmaFailure
;
5300 /* build and send transmit frame */
5301 for (count
= 0; count
< TESTFRAMESIZE
;++count
)
5302 buf
[count
] = (unsigned char)count
;
5304 memset(info
->tmp_rx_buf
,0,TESTFRAMESIZE
);
5306 /* program hardware for HDLC and enabled receiver */
5307 spin_lock_irqsave(&info
->lock
,flags
);
5309 enable_loopback(info
,1);
5311 info
->tx_count
= count
;
5312 tx_load_dma_buffer(info
,buf
,count
);
5314 spin_unlock_irqrestore(&info
->lock
,flags
);
5316 /* wait for receive complete */
5317 /* Set a timeout for waiting for interrupt. */
5318 for ( timeout
= 100; timeout
; --timeout
) {
5319 msleep_interruptible(10);
5321 if (rx_get_frame(info
)) {
5327 /* verify received frame length and contents */
5329 ( info
->tmp_rx_buf_count
!= count
||
5330 memcmp(buf
, info
->tmp_rx_buf
,count
))) {
5334 spin_lock_irqsave(&info
->lock
,flags
);
5335 reset_adapter(info
);
5336 spin_unlock_irqrestore(&info
->lock
,flags
);
5338 info
->params
.clock_speed
= speed
;
5344 /* Perform diagnostics on hardware
5346 static int adapter_test( SLMP_INFO
*info
)
5348 unsigned long flags
;
5349 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5350 printk( "%s(%d):Testing device %s\n",
5351 __FILE__
,__LINE__
,info
->device_name
);
5353 spin_lock_irqsave(&info
->lock
,flags
);
5355 spin_unlock_irqrestore(&info
->lock
,flags
);
5357 info
->port_array
[0]->port_count
= 0;
5359 if ( register_test(info
->port_array
[0]) &&
5360 register_test(info
->port_array
[1])) {
5362 info
->port_array
[0]->port_count
= 2;
5364 if ( register_test(info
->port_array
[2]) &&
5365 register_test(info
->port_array
[3]) )
5366 info
->port_array
[0]->port_count
+= 2;
5369 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5370 __FILE__
,__LINE__
,info
->device_name
, (unsigned long)(info
->phys_sca_base
));
5374 if ( !irq_test(info
->port_array
[0]) ||
5375 !irq_test(info
->port_array
[1]) ||
5376 (info
->port_count
== 4 && !irq_test(info
->port_array
[2])) ||
5377 (info
->port_count
== 4 && !irq_test(info
->port_array
[3]))) {
5378 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5379 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
5383 if (!loopback_test(info
->port_array
[0]) ||
5384 !loopback_test(info
->port_array
[1]) ||
5385 (info
->port_count
== 4 && !loopback_test(info
->port_array
[2])) ||
5386 (info
->port_count
== 4 && !loopback_test(info
->port_array
[3]))) {
5387 printk( "%s(%d):DMA test failure for device %s\n",
5388 __FILE__
,__LINE__
,info
->device_name
);
5392 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5393 printk( "%s(%d):device %s passed diagnostics\n",
5394 __FILE__
,__LINE__
,info
->device_name
);
5396 info
->port_array
[0]->init_error
= 0;
5397 info
->port_array
[1]->init_error
= 0;
5398 if ( info
->port_count
> 2 ) {
5399 info
->port_array
[2]->init_error
= 0;
5400 info
->port_array
[3]->init_error
= 0;
5406 /* Test the shared memory on a PCI adapter.
5408 static bool memory_test(SLMP_INFO
*info
)
5410 static unsigned long testval
[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5411 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5412 unsigned long count
= ARRAY_SIZE(testval
);
5414 unsigned long limit
= SCA_MEM_SIZE
/sizeof(unsigned long);
5415 unsigned long * addr
= (unsigned long *)info
->memory_base
;
5417 /* Test data lines with test pattern at one location. */
5419 for ( i
= 0 ; i
< count
; i
++ ) {
5421 if ( *addr
!= testval
[i
] )
5425 /* Test address lines with incrementing pattern over */
5426 /* entire address range. */
5428 for ( i
= 0 ; i
< limit
; i
++ ) {
5433 addr
= (unsigned long *)info
->memory_base
;
5435 for ( i
= 0 ; i
< limit
; i
++ ) {
5436 if ( *addr
!= i
* 4 )
5441 memset( info
->memory_base
, 0, SCA_MEM_SIZE
);
5445 /* Load data into PCI adapter shared memory.
5447 * The PCI9050 releases control of the local bus
5448 * after completing the current read or write operation.
5450 * While the PCI9050 write FIFO not empty, the
5451 * PCI9050 treats all of the writes as a single transaction
5452 * and does not release the bus. This causes DMA latency problems
5453 * at high speeds when copying large data blocks to the shared memory.
5455 * This function breaks a write into multiple transations by
5456 * interleaving a read which flushes the write FIFO and 'completes'
5457 * the write transation. This allows any pending DMA request to gain control
5458 * of the local bus in a timely fasion.
5460 static void load_pci_memory(SLMP_INFO
*info
, char* dest
, const char* src
, unsigned short count
)
5462 /* A load interval of 16 allows for 4 32-bit writes at */
5463 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5465 unsigned short interval
= count
/ sca_pci_load_interval
;
5468 for ( i
= 0 ; i
< interval
; i
++ )
5470 memcpy(dest
, src
, sca_pci_load_interval
);
5471 read_status_reg(info
);
5472 dest
+= sca_pci_load_interval
;
5473 src
+= sca_pci_load_interval
;
5476 memcpy(dest
, src
, count
% sca_pci_load_interval
);
5479 static void trace_block(SLMP_INFO
*info
,const char* data
, int count
, int xmit
)
5484 printk("%s tx data:\n",info
->device_name
);
5486 printk("%s rx data:\n",info
->device_name
);
5494 for(i
=0;i
<linecount
;i
++)
5495 printk("%02X ",(unsigned char)data
[i
]);
5498 for(i
=0;i
<linecount
;i
++) {
5499 if (data
[i
]>=040 && data
[i
]<=0176)
5500 printk("%c",data
[i
]);
5509 } /* end of trace_block() */
5511 /* called when HDLC frame times out
5512 * update stats and do tx completion processing
5514 static void tx_timeout(unsigned long context
)
5516 SLMP_INFO
*info
= (SLMP_INFO
*)context
;
5517 unsigned long flags
;
5519 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5520 printk( "%s(%d):%s tx_timeout()\n",
5521 __FILE__
,__LINE__
,info
->device_name
);
5522 if(info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
5523 info
->icount
.txtimeout
++;
5525 spin_lock_irqsave(&info
->lock
,flags
);
5526 info
->tx_active
= false;
5527 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
5529 spin_unlock_irqrestore(&info
->lock
,flags
);
5531 #if SYNCLINK_GENERIC_HDLC
5533 hdlcdev_tx_done(info
);
5539 /* called to periodically check the DSR/RI modem signal input status
5541 static void status_timeout(unsigned long context
)
5544 SLMP_INFO
*info
= (SLMP_INFO
*)context
;
5545 unsigned long flags
;
5546 unsigned char delta
;
5549 spin_lock_irqsave(&info
->lock
,flags
);
5551 spin_unlock_irqrestore(&info
->lock
,flags
);
5553 /* check for DSR/RI state change */
5555 delta
= info
->old_signals
^ info
->serial_signals
;
5556 info
->old_signals
= info
->serial_signals
;
5558 if (delta
& SerialSignal_DSR
)
5559 status
|= MISCSTATUS_DSR_LATCHED
|(info
->serial_signals
&SerialSignal_DSR
);
5561 if (delta
& SerialSignal_RI
)
5562 status
|= MISCSTATUS_RI_LATCHED
|(info
->serial_signals
&SerialSignal_RI
);
5564 if (delta
& SerialSignal_DCD
)
5565 status
|= MISCSTATUS_DCD_LATCHED
|(info
->serial_signals
&SerialSignal_DCD
);
5567 if (delta
& SerialSignal_CTS
)
5568 status
|= MISCSTATUS_CTS_LATCHED
|(info
->serial_signals
&SerialSignal_CTS
);
5571 isr_io_pin(info
,status
);
5573 mod_timer(&info
->status_timer
, jiffies
+ msecs_to_jiffies(10));
5577 /* Register Access Routines -
5578 * All registers are memory mapped
5580 #define CALC_REGADDR() \
5581 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5582 if (info->port_num > 1) \
5583 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5584 if ( info->port_num & 1) { \
5586 RegAddr += 0x40; /* DMA access */ \
5587 else if (Addr > 0x1f && Addr < 0x60) \
5588 RegAddr += 0x20; /* MSCI access */ \
5592 static unsigned char read_reg(SLMP_INFO
* info
, unsigned char Addr
)
5597 static void write_reg(SLMP_INFO
* info
, unsigned char Addr
, unsigned char Value
)
5603 static u16
read_reg16(SLMP_INFO
* info
, unsigned char Addr
)
5606 return *((u16
*)RegAddr
);
5609 static void write_reg16(SLMP_INFO
* info
, unsigned char Addr
, u16 Value
)
5612 *((u16
*)RegAddr
) = Value
;
5615 static unsigned char read_status_reg(SLMP_INFO
* info
)
5617 unsigned char *RegAddr
= (unsigned char *)info
->statctrl_base
;
5621 static void write_control_reg(SLMP_INFO
* info
)
5623 unsigned char *RegAddr
= (unsigned char *)info
->statctrl_base
;
5624 *RegAddr
= info
->port_array
[0]->ctrlreg_value
;
5628 static int __devinit
synclinkmp_init_one (struct pci_dev
*dev
,
5629 const struct pci_device_id
*ent
)
5631 if (pci_enable_device(dev
)) {
5632 printk("error enabling pci device %p\n", dev
);
5635 device_init( ++synclinkmp_adapter_count
, dev
);
5639 static void __devexit
synclinkmp_remove_one (struct pci_dev
*dev
)