2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
7 * written by Paul Fulghum for Microgate Corporation
10 * Microgate and SyncLink are trademarks of Microgate Corporation
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30 # define BREAKPOINT() asm(" int $3");
32 # define BREAKPOINT() { }
35 #define MAX_DEVICES 12
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
53 #include <linux/slab.h>
54 #include <linux/netdevice.h>
55 #include <linux/vmalloc.h>
56 #include <linux/init.h>
57 #include <linux/delay.h>
58 #include <linux/ioctl.h>
60 #include <asm/system.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
74 #define SYNCLINK_GENERIC_HDLC 0
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
82 #include <asm/uaccess.h>
84 static MGSL_PARAMS default_params
= {
85 MGSL_MODE_HDLC
, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE
/* unsigned char parity; */
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
108 #define BUFFERLISTSIZE 4096
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
113 u16 next
; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr
; /* lower 16 bits of buffer addr */
115 u8 buf_base
; /* upper 8 bits of buffer addr */
117 u16 length
; /* length of buffer */
118 u8 status
; /* status of buffer */
120 } SCADESC
, *PSCADESC
;
122 typedef struct _SCADESC_EX
124 /* device driver bookkeeping section */
125 char *virt_addr
; /* virtual address of data buffer */
126 u16 phys_entry
; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX
, *PSCADESC_EX
;
129 /* The queue of BH actions to be performed */
132 #define BH_TRANSMIT 2
135 #define IO_PIN_SHUTDOWN_LIMIT 100
137 struct _input_signal_events
{
149 * Device instance data structure
151 typedef struct _synclinkmp_info
{
152 void *if_ptr
; /* General purpose pointer (used by SPPP) */
154 struct tty_port port
;
156 unsigned short close_delay
;
157 unsigned short closing_wait
; /* time to wait before closing */
159 struct mgsl_icount icount
;
162 int x_char
; /* xon/xoff character */
163 u16 read_status_mask1
; /* break detection (SR1 indications) */
164 u16 read_status_mask2
; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1
; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2
; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf
;
172 wait_queue_head_t status_event_wait_q
;
173 wait_queue_head_t event_wait_q
;
174 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info
*next_device
; /* device list link */
176 struct timer_list status_timer
; /* input signal status check timer */
178 spinlock_t lock
; /* spinlock for synchronizing with ISR */
179 struct work_struct task
; /* task structure for scheduling bh */
181 u32 max_frame_size
; /* as set by device config */
185 bool bh_running
; /* Protection from multiple */
189 int dcd_chkcount
; /* check counts to prevent */
190 int cts_chkcount
; /* too many IRQs if a signal */
191 int dsr_chkcount
; /* is floating */
194 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys
;
197 unsigned int rx_buf_count
; /* count of total allocated Rx buffers */
198 SCADESC
*rx_buf_list
; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex
[SCAMAXDESC
]; /* list of receive buffer entries */
200 unsigned int current_rx_buf
;
202 unsigned int tx_buf_count
; /* count of total allocated Tx buffers */
203 SCADESC
*tx_buf_list
; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex
[SCAMAXDESC
]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf
;
207 unsigned char *tmp_rx_buf
;
208 unsigned int tmp_rx_buf_count
;
217 unsigned char ie0_value
;
218 unsigned char ie1_value
;
219 unsigned char ie2_value
;
220 unsigned char ctrlreg_value
;
221 unsigned char old_signals
;
223 char device_name
[25]; /* device instance name */
229 struct _synclinkmp_info
*port_array
[SCA_MAX_PORTS
];
231 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
233 unsigned int irq_level
; /* interrupt level */
234 unsigned long irq_flags
;
235 bool irq_requested
; /* true if IRQ requested */
237 MGSL_PARAMS params
; /* communications parameters */
239 unsigned char serial_signals
; /* current serial signal states */
241 bool irq_occurred
; /* for diagnostics use */
242 unsigned int init_error
; /* Initialization startup error */
245 unsigned char* memory_base
; /* shared memory address (PCI only) */
246 u32 phys_memory_base
;
247 int shared_mem_requested
;
249 unsigned char* sca_base
; /* HD64570 SCA Memory address */
252 bool sca_base_requested
;
254 unsigned char* lcr_base
; /* local config registers (PCI only) */
257 int lcr_mem_requested
;
259 unsigned char* statctrl_base
; /* status/control register memory */
260 u32 phys_statctrl_base
;
262 bool sca_statctrl_requested
;
265 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
266 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
267 bool drop_rts_on_tx_done
;
269 struct _input_signal_events input_signal_events
;
271 /* SPPP/Cisco HDLC device parts */
275 #if SYNCLINK_GENERIC_HDLC
276 struct net_device
*netdev
;
281 #define MGSL_MAGIC 0x5401
284 * define serial signal status change macros
286 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
287 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
288 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
289 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
291 /* Common Register macros */
310 /* MSCI Register macros */
340 /* Timer Register Macros */
350 /* DMA Controller Register macros */
381 /* combine with timer or DMA register address */
389 /* SCA Command Codes */
392 #define TXENABLE 0x02
393 #define TXDISABLE 0x03
394 #define TXCRCINIT 0x04
395 #define TXCRCEXCL 0x05
399 #define TXBUFCLR 0x09
401 #define RXENABLE 0x12
402 #define RXDISABLE 0x13
403 #define RXCRCINIT 0x14
404 #define RXREJECT 0x15
405 #define SEARCHMP 0x16
406 #define RXCRCEXCL 0x17
407 #define RXCRCCALC 0x18
411 /* DMA command codes */
413 #define FEICLEAR 0x02
447 * Global linked list of SyncLink devices
449 static SLMP_INFO
*synclinkmp_device_list
= NULL
;
450 static int synclinkmp_adapter_count
= -1;
451 static int synclinkmp_device_count
= 0;
454 * Set this param to non-zero to load eax with the
455 * .text section address and breakpoint on module load.
456 * This is useful for use with gdb and add-symbol-file command.
458 static int break_on_load
= 0;
461 * Driver major number, defaults to zero to get auto
462 * assigned major number. May be forced as module parameter.
464 static int ttymajor
= 0;
467 * Array of user specified options for ISA adapters.
469 static int debug_level
= 0;
470 static int maxframe
[MAX_DEVICES
] = {0,};
472 module_param(break_on_load
, bool, 0);
473 module_param(ttymajor
, int, 0);
474 module_param(debug_level
, int, 0);
475 module_param_array(maxframe
, int, NULL
, 0);
477 static char *driver_name
= "SyncLink MultiPort driver";
478 static char *driver_version
= "$Revision: 4.38 $";
480 static int synclinkmp_init_one(struct pci_dev
*dev
,const struct pci_device_id
*ent
);
481 static void synclinkmp_remove_one(struct pci_dev
*dev
);
483 static struct pci_device_id synclinkmp_pci_tbl
[] = {
484 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_SCA
, PCI_ANY_ID
, PCI_ANY_ID
, },
485 { 0, }, /* terminate list */
487 MODULE_DEVICE_TABLE(pci
, synclinkmp_pci_tbl
);
489 MODULE_LICENSE("GPL");
491 static struct pci_driver synclinkmp_pci_driver
= {
492 .name
= "synclinkmp",
493 .id_table
= synclinkmp_pci_tbl
,
494 .probe
= synclinkmp_init_one
,
495 .remove
= __devexit_p(synclinkmp_remove_one
),
499 static struct tty_driver
*serial_driver
;
501 /* number of characters left in xmit buffer before we ask for more */
502 #define WAKEUP_CHARS 256
507 static int open(struct tty_struct
*tty
, struct file
* filp
);
508 static void close(struct tty_struct
*tty
, struct file
* filp
);
509 static void hangup(struct tty_struct
*tty
);
510 static void set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
);
512 static int write(struct tty_struct
*tty
, const unsigned char *buf
, int count
);
513 static int put_char(struct tty_struct
*tty
, unsigned char ch
);
514 static void send_xchar(struct tty_struct
*tty
, char ch
);
515 static void wait_until_sent(struct tty_struct
*tty
, int timeout
);
516 static int write_room(struct tty_struct
*tty
);
517 static void flush_chars(struct tty_struct
*tty
);
518 static void flush_buffer(struct tty_struct
*tty
);
519 static void tx_hold(struct tty_struct
*tty
);
520 static void tx_release(struct tty_struct
*tty
);
522 static int ioctl(struct tty_struct
*tty
, struct file
*file
, unsigned int cmd
, unsigned long arg
);
523 static int read_proc(char *page
, char **start
, off_t off
, int count
,int *eof
, void *data
);
524 static int chars_in_buffer(struct tty_struct
*tty
);
525 static void throttle(struct tty_struct
* tty
);
526 static void unthrottle(struct tty_struct
* tty
);
527 static int set_break(struct tty_struct
*tty
, int break_state
);
529 #if SYNCLINK_GENERIC_HDLC
530 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
531 static void hdlcdev_tx_done(SLMP_INFO
*info
);
532 static void hdlcdev_rx(SLMP_INFO
*info
, char *buf
, int size
);
533 static int hdlcdev_init(SLMP_INFO
*info
);
534 static void hdlcdev_exit(SLMP_INFO
*info
);
539 static int get_stats(SLMP_INFO
*info
, struct mgsl_icount __user
*user_icount
);
540 static int get_params(SLMP_INFO
*info
, MGSL_PARAMS __user
*params
);
541 static int set_params(SLMP_INFO
*info
, MGSL_PARAMS __user
*params
);
542 static int get_txidle(SLMP_INFO
*info
, int __user
*idle_mode
);
543 static int set_txidle(SLMP_INFO
*info
, int idle_mode
);
544 static int tx_enable(SLMP_INFO
*info
, int enable
);
545 static int tx_abort(SLMP_INFO
*info
);
546 static int rx_enable(SLMP_INFO
*info
, int enable
);
547 static int modem_input_wait(SLMP_INFO
*info
,int arg
);
548 static int wait_mgsl_event(SLMP_INFO
*info
, int __user
*mask_ptr
);
549 static int tiocmget(struct tty_struct
*tty
, struct file
*file
);
550 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
551 unsigned int set
, unsigned int clear
);
552 static int set_break(struct tty_struct
*tty
, int break_state
);
554 static void add_device(SLMP_INFO
*info
);
555 static void device_init(int adapter_num
, struct pci_dev
*pdev
);
556 static int claim_resources(SLMP_INFO
*info
);
557 static void release_resources(SLMP_INFO
*info
);
559 static int startup(SLMP_INFO
*info
);
560 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,SLMP_INFO
*info
);
561 static void shutdown(SLMP_INFO
*info
);
562 static void program_hw(SLMP_INFO
*info
);
563 static void change_params(SLMP_INFO
*info
);
565 static bool init_adapter(SLMP_INFO
*info
);
566 static bool register_test(SLMP_INFO
*info
);
567 static bool irq_test(SLMP_INFO
*info
);
568 static bool loopback_test(SLMP_INFO
*info
);
569 static int adapter_test(SLMP_INFO
*info
);
570 static bool memory_test(SLMP_INFO
*info
);
572 static void reset_adapter(SLMP_INFO
*info
);
573 static void reset_port(SLMP_INFO
*info
);
574 static void async_mode(SLMP_INFO
*info
);
575 static void hdlc_mode(SLMP_INFO
*info
);
577 static void rx_stop(SLMP_INFO
*info
);
578 static void rx_start(SLMP_INFO
*info
);
579 static void rx_reset_buffers(SLMP_INFO
*info
);
580 static void rx_free_frame_buffers(SLMP_INFO
*info
, unsigned int first
, unsigned int last
);
581 static bool rx_get_frame(SLMP_INFO
*info
);
583 static void tx_start(SLMP_INFO
*info
);
584 static void tx_stop(SLMP_INFO
*info
);
585 static void tx_load_fifo(SLMP_INFO
*info
);
586 static void tx_set_idle(SLMP_INFO
*info
);
587 static void tx_load_dma_buffer(SLMP_INFO
*info
, const char *buf
, unsigned int count
);
589 static void get_signals(SLMP_INFO
*info
);
590 static void set_signals(SLMP_INFO
*info
);
591 static void enable_loopback(SLMP_INFO
*info
, int enable
);
592 static void set_rate(SLMP_INFO
*info
, u32 data_rate
);
594 static int bh_action(SLMP_INFO
*info
);
595 static void bh_handler(struct work_struct
*work
);
596 static void bh_receive(SLMP_INFO
*info
);
597 static void bh_transmit(SLMP_INFO
*info
);
598 static void bh_status(SLMP_INFO
*info
);
599 static void isr_timer(SLMP_INFO
*info
);
600 static void isr_rxint(SLMP_INFO
*info
);
601 static void isr_rxrdy(SLMP_INFO
*info
);
602 static void isr_txint(SLMP_INFO
*info
);
603 static void isr_txrdy(SLMP_INFO
*info
);
604 static void isr_rxdmaok(SLMP_INFO
*info
);
605 static void isr_rxdmaerror(SLMP_INFO
*info
);
606 static void isr_txdmaok(SLMP_INFO
*info
);
607 static void isr_txdmaerror(SLMP_INFO
*info
);
608 static void isr_io_pin(SLMP_INFO
*info
, u16 status
);
610 static int alloc_dma_bufs(SLMP_INFO
*info
);
611 static void free_dma_bufs(SLMP_INFO
*info
);
612 static int alloc_buf_list(SLMP_INFO
*info
);
613 static int alloc_frame_bufs(SLMP_INFO
*info
, SCADESC
*list
, SCADESC_EX
*list_ex
,int count
);
614 static int alloc_tmp_rx_buf(SLMP_INFO
*info
);
615 static void free_tmp_rx_buf(SLMP_INFO
*info
);
617 static void load_pci_memory(SLMP_INFO
*info
, char* dest
, const char* src
, unsigned short count
);
618 static void trace_block(SLMP_INFO
*info
, const char* data
, int count
, int xmit
);
619 static void tx_timeout(unsigned long context
);
620 static void status_timeout(unsigned long context
);
622 static unsigned char read_reg(SLMP_INFO
*info
, unsigned char addr
);
623 static void write_reg(SLMP_INFO
*info
, unsigned char addr
, unsigned char val
);
624 static u16
read_reg16(SLMP_INFO
*info
, unsigned char addr
);
625 static void write_reg16(SLMP_INFO
*info
, unsigned char addr
, u16 val
);
626 static unsigned char read_status_reg(SLMP_INFO
* info
);
627 static void write_control_reg(SLMP_INFO
* info
);
630 static unsigned char rx_active_fifo_level
= 16; // rx request FIFO activation level in bytes
631 static unsigned char tx_active_fifo_level
= 16; // tx request FIFO activation level in bytes
632 static unsigned char tx_negate_fifo_level
= 32; // tx request FIFO negation level in bytes
634 static u32 misc_ctrl_value
= 0x007e4040;
635 static u32 lcr1_brdr_value
= 0x00800028;
637 static u32 read_ahead_count
= 8;
639 /* DPCR, DMA Priority Control
641 * 07..05 Not used, must be 0
642 * 04 BRC, bus release condition: 0=all transfers complete
643 * 1=release after 1 xfer on all channels
644 * 03 CCC, channel change condition: 0=every cycle
645 * 1=after each channel completes all xfers
646 * 02..00 PR<2..0>, priority 100=round robin
650 static unsigned char dma_priority
= 0x04;
652 // Number of bytes that can be written to shared RAM
653 // in a single write operation
654 static u32 sca_pci_load_interval
= 64;
657 * 1st function defined in .text section. Calling this function in
658 * init_module() followed by a breakpoint allows a remote debugger
659 * (gdb) to get the .text address for the add-symbol-file command.
660 * This allows remote debugging of dynamically loadable modules.
662 static void* synclinkmp_get_text_ptr(void);
663 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr
;}
665 static inline int sanity_check(SLMP_INFO
*info
,
666 char *name
, const char *routine
)
669 static const char *badmagic
=
670 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
671 static const char *badinfo
=
672 "Warning: null synclinkmp_struct for (%s) in %s\n";
675 printk(badinfo
, name
, routine
);
678 if (info
->magic
!= MGSL_MAGIC
) {
679 printk(badmagic
, name
, routine
);
690 * line discipline callback wrappers
692 * The wrappers maintain line discipline references
693 * while calling into the line discipline.
695 * ldisc_receive_buf - pass receive data to line discipline
698 static void ldisc_receive_buf(struct tty_struct
*tty
,
699 const __u8
*data
, char *flags
, int count
)
701 struct tty_ldisc
*ld
;
704 ld
= tty_ldisc_ref(tty
);
706 if (ld
->ops
->receive_buf
)
707 ld
->ops
->receive_buf(tty
, data
, flags
, count
);
714 /* Called when a port is opened. Init and enable port.
716 static int open(struct tty_struct
*tty
, struct file
*filp
)
723 if ((line
< 0) || (line
>= synclinkmp_device_count
)) {
724 printk("%s(%d): open with invalid line #%d.\n",
725 __FILE__
,__LINE__
,line
);
729 info
= synclinkmp_device_list
;
730 while(info
&& info
->line
!= line
)
731 info
= info
->next_device
;
732 if (sanity_check(info
, tty
->name
, "open"))
734 if ( info
->init_error
) {
735 printk("%s(%d):%s device is not allocated, init error=%d\n",
736 __FILE__
,__LINE__
,info
->device_name
,info
->init_error
);
740 tty
->driver_data
= info
;
741 info
->port
.tty
= tty
;
743 if (debug_level
>= DEBUG_LEVEL_INFO
)
744 printk("%s(%d):%s open(), old ref count = %d\n",
745 __FILE__
,__LINE__
,tty
->driver
->name
, info
->port
.count
);
747 /* If port is closing, signal caller to try again */
748 if (tty_hung_up_p(filp
) || info
->port
.flags
& ASYNC_CLOSING
){
749 if (info
->port
.flags
& ASYNC_CLOSING
)
750 interruptible_sleep_on(&info
->port
.close_wait
);
751 retval
= ((info
->port
.flags
& ASYNC_HUP_NOTIFY
) ?
752 -EAGAIN
: -ERESTARTSYS
);
756 info
->port
.tty
->low_latency
= (info
->port
.flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
758 spin_lock_irqsave(&info
->netlock
, flags
);
759 if (info
->netcount
) {
761 spin_unlock_irqrestore(&info
->netlock
, flags
);
765 spin_unlock_irqrestore(&info
->netlock
, flags
);
767 if (info
->port
.count
== 1) {
768 /* 1st open on this device, init hardware */
769 retval
= startup(info
);
774 retval
= block_til_ready(tty
, filp
, info
);
776 if (debug_level
>= DEBUG_LEVEL_INFO
)
777 printk("%s(%d):%s block_til_ready() returned %d\n",
778 __FILE__
,__LINE__
, info
->device_name
, retval
);
782 if (debug_level
>= DEBUG_LEVEL_INFO
)
783 printk("%s(%d):%s open() success\n",
784 __FILE__
,__LINE__
, info
->device_name
);
790 info
->port
.tty
= NULL
; /* tty layer will release tty struct */
798 /* Called when port is closed. Wait for remaining data to be
799 * sent. Disable port and free resources.
801 static void close(struct tty_struct
*tty
, struct file
*filp
)
803 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
805 if (sanity_check(info
, tty
->name
, "close"))
808 if (debug_level
>= DEBUG_LEVEL_INFO
)
809 printk("%s(%d):%s close() entry, count=%d\n",
810 __FILE__
,__LINE__
, info
->device_name
, info
->port
.count
);
812 if (!info
->port
.count
)
815 if (tty_hung_up_p(filp
))
818 if ((tty
->count
== 1) && (info
->port
.count
!= 1)) {
820 * tty->count is 1 and the tty structure will be freed.
821 * info->port.count should be one in this case.
822 * if it's not, correct it so that the port is shutdown.
824 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
825 "info->port.count is %d\n",
826 __FILE__
,__LINE__
, info
->device_name
, info
->port
.count
);
827 info
->port
.count
= 1;
832 /* if at least one open remaining, leave hardware active */
833 if (info
->port
.count
)
836 info
->port
.flags
|= ASYNC_CLOSING
;
838 /* set tty->closing to notify line discipline to
839 * only process XON/XOFF characters. Only the N_TTY
840 * discipline appears to use this (ppp does not).
844 /* wait for transmit data to clear all layers */
846 if (info
->port
.closing_wait
!= ASYNC_CLOSING_WAIT_NONE
) {
847 if (debug_level
>= DEBUG_LEVEL_INFO
)
848 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
849 __FILE__
,__LINE__
, info
->device_name
);
850 tty_wait_until_sent(tty
, info
->port
.closing_wait
);
853 if (info
->port
.flags
& ASYNC_INITIALIZED
)
854 wait_until_sent(tty
, info
->timeout
);
858 tty_ldisc_flush(tty
);
863 info
->port
.tty
= NULL
;
865 if (info
->port
.blocked_open
) {
866 if (info
->port
.close_delay
) {
867 msleep_interruptible(jiffies_to_msecs(info
->port
.close_delay
));
869 wake_up_interruptible(&info
->port
.open_wait
);
872 info
->port
.flags
&= ~(ASYNC_NORMAL_ACTIVE
|ASYNC_CLOSING
);
874 wake_up_interruptible(&info
->port
.close_wait
);
877 if (debug_level
>= DEBUG_LEVEL_INFO
)
878 printk("%s(%d):%s close() exit, count=%d\n", __FILE__
,__LINE__
,
879 tty
->driver
->name
, info
->port
.count
);
882 /* Called by tty_hangup() when a hangup is signaled.
883 * This is the same as closing all open descriptors for the port.
885 static void hangup(struct tty_struct
*tty
)
887 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
889 if (debug_level
>= DEBUG_LEVEL_INFO
)
890 printk("%s(%d):%s hangup()\n",
891 __FILE__
,__LINE__
, info
->device_name
);
893 if (sanity_check(info
, tty
->name
, "hangup"))
899 info
->port
.count
= 0;
900 info
->port
.flags
&= ~ASYNC_NORMAL_ACTIVE
;
901 info
->port
.tty
= NULL
;
903 wake_up_interruptible(&info
->port
.open_wait
);
906 /* Set new termios settings
908 static void set_termios(struct tty_struct
*tty
, struct ktermios
*old_termios
)
910 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
913 if (debug_level
>= DEBUG_LEVEL_INFO
)
914 printk("%s(%d):%s set_termios()\n", __FILE__
,__LINE__
,
919 /* Handle transition to B0 status */
920 if (old_termios
->c_cflag
& CBAUD
&&
921 !(tty
->termios
->c_cflag
& CBAUD
)) {
922 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
923 spin_lock_irqsave(&info
->lock
,flags
);
925 spin_unlock_irqrestore(&info
->lock
,flags
);
928 /* Handle transition away from B0 status */
929 if (!(old_termios
->c_cflag
& CBAUD
) &&
930 tty
->termios
->c_cflag
& CBAUD
) {
931 info
->serial_signals
|= SerialSignal_DTR
;
932 if (!(tty
->termios
->c_cflag
& CRTSCTS
) ||
933 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
934 info
->serial_signals
|= SerialSignal_RTS
;
936 spin_lock_irqsave(&info
->lock
,flags
);
938 spin_unlock_irqrestore(&info
->lock
,flags
);
941 /* Handle turning off CRTSCTS */
942 if (old_termios
->c_cflag
& CRTSCTS
&&
943 !(tty
->termios
->c_cflag
& CRTSCTS
)) {
949 /* Send a block of data
953 * tty pointer to tty information structure
954 * buf pointer to buffer containing send data
955 * count size of send data in bytes
957 * Return Value: number of characters written
959 static int write(struct tty_struct
*tty
,
960 const unsigned char *buf
, int count
)
963 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
966 if (debug_level
>= DEBUG_LEVEL_INFO
)
967 printk("%s(%d):%s write() count=%d\n",
968 __FILE__
,__LINE__
,info
->device_name
,count
);
970 if (sanity_check(info
, tty
->name
, "write"))
976 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
977 if (count
> info
->max_frame_size
) {
983 if (info
->tx_count
) {
984 /* send accumulated data from send_char() calls */
985 /* as frame and wait before accepting more data. */
986 tx_load_dma_buffer(info
, info
->tx_buf
, info
->tx_count
);
989 ret
= info
->tx_count
= count
;
990 tx_load_dma_buffer(info
, buf
, count
);
995 c
= min_t(int, count
,
996 min(info
->max_frame_size
- info
->tx_count
- 1,
997 info
->max_frame_size
- info
->tx_put
));
1001 memcpy(info
->tx_buf
+ info
->tx_put
, buf
, c
);
1003 spin_lock_irqsave(&info
->lock
,flags
);
1005 if (info
->tx_put
>= info
->max_frame_size
)
1006 info
->tx_put
-= info
->max_frame_size
;
1007 info
->tx_count
+= c
;
1008 spin_unlock_irqrestore(&info
->lock
,flags
);
1015 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1017 ret
= info
->tx_count
= 0;
1020 tx_load_dma_buffer(info
, info
->tx_buf
, info
->tx_count
);
1023 if (info
->tx_count
&& !tty
->stopped
&& !tty
->hw_stopped
) {
1024 spin_lock_irqsave(&info
->lock
,flags
);
1025 if (!info
->tx_active
)
1027 spin_unlock_irqrestore(&info
->lock
,flags
);
1031 if (debug_level
>= DEBUG_LEVEL_INFO
)
1032 printk( "%s(%d):%s write() returning=%d\n",
1033 __FILE__
,__LINE__
,info
->device_name
,ret
);
1037 /* Add a character to the transmit buffer.
1039 static int put_char(struct tty_struct
*tty
, unsigned char ch
)
1041 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1042 unsigned long flags
;
1045 if ( debug_level
>= DEBUG_LEVEL_INFO
) {
1046 printk( "%s(%d):%s put_char(%d)\n",
1047 __FILE__
,__LINE__
,info
->device_name
,ch
);
1050 if (sanity_check(info
, tty
->name
, "put_char"))
1056 spin_lock_irqsave(&info
->lock
,flags
);
1058 if ( (info
->params
.mode
!= MGSL_MODE_HDLC
) ||
1059 !info
->tx_active
) {
1061 if (info
->tx_count
< info
->max_frame_size
- 1) {
1062 info
->tx_buf
[info
->tx_put
++] = ch
;
1063 if (info
->tx_put
>= info
->max_frame_size
)
1064 info
->tx_put
-= info
->max_frame_size
;
1070 spin_unlock_irqrestore(&info
->lock
,flags
);
1074 /* Send a high-priority XON/XOFF character
1076 static void send_xchar(struct tty_struct
*tty
, char ch
)
1078 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1079 unsigned long flags
;
1081 if (debug_level
>= DEBUG_LEVEL_INFO
)
1082 printk("%s(%d):%s send_xchar(%d)\n",
1083 __FILE__
,__LINE__
, info
->device_name
, ch
);
1085 if (sanity_check(info
, tty
->name
, "send_xchar"))
1090 /* Make sure transmit interrupts are on */
1091 spin_lock_irqsave(&info
->lock
,flags
);
1092 if (!info
->tx_enabled
)
1094 spin_unlock_irqrestore(&info
->lock
,flags
);
1098 /* Wait until the transmitter is empty.
1100 static void wait_until_sent(struct tty_struct
*tty
, int timeout
)
1102 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
1103 unsigned long orig_jiffies
, char_time
;
1108 if (debug_level
>= DEBUG_LEVEL_INFO
)
1109 printk("%s(%d):%s wait_until_sent() entry\n",
1110 __FILE__
,__LINE__
, info
->device_name
);
1112 if (sanity_check(info
, tty
->name
, "wait_until_sent"))
1117 if (!(info
->port
.flags
& ASYNC_INITIALIZED
))
1120 orig_jiffies
= jiffies
;
1122 /* Set check interval to 1/5 of estimated time to
1123 * send a character, and make it at least 1. The check
1124 * interval should also be less than the timeout.
1125 * Note: use tight timings here to satisfy the NIST-PCTS.
1128 if ( info
->params
.data_rate
) {
1129 char_time
= info
->timeout
/(32 * 5);
1136 char_time
= min_t(unsigned long, char_time
, timeout
);
1138 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
1139 while (info
->tx_active
) {
1140 msleep_interruptible(jiffies_to_msecs(char_time
));
1141 if (signal_pending(current
))
1143 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
1147 //TODO: determine if there is something similar to USC16C32
1148 // TXSTATUS_ALL_SENT status
1149 while ( info
->tx_active
&& info
->tx_enabled
) {
1150 msleep_interruptible(jiffies_to_msecs(char_time
));
1151 if (signal_pending(current
))
1153 if (timeout
&& time_after(jiffies
, orig_jiffies
+ timeout
))
1160 if (debug_level
>= DEBUG_LEVEL_INFO
)
1161 printk("%s(%d):%s wait_until_sent() exit\n",
1162 __FILE__
,__LINE__
, info
->device_name
);
1165 /* Return the count of free bytes in transmit buffer
1167 static int write_room(struct tty_struct
*tty
)
1169 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1172 if (sanity_check(info
, tty
->name
, "write_room"))
1176 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1177 ret
= (info
->tx_active
) ? 0 : HDLC_MAX_FRAME_SIZE
;
1179 ret
= info
->max_frame_size
- info
->tx_count
- 1;
1185 if (debug_level
>= DEBUG_LEVEL_INFO
)
1186 printk("%s(%d):%s write_room()=%d\n",
1187 __FILE__
, __LINE__
, info
->device_name
, ret
);
1192 /* enable transmitter and send remaining buffered characters
1194 static void flush_chars(struct tty_struct
*tty
)
1196 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1197 unsigned long flags
;
1199 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1200 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1201 __FILE__
,__LINE__
,info
->device_name
,info
->tx_count
);
1203 if (sanity_check(info
, tty
->name
, "flush_chars"))
1206 if (info
->tx_count
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
1210 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1211 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1212 __FILE__
,__LINE__
,info
->device_name
);
1214 spin_lock_irqsave(&info
->lock
,flags
);
1216 if (!info
->tx_active
) {
1217 if ( (info
->params
.mode
== MGSL_MODE_HDLC
) &&
1219 /* operating in synchronous (frame oriented) mode */
1220 /* copy data from circular tx_buf to */
1221 /* transmit DMA buffer. */
1222 tx_load_dma_buffer(info
,
1223 info
->tx_buf
,info
->tx_count
);
1228 spin_unlock_irqrestore(&info
->lock
,flags
);
1231 /* Discard all data in the send buffer
1233 static void flush_buffer(struct tty_struct
*tty
)
1235 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1236 unsigned long flags
;
1238 if (debug_level
>= DEBUG_LEVEL_INFO
)
1239 printk("%s(%d):%s flush_buffer() entry\n",
1240 __FILE__
,__LINE__
, info
->device_name
);
1242 if (sanity_check(info
, tty
->name
, "flush_buffer"))
1245 spin_lock_irqsave(&info
->lock
,flags
);
1246 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
1247 del_timer(&info
->tx_timer
);
1248 spin_unlock_irqrestore(&info
->lock
,flags
);
1253 /* throttle (stop) transmitter
1255 static void tx_hold(struct tty_struct
*tty
)
1257 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1258 unsigned long flags
;
1260 if (sanity_check(info
, tty
->name
, "tx_hold"))
1263 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1264 printk("%s(%d):%s tx_hold()\n",
1265 __FILE__
,__LINE__
,info
->device_name
);
1267 spin_lock_irqsave(&info
->lock
,flags
);
1268 if (info
->tx_enabled
)
1270 spin_unlock_irqrestore(&info
->lock
,flags
);
1273 /* release (start) transmitter
1275 static void tx_release(struct tty_struct
*tty
)
1277 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1278 unsigned long flags
;
1280 if (sanity_check(info
, tty
->name
, "tx_release"))
1283 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1284 printk("%s(%d):%s tx_release()\n",
1285 __FILE__
,__LINE__
,info
->device_name
);
1287 spin_lock_irqsave(&info
->lock
,flags
);
1288 if (!info
->tx_enabled
)
1290 spin_unlock_irqrestore(&info
->lock
,flags
);
1293 /* Service an IOCTL request
1297 * tty pointer to tty instance data
1298 * file pointer to associated file object for device
1299 * cmd IOCTL command code
1300 * arg command argument/context
1302 * Return Value: 0 if success, otherwise error code
1304 static int do_ioctl(struct tty_struct
*tty
, struct file
*file
,
1305 unsigned int cmd
, unsigned long arg
)
1307 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1309 struct mgsl_icount cnow
; /* kernel counter temps */
1310 struct serial_icounter_struct __user
*p_cuser
; /* user space */
1311 unsigned long flags
;
1312 void __user
*argp
= (void __user
*)arg
;
1314 if (debug_level
>= DEBUG_LEVEL_INFO
)
1315 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__
,__LINE__
,
1316 info
->device_name
, cmd
);
1318 if (sanity_check(info
, tty
->name
, "ioctl"))
1321 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
1322 (cmd
!= TIOCMIWAIT
) && (cmd
!= TIOCGICOUNT
)) {
1323 if (tty
->flags
& (1 << TTY_IO_ERROR
))
1328 case MGSL_IOCGPARAMS
:
1329 return get_params(info
, argp
);
1330 case MGSL_IOCSPARAMS
:
1331 return set_params(info
, argp
);
1332 case MGSL_IOCGTXIDLE
:
1333 return get_txidle(info
, argp
);
1334 case MGSL_IOCSTXIDLE
:
1335 return set_txidle(info
, (int)arg
);
1336 case MGSL_IOCTXENABLE
:
1337 return tx_enable(info
, (int)arg
);
1338 case MGSL_IOCRXENABLE
:
1339 return rx_enable(info
, (int)arg
);
1340 case MGSL_IOCTXABORT
:
1341 return tx_abort(info
);
1342 case MGSL_IOCGSTATS
:
1343 return get_stats(info
, argp
);
1344 case MGSL_IOCWAITEVENT
:
1345 return wait_mgsl_event(info
, argp
);
1346 case MGSL_IOCLOOPTXDONE
:
1347 return 0; // TODO: Not supported, need to document
1348 /* Wait for modem input (DCD,RI,DSR,CTS) change
1349 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1352 return modem_input_wait(info
,(int)arg
);
1355 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1356 * Return: write counters to the user passed counter struct
1357 * NB: both 1->0 and 0->1 transitions are counted except for
1358 * RI where only 0->1 is counted.
1361 spin_lock_irqsave(&info
->lock
,flags
);
1362 cnow
= info
->icount
;
1363 spin_unlock_irqrestore(&info
->lock
,flags
);
1365 PUT_USER(error
,cnow
.cts
, &p_cuser
->cts
);
1366 if (error
) return error
;
1367 PUT_USER(error
,cnow
.dsr
, &p_cuser
->dsr
);
1368 if (error
) return error
;
1369 PUT_USER(error
,cnow
.rng
, &p_cuser
->rng
);
1370 if (error
) return error
;
1371 PUT_USER(error
,cnow
.dcd
, &p_cuser
->dcd
);
1372 if (error
) return error
;
1373 PUT_USER(error
,cnow
.rx
, &p_cuser
->rx
);
1374 if (error
) return error
;
1375 PUT_USER(error
,cnow
.tx
, &p_cuser
->tx
);
1376 if (error
) return error
;
1377 PUT_USER(error
,cnow
.frame
, &p_cuser
->frame
);
1378 if (error
) return error
;
1379 PUT_USER(error
,cnow
.overrun
, &p_cuser
->overrun
);
1380 if (error
) return error
;
1381 PUT_USER(error
,cnow
.parity
, &p_cuser
->parity
);
1382 if (error
) return error
;
1383 PUT_USER(error
,cnow
.brk
, &p_cuser
->brk
);
1384 if (error
) return error
;
1385 PUT_USER(error
,cnow
.buf_overrun
, &p_cuser
->buf_overrun
);
1386 if (error
) return error
;
1389 return -ENOIOCTLCMD
;
1394 static int ioctl(struct tty_struct
*tty
, struct file
*file
,
1395 unsigned int cmd
, unsigned long arg
)
1399 ret
= do_ioctl(tty
, file
, cmd
, arg
);
1405 * /proc fs routines....
1408 static inline int line_info(char *buf
, SLMP_INFO
*info
)
1412 unsigned long flags
;
1414 ret
= sprintf(buf
, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1415 "\tIRQ=%d MaxFrameSize=%u\n",
1417 info
->phys_sca_base
,
1418 info
->phys_memory_base
,
1419 info
->phys_statctrl_base
,
1420 info
->phys_lcr_base
,
1422 info
->max_frame_size
);
1424 /* output current serial signal states */
1425 spin_lock_irqsave(&info
->lock
,flags
);
1427 spin_unlock_irqrestore(&info
->lock
,flags
);
1431 if (info
->serial_signals
& SerialSignal_RTS
)
1432 strcat(stat_buf
, "|RTS");
1433 if (info
->serial_signals
& SerialSignal_CTS
)
1434 strcat(stat_buf
, "|CTS");
1435 if (info
->serial_signals
& SerialSignal_DTR
)
1436 strcat(stat_buf
, "|DTR");
1437 if (info
->serial_signals
& SerialSignal_DSR
)
1438 strcat(stat_buf
, "|DSR");
1439 if (info
->serial_signals
& SerialSignal_DCD
)
1440 strcat(stat_buf
, "|CD");
1441 if (info
->serial_signals
& SerialSignal_RI
)
1442 strcat(stat_buf
, "|RI");
1444 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
1445 ret
+= sprintf(buf
+ret
, "\tHDLC txok:%d rxok:%d",
1446 info
->icount
.txok
, info
->icount
.rxok
);
1447 if (info
->icount
.txunder
)
1448 ret
+= sprintf(buf
+ret
, " txunder:%d", info
->icount
.txunder
);
1449 if (info
->icount
.txabort
)
1450 ret
+= sprintf(buf
+ret
, " txabort:%d", info
->icount
.txabort
);
1451 if (info
->icount
.rxshort
)
1452 ret
+= sprintf(buf
+ret
, " rxshort:%d", info
->icount
.rxshort
);
1453 if (info
->icount
.rxlong
)
1454 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxlong
);
1455 if (info
->icount
.rxover
)
1456 ret
+= sprintf(buf
+ret
, " rxover:%d", info
->icount
.rxover
);
1457 if (info
->icount
.rxcrc
)
1458 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxcrc
);
1460 ret
+= sprintf(buf
+ret
, "\tASYNC tx:%d rx:%d",
1461 info
->icount
.tx
, info
->icount
.rx
);
1462 if (info
->icount
.frame
)
1463 ret
+= sprintf(buf
+ret
, " fe:%d", info
->icount
.frame
);
1464 if (info
->icount
.parity
)
1465 ret
+= sprintf(buf
+ret
, " pe:%d", info
->icount
.parity
);
1466 if (info
->icount
.brk
)
1467 ret
+= sprintf(buf
+ret
, " brk:%d", info
->icount
.brk
);
1468 if (info
->icount
.overrun
)
1469 ret
+= sprintf(buf
+ret
, " oe:%d", info
->icount
.overrun
);
1472 /* Append serial signal status to end */
1473 ret
+= sprintf(buf
+ret
, " %s\n", stat_buf
+1);
1475 ret
+= sprintf(buf
+ret
, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1476 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
1482 /* Called to print information about devices
1484 static int read_proc(char *page
, char **start
, off_t off
, int count
,
1485 int *eof
, void *data
)
1491 len
+= sprintf(page
, "synclinkmp driver:%s\n", driver_version
);
1493 info
= synclinkmp_device_list
;
1495 l
= line_info(page
+ len
, info
);
1497 if (len
+begin
> off
+count
)
1499 if (len
+begin
< off
) {
1503 info
= info
->next_device
;
1508 if (off
>= len
+begin
)
1510 *start
= page
+ (off
-begin
);
1511 return ((count
< begin
+len
-off
) ? count
: begin
+len
-off
);
1514 /* Return the count of bytes in transmit buffer
1516 static int chars_in_buffer(struct tty_struct
*tty
)
1518 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1520 if (sanity_check(info
, tty
->name
, "chars_in_buffer"))
1523 if (debug_level
>= DEBUG_LEVEL_INFO
)
1524 printk("%s(%d):%s chars_in_buffer()=%d\n",
1525 __FILE__
, __LINE__
, info
->device_name
, info
->tx_count
);
1527 return info
->tx_count
;
1530 /* Signal remote device to throttle send data (our receive data)
1532 static void throttle(struct tty_struct
* tty
)
1534 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1535 unsigned long flags
;
1537 if (debug_level
>= DEBUG_LEVEL_INFO
)
1538 printk("%s(%d):%s throttle() entry\n",
1539 __FILE__
,__LINE__
, info
->device_name
);
1541 if (sanity_check(info
, tty
->name
, "throttle"))
1545 send_xchar(tty
, STOP_CHAR(tty
));
1547 if (tty
->termios
->c_cflag
& CRTSCTS
) {
1548 spin_lock_irqsave(&info
->lock
,flags
);
1549 info
->serial_signals
&= ~SerialSignal_RTS
;
1551 spin_unlock_irqrestore(&info
->lock
,flags
);
1555 /* Signal remote device to stop throttling send data (our receive data)
1557 static void unthrottle(struct tty_struct
* tty
)
1559 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
1560 unsigned long flags
;
1562 if (debug_level
>= DEBUG_LEVEL_INFO
)
1563 printk("%s(%d):%s unthrottle() entry\n",
1564 __FILE__
,__LINE__
, info
->device_name
);
1566 if (sanity_check(info
, tty
->name
, "unthrottle"))
1573 send_xchar(tty
, START_CHAR(tty
));
1576 if (tty
->termios
->c_cflag
& CRTSCTS
) {
1577 spin_lock_irqsave(&info
->lock
,flags
);
1578 info
->serial_signals
|= SerialSignal_RTS
;
1580 spin_unlock_irqrestore(&info
->lock
,flags
);
1584 /* set or clear transmit break condition
1585 * break_state -1=set break condition, 0=clear
1587 static int set_break(struct tty_struct
*tty
, int break_state
)
1589 unsigned char RegValue
;
1590 SLMP_INFO
* info
= (SLMP_INFO
*)tty
->driver_data
;
1591 unsigned long flags
;
1593 if (debug_level
>= DEBUG_LEVEL_INFO
)
1594 printk("%s(%d):%s set_break(%d)\n",
1595 __FILE__
,__LINE__
, info
->device_name
, break_state
);
1597 if (sanity_check(info
, tty
->name
, "set_break"))
1600 spin_lock_irqsave(&info
->lock
,flags
);
1601 RegValue
= read_reg(info
, CTL
);
1602 if (break_state
== -1)
1606 write_reg(info
, CTL
, RegValue
);
1607 spin_unlock_irqrestore(&info
->lock
,flags
);
1611 #if SYNCLINK_GENERIC_HDLC
1614 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1615 * set encoding and frame check sequence (FCS) options
1617 * dev pointer to network device structure
1618 * encoding serial encoding setting
1619 * parity FCS setting
1621 * returns 0 if success, otherwise error code
1623 static int hdlcdev_attach(struct net_device
*dev
, unsigned short encoding
,
1624 unsigned short parity
)
1626 SLMP_INFO
*info
= dev_to_port(dev
);
1627 unsigned char new_encoding
;
1628 unsigned short new_crctype
;
1630 /* return error if TTY interface open */
1631 if (info
->port
.count
)
1636 case ENCODING_NRZ
: new_encoding
= HDLC_ENCODING_NRZ
; break;
1637 case ENCODING_NRZI
: new_encoding
= HDLC_ENCODING_NRZI_SPACE
; break;
1638 case ENCODING_FM_MARK
: new_encoding
= HDLC_ENCODING_BIPHASE_MARK
; break;
1639 case ENCODING_FM_SPACE
: new_encoding
= HDLC_ENCODING_BIPHASE_SPACE
; break;
1640 case ENCODING_MANCHESTER
: new_encoding
= HDLC_ENCODING_BIPHASE_LEVEL
; break;
1641 default: return -EINVAL
;
1646 case PARITY_NONE
: new_crctype
= HDLC_CRC_NONE
; break;
1647 case PARITY_CRC16_PR1_CCITT
: new_crctype
= HDLC_CRC_16_CCITT
; break;
1648 case PARITY_CRC32_PR1_CCITT
: new_crctype
= HDLC_CRC_32_CCITT
; break;
1649 default: return -EINVAL
;
1652 info
->params
.encoding
= new_encoding
;
1653 info
->params
.crc_type
= new_crctype
;
1655 /* if network interface up, reprogram hardware */
1663 * called by generic HDLC layer to send frame
1665 * skb socket buffer containing HDLC frame
1666 * dev pointer to network device structure
1668 * returns 0 if success, otherwise error code
1670 static int hdlcdev_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1672 SLMP_INFO
*info
= dev_to_port(dev
);
1673 unsigned long flags
;
1675 if (debug_level
>= DEBUG_LEVEL_INFO
)
1676 printk(KERN_INFO
"%s:hdlc_xmit(%s)\n",__FILE__
,dev
->name
);
1678 /* stop sending until this frame completes */
1679 netif_stop_queue(dev
);
1681 /* copy data to device buffers */
1682 info
->tx_count
= skb
->len
;
1683 tx_load_dma_buffer(info
, skb
->data
, skb
->len
);
1685 /* update network statistics */
1686 dev
->stats
.tx_packets
++;
1687 dev
->stats
.tx_bytes
+= skb
->len
;
1689 /* done with socket buffer, so free it */
1692 /* save start time for transmit timeout detection */
1693 dev
->trans_start
= jiffies
;
1695 /* start hardware transmitter if necessary */
1696 spin_lock_irqsave(&info
->lock
,flags
);
1697 if (!info
->tx_active
)
1699 spin_unlock_irqrestore(&info
->lock
,flags
);
1705 * called by network layer when interface enabled
1706 * claim resources and initialize hardware
1708 * dev pointer to network device structure
1710 * returns 0 if success, otherwise error code
1712 static int hdlcdev_open(struct net_device
*dev
)
1714 SLMP_INFO
*info
= dev_to_port(dev
);
1716 unsigned long flags
;
1718 if (debug_level
>= DEBUG_LEVEL_INFO
)
1719 printk("%s:hdlcdev_open(%s)\n",__FILE__
,dev
->name
);
1721 /* generic HDLC layer open processing */
1722 if ((rc
= hdlc_open(dev
)))
1725 /* arbitrate between network and tty opens */
1726 spin_lock_irqsave(&info
->netlock
, flags
);
1727 if (info
->port
.count
!= 0 || info
->netcount
!= 0) {
1728 printk(KERN_WARNING
"%s: hdlc_open returning busy\n", dev
->name
);
1729 spin_unlock_irqrestore(&info
->netlock
, flags
);
1733 spin_unlock_irqrestore(&info
->netlock
, flags
);
1735 /* claim resources and init adapter */
1736 if ((rc
= startup(info
)) != 0) {
1737 spin_lock_irqsave(&info
->netlock
, flags
);
1739 spin_unlock_irqrestore(&info
->netlock
, flags
);
1743 /* assert DTR and RTS, apply hardware settings */
1744 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1747 /* enable network layer transmit */
1748 dev
->trans_start
= jiffies
;
1749 netif_start_queue(dev
);
1751 /* inform generic HDLC layer of current DCD status */
1752 spin_lock_irqsave(&info
->lock
, flags
);
1754 spin_unlock_irqrestore(&info
->lock
, flags
);
1755 if (info
->serial_signals
& SerialSignal_DCD
)
1756 netif_carrier_on(dev
);
1758 netif_carrier_off(dev
);
1763 * called by network layer when interface is disabled
1764 * shutdown hardware and release resources
1766 * dev pointer to network device structure
1768 * returns 0 if success, otherwise error code
1770 static int hdlcdev_close(struct net_device
*dev
)
1772 SLMP_INFO
*info
= dev_to_port(dev
);
1773 unsigned long flags
;
1775 if (debug_level
>= DEBUG_LEVEL_INFO
)
1776 printk("%s:hdlcdev_close(%s)\n",__FILE__
,dev
->name
);
1778 netif_stop_queue(dev
);
1780 /* shutdown adapter and release resources */
1785 spin_lock_irqsave(&info
->netlock
, flags
);
1787 spin_unlock_irqrestore(&info
->netlock
, flags
);
1793 * called by network layer to process IOCTL call to network device
1795 * dev pointer to network device structure
1796 * ifr pointer to network interface request structure
1797 * cmd IOCTL command code
1799 * returns 0 if success, otherwise error code
1801 static int hdlcdev_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1803 const size_t size
= sizeof(sync_serial_settings
);
1804 sync_serial_settings new_line
;
1805 sync_serial_settings __user
*line
= ifr
->ifr_settings
.ifs_ifsu
.sync
;
1806 SLMP_INFO
*info
= dev_to_port(dev
);
1809 if (debug_level
>= DEBUG_LEVEL_INFO
)
1810 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__
,dev
->name
);
1812 /* return error if TTY interface open */
1813 if (info
->port
.count
)
1816 if (cmd
!= SIOCWANDEV
)
1817 return hdlc_ioctl(dev
, ifr
, cmd
);
1819 switch(ifr
->ifr_settings
.type
) {
1820 case IF_GET_IFACE
: /* return current sync_serial_settings */
1822 ifr
->ifr_settings
.type
= IF_IFACE_SYNC_SERIAL
;
1823 if (ifr
->ifr_settings
.size
< size
) {
1824 ifr
->ifr_settings
.size
= size
; /* data size wanted */
1828 flags
= info
->params
.flags
& (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1829 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1830 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1831 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1834 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
): new_line
.clock_type
= CLOCK_EXT
; break;
1835 case (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_INT
; break;
1836 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
): new_line
.clock_type
= CLOCK_TXINT
; break;
1837 case (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
): new_line
.clock_type
= CLOCK_TXFROMRX
; break;
1838 default: new_line
.clock_type
= CLOCK_DEFAULT
;
1841 new_line
.clock_rate
= info
->params
.clock_speed
;
1842 new_line
.loopback
= info
->params
.loopback
? 1:0;
1844 if (copy_to_user(line
, &new_line
, size
))
1848 case IF_IFACE_SYNC_SERIAL
: /* set sync_serial_settings */
1850 if(!capable(CAP_NET_ADMIN
))
1852 if (copy_from_user(&new_line
, line
, size
))
1855 switch (new_line
.clock_type
)
1857 case CLOCK_EXT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_TXCPIN
; break;
1858 case CLOCK_TXFROMRX
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_RXCPIN
; break;
1859 case CLOCK_INT
: flags
= HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
; break;
1860 case CLOCK_TXINT
: flags
= HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_TXC_BRG
; break;
1861 case CLOCK_DEFAULT
: flags
= info
->params
.flags
&
1862 (HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1863 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1864 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1865 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
); break;
1866 default: return -EINVAL
;
1869 if (new_line
.loopback
!= 0 && new_line
.loopback
!= 1)
1872 info
->params
.flags
&= ~(HDLC_FLAG_RXC_RXCPIN
| HDLC_FLAG_RXC_DPLL
|
1873 HDLC_FLAG_RXC_BRG
| HDLC_FLAG_RXC_TXCPIN
|
1874 HDLC_FLAG_TXC_TXCPIN
| HDLC_FLAG_TXC_DPLL
|
1875 HDLC_FLAG_TXC_BRG
| HDLC_FLAG_TXC_RXCPIN
);
1876 info
->params
.flags
|= flags
;
1878 info
->params
.loopback
= new_line
.loopback
;
1880 if (flags
& (HDLC_FLAG_RXC_BRG
| HDLC_FLAG_TXC_BRG
))
1881 info
->params
.clock_speed
= new_line
.clock_rate
;
1883 info
->params
.clock_speed
= 0;
1885 /* if network interface up, reprogram hardware */
1891 return hdlc_ioctl(dev
, ifr
, cmd
);
1896 * called by network layer when transmit timeout is detected
1898 * dev pointer to network device structure
1900 static void hdlcdev_tx_timeout(struct net_device
*dev
)
1902 SLMP_INFO
*info
= dev_to_port(dev
);
1903 unsigned long flags
;
1905 if (debug_level
>= DEBUG_LEVEL_INFO
)
1906 printk("hdlcdev_tx_timeout(%s)\n",dev
->name
);
1908 dev
->stats
.tx_errors
++;
1909 dev
->stats
.tx_aborted_errors
++;
1911 spin_lock_irqsave(&info
->lock
,flags
);
1913 spin_unlock_irqrestore(&info
->lock
,flags
);
1915 netif_wake_queue(dev
);
1919 * called by device driver when transmit completes
1920 * reenable network layer transmit if stopped
1922 * info pointer to device instance information
1924 static void hdlcdev_tx_done(SLMP_INFO
*info
)
1926 if (netif_queue_stopped(info
->netdev
))
1927 netif_wake_queue(info
->netdev
);
1931 * called by device driver when frame received
1932 * pass frame to network layer
1934 * info pointer to device instance information
1935 * buf pointer to buffer contianing frame data
1936 * size count of data bytes in buf
1938 static void hdlcdev_rx(SLMP_INFO
*info
, char *buf
, int size
)
1940 struct sk_buff
*skb
= dev_alloc_skb(size
);
1941 struct net_device
*dev
= info
->netdev
;
1943 if (debug_level
>= DEBUG_LEVEL_INFO
)
1944 printk("hdlcdev_rx(%s)\n",dev
->name
);
1947 printk(KERN_NOTICE
"%s: can't alloc skb, dropping packet\n",
1949 dev
->stats
.rx_dropped
++;
1953 memcpy(skb_put(skb
, size
), buf
, size
);
1955 skb
->protocol
= hdlc_type_trans(skb
, dev
);
1957 dev
->stats
.rx_packets
++;
1958 dev
->stats
.rx_bytes
+= size
;
1962 dev
->last_rx
= jiffies
;
1966 * called by device driver when adding device instance
1967 * do generic HDLC initialization
1969 * info pointer to device instance information
1971 * returns 0 if success, otherwise error code
1973 static int hdlcdev_init(SLMP_INFO
*info
)
1976 struct net_device
*dev
;
1979 /* allocate and initialize network and HDLC layer objects */
1981 if (!(dev
= alloc_hdlcdev(info
))) {
1982 printk(KERN_ERR
"%s:hdlc device allocation failure\n",__FILE__
);
1986 /* for network layer reporting purposes only */
1987 dev
->mem_start
= info
->phys_sca_base
;
1988 dev
->mem_end
= info
->phys_sca_base
+ SCA_BASE_SIZE
- 1;
1989 dev
->irq
= info
->irq_level
;
1991 /* network layer callbacks and settings */
1992 dev
->do_ioctl
= hdlcdev_ioctl
;
1993 dev
->open
= hdlcdev_open
;
1994 dev
->stop
= hdlcdev_close
;
1995 dev
->tx_timeout
= hdlcdev_tx_timeout
;
1996 dev
->watchdog_timeo
= 10*HZ
;
1997 dev
->tx_queue_len
= 50;
1999 /* generic HDLC layer callbacks and settings */
2000 hdlc
= dev_to_hdlc(dev
);
2001 hdlc
->attach
= hdlcdev_attach
;
2002 hdlc
->xmit
= hdlcdev_xmit
;
2004 /* register objects with HDLC layer */
2005 if ((rc
= register_hdlc_device(dev
))) {
2006 printk(KERN_WARNING
"%s:unable to register hdlc device\n",__FILE__
);
2016 * called by device driver when removing device instance
2017 * do generic HDLC cleanup
2019 * info pointer to device instance information
2021 static void hdlcdev_exit(SLMP_INFO
*info
)
2023 unregister_hdlc_device(info
->netdev
);
2024 free_netdev(info
->netdev
);
2025 info
->netdev
= NULL
;
2028 #endif /* CONFIG_HDLC */
2031 /* Return next bottom half action to perform.
2032 * Return Value: BH action code or 0 if nothing to do.
2034 static int bh_action(SLMP_INFO
*info
)
2036 unsigned long flags
;
2039 spin_lock_irqsave(&info
->lock
,flags
);
2041 if (info
->pending_bh
& BH_RECEIVE
) {
2042 info
->pending_bh
&= ~BH_RECEIVE
;
2044 } else if (info
->pending_bh
& BH_TRANSMIT
) {
2045 info
->pending_bh
&= ~BH_TRANSMIT
;
2047 } else if (info
->pending_bh
& BH_STATUS
) {
2048 info
->pending_bh
&= ~BH_STATUS
;
2053 /* Mark BH routine as complete */
2054 info
->bh_running
= false;
2055 info
->bh_requested
= false;
2058 spin_unlock_irqrestore(&info
->lock
,flags
);
2063 /* Perform bottom half processing of work items queued by ISR.
2065 static void bh_handler(struct work_struct
*work
)
2067 SLMP_INFO
*info
= container_of(work
, SLMP_INFO
, task
);
2073 if ( debug_level
>= DEBUG_LEVEL_BH
)
2074 printk( "%s(%d):%s bh_handler() entry\n",
2075 __FILE__
,__LINE__
,info
->device_name
);
2077 info
->bh_running
= true;
2079 while((action
= bh_action(info
)) != 0) {
2081 /* Process work item */
2082 if ( debug_level
>= DEBUG_LEVEL_BH
)
2083 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2084 __FILE__
,__LINE__
,info
->device_name
, action
);
2098 /* unknown work item ID */
2099 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2100 __FILE__
,__LINE__
,info
->device_name
,action
);
2105 if ( debug_level
>= DEBUG_LEVEL_BH
)
2106 printk( "%s(%d):%s bh_handler() exit\n",
2107 __FILE__
,__LINE__
,info
->device_name
);
2110 static void bh_receive(SLMP_INFO
*info
)
2112 if ( debug_level
>= DEBUG_LEVEL_BH
)
2113 printk( "%s(%d):%s bh_receive()\n",
2114 __FILE__
,__LINE__
,info
->device_name
);
2116 while( rx_get_frame(info
) );
2119 static void bh_transmit(SLMP_INFO
*info
)
2121 struct tty_struct
*tty
= info
->port
.tty
;
2123 if ( debug_level
>= DEBUG_LEVEL_BH
)
2124 printk( "%s(%d):%s bh_transmit() entry\n",
2125 __FILE__
,__LINE__
,info
->device_name
);
2131 static void bh_status(SLMP_INFO
*info
)
2133 if ( debug_level
>= DEBUG_LEVEL_BH
)
2134 printk( "%s(%d):%s bh_status() entry\n",
2135 __FILE__
,__LINE__
,info
->device_name
);
2137 info
->ri_chkcount
= 0;
2138 info
->dsr_chkcount
= 0;
2139 info
->dcd_chkcount
= 0;
2140 info
->cts_chkcount
= 0;
2143 static void isr_timer(SLMP_INFO
* info
)
2145 unsigned char timer
= (info
->port_num
& 1) ? TIMER2
: TIMER0
;
2147 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2148 write_reg(info
, IER2
, 0);
2150 /* TMCS, Timer Control/Status Register
2152 * 07 CMF, Compare match flag (read only) 1=match
2153 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2154 * 05 Reserved, must be 0
2155 * 04 TME, Timer Enable
2156 * 03..00 Reserved, must be 0
2160 write_reg(info
, (unsigned char)(timer
+ TMCS
), 0);
2162 info
->irq_occurred
= true;
2164 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2165 printk("%s(%d):%s isr_timer()\n",
2166 __FILE__
,__LINE__
,info
->device_name
);
2169 static void isr_rxint(SLMP_INFO
* info
)
2171 struct tty_struct
*tty
= info
->port
.tty
;
2172 struct mgsl_icount
*icount
= &info
->icount
;
2173 unsigned char status
= read_reg(info
, SR1
) & info
->ie1_value
& (FLGD
+ IDLD
+ CDCD
+ BRKD
);
2174 unsigned char status2
= read_reg(info
, SR2
) & info
->ie2_value
& OVRN
;
2176 /* clear status bits */
2178 write_reg(info
, SR1
, status
);
2181 write_reg(info
, SR2
, status2
);
2183 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2184 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2185 __FILE__
,__LINE__
,info
->device_name
,status
,status2
);
2187 if (info
->params
.mode
== MGSL_MODE_ASYNC
) {
2188 if (status
& BRKD
) {
2191 /* process break detection if tty control
2192 * is not set to ignore it
2195 if (!(status
& info
->ignore_status_mask1
)) {
2196 if (info
->read_status_mask1
& BRKD
) {
2197 tty_insert_flip_char(tty
, 0, TTY_BREAK
);
2198 if (info
->port
.flags
& ASYNC_SAK
)
2206 if (status
& (FLGD
|IDLD
)) {
2208 info
->icount
.exithunt
++;
2209 else if (status
& IDLD
)
2210 info
->icount
.rxidle
++;
2211 wake_up_interruptible(&info
->event_wait_q
);
2215 if (status
& CDCD
) {
2216 /* simulate a common modem status change interrupt
2219 get_signals( info
);
2221 MISCSTATUS_DCD_LATCHED
|(info
->serial_signals
&SerialSignal_DCD
));
2226 * handle async rx data interrupts
2228 static void isr_rxrdy(SLMP_INFO
* info
)
2231 unsigned char DataByte
;
2232 struct tty_struct
*tty
= info
->port
.tty
;
2233 struct mgsl_icount
*icount
= &info
->icount
;
2235 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2236 printk("%s(%d):%s isr_rxrdy\n",
2237 __FILE__
,__LINE__
,info
->device_name
);
2239 while((status
= read_reg(info
,CST0
)) & BIT0
)
2243 DataByte
= read_reg(info
,TRB
);
2247 if ( status
& (PE
+ FRME
+ OVRN
) ) {
2248 printk("%s(%d):%s rxerr=%04X\n",
2249 __FILE__
,__LINE__
,info
->device_name
,status
);
2251 /* update error statistics */
2254 else if (status
& FRME
)
2256 else if (status
& OVRN
)
2259 /* discard char if tty control flags say so */
2260 if (status
& info
->ignore_status_mask2
)
2263 status
&= info
->read_status_mask2
;
2268 else if (status
& FRME
)
2270 if (status
& OVRN
) {
2271 /* Overrun is special, since it's
2272 * reported immediately, and doesn't
2273 * affect the current character
2278 } /* end of if (error) */
2281 tty_insert_flip_char(tty
, DataByte
, flag
);
2283 tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
2287 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
2288 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2289 __FILE__
,__LINE__
,info
->device_name
,
2290 icount
->rx
,icount
->brk
,icount
->parity
,
2291 icount
->frame
,icount
->overrun
);
2295 tty_flip_buffer_push(tty
);
2298 static void isr_txeom(SLMP_INFO
* info
, unsigned char status
)
2300 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2301 printk("%s(%d):%s isr_txeom status=%02x\n",
2302 __FILE__
,__LINE__
,info
->device_name
,status
);
2304 write_reg(info
, TXDMA
+ DIR, 0x00); /* disable Tx DMA IRQs */
2305 write_reg(info
, TXDMA
+ DSR
, 0xc0); /* clear IRQs and disable DMA */
2306 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
2308 if (status
& UDRN
) {
2309 write_reg(info
, CMD
, TXRESET
);
2310 write_reg(info
, CMD
, TXENABLE
);
2312 write_reg(info
, CMD
, TXBUFCLR
);
2314 /* disable and clear tx interrupts */
2315 info
->ie0_value
&= ~TXRDYE
;
2316 info
->ie1_value
&= ~(IDLE
+ UDRN
);
2317 write_reg16(info
, IE0
, (unsigned short)((info
->ie1_value
<< 8) + info
->ie0_value
));
2318 write_reg(info
, SR1
, (unsigned char)(UDRN
+ IDLE
));
2320 if ( info
->tx_active
) {
2321 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
2323 info
->icount
.txunder
++;
2324 else if (status
& IDLE
)
2325 info
->icount
.txok
++;
2328 info
->tx_active
= false;
2329 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
2331 del_timer(&info
->tx_timer
);
2333 if (info
->params
.mode
!= MGSL_MODE_ASYNC
&& info
->drop_rts_on_tx_done
) {
2334 info
->serial_signals
&= ~SerialSignal_RTS
;
2335 info
->drop_rts_on_tx_done
= false;
2339 #if SYNCLINK_GENERIC_HDLC
2341 hdlcdev_tx_done(info
);
2345 if (info
->port
.tty
&& (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
)) {
2349 info
->pending_bh
|= BH_TRANSMIT
;
2356 * handle tx status interrupts
2358 static void isr_txint(SLMP_INFO
* info
)
2360 unsigned char status
= read_reg(info
, SR1
) & info
->ie1_value
& (UDRN
+ IDLE
+ CCTS
);
2362 /* clear status bits */
2363 write_reg(info
, SR1
, status
);
2365 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2366 printk("%s(%d):%s isr_txint status=%02x\n",
2367 __FILE__
,__LINE__
,info
->device_name
,status
);
2369 if (status
& (UDRN
+ IDLE
))
2370 isr_txeom(info
, status
);
2372 if (status
& CCTS
) {
2373 /* simulate a common modem status change interrupt
2376 get_signals( info
);
2378 MISCSTATUS_CTS_LATCHED
|(info
->serial_signals
&SerialSignal_CTS
));
2384 * handle async tx data interrupts
2386 static void isr_txrdy(SLMP_INFO
* info
)
2388 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2389 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2390 __FILE__
,__LINE__
,info
->device_name
,info
->tx_count
);
2392 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
2393 /* disable TXRDY IRQ, enable IDLE IRQ */
2394 info
->ie0_value
&= ~TXRDYE
;
2395 info
->ie1_value
|= IDLE
;
2396 write_reg16(info
, IE0
, (unsigned short)((info
->ie1_value
<< 8) + info
->ie0_value
));
2400 if (info
->port
.tty
&& (info
->port
.tty
->stopped
|| info
->port
.tty
->hw_stopped
)) {
2405 if ( info
->tx_count
)
2406 tx_load_fifo( info
);
2408 info
->tx_active
= false;
2409 info
->ie0_value
&= ~TXRDYE
;
2410 write_reg(info
, IE0
, info
->ie0_value
);
2413 if (info
->tx_count
< WAKEUP_CHARS
)
2414 info
->pending_bh
|= BH_TRANSMIT
;
2417 static void isr_rxdmaok(SLMP_INFO
* info
)
2419 /* BIT7 = EOT (end of transfer)
2420 * BIT6 = EOM (end of message/frame)
2422 unsigned char status
= read_reg(info
,RXDMA
+ DSR
) & 0xc0;
2424 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2425 write_reg(info
, RXDMA
+ DSR
, (unsigned char)(status
| 1));
2427 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2428 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2429 __FILE__
,__LINE__
,info
->device_name
,status
);
2431 info
->pending_bh
|= BH_RECEIVE
;
2434 static void isr_rxdmaerror(SLMP_INFO
* info
)
2436 /* BIT5 = BOF (buffer overflow)
2437 * BIT4 = COF (counter overflow)
2439 unsigned char status
= read_reg(info
,RXDMA
+ DSR
) & 0x30;
2441 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2442 write_reg(info
, RXDMA
+ DSR
, (unsigned char)(status
| 1));
2444 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2445 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2446 __FILE__
,__LINE__
,info
->device_name
,status
);
2448 info
->rx_overflow
= true;
2449 info
->pending_bh
|= BH_RECEIVE
;
2452 static void isr_txdmaok(SLMP_INFO
* info
)
2454 unsigned char status_reg1
= read_reg(info
, SR1
);
2456 write_reg(info
, TXDMA
+ DIR, 0x00); /* disable Tx DMA IRQs */
2457 write_reg(info
, TXDMA
+ DSR
, 0xc0); /* clear IRQs and disable DMA */
2458 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
2460 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2461 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2462 __FILE__
,__LINE__
,info
->device_name
,status_reg1
);
2464 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2465 write_reg16(info
, TRC0
, 0);
2466 info
->ie0_value
|= TXRDYE
;
2467 write_reg(info
, IE0
, info
->ie0_value
);
2470 static void isr_txdmaerror(SLMP_INFO
* info
)
2472 /* BIT5 = BOF (buffer overflow)
2473 * BIT4 = COF (counter overflow)
2475 unsigned char status
= read_reg(info
,TXDMA
+ DSR
) & 0x30;
2477 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2478 write_reg(info
, TXDMA
+ DSR
, (unsigned char)(status
| 1));
2480 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2481 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2482 __FILE__
,__LINE__
,info
->device_name
,status
);
2485 /* handle input serial signal changes
2487 static void isr_io_pin( SLMP_INFO
*info
, u16 status
)
2489 struct mgsl_icount
*icount
;
2491 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2492 printk("%s(%d):isr_io_pin status=%04X\n",
2493 __FILE__
,__LINE__
,status
);
2495 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
2496 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
2497 icount
= &info
->icount
;
2498 /* update input line counters */
2499 if (status
& MISCSTATUS_RI_LATCHED
) {
2501 if ( status
& SerialSignal_RI
)
2502 info
->input_signal_events
.ri_up
++;
2504 info
->input_signal_events
.ri_down
++;
2506 if (status
& MISCSTATUS_DSR_LATCHED
) {
2508 if ( status
& SerialSignal_DSR
)
2509 info
->input_signal_events
.dsr_up
++;
2511 info
->input_signal_events
.dsr_down
++;
2513 if (status
& MISCSTATUS_DCD_LATCHED
) {
2514 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
) {
2515 info
->ie1_value
&= ~CDCD
;
2516 write_reg(info
, IE1
, info
->ie1_value
);
2519 if (status
& SerialSignal_DCD
) {
2520 info
->input_signal_events
.dcd_up
++;
2522 info
->input_signal_events
.dcd_down
++;
2523 #if SYNCLINK_GENERIC_HDLC
2524 if (info
->netcount
) {
2525 if (status
& SerialSignal_DCD
)
2526 netif_carrier_on(info
->netdev
);
2528 netif_carrier_off(info
->netdev
);
2532 if (status
& MISCSTATUS_CTS_LATCHED
)
2534 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
) {
2535 info
->ie1_value
&= ~CCTS
;
2536 write_reg(info
, IE1
, info
->ie1_value
);
2539 if ( status
& SerialSignal_CTS
)
2540 info
->input_signal_events
.cts_up
++;
2542 info
->input_signal_events
.cts_down
++;
2544 wake_up_interruptible(&info
->status_event_wait_q
);
2545 wake_up_interruptible(&info
->event_wait_q
);
2547 if ( (info
->port
.flags
& ASYNC_CHECK_CD
) &&
2548 (status
& MISCSTATUS_DCD_LATCHED
) ) {
2549 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2550 printk("%s CD now %s...", info
->device_name
,
2551 (status
& SerialSignal_DCD
) ? "on" : "off");
2552 if (status
& SerialSignal_DCD
)
2553 wake_up_interruptible(&info
->port
.open_wait
);
2555 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2556 printk("doing serial hangup...");
2558 tty_hangup(info
->port
.tty
);
2562 if ( (info
->port
.flags
& ASYNC_CTS_FLOW
) &&
2563 (status
& MISCSTATUS_CTS_LATCHED
) ) {
2564 if ( info
->port
.tty
) {
2565 if (info
->port
.tty
->hw_stopped
) {
2566 if (status
& SerialSignal_CTS
) {
2567 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2568 printk("CTS tx start...");
2569 info
->port
.tty
->hw_stopped
= 0;
2571 info
->pending_bh
|= BH_TRANSMIT
;
2575 if (!(status
& SerialSignal_CTS
)) {
2576 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2577 printk("CTS tx stop...");
2578 info
->port
.tty
->hw_stopped
= 1;
2586 info
->pending_bh
|= BH_STATUS
;
2589 /* Interrupt service routine entry point.
2592 * irq interrupt number that caused interrupt
2593 * dev_id device ID supplied during interrupt registration
2594 * regs interrupted processor context
2596 static irqreturn_t
synclinkmp_interrupt(int dummy
, void *dev_id
)
2598 SLMP_INFO
*info
= dev_id
;
2599 unsigned char status
, status0
, status1
=0;
2600 unsigned char dmastatus
, dmastatus0
, dmastatus1
=0;
2601 unsigned char timerstatus0
, timerstatus1
=0;
2602 unsigned char shift
;
2606 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2607 printk(KERN_DEBUG
"%s(%d): synclinkmp_interrupt(%d)entry.\n",
2608 __FILE__
, __LINE__
, info
->irq_level
);
2610 spin_lock(&info
->lock
);
2614 /* get status for SCA0 (ports 0-1) */
2615 tmp
= read_reg16(info
, ISR0
); /* get ISR0 and ISR1 in one read */
2616 status0
= (unsigned char)tmp
;
2617 dmastatus0
= (unsigned char)(tmp
>>8);
2618 timerstatus0
= read_reg(info
, ISR2
);
2620 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2621 printk(KERN_DEBUG
"%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2622 __FILE__
, __LINE__
, info
->device_name
,
2623 status0
, dmastatus0
, timerstatus0
);
2625 if (info
->port_count
== 4) {
2626 /* get status for SCA1 (ports 2-3) */
2627 tmp
= read_reg16(info
->port_array
[2], ISR0
);
2628 status1
= (unsigned char)tmp
;
2629 dmastatus1
= (unsigned char)(tmp
>>8);
2630 timerstatus1
= read_reg(info
->port_array
[2], ISR2
);
2632 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2633 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2634 __FILE__
,__LINE__
,info
->device_name
,
2635 status1
,dmastatus1
,timerstatus1
);
2638 if (!status0
&& !dmastatus0
&& !timerstatus0
&&
2639 !status1
&& !dmastatus1
&& !timerstatus1
)
2642 for(i
=0; i
< info
->port_count
; i
++) {
2643 if (info
->port_array
[i
] == NULL
)
2647 dmastatus
= dmastatus0
;
2650 dmastatus
= dmastatus1
;
2653 shift
= i
& 1 ? 4 :0;
2655 if (status
& BIT0
<< shift
)
2656 isr_rxrdy(info
->port_array
[i
]);
2657 if (status
& BIT1
<< shift
)
2658 isr_txrdy(info
->port_array
[i
]);
2659 if (status
& BIT2
<< shift
)
2660 isr_rxint(info
->port_array
[i
]);
2661 if (status
& BIT3
<< shift
)
2662 isr_txint(info
->port_array
[i
]);
2664 if (dmastatus
& BIT0
<< shift
)
2665 isr_rxdmaerror(info
->port_array
[i
]);
2666 if (dmastatus
& BIT1
<< shift
)
2667 isr_rxdmaok(info
->port_array
[i
]);
2668 if (dmastatus
& BIT2
<< shift
)
2669 isr_txdmaerror(info
->port_array
[i
]);
2670 if (dmastatus
& BIT3
<< shift
)
2671 isr_txdmaok(info
->port_array
[i
]);
2674 if (timerstatus0
& (BIT5
| BIT4
))
2675 isr_timer(info
->port_array
[0]);
2676 if (timerstatus0
& (BIT7
| BIT6
))
2677 isr_timer(info
->port_array
[1]);
2678 if (timerstatus1
& (BIT5
| BIT4
))
2679 isr_timer(info
->port_array
[2]);
2680 if (timerstatus1
& (BIT7
| BIT6
))
2681 isr_timer(info
->port_array
[3]);
2684 for(i
=0; i
< info
->port_count
; i
++) {
2685 SLMP_INFO
* port
= info
->port_array
[i
];
2687 /* Request bottom half processing if there's something
2688 * for it to do and the bh is not already running.
2690 * Note: startup adapter diags require interrupts.
2691 * do not request bottom half processing if the
2692 * device is not open in a normal mode.
2694 if ( port
&& (port
->port
.count
|| port
->netcount
) &&
2695 port
->pending_bh
&& !port
->bh_running
&&
2696 !port
->bh_requested
) {
2697 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2698 printk("%s(%d):%s queueing bh task.\n",
2699 __FILE__
,__LINE__
,port
->device_name
);
2700 schedule_work(&port
->task
);
2701 port
->bh_requested
= true;
2705 spin_unlock(&info
->lock
);
2707 if ( debug_level
>= DEBUG_LEVEL_ISR
)
2708 printk(KERN_DEBUG
"%s(%d):synclinkmp_interrupt(%d)exit.\n",
2709 __FILE__
, __LINE__
, info
->irq_level
);
2713 /* Initialize and start device.
2715 static int startup(SLMP_INFO
* info
)
2717 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2718 printk("%s(%d):%s tx_releaseup()\n",__FILE__
,__LINE__
,info
->device_name
);
2720 if (info
->port
.flags
& ASYNC_INITIALIZED
)
2723 if (!info
->tx_buf
) {
2724 info
->tx_buf
= kmalloc(info
->max_frame_size
, GFP_KERNEL
);
2725 if (!info
->tx_buf
) {
2726 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
2727 __FILE__
,__LINE__
,info
->device_name
);
2732 info
->pending_bh
= 0;
2734 memset(&info
->icount
, 0, sizeof(info
->icount
));
2736 /* program hardware for current parameters */
2739 change_params(info
);
2741 mod_timer(&info
->status_timer
, jiffies
+ msecs_to_jiffies(10));
2744 clear_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
2746 info
->port
.flags
|= ASYNC_INITIALIZED
;
2751 /* Called by close() and hangup() to shutdown hardware
2753 static void shutdown(SLMP_INFO
* info
)
2755 unsigned long flags
;
2757 if (!(info
->port
.flags
& ASYNC_INITIALIZED
))
2760 if (debug_level
>= DEBUG_LEVEL_INFO
)
2761 printk("%s(%d):%s synclinkmp_shutdown()\n",
2762 __FILE__
,__LINE__
, info
->device_name
);
2764 /* clear status wait queue because status changes */
2765 /* can't happen after shutting down the hardware */
2766 wake_up_interruptible(&info
->status_event_wait_q
);
2767 wake_up_interruptible(&info
->event_wait_q
);
2769 del_timer(&info
->tx_timer
);
2770 del_timer(&info
->status_timer
);
2772 kfree(info
->tx_buf
);
2773 info
->tx_buf
= NULL
;
2775 spin_lock_irqsave(&info
->lock
,flags
);
2779 if (!info
->port
.tty
|| info
->port
.tty
->termios
->c_cflag
& HUPCL
) {
2780 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
2784 spin_unlock_irqrestore(&info
->lock
,flags
);
2787 set_bit(TTY_IO_ERROR
, &info
->port
.tty
->flags
);
2789 info
->port
.flags
&= ~ASYNC_INITIALIZED
;
2792 static void program_hw(SLMP_INFO
*info
)
2794 unsigned long flags
;
2796 spin_lock_irqsave(&info
->lock
,flags
);
2801 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
2803 if (info
->params
.mode
== MGSL_MODE_HDLC
|| info
->netcount
)
2810 info
->dcd_chkcount
= 0;
2811 info
->cts_chkcount
= 0;
2812 info
->ri_chkcount
= 0;
2813 info
->dsr_chkcount
= 0;
2815 info
->ie1_value
|= (CDCD
|CCTS
);
2816 write_reg(info
, IE1
, info
->ie1_value
);
2820 if (info
->netcount
|| (info
->port
.tty
&& info
->port
.tty
->termios
->c_cflag
& CREAD
) )
2823 spin_unlock_irqrestore(&info
->lock
,flags
);
2826 /* Reconfigure adapter based on new parameters
2828 static void change_params(SLMP_INFO
*info
)
2833 if (!info
->port
.tty
|| !info
->port
.tty
->termios
)
2836 if (debug_level
>= DEBUG_LEVEL_INFO
)
2837 printk("%s(%d):%s change_params()\n",
2838 __FILE__
,__LINE__
, info
->device_name
);
2840 cflag
= info
->port
.tty
->termios
->c_cflag
;
2842 /* if B0 rate (hangup) specified then negate DTR and RTS */
2843 /* otherwise assert DTR and RTS */
2845 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
2847 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
2849 /* byte size and parity */
2851 switch (cflag
& CSIZE
) {
2852 case CS5
: info
->params
.data_bits
= 5; break;
2853 case CS6
: info
->params
.data_bits
= 6; break;
2854 case CS7
: info
->params
.data_bits
= 7; break;
2855 case CS8
: info
->params
.data_bits
= 8; break;
2856 /* Never happens, but GCC is too dumb to figure it out */
2857 default: info
->params
.data_bits
= 7; break;
2861 info
->params
.stop_bits
= 2;
2863 info
->params
.stop_bits
= 1;
2865 info
->params
.parity
= ASYNC_PARITY_NONE
;
2866 if (cflag
& PARENB
) {
2868 info
->params
.parity
= ASYNC_PARITY_ODD
;
2870 info
->params
.parity
= ASYNC_PARITY_EVEN
;
2873 info
->params
.parity
= ASYNC_PARITY_SPACE
;
2877 /* calculate number of jiffies to transmit a full
2878 * FIFO (32 bytes) at specified data rate
2880 bits_per_char
= info
->params
.data_bits
+
2881 info
->params
.stop_bits
+ 1;
2883 /* if port data rate is set to 460800 or less then
2884 * allow tty settings to override, otherwise keep the
2885 * current data rate.
2887 if (info
->params
.data_rate
<= 460800) {
2888 info
->params
.data_rate
= tty_get_baud_rate(info
->port
.tty
);
2891 if ( info
->params
.data_rate
) {
2892 info
->timeout
= (32*HZ
*bits_per_char
) /
2893 info
->params
.data_rate
;
2895 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
2897 if (cflag
& CRTSCTS
)
2898 info
->port
.flags
|= ASYNC_CTS_FLOW
;
2900 info
->port
.flags
&= ~ASYNC_CTS_FLOW
;
2903 info
->port
.flags
&= ~ASYNC_CHECK_CD
;
2905 info
->port
.flags
|= ASYNC_CHECK_CD
;
2907 /* process tty input control flags */
2909 info
->read_status_mask2
= OVRN
;
2910 if (I_INPCK(info
->port
.tty
))
2911 info
->read_status_mask2
|= PE
| FRME
;
2912 if (I_BRKINT(info
->port
.tty
) || I_PARMRK(info
->port
.tty
))
2913 info
->read_status_mask1
|= BRKD
;
2914 if (I_IGNPAR(info
->port
.tty
))
2915 info
->ignore_status_mask2
|= PE
| FRME
;
2916 if (I_IGNBRK(info
->port
.tty
)) {
2917 info
->ignore_status_mask1
|= BRKD
;
2918 /* If ignoring parity and break indicators, ignore
2919 * overruns too. (For real raw support).
2921 if (I_IGNPAR(info
->port
.tty
))
2922 info
->ignore_status_mask2
|= OVRN
;
2928 static int get_stats(SLMP_INFO
* info
, struct mgsl_icount __user
*user_icount
)
2932 if (debug_level
>= DEBUG_LEVEL_INFO
)
2933 printk("%s(%d):%s get_params()\n",
2934 __FILE__
,__LINE__
, info
->device_name
);
2937 memset(&info
->icount
, 0, sizeof(info
->icount
));
2939 COPY_TO_USER(err
, user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2947 static int get_params(SLMP_INFO
* info
, MGSL_PARAMS __user
*user_params
)
2950 if (debug_level
>= DEBUG_LEVEL_INFO
)
2951 printk("%s(%d):%s get_params()\n",
2952 __FILE__
,__LINE__
, info
->device_name
);
2954 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2956 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2957 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2958 __FILE__
,__LINE__
,info
->device_name
);
2965 static int set_params(SLMP_INFO
* info
, MGSL_PARAMS __user
*new_params
)
2967 unsigned long flags
;
2968 MGSL_PARAMS tmp_params
;
2971 if (debug_level
>= DEBUG_LEVEL_INFO
)
2972 printk("%s(%d):%s set_params\n",
2973 __FILE__
,__LINE__
,info
->device_name
);
2974 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2976 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2977 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2978 __FILE__
,__LINE__
,info
->device_name
);
2982 spin_lock_irqsave(&info
->lock
,flags
);
2983 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2984 spin_unlock_irqrestore(&info
->lock
,flags
);
2986 change_params(info
);
2991 static int get_txidle(SLMP_INFO
* info
, int __user
*idle_mode
)
2995 if (debug_level
>= DEBUG_LEVEL_INFO
)
2996 printk("%s(%d):%s get_txidle()=%d\n",
2997 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
2999 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
3001 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3002 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3003 __FILE__
,__LINE__
,info
->device_name
);
3010 static int set_txidle(SLMP_INFO
* info
, int idle_mode
)
3012 unsigned long flags
;
3014 if (debug_level
>= DEBUG_LEVEL_INFO
)
3015 printk("%s(%d):%s set_txidle(%d)\n",
3016 __FILE__
,__LINE__
,info
->device_name
, idle_mode
);
3018 spin_lock_irqsave(&info
->lock
,flags
);
3019 info
->idle_mode
= idle_mode
;
3020 tx_set_idle( info
);
3021 spin_unlock_irqrestore(&info
->lock
,flags
);
3025 static int tx_enable(SLMP_INFO
* info
, int enable
)
3027 unsigned long flags
;
3029 if (debug_level
>= DEBUG_LEVEL_INFO
)
3030 printk("%s(%d):%s tx_enable(%d)\n",
3031 __FILE__
,__LINE__
,info
->device_name
, enable
);
3033 spin_lock_irqsave(&info
->lock
,flags
);
3035 if ( !info
->tx_enabled
) {
3039 if ( info
->tx_enabled
)
3042 spin_unlock_irqrestore(&info
->lock
,flags
);
3046 /* abort send HDLC frame
3048 static int tx_abort(SLMP_INFO
* info
)
3050 unsigned long flags
;
3052 if (debug_level
>= DEBUG_LEVEL_INFO
)
3053 printk("%s(%d):%s tx_abort()\n",
3054 __FILE__
,__LINE__
,info
->device_name
);
3056 spin_lock_irqsave(&info
->lock
,flags
);
3057 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
3058 info
->ie1_value
&= ~UDRN
;
3059 info
->ie1_value
|= IDLE
;
3060 write_reg(info
, IE1
, info
->ie1_value
); /* disable tx status interrupts */
3061 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
)); /* clear pending */
3063 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
3064 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
3066 write_reg(info
, CMD
, TXABORT
);
3068 spin_unlock_irqrestore(&info
->lock
,flags
);
3072 static int rx_enable(SLMP_INFO
* info
, int enable
)
3074 unsigned long flags
;
3076 if (debug_level
>= DEBUG_LEVEL_INFO
)
3077 printk("%s(%d):%s rx_enable(%d)\n",
3078 __FILE__
,__LINE__
,info
->device_name
,enable
);
3080 spin_lock_irqsave(&info
->lock
,flags
);
3082 if ( !info
->rx_enabled
)
3085 if ( info
->rx_enabled
)
3088 spin_unlock_irqrestore(&info
->lock
,flags
);
3092 /* wait for specified event to occur
3094 static int wait_mgsl_event(SLMP_INFO
* info
, int __user
*mask_ptr
)
3096 unsigned long flags
;
3099 struct mgsl_icount cprev
, cnow
;
3102 struct _input_signal_events oldsigs
, newsigs
;
3103 DECLARE_WAITQUEUE(wait
, current
);
3105 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
3110 if (debug_level
>= DEBUG_LEVEL_INFO
)
3111 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3112 __FILE__
,__LINE__
,info
->device_name
,mask
);
3114 spin_lock_irqsave(&info
->lock
,flags
);
3116 /* return immediately if state matches requested events */
3118 s
= info
->serial_signals
;
3121 ( ((s
& SerialSignal_DSR
) ? MgslEvent_DsrActive
:MgslEvent_DsrInactive
) +
3122 ((s
& SerialSignal_DCD
) ? MgslEvent_DcdActive
:MgslEvent_DcdInactive
) +
3123 ((s
& SerialSignal_CTS
) ? MgslEvent_CtsActive
:MgslEvent_CtsInactive
) +
3124 ((s
& SerialSignal_RI
) ? MgslEvent_RiActive
:MgslEvent_RiInactive
) );
3126 spin_unlock_irqrestore(&info
->lock
,flags
);
3130 /* save current irq counts */
3131 cprev
= info
->icount
;
3132 oldsigs
= info
->input_signal_events
;
3134 /* enable hunt and idle irqs if needed */
3135 if (mask
& (MgslEvent_ExitHuntMode
+MgslEvent_IdleReceived
)) {
3136 unsigned char oldval
= info
->ie1_value
;
3137 unsigned char newval
= oldval
+
3138 (mask
& MgslEvent_ExitHuntMode
? FLGD
:0) +
3139 (mask
& MgslEvent_IdleReceived
? IDLD
:0);
3140 if ( oldval
!= newval
) {
3141 info
->ie1_value
= newval
;
3142 write_reg(info
, IE1
, info
->ie1_value
);
3146 set_current_state(TASK_INTERRUPTIBLE
);
3147 add_wait_queue(&info
->event_wait_q
, &wait
);
3149 spin_unlock_irqrestore(&info
->lock
,flags
);
3153 if (signal_pending(current
)) {
3158 /* get current irq counts */
3159 spin_lock_irqsave(&info
->lock
,flags
);
3160 cnow
= info
->icount
;
3161 newsigs
= info
->input_signal_events
;
3162 set_current_state(TASK_INTERRUPTIBLE
);
3163 spin_unlock_irqrestore(&info
->lock
,flags
);
3165 /* if no change, wait aborted for some reason */
3166 if (newsigs
.dsr_up
== oldsigs
.dsr_up
&&
3167 newsigs
.dsr_down
== oldsigs
.dsr_down
&&
3168 newsigs
.dcd_up
== oldsigs
.dcd_up
&&
3169 newsigs
.dcd_down
== oldsigs
.dcd_down
&&
3170 newsigs
.cts_up
== oldsigs
.cts_up
&&
3171 newsigs
.cts_down
== oldsigs
.cts_down
&&
3172 newsigs
.ri_up
== oldsigs
.ri_up
&&
3173 newsigs
.ri_down
== oldsigs
.ri_down
&&
3174 cnow
.exithunt
== cprev
.exithunt
&&
3175 cnow
.rxidle
== cprev
.rxidle
) {
3181 ( (newsigs
.dsr_up
!= oldsigs
.dsr_up
? MgslEvent_DsrActive
:0) +
3182 (newsigs
.dsr_down
!= oldsigs
.dsr_down
? MgslEvent_DsrInactive
:0) +
3183 (newsigs
.dcd_up
!= oldsigs
.dcd_up
? MgslEvent_DcdActive
:0) +
3184 (newsigs
.dcd_down
!= oldsigs
.dcd_down
? MgslEvent_DcdInactive
:0) +
3185 (newsigs
.cts_up
!= oldsigs
.cts_up
? MgslEvent_CtsActive
:0) +
3186 (newsigs
.cts_down
!= oldsigs
.cts_down
? MgslEvent_CtsInactive
:0) +
3187 (newsigs
.ri_up
!= oldsigs
.ri_up
? MgslEvent_RiActive
:0) +
3188 (newsigs
.ri_down
!= oldsigs
.ri_down
? MgslEvent_RiInactive
:0) +
3189 (cnow
.exithunt
!= cprev
.exithunt
? MgslEvent_ExitHuntMode
:0) +
3190 (cnow
.rxidle
!= cprev
.rxidle
? MgslEvent_IdleReceived
:0) );
3198 remove_wait_queue(&info
->event_wait_q
, &wait
);
3199 set_current_state(TASK_RUNNING
);
3202 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
3203 spin_lock_irqsave(&info
->lock
,flags
);
3204 if (!waitqueue_active(&info
->event_wait_q
)) {
3205 /* disable enable exit hunt mode/idle rcvd IRQs */
3206 info
->ie1_value
&= ~(FLGD
|IDLD
);
3207 write_reg(info
, IE1
, info
->ie1_value
);
3209 spin_unlock_irqrestore(&info
->lock
,flags
);
3213 PUT_USER(rc
, events
, mask_ptr
);
3218 static int modem_input_wait(SLMP_INFO
*info
,int arg
)
3220 unsigned long flags
;
3222 struct mgsl_icount cprev
, cnow
;
3223 DECLARE_WAITQUEUE(wait
, current
);
3225 /* save current irq counts */
3226 spin_lock_irqsave(&info
->lock
,flags
);
3227 cprev
= info
->icount
;
3228 add_wait_queue(&info
->status_event_wait_q
, &wait
);
3229 set_current_state(TASK_INTERRUPTIBLE
);
3230 spin_unlock_irqrestore(&info
->lock
,flags
);
3234 if (signal_pending(current
)) {
3239 /* get new irq counts */
3240 spin_lock_irqsave(&info
->lock
,flags
);
3241 cnow
= info
->icount
;
3242 set_current_state(TASK_INTERRUPTIBLE
);
3243 spin_unlock_irqrestore(&info
->lock
,flags
);
3245 /* if no change, wait aborted for some reason */
3246 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
3247 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
) {
3252 /* check for change in caller specified modem input */
3253 if ((arg
& TIOCM_RNG
&& cnow
.rng
!= cprev
.rng
) ||
3254 (arg
& TIOCM_DSR
&& cnow
.dsr
!= cprev
.dsr
) ||
3255 (arg
& TIOCM_CD
&& cnow
.dcd
!= cprev
.dcd
) ||
3256 (arg
& TIOCM_CTS
&& cnow
.cts
!= cprev
.cts
)) {
3263 remove_wait_queue(&info
->status_event_wait_q
, &wait
);
3264 set_current_state(TASK_RUNNING
);
3268 /* return the state of the serial control and status signals
3270 static int tiocmget(struct tty_struct
*tty
, struct file
*file
)
3272 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
3273 unsigned int result
;
3274 unsigned long flags
;
3276 spin_lock_irqsave(&info
->lock
,flags
);
3278 spin_unlock_irqrestore(&info
->lock
,flags
);
3280 result
= ((info
->serial_signals
& SerialSignal_RTS
) ? TIOCM_RTS
:0) +
3281 ((info
->serial_signals
& SerialSignal_DTR
) ? TIOCM_DTR
:0) +
3282 ((info
->serial_signals
& SerialSignal_DCD
) ? TIOCM_CAR
:0) +
3283 ((info
->serial_signals
& SerialSignal_RI
) ? TIOCM_RNG
:0) +
3284 ((info
->serial_signals
& SerialSignal_DSR
) ? TIOCM_DSR
:0) +
3285 ((info
->serial_signals
& SerialSignal_CTS
) ? TIOCM_CTS
:0);
3287 if (debug_level
>= DEBUG_LEVEL_INFO
)
3288 printk("%s(%d):%s tiocmget() value=%08X\n",
3289 __FILE__
,__LINE__
, info
->device_name
, result
);
3293 /* set modem control signals (DTR/RTS)
3295 static int tiocmset(struct tty_struct
*tty
, struct file
*file
,
3296 unsigned int set
, unsigned int clear
)
3298 SLMP_INFO
*info
= (SLMP_INFO
*)tty
->driver_data
;
3299 unsigned long flags
;
3301 if (debug_level
>= DEBUG_LEVEL_INFO
)
3302 printk("%s(%d):%s tiocmset(%x,%x)\n",
3303 __FILE__
,__LINE__
,info
->device_name
, set
, clear
);
3305 if (set
& TIOCM_RTS
)
3306 info
->serial_signals
|= SerialSignal_RTS
;
3307 if (set
& TIOCM_DTR
)
3308 info
->serial_signals
|= SerialSignal_DTR
;
3309 if (clear
& TIOCM_RTS
)
3310 info
->serial_signals
&= ~SerialSignal_RTS
;
3311 if (clear
& TIOCM_DTR
)
3312 info
->serial_signals
&= ~SerialSignal_DTR
;
3314 spin_lock_irqsave(&info
->lock
,flags
);
3316 spin_unlock_irqrestore(&info
->lock
,flags
);
3323 /* Block the current process until the specified port is ready to open.
3325 static int block_til_ready(struct tty_struct
*tty
, struct file
*filp
,
3328 DECLARE_WAITQUEUE(wait
, current
);
3330 bool do_clocal
= false;
3331 bool extra_count
= false;
3332 unsigned long flags
;
3334 if (debug_level
>= DEBUG_LEVEL_INFO
)
3335 printk("%s(%d):%s block_til_ready()\n",
3336 __FILE__
,__LINE__
, tty
->driver
->name
);
3338 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3339 /* nonblock mode is set or port is not enabled */
3340 /* just verify that callout device is not active */
3341 info
->port
.flags
|= ASYNC_NORMAL_ACTIVE
;
3345 if (tty
->termios
->c_cflag
& CLOCAL
)
3348 /* Wait for carrier detect and the line to become
3349 * free (i.e., not in use by the callout). While we are in
3350 * this loop, info->port.count is dropped by one, so that
3351 * close() knows when to free things. We restore it upon
3352 * exit, either normal or abnormal.
3356 add_wait_queue(&info
->port
.open_wait
, &wait
);
3358 if (debug_level
>= DEBUG_LEVEL_INFO
)
3359 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3360 __FILE__
,__LINE__
, tty
->driver
->name
, info
->port
.count
);
3362 spin_lock_irqsave(&info
->lock
, flags
);
3363 if (!tty_hung_up_p(filp
)) {
3367 spin_unlock_irqrestore(&info
->lock
, flags
);
3368 info
->port
.blocked_open
++;
3371 if ((tty
->termios
->c_cflag
& CBAUD
)) {
3372 spin_lock_irqsave(&info
->lock
,flags
);
3373 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3375 spin_unlock_irqrestore(&info
->lock
,flags
);
3378 set_current_state(TASK_INTERRUPTIBLE
);
3380 if (tty_hung_up_p(filp
) || !(info
->port
.flags
& ASYNC_INITIALIZED
)){
3381 retval
= (info
->port
.flags
& ASYNC_HUP_NOTIFY
) ?
3382 -EAGAIN
: -ERESTARTSYS
;
3386 spin_lock_irqsave(&info
->lock
,flags
);
3388 spin_unlock_irqrestore(&info
->lock
,flags
);
3390 if (!(info
->port
.flags
& ASYNC_CLOSING
) &&
3391 (do_clocal
|| (info
->serial_signals
& SerialSignal_DCD
)) ) {
3395 if (signal_pending(current
)) {
3396 retval
= -ERESTARTSYS
;
3400 if (debug_level
>= DEBUG_LEVEL_INFO
)
3401 printk("%s(%d):%s block_til_ready() count=%d\n",
3402 __FILE__
,__LINE__
, tty
->driver
->name
, info
->port
.count
);
3407 set_current_state(TASK_RUNNING
);
3408 remove_wait_queue(&info
->port
.open_wait
, &wait
);
3412 info
->port
.blocked_open
--;
3414 if (debug_level
>= DEBUG_LEVEL_INFO
)
3415 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3416 __FILE__
,__LINE__
, tty
->driver
->name
, info
->port
.count
);
3419 info
->port
.flags
|= ASYNC_NORMAL_ACTIVE
;
3424 static int alloc_dma_bufs(SLMP_INFO
*info
)
3426 unsigned short BuffersPerFrame
;
3427 unsigned short BufferCount
;
3429 // Force allocation to start at 64K boundary for each port.
3430 // This is necessary because *all* buffer descriptors for a port
3431 // *must* be in the same 64K block. All descriptors on a port
3432 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3433 // into the CBP register.
3434 info
->port_array
[0]->last_mem_alloc
= (SCA_MEM_SIZE
/4) * info
->port_num
;
3436 /* Calculate the number of DMA buffers necessary to hold the */
3437 /* largest allowable frame size. Note: If the max frame size is */
3438 /* not an even multiple of the DMA buffer size then we need to */
3439 /* round the buffer count per frame up one. */
3441 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/SCABUFSIZE
);
3442 if ( info
->max_frame_size
% SCABUFSIZE
)
3445 /* calculate total number of data buffers (SCABUFSIZE) possible
3446 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3447 * for the descriptor list (BUFFERLISTSIZE).
3449 BufferCount
= (SCA_MEM_SIZE
/4 - BUFFERLISTSIZE
)/SCABUFSIZE
;
3451 /* limit number of buffers to maximum amount of descriptors */
3452 if (BufferCount
> BUFFERLISTSIZE
/sizeof(SCADESC
))
3453 BufferCount
= BUFFERLISTSIZE
/sizeof(SCADESC
);
3455 /* use enough buffers to transmit one max size frame */
3456 info
->tx_buf_count
= BuffersPerFrame
+ 1;
3458 /* never use more than half the available buffers for transmit */
3459 if (info
->tx_buf_count
> (BufferCount
/2))
3460 info
->tx_buf_count
= BufferCount
/2;
3462 if (info
->tx_buf_count
> SCAMAXDESC
)
3463 info
->tx_buf_count
= SCAMAXDESC
;
3465 /* use remaining buffers for receive */
3466 info
->rx_buf_count
= BufferCount
- info
->tx_buf_count
;
3468 if (info
->rx_buf_count
> SCAMAXDESC
)
3469 info
->rx_buf_count
= SCAMAXDESC
;
3471 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3472 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3473 __FILE__
,__LINE__
, info
->device_name
,
3474 info
->tx_buf_count
,info
->rx_buf_count
);
3476 if ( alloc_buf_list( info
) < 0 ||
3477 alloc_frame_bufs(info
,
3479 info
->rx_buf_list_ex
,
3480 info
->rx_buf_count
) < 0 ||
3481 alloc_frame_bufs(info
,
3483 info
->tx_buf_list_ex
,
3484 info
->tx_buf_count
) < 0 ||
3485 alloc_tmp_rx_buf(info
) < 0 ) {
3486 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3487 __FILE__
,__LINE__
, info
->device_name
);
3491 rx_reset_buffers( info
);
3496 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3498 static int alloc_buf_list(SLMP_INFO
*info
)
3502 /* build list in adapter shared memory */
3503 info
->buffer_list
= info
->memory_base
+ info
->port_array
[0]->last_mem_alloc
;
3504 info
->buffer_list_phys
= info
->port_array
[0]->last_mem_alloc
;
3505 info
->port_array
[0]->last_mem_alloc
+= BUFFERLISTSIZE
;
3507 memset(info
->buffer_list
, 0, BUFFERLISTSIZE
);
3509 /* Save virtual address pointers to the receive and */
3510 /* transmit buffer lists. (Receive 1st). These pointers will */
3511 /* be used by the processor to access the lists. */
3512 info
->rx_buf_list
= (SCADESC
*)info
->buffer_list
;
3514 info
->tx_buf_list
= (SCADESC
*)info
->buffer_list
;
3515 info
->tx_buf_list
+= info
->rx_buf_count
;
3517 /* Build links for circular buffer entry lists (tx and rx)
3519 * Note: links are physical addresses read by the SCA device
3520 * to determine the next buffer entry to use.
3523 for ( i
= 0; i
< info
->rx_buf_count
; i
++ ) {
3524 /* calculate and store physical address of this buffer entry */
3525 info
->rx_buf_list_ex
[i
].phys_entry
=
3526 info
->buffer_list_phys
+ (i
* sizeof(SCABUFSIZE
));
3528 /* calculate and store physical address of */
3529 /* next entry in cirular list of entries */
3530 info
->rx_buf_list
[i
].next
= info
->buffer_list_phys
;
3531 if ( i
< info
->rx_buf_count
- 1 )
3532 info
->rx_buf_list
[i
].next
+= (i
+ 1) * sizeof(SCADESC
);
3534 info
->rx_buf_list
[i
].length
= SCABUFSIZE
;
3537 for ( i
= 0; i
< info
->tx_buf_count
; i
++ ) {
3538 /* calculate and store physical address of this buffer entry */
3539 info
->tx_buf_list_ex
[i
].phys_entry
= info
->buffer_list_phys
+
3540 ((info
->rx_buf_count
+ i
) * sizeof(SCADESC
));
3542 /* calculate and store physical address of */
3543 /* next entry in cirular list of entries */
3545 info
->tx_buf_list
[i
].next
= info
->buffer_list_phys
+
3546 info
->rx_buf_count
* sizeof(SCADESC
);
3548 if ( i
< info
->tx_buf_count
- 1 )
3549 info
->tx_buf_list
[i
].next
+= (i
+ 1) * sizeof(SCADESC
);
3555 /* Allocate the frame DMA buffers used by the specified buffer list.
3557 static int alloc_frame_bufs(SLMP_INFO
*info
, SCADESC
*buf_list
,SCADESC_EX
*buf_list_ex
,int count
)
3560 unsigned long phys_addr
;
3562 for ( i
= 0; i
< count
; i
++ ) {
3563 buf_list_ex
[i
].virt_addr
= info
->memory_base
+ info
->port_array
[0]->last_mem_alloc
;
3564 phys_addr
= info
->port_array
[0]->last_mem_alloc
;
3565 info
->port_array
[0]->last_mem_alloc
+= SCABUFSIZE
;
3567 buf_list
[i
].buf_ptr
= (unsigned short)phys_addr
;
3568 buf_list
[i
].buf_base
= (unsigned char)(phys_addr
>> 16);
3574 static void free_dma_bufs(SLMP_INFO
*info
)
3576 info
->buffer_list
= NULL
;
3577 info
->rx_buf_list
= NULL
;
3578 info
->tx_buf_list
= NULL
;
3581 /* allocate buffer large enough to hold max_frame_size.
3582 * This buffer is used to pass an assembled frame to the line discipline.
3584 static int alloc_tmp_rx_buf(SLMP_INFO
*info
)
3586 info
->tmp_rx_buf
= kmalloc(info
->max_frame_size
, GFP_KERNEL
);
3587 if (info
->tmp_rx_buf
== NULL
)
3592 static void free_tmp_rx_buf(SLMP_INFO
*info
)
3594 kfree(info
->tmp_rx_buf
);
3595 info
->tmp_rx_buf
= NULL
;
3598 static int claim_resources(SLMP_INFO
*info
)
3600 if (request_mem_region(info
->phys_memory_base
,SCA_MEM_SIZE
,"synclinkmp") == NULL
) {
3601 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3602 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3603 info
->init_error
= DiagStatus_AddressConflict
;
3607 info
->shared_mem_requested
= true;
3609 if (request_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128,"synclinkmp") == NULL
) {
3610 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3611 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
3612 info
->init_error
= DiagStatus_AddressConflict
;
3616 info
->lcr_mem_requested
= true;
3618 if (request_mem_region(info
->phys_sca_base
+ info
->sca_offset
,SCA_BASE_SIZE
,"synclinkmp") == NULL
) {
3619 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3620 __FILE__
,__LINE__
,info
->device_name
, info
->phys_sca_base
);
3621 info
->init_error
= DiagStatus_AddressConflict
;
3625 info
->sca_base_requested
= true;
3627 if (request_mem_region(info
->phys_statctrl_base
+ info
->statctrl_offset
,SCA_REG_SIZE
,"synclinkmp") == NULL
) {
3628 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3629 __FILE__
,__LINE__
,info
->device_name
, info
->phys_statctrl_base
);
3630 info
->init_error
= DiagStatus_AddressConflict
;
3634 info
->sca_statctrl_requested
= true;
3636 info
->memory_base
= ioremap_nocache(info
->phys_memory_base
,
3638 if (!info
->memory_base
) {
3639 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3640 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3641 info
->init_error
= DiagStatus_CantAssignPciResources
;
3645 info
->lcr_base
= ioremap_nocache(info
->phys_lcr_base
, PAGE_SIZE
);
3646 if (!info
->lcr_base
) {
3647 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3648 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
3649 info
->init_error
= DiagStatus_CantAssignPciResources
;
3652 info
->lcr_base
+= info
->lcr_offset
;
3654 info
->sca_base
= ioremap_nocache(info
->phys_sca_base
, PAGE_SIZE
);
3655 if (!info
->sca_base
) {
3656 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3657 __FILE__
,__LINE__
,info
->device_name
, info
->phys_sca_base
);
3658 info
->init_error
= DiagStatus_CantAssignPciResources
;
3661 info
->sca_base
+= info
->sca_offset
;
3663 info
->statctrl_base
= ioremap_nocache(info
->phys_statctrl_base
,
3665 if (!info
->statctrl_base
) {
3666 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3667 __FILE__
,__LINE__
,info
->device_name
, info
->phys_statctrl_base
);
3668 info
->init_error
= DiagStatus_CantAssignPciResources
;
3671 info
->statctrl_base
+= info
->statctrl_offset
;
3673 if ( !memory_test(info
) ) {
3674 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3675 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
3676 info
->init_error
= DiagStatus_MemoryError
;
3683 release_resources( info
);
3687 static void release_resources(SLMP_INFO
*info
)
3689 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3690 printk( "%s(%d):%s release_resources() entry\n",
3691 __FILE__
,__LINE__
,info
->device_name
);
3693 if ( info
->irq_requested
) {
3694 free_irq(info
->irq_level
, info
);
3695 info
->irq_requested
= false;
3698 if ( info
->shared_mem_requested
) {
3699 release_mem_region(info
->phys_memory_base
,SCA_MEM_SIZE
);
3700 info
->shared_mem_requested
= false;
3702 if ( info
->lcr_mem_requested
) {
3703 release_mem_region(info
->phys_lcr_base
+ info
->lcr_offset
,128);
3704 info
->lcr_mem_requested
= false;
3706 if ( info
->sca_base_requested
) {
3707 release_mem_region(info
->phys_sca_base
+ info
->sca_offset
,SCA_BASE_SIZE
);
3708 info
->sca_base_requested
= false;
3710 if ( info
->sca_statctrl_requested
) {
3711 release_mem_region(info
->phys_statctrl_base
+ info
->statctrl_offset
,SCA_REG_SIZE
);
3712 info
->sca_statctrl_requested
= false;
3715 if (info
->memory_base
){
3716 iounmap(info
->memory_base
);
3717 info
->memory_base
= NULL
;
3720 if (info
->sca_base
) {
3721 iounmap(info
->sca_base
- info
->sca_offset
);
3722 info
->sca_base
=NULL
;
3725 if (info
->statctrl_base
) {
3726 iounmap(info
->statctrl_base
- info
->statctrl_offset
);
3727 info
->statctrl_base
=NULL
;
3730 if (info
->lcr_base
){
3731 iounmap(info
->lcr_base
- info
->lcr_offset
);
3732 info
->lcr_base
= NULL
;
3735 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3736 printk( "%s(%d):%s release_resources() exit\n",
3737 __FILE__
,__LINE__
,info
->device_name
);
3740 /* Add the specified device instance data structure to the
3741 * global linked list of devices and increment the device count.
3743 static void add_device(SLMP_INFO
*info
)
3745 info
->next_device
= NULL
;
3746 info
->line
= synclinkmp_device_count
;
3747 sprintf(info
->device_name
,"ttySLM%dp%d",info
->adapter_num
,info
->port_num
);
3749 if (info
->line
< MAX_DEVICES
) {
3750 if (maxframe
[info
->line
])
3751 info
->max_frame_size
= maxframe
[info
->line
];
3754 synclinkmp_device_count
++;
3756 if ( !synclinkmp_device_list
)
3757 synclinkmp_device_list
= info
;
3759 SLMP_INFO
*current_dev
= synclinkmp_device_list
;
3760 while( current_dev
->next_device
)
3761 current_dev
= current_dev
->next_device
;
3762 current_dev
->next_device
= info
;
3765 if ( info
->max_frame_size
< 4096 )
3766 info
->max_frame_size
= 4096;
3767 else if ( info
->max_frame_size
> 65535 )
3768 info
->max_frame_size
= 65535;
3770 printk( "SyncLink MultiPort %s: "
3771 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3773 info
->phys_sca_base
,
3774 info
->phys_memory_base
,
3775 info
->phys_statctrl_base
,
3776 info
->phys_lcr_base
,
3778 info
->max_frame_size
);
3780 #if SYNCLINK_GENERIC_HDLC
3785 /* Allocate and initialize a device instance structure
3787 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3789 static SLMP_INFO
*alloc_dev(int adapter_num
, int port_num
, struct pci_dev
*pdev
)
3793 info
= kzalloc(sizeof(SLMP_INFO
),
3797 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3798 __FILE__
,__LINE__
, adapter_num
, port_num
);
3800 tty_port_init(&info
->port
);
3801 info
->magic
= MGSL_MAGIC
;
3802 INIT_WORK(&info
->task
, bh_handler
);
3803 info
->max_frame_size
= 4096;
3804 info
->port
.close_delay
= 5*HZ
/10;
3805 info
->port
.closing_wait
= 30*HZ
;
3806 init_waitqueue_head(&info
->status_event_wait_q
);
3807 init_waitqueue_head(&info
->event_wait_q
);
3808 spin_lock_init(&info
->netlock
);
3809 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
3810 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
3811 info
->adapter_num
= adapter_num
;
3812 info
->port_num
= port_num
;
3814 /* Copy configuration info to device instance data */
3815 info
->irq_level
= pdev
->irq
;
3816 info
->phys_lcr_base
= pci_resource_start(pdev
,0);
3817 info
->phys_sca_base
= pci_resource_start(pdev
,2);
3818 info
->phys_memory_base
= pci_resource_start(pdev
,3);
3819 info
->phys_statctrl_base
= pci_resource_start(pdev
,4);
3821 /* Because veremap only works on page boundaries we must map
3822 * a larger area than is actually implemented for the LCR
3823 * memory range. We map a full page starting at the page boundary.
3825 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
3826 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
3828 info
->sca_offset
= info
->phys_sca_base
& (PAGE_SIZE
-1);
3829 info
->phys_sca_base
&= ~(PAGE_SIZE
-1);
3831 info
->statctrl_offset
= info
->phys_statctrl_base
& (PAGE_SIZE
-1);
3832 info
->phys_statctrl_base
&= ~(PAGE_SIZE
-1);
3834 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
3835 info
->irq_flags
= IRQF_SHARED
;
3837 setup_timer(&info
->tx_timer
, tx_timeout
, (unsigned long)info
);
3838 setup_timer(&info
->status_timer
, status_timeout
,
3839 (unsigned long)info
);
3841 /* Store the PCI9050 misc control register value because a flaw
3842 * in the PCI9050 prevents LCR registers from being read if
3843 * BIOS assigns an LCR base address with bit 7 set.
3845 * Only the misc control register is accessed for which only
3846 * write access is needed, so set an initial value and change
3847 * bits to the device instance data as we write the value
3848 * to the actual misc control register.
3850 info
->misc_ctrl_value
= 0x087e4546;
3852 /* initial port state is unknown - if startup errors
3853 * occur, init_error will be set to indicate the
3854 * problem. Once the port is fully initialized,
3855 * this value will be set to 0 to indicate the
3856 * port is available.
3858 info
->init_error
= -1;
3864 static void device_init(int adapter_num
, struct pci_dev
*pdev
)
3866 SLMP_INFO
*port_array
[SCA_MAX_PORTS
];
3869 /* allocate device instances for up to SCA_MAX_PORTS devices */
3870 for ( port
= 0; port
< SCA_MAX_PORTS
; ++port
) {
3871 port_array
[port
] = alloc_dev(adapter_num
,port
,pdev
);
3872 if( port_array
[port
] == NULL
) {
3873 for ( --port
; port
>= 0; --port
)
3874 kfree(port_array
[port
]);
3879 /* give copy of port_array to all ports and add to device list */
3880 for ( port
= 0; port
< SCA_MAX_PORTS
; ++port
) {
3881 memcpy(port_array
[port
]->port_array
,port_array
,sizeof(port_array
));
3882 add_device( port_array
[port
] );
3883 spin_lock_init(&port_array
[port
]->lock
);
3886 /* Allocate and claim adapter resources */
3887 if ( !claim_resources(port_array
[0]) ) {
3889 alloc_dma_bufs(port_array
[0]);
3891 /* copy resource information from first port to others */
3892 for ( port
= 1; port
< SCA_MAX_PORTS
; ++port
) {
3893 port_array
[port
]->lock
= port_array
[0]->lock
;
3894 port_array
[port
]->irq_level
= port_array
[0]->irq_level
;
3895 port_array
[port
]->memory_base
= port_array
[0]->memory_base
;
3896 port_array
[port
]->sca_base
= port_array
[0]->sca_base
;
3897 port_array
[port
]->statctrl_base
= port_array
[0]->statctrl_base
;
3898 port_array
[port
]->lcr_base
= port_array
[0]->lcr_base
;
3899 alloc_dma_bufs(port_array
[port
]);
3902 if ( request_irq(port_array
[0]->irq_level
,
3903 synclinkmp_interrupt
,
3904 port_array
[0]->irq_flags
,
3905 port_array
[0]->device_name
,
3906 port_array
[0]) < 0 ) {
3907 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3909 port_array
[0]->device_name
,
3910 port_array
[0]->irq_level
);
3913 port_array
[0]->irq_requested
= true;
3914 adapter_test(port_array
[0]);
3919 static const struct tty_operations ops
= {
3923 .put_char
= put_char
,
3924 .flush_chars
= flush_chars
,
3925 .write_room
= write_room
,
3926 .chars_in_buffer
= chars_in_buffer
,
3927 .flush_buffer
= flush_buffer
,
3929 .throttle
= throttle
,
3930 .unthrottle
= unthrottle
,
3931 .send_xchar
= send_xchar
,
3932 .break_ctl
= set_break
,
3933 .wait_until_sent
= wait_until_sent
,
3934 .read_proc
= read_proc
,
3935 .set_termios
= set_termios
,
3937 .start
= tx_release
,
3939 .tiocmget
= tiocmget
,
3940 .tiocmset
= tiocmset
,
3943 static void synclinkmp_cleanup(void)
3949 printk("Unloading %s %s\n", driver_name
, driver_version
);
3951 if (serial_driver
) {
3952 if ((rc
= tty_unregister_driver(serial_driver
)))
3953 printk("%s(%d) failed to unregister tty driver err=%d\n",
3954 __FILE__
,__LINE__
,rc
);
3955 put_tty_driver(serial_driver
);
3959 info
= synclinkmp_device_list
;
3962 info
= info
->next_device
;
3965 /* release devices */
3966 info
= synclinkmp_device_list
;
3968 #if SYNCLINK_GENERIC_HDLC
3971 free_dma_bufs(info
);
3972 free_tmp_rx_buf(info
);
3973 if ( info
->port_num
== 0 ) {
3975 write_reg(info
, LPR
, 1); /* set low power mode */
3976 release_resources(info
);
3979 info
= info
->next_device
;
3983 pci_unregister_driver(&synclinkmp_pci_driver
);
3986 /* Driver initialization entry point.
3989 static int __init
synclinkmp_init(void)
3993 if (break_on_load
) {
3994 synclinkmp_get_text_ptr();
3998 printk("%s %s\n", driver_name
, driver_version
);
4000 if ((rc
= pci_register_driver(&synclinkmp_pci_driver
)) < 0) {
4001 printk("%s:failed to register PCI driver, error=%d\n",__FILE__
,rc
);
4005 serial_driver
= alloc_tty_driver(128);
4006 if (!serial_driver
) {
4011 /* Initialize the tty_driver structure */
4013 serial_driver
->owner
= THIS_MODULE
;
4014 serial_driver
->driver_name
= "synclinkmp";
4015 serial_driver
->name
= "ttySLM";
4016 serial_driver
->major
= ttymajor
;
4017 serial_driver
->minor_start
= 64;
4018 serial_driver
->type
= TTY_DRIVER_TYPE_SERIAL
;
4019 serial_driver
->subtype
= SERIAL_TYPE_NORMAL
;
4020 serial_driver
->init_termios
= tty_std_termios
;
4021 serial_driver
->init_termios
.c_cflag
=
4022 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4023 serial_driver
->init_termios
.c_ispeed
= 9600;
4024 serial_driver
->init_termios
.c_ospeed
= 9600;
4025 serial_driver
->flags
= TTY_DRIVER_REAL_RAW
;
4026 tty_set_operations(serial_driver
, &ops
);
4027 if ((rc
= tty_register_driver(serial_driver
)) < 0) {
4028 printk("%s(%d):Couldn't register serial driver\n",
4030 put_tty_driver(serial_driver
);
4031 serial_driver
= NULL
;
4035 printk("%s %s, tty major#%d\n",
4036 driver_name
, driver_version
,
4037 serial_driver
->major
);
4042 synclinkmp_cleanup();
4046 static void __exit
synclinkmp_exit(void)
4048 synclinkmp_cleanup();
4051 module_init(synclinkmp_init
);
4052 module_exit(synclinkmp_exit
);
4054 /* Set the port for internal loopback mode.
4055 * The TxCLK and RxCLK signals are generated from the BRG and
4056 * the TxD is looped back to the RxD internally.
4058 static void enable_loopback(SLMP_INFO
*info
, int enable
)
4061 /* MD2 (Mode Register 2)
4062 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4064 write_reg(info
, MD2
, (unsigned char)(read_reg(info
, MD2
) | (BIT1
+ BIT0
)));
4066 /* degate external TxC clock source */
4067 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4068 write_control_reg(info
);
4070 /* RXS/TXS (Rx/Tx clock source)
4071 * 07 Reserved, must be 0
4072 * 06..04 Clock Source, 100=BRG
4073 * 03..00 Clock Divisor, 0000=1
4075 write_reg(info
, RXS
, 0x40);
4076 write_reg(info
, TXS
, 0x40);
4079 /* MD2 (Mode Register 2)
4080 * 01..00 CNCT<1..0> Channel connection, 0=normal
4082 write_reg(info
, MD2
, (unsigned char)(read_reg(info
, MD2
) & ~(BIT1
+ BIT0
)));
4084 /* RXS/TXS (Rx/Tx clock source)
4085 * 07 Reserved, must be 0
4086 * 06..04 Clock Source, 000=RxC/TxC Pin
4087 * 03..00 Clock Divisor, 0000=1
4089 write_reg(info
, RXS
, 0x00);
4090 write_reg(info
, TXS
, 0x00);
4093 /* set LinkSpeed if available, otherwise default to 2Mbps */
4094 if (info
->params
.clock_speed
)
4095 set_rate(info
, info
->params
.clock_speed
);
4097 set_rate(info
, 3686400);
4100 /* Set the baud rate register to the desired speed
4102 * data_rate data rate of clock in bits per second
4103 * A data rate of 0 disables the AUX clock.
4105 static void set_rate( SLMP_INFO
*info
, u32 data_rate
)
4108 unsigned char BRValue
;
4111 /* fBRG = fCLK/(TMC * 2^BR)
4113 if (data_rate
!= 0) {
4114 Divisor
= 14745600/data_rate
;
4121 if (TMCValue
!= 1 && TMCValue
!= 2) {
4122 /* BRValue of 0 provides 50/50 duty cycle *only* when
4123 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4130 /* while TMCValue is too big for TMC register, divide
4131 * by 2 and increment BR exponent.
4133 for(; TMCValue
> 256 && BRValue
< 10; BRValue
++)
4136 write_reg(info
, TXS
,
4137 (unsigned char)((read_reg(info
, TXS
) & 0xf0) | BRValue
));
4138 write_reg(info
, RXS
,
4139 (unsigned char)((read_reg(info
, RXS
) & 0xf0) | BRValue
));
4140 write_reg(info
, TMC
, (unsigned char)TMCValue
);
4143 write_reg(info
, TXS
,0);
4144 write_reg(info
, RXS
,0);
4145 write_reg(info
, TMC
, 0);
4151 static void rx_stop(SLMP_INFO
*info
)
4153 if (debug_level
>= DEBUG_LEVEL_ISR
)
4154 printk("%s(%d):%s rx_stop()\n",
4155 __FILE__
,__LINE__
, info
->device_name
);
4157 write_reg(info
, CMD
, RXRESET
);
4159 info
->ie0_value
&= ~RXRDYE
;
4160 write_reg(info
, IE0
, info
->ie0_value
); /* disable Rx data interrupts */
4162 write_reg(info
, RXDMA
+ DSR
, 0); /* disable Rx DMA */
4163 write_reg(info
, RXDMA
+ DCMD
, SWABORT
); /* reset/init Rx DMA */
4164 write_reg(info
, RXDMA
+ DIR, 0); /* disable Rx DMA interrupts */
4166 info
->rx_enabled
= false;
4167 info
->rx_overflow
= false;
4170 /* enable the receiver
4172 static void rx_start(SLMP_INFO
*info
)
4176 if (debug_level
>= DEBUG_LEVEL_ISR
)
4177 printk("%s(%d):%s rx_start()\n",
4178 __FILE__
,__LINE__
, info
->device_name
);
4180 write_reg(info
, CMD
, RXRESET
);
4182 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
4183 /* HDLC, disabe IRQ on rxdata */
4184 info
->ie0_value
&= ~RXRDYE
;
4185 write_reg(info
, IE0
, info
->ie0_value
);
4187 /* Reset all Rx DMA buffers and program rx dma */
4188 write_reg(info
, RXDMA
+ DSR
, 0); /* disable Rx DMA */
4189 write_reg(info
, RXDMA
+ DCMD
, SWABORT
); /* reset/init Rx DMA */
4191 for (i
= 0; i
< info
->rx_buf_count
; i
++) {
4192 info
->rx_buf_list
[i
].status
= 0xff;
4194 // throttle to 4 shared memory writes at a time to prevent
4195 // hogging local bus (keep latency time for DMA requests low).
4197 read_status_reg(info
);
4199 info
->current_rx_buf
= 0;
4201 /* set current/1st descriptor address */
4202 write_reg16(info
, RXDMA
+ CDA
,
4203 info
->rx_buf_list_ex
[0].phys_entry
);
4205 /* set new last rx descriptor address */
4206 write_reg16(info
, RXDMA
+ EDA
,
4207 info
->rx_buf_list_ex
[info
->rx_buf_count
- 1].phys_entry
);
4209 /* set buffer length (shared by all rx dma data buffers) */
4210 write_reg16(info
, RXDMA
+ BFL
, SCABUFSIZE
);
4212 write_reg(info
, RXDMA
+ DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4213 write_reg(info
, RXDMA
+ DSR
, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4215 /* async, enable IRQ on rxdata */
4216 info
->ie0_value
|= RXRDYE
;
4217 write_reg(info
, IE0
, info
->ie0_value
);
4220 write_reg(info
, CMD
, RXENABLE
);
4222 info
->rx_overflow
= false;
4223 info
->rx_enabled
= true;
4226 /* Enable the transmitter and send a transmit frame if
4227 * one is loaded in the DMA buffers.
4229 static void tx_start(SLMP_INFO
*info
)
4231 if (debug_level
>= DEBUG_LEVEL_ISR
)
4232 printk("%s(%d):%s tx_start() tx_count=%d\n",
4233 __FILE__
,__LINE__
, info
->device_name
,info
->tx_count
);
4235 if (!info
->tx_enabled
) {
4236 write_reg(info
, CMD
, TXRESET
);
4237 write_reg(info
, CMD
, TXENABLE
);
4238 info
->tx_enabled
= true;
4241 if ( info
->tx_count
) {
4243 /* If auto RTS enabled and RTS is inactive, then assert */
4244 /* RTS and set a flag indicating that the driver should */
4245 /* negate RTS when the transmission completes. */
4247 info
->drop_rts_on_tx_done
= false;
4249 if (info
->params
.mode
!= MGSL_MODE_ASYNC
) {
4251 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
4252 get_signals( info
);
4253 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
4254 info
->serial_signals
|= SerialSignal_RTS
;
4255 set_signals( info
);
4256 info
->drop_rts_on_tx_done
= true;
4260 write_reg16(info
, TRC0
,
4261 (unsigned short)(((tx_negate_fifo_level
-1)<<8) + tx_active_fifo_level
));
4263 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
4264 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
4266 /* set TX CDA (current descriptor address) */
4267 write_reg16(info
, TXDMA
+ CDA
,
4268 info
->tx_buf_list_ex
[0].phys_entry
);
4270 /* set TX EDA (last descriptor address) */
4271 write_reg16(info
, TXDMA
+ EDA
,
4272 info
->tx_buf_list_ex
[info
->last_tx_buf
].phys_entry
);
4274 /* enable underrun IRQ */
4275 info
->ie1_value
&= ~IDLE
;
4276 info
->ie1_value
|= UDRN
;
4277 write_reg(info
, IE1
, info
->ie1_value
);
4278 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
));
4280 write_reg(info
, TXDMA
+ DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4281 write_reg(info
, TXDMA
+ DSR
, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4283 mod_timer(&info
->tx_timer
, jiffies
+
4284 msecs_to_jiffies(5000));
4288 /* async, enable IRQ on txdata */
4289 info
->ie0_value
|= TXRDYE
;
4290 write_reg(info
, IE0
, info
->ie0_value
);
4293 info
->tx_active
= true;
4297 /* stop the transmitter and DMA
4299 static void tx_stop( SLMP_INFO
*info
)
4301 if (debug_level
>= DEBUG_LEVEL_ISR
)
4302 printk("%s(%d):%s tx_stop()\n",
4303 __FILE__
,__LINE__
, info
->device_name
);
4305 del_timer(&info
->tx_timer
);
4307 write_reg(info
, TXDMA
+ DSR
, 0); /* disable DMA channel */
4308 write_reg(info
, TXDMA
+ DCMD
, SWABORT
); /* reset/init DMA channel */
4310 write_reg(info
, CMD
, TXRESET
);
4312 info
->ie1_value
&= ~(UDRN
+ IDLE
);
4313 write_reg(info
, IE1
, info
->ie1_value
); /* disable tx status interrupts */
4314 write_reg(info
, SR1
, (unsigned char)(IDLE
+ UDRN
)); /* clear pending */
4316 info
->ie0_value
&= ~TXRDYE
;
4317 write_reg(info
, IE0
, info
->ie0_value
); /* disable tx data interrupts */
4319 info
->tx_enabled
= false;
4320 info
->tx_active
= false;
4323 /* Fill the transmit FIFO until the FIFO is full or
4324 * there is no more data to load.
4326 static void tx_load_fifo(SLMP_INFO
*info
)
4330 /* do nothing is now tx data available and no XON/XOFF pending */
4332 if ( !info
->tx_count
&& !info
->x_char
)
4335 /* load the Transmit FIFO until FIFOs full or all data sent */
4337 while( info
->tx_count
&& (read_reg(info
,SR0
) & BIT1
) ) {
4339 /* there is more space in the transmit FIFO and */
4340 /* there is more data in transmit buffer */
4342 if ( (info
->tx_count
> 1) && !info
->x_char
) {
4344 TwoBytes
[0] = info
->tx_buf
[info
->tx_get
++];
4345 if (info
->tx_get
>= info
->max_frame_size
)
4346 info
->tx_get
-= info
->max_frame_size
;
4347 TwoBytes
[1] = info
->tx_buf
[info
->tx_get
++];
4348 if (info
->tx_get
>= info
->max_frame_size
)
4349 info
->tx_get
-= info
->max_frame_size
;
4351 write_reg16(info
, TRB
, *((u16
*)TwoBytes
));
4353 info
->tx_count
-= 2;
4354 info
->icount
.tx
+= 2;
4356 /* only 1 byte left to transmit or 1 FIFO slot left */
4359 /* transmit pending high priority char */
4360 write_reg(info
, TRB
, info
->x_char
);
4363 write_reg(info
, TRB
, info
->tx_buf
[info
->tx_get
++]);
4364 if (info
->tx_get
>= info
->max_frame_size
)
4365 info
->tx_get
-= info
->max_frame_size
;
4373 /* Reset a port to a known state
4375 static void reset_port(SLMP_INFO
*info
)
4377 if (info
->sca_base
) {
4382 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
4385 /* disable all port interrupts */
4386 info
->ie0_value
= 0;
4387 info
->ie1_value
= 0;
4388 info
->ie2_value
= 0;
4389 write_reg(info
, IE0
, info
->ie0_value
);
4390 write_reg(info
, IE1
, info
->ie1_value
);
4391 write_reg(info
, IE2
, info
->ie2_value
);
4393 write_reg(info
, CMD
, CHRESET
);
4397 /* Reset all the ports to a known state.
4399 static void reset_adapter(SLMP_INFO
*info
)
4403 for ( i
=0; i
< SCA_MAX_PORTS
; ++i
) {
4404 if (info
->port_array
[i
])
4405 reset_port(info
->port_array
[i
]);
4409 /* Program port for asynchronous communications.
4411 static void async_mode(SLMP_INFO
*info
)
4414 unsigned char RegValue
;
4419 /* MD0, Mode Register 0
4421 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4422 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4423 * 03 Reserved, must be 0
4424 * 02 CRCCC, CRC Calculation, 0=disabled
4425 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4430 if (info
->params
.stop_bits
!= 1)
4432 write_reg(info
, MD0
, RegValue
);
4434 /* MD1, Mode Register 1
4436 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4437 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4438 * 03..02 RXCHR<1..0>, rx char size
4439 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4444 switch (info
->params
.data_bits
) {
4445 case 7: RegValue
|= BIT4
+ BIT2
; break;
4446 case 6: RegValue
|= BIT5
+ BIT3
; break;
4447 case 5: RegValue
|= BIT5
+ BIT4
+ BIT3
+ BIT2
; break;
4449 if (info
->params
.parity
!= ASYNC_PARITY_NONE
) {
4451 if (info
->params
.parity
== ASYNC_PARITY_ODD
)
4454 write_reg(info
, MD1
, RegValue
);
4456 /* MD2, Mode Register 2
4458 * 07..02 Reserved, must be 0
4459 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4464 if (info
->params
.loopback
)
4465 RegValue
|= (BIT1
+ BIT0
);
4466 write_reg(info
, MD2
, RegValue
);
4468 /* RXS, Receive clock source
4470 * 07 Reserved, must be 0
4471 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4472 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4475 write_reg(info
, RXS
, RegValue
);
4477 /* TXS, Transmit clock source
4479 * 07 Reserved, must be 0
4480 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4481 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4484 write_reg(info
, TXS
, RegValue
);
4488 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4490 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4491 write_control_reg(info
);
4495 /* RRC Receive Ready Control 0
4497 * 07..05 Reserved, must be 0
4498 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4500 write_reg(info
, RRC
, 0x00);
4502 /* TRC0 Transmit Ready Control 0
4504 * 07..05 Reserved, must be 0
4505 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4507 write_reg(info
, TRC0
, 0x10);
4509 /* TRC1 Transmit Ready Control 1
4511 * 07..05 Reserved, must be 0
4512 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4514 write_reg(info
, TRC1
, 0x1e);
4516 /* CTL, MSCI control register
4518 * 07..06 Reserved, set to 0
4519 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4520 * 04 IDLC, idle control, 0=mark 1=idle register
4521 * 03 BRK, break, 0=off 1 =on (async)
4522 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4523 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4524 * 00 RTS, RTS output control, 0=active 1=inactive
4529 if (!(info
->serial_signals
& SerialSignal_RTS
))
4531 write_reg(info
, CTL
, RegValue
);
4533 /* enable status interrupts */
4534 info
->ie0_value
|= TXINTE
+ RXINTE
;
4535 write_reg(info
, IE0
, info
->ie0_value
);
4537 /* enable break detect interrupt */
4538 info
->ie1_value
= BRKD
;
4539 write_reg(info
, IE1
, info
->ie1_value
);
4541 /* enable rx overrun interrupt */
4542 info
->ie2_value
= OVRN
;
4543 write_reg(info
, IE2
, info
->ie2_value
);
4545 set_rate( info
, info
->params
.data_rate
* 16 );
4548 /* Program the SCA for HDLC communications.
4550 static void hdlc_mode(SLMP_INFO
*info
)
4552 unsigned char RegValue
;
4555 // Can't use DPLL because SCA outputs recovered clock on RxC when
4556 // DPLL mode selected. This causes output contention with RxC receiver.
4557 // Use of DPLL would require external hardware to disable RxC receiver
4558 // when DPLL mode selected.
4559 info
->params
.flags
&= ~(HDLC_FLAG_TXC_DPLL
+ HDLC_FLAG_RXC_DPLL
);
4561 /* disable DMA interrupts */
4562 write_reg(info
, TXDMA
+ DIR, 0);
4563 write_reg(info
, RXDMA
+ DIR, 0);
4565 /* MD0, Mode Register 0
4567 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4568 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4569 * 03 Reserved, must be 0
4570 * 02 CRCCC, CRC Calculation, 1=enabled
4571 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4572 * 00 CRC0, CRC initial value, 1 = all 1s
4577 if (info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
4579 if (info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
4581 if (info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
4582 RegValue
|= BIT2
+ BIT1
;
4583 write_reg(info
, MD0
, RegValue
);
4585 /* MD1, Mode Register 1
4587 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4588 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4589 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4590 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4595 write_reg(info
, MD1
, RegValue
);
4597 /* MD2, Mode Register 2
4599 * 07 NRZFM, 0=NRZ, 1=FM
4600 * 06..05 CODE<1..0> Encoding, 00=NRZ
4601 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4602 * 02 Reserved, must be 0
4603 * 01..00 CNCT<1..0> Channel connection, 0=normal
4608 switch(info
->params
.encoding
) {
4609 case HDLC_ENCODING_NRZI
: RegValue
|= BIT5
; break;
4610 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT7
+ BIT5
; break; /* aka FM1 */
4611 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT7
+ BIT6
; break; /* aka FM0 */
4612 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT7
; break; /* aka Manchester */
4614 case HDLC_ENCODING_NRZB
: /* not supported */
4615 case HDLC_ENCODING_NRZI_MARK
: /* not supported */
4616 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: /* not supported */
4619 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
4622 } else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
4628 write_reg(info
, MD2
, RegValue
);
4631 /* RXS, Receive clock source
4633 * 07 Reserved, must be 0
4634 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4635 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4638 if (info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4640 if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4641 RegValue
|= BIT6
+ BIT5
;
4642 write_reg(info
, RXS
, RegValue
);
4644 /* TXS, Transmit clock source
4646 * 07 Reserved, must be 0
4647 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4648 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4651 if (info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4653 if (info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4654 RegValue
|= BIT6
+ BIT5
;
4655 write_reg(info
, TXS
, RegValue
);
4657 if (info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4658 set_rate(info
, info
->params
.clock_speed
* DpllDivisor
);
4660 set_rate(info
, info
->params
.clock_speed
);
4662 /* GPDATA (General Purpose I/O Data Register)
4664 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4666 if (info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4667 info
->port_array
[0]->ctrlreg_value
|= (BIT0
<< (info
->port_num
* 2));
4669 info
->port_array
[0]->ctrlreg_value
&= ~(BIT0
<< (info
->port_num
* 2));
4670 write_control_reg(info
);
4672 /* RRC Receive Ready Control 0
4674 * 07..05 Reserved, must be 0
4675 * 04..00 RRC<4..0> Rx FIFO trigger active
4677 write_reg(info
, RRC
, rx_active_fifo_level
);
4679 /* TRC0 Transmit Ready Control 0
4681 * 07..05 Reserved, must be 0
4682 * 04..00 TRC<4..0> Tx FIFO trigger active
4684 write_reg(info
, TRC0
, tx_active_fifo_level
);
4686 /* TRC1 Transmit Ready Control 1
4688 * 07..05 Reserved, must be 0
4689 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4691 write_reg(info
, TRC1
, (unsigned char)(tx_negate_fifo_level
- 1));
4693 /* DMR, DMA Mode Register
4695 * 07..05 Reserved, must be 0
4696 * 04 TMOD, Transfer Mode: 1=chained-block
4697 * 03 Reserved, must be 0
4698 * 02 NF, Number of Frames: 1=multi-frame
4699 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4700 * 00 Reserved, must be 0
4704 write_reg(info
, TXDMA
+ DMR
, 0x14);
4705 write_reg(info
, RXDMA
+ DMR
, 0x14);
4707 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4708 write_reg(info
, RXDMA
+ CPB
,
4709 (unsigned char)(info
->buffer_list_phys
>> 16));
4711 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4712 write_reg(info
, TXDMA
+ CPB
,
4713 (unsigned char)(info
->buffer_list_phys
>> 16));
4715 /* enable status interrupts. other code enables/disables
4716 * the individual sources for these two interrupt classes.
4718 info
->ie0_value
|= TXINTE
+ RXINTE
;
4719 write_reg(info
, IE0
, info
->ie0_value
);
4721 /* CTL, MSCI control register
4723 * 07..06 Reserved, set to 0
4724 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4725 * 04 IDLC, idle control, 0=mark 1=idle register
4726 * 03 BRK, break, 0=off 1 =on (async)
4727 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4728 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4729 * 00 RTS, RTS output control, 0=active 1=inactive
4734 if (!(info
->serial_signals
& SerialSignal_RTS
))
4736 write_reg(info
, CTL
, RegValue
);
4738 /* preamble not supported ! */
4744 set_rate(info
, info
->params
.clock_speed
);
4746 if (info
->params
.loopback
)
4747 enable_loopback(info
,1);
4750 /* Set the transmit HDLC idle mode
4752 static void tx_set_idle(SLMP_INFO
*info
)
4754 unsigned char RegValue
= 0xff;
4756 /* Map API idle mode to SCA register bits */
4757 switch(info
->idle_mode
) {
4758 case HDLC_TXIDLE_FLAGS
: RegValue
= 0x7e; break;
4759 case HDLC_TXIDLE_ALT_ZEROS_ONES
: RegValue
= 0xaa; break;
4760 case HDLC_TXIDLE_ZEROS
: RegValue
= 0x00; break;
4761 case HDLC_TXIDLE_ONES
: RegValue
= 0xff; break;
4762 case HDLC_TXIDLE_ALT_MARK_SPACE
: RegValue
= 0xaa; break;
4763 case HDLC_TXIDLE_SPACE
: RegValue
= 0x00; break;
4764 case HDLC_TXIDLE_MARK
: RegValue
= 0xff; break;
4767 write_reg(info
, IDL
, RegValue
);
4770 /* Query the adapter for the state of the V24 status (input) signals.
4772 static void get_signals(SLMP_INFO
*info
)
4774 u16 status
= read_reg(info
, SR3
);
4775 u16 gpstatus
= read_status_reg(info
);
4778 /* clear all serial signals except DTR and RTS */
4779 info
->serial_signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
4781 /* set serial signal bits to reflect MISR */
4783 if (!(status
& BIT3
))
4784 info
->serial_signals
|= SerialSignal_CTS
;
4786 if ( !(status
& BIT2
))
4787 info
->serial_signals
|= SerialSignal_DCD
;
4789 testbit
= BIT1
<< (info
->port_num
* 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4790 if (!(gpstatus
& testbit
))
4791 info
->serial_signals
|= SerialSignal_RI
;
4793 testbit
= BIT0
<< (info
->port_num
* 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4794 if (!(gpstatus
& testbit
))
4795 info
->serial_signals
|= SerialSignal_DSR
;
4798 /* Set the state of DTR and RTS based on contents of
4799 * serial_signals member of device context.
4801 static void set_signals(SLMP_INFO
*info
)
4803 unsigned char RegValue
;
4806 RegValue
= read_reg(info
, CTL
);
4807 if (info
->serial_signals
& SerialSignal_RTS
)
4811 write_reg(info
, CTL
, RegValue
);
4813 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4814 EnableBit
= BIT1
<< (info
->port_num
*2);
4815 if (info
->serial_signals
& SerialSignal_DTR
)
4816 info
->port_array
[0]->ctrlreg_value
&= ~EnableBit
;
4818 info
->port_array
[0]->ctrlreg_value
|= EnableBit
;
4819 write_control_reg(info
);
4822 /*******************/
4823 /* DMA Buffer Code */
4824 /*******************/
4826 /* Set the count for all receive buffers to SCABUFSIZE
4827 * and set the current buffer to the first buffer. This effectively
4828 * makes all buffers free and discards any data in buffers.
4830 static void rx_reset_buffers(SLMP_INFO
*info
)
4832 rx_free_frame_buffers(info
, 0, info
->rx_buf_count
- 1);
4835 /* Free the buffers used by a received frame
4837 * info pointer to device instance data
4838 * first index of 1st receive buffer of frame
4839 * last index of last receive buffer of frame
4841 static void rx_free_frame_buffers(SLMP_INFO
*info
, unsigned int first
, unsigned int last
)
4846 /* reset current buffer for reuse */
4847 info
->rx_buf_list
[first
].status
= 0xff;
4849 if (first
== last
) {
4851 /* set new last rx descriptor address */
4852 write_reg16(info
, RXDMA
+ EDA
, info
->rx_buf_list_ex
[first
].phys_entry
);
4856 if (first
== info
->rx_buf_count
)
4860 /* set current buffer to next buffer after last buffer of frame */
4861 info
->current_rx_buf
= first
;
4864 /* Return a received frame from the receive DMA buffers.
4865 * Only frames received without errors are returned.
4867 * Return Value: true if frame returned, otherwise false
4869 static bool rx_get_frame(SLMP_INFO
*info
)
4871 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
4872 unsigned short status
;
4873 unsigned int framesize
= 0;
4874 bool ReturnCode
= false;
4875 unsigned long flags
;
4876 struct tty_struct
*tty
= info
->port
.tty
;
4877 unsigned char addr_field
= 0xff;
4879 SCADESC_EX
*desc_ex
;
4882 /* assume no frame returned, set zero length */
4887 * current_rx_buf points to the 1st buffer of the next available
4888 * receive frame. To find the last buffer of the frame look for
4889 * a non-zero status field in the buffer entries. (The status
4890 * field is set by the 16C32 after completing a receive frame.
4892 StartIndex
= EndIndex
= info
->current_rx_buf
;
4895 desc
= &info
->rx_buf_list
[EndIndex
];
4896 desc_ex
= &info
->rx_buf_list_ex
[EndIndex
];
4898 if (desc
->status
== 0xff)
4899 goto Cleanup
; /* current desc still in use, no frames available */
4901 if (framesize
== 0 && info
->params
.addr_filter
!= 0xff)
4902 addr_field
= desc_ex
->virt_addr
[0];
4904 framesize
+= desc
->length
;
4906 /* Status != 0 means last buffer of frame */
4911 if (EndIndex
== info
->rx_buf_count
)
4914 if (EndIndex
== info
->current_rx_buf
) {
4915 /* all buffers have been 'used' but none mark */
4916 /* the end of a frame. Reset buffers and receiver. */
4917 if ( info
->rx_enabled
){
4918 spin_lock_irqsave(&info
->lock
,flags
);
4920 spin_unlock_irqrestore(&info
->lock
,flags
);
4927 /* check status of receive frame */
4929 /* frame status is byte stored after frame data
4931 * 7 EOM (end of msg), 1 = last buffer of frame
4932 * 6 Short Frame, 1 = short frame
4933 * 5 Abort, 1 = frame aborted
4934 * 4 Residue, 1 = last byte is partial
4935 * 3 Overrun, 1 = overrun occurred during frame reception
4936 * 2 CRC, 1 = CRC error detected
4939 status
= desc
->status
;
4941 /* ignore CRC bit if not using CRC (bit is undefined) */
4942 /* Note:CRC is not save to data buffer */
4943 if (info
->params
.crc_type
== HDLC_CRC_NONE
)
4946 if (framesize
== 0 ||
4947 (addr_field
!= 0xff && addr_field
!= info
->params
.addr_filter
)) {
4948 /* discard 0 byte frames, this seems to occur sometime
4949 * when remote is idling flags.
4951 rx_free_frame_buffers(info
, StartIndex
, EndIndex
);
4958 if (status
& (BIT6
+BIT5
+BIT3
+BIT2
)) {
4959 /* received frame has errors,
4960 * update counts and mark frame size as 0
4963 info
->icount
.rxshort
++;
4964 else if (status
& BIT5
)
4965 info
->icount
.rxabort
++;
4966 else if (status
& BIT3
)
4967 info
->icount
.rxover
++;
4969 info
->icount
.rxcrc
++;
4972 #if SYNCLINK_GENERIC_HDLC
4974 info
->netdev
->stats
.rx_errors
++;
4975 info
->netdev
->stats
.rx_frame_errors
++;
4980 if ( debug_level
>= DEBUG_LEVEL_BH
)
4981 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4982 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
4984 if ( debug_level
>= DEBUG_LEVEL_DATA
)
4985 trace_block(info
,info
->rx_buf_list_ex
[StartIndex
].virt_addr
,
4986 min_t(int, framesize
,SCABUFSIZE
),0);
4989 if (framesize
> info
->max_frame_size
)
4990 info
->icount
.rxlong
++;
4992 /* copy dma buffer(s) to contiguous intermediate buffer */
4993 int copy_count
= framesize
;
4994 int index
= StartIndex
;
4995 unsigned char *ptmp
= info
->tmp_rx_buf
;
4996 info
->tmp_rx_buf_count
= framesize
;
4998 info
->icount
.rxok
++;
5001 int partial_count
= min(copy_count
,SCABUFSIZE
);
5003 info
->rx_buf_list_ex
[index
].virt_addr
,
5005 ptmp
+= partial_count
;
5006 copy_count
-= partial_count
;
5008 if ( ++index
== info
->rx_buf_count
)
5012 #if SYNCLINK_GENERIC_HDLC
5014 hdlcdev_rx(info
,info
->tmp_rx_buf
,framesize
);
5017 ldisc_receive_buf(tty
,info
->tmp_rx_buf
,
5018 info
->flag_buf
, framesize
);
5021 /* Free the buffers used by this frame. */
5022 rx_free_frame_buffers( info
, StartIndex
, EndIndex
);
5027 if ( info
->rx_enabled
&& info
->rx_overflow
) {
5028 /* Receiver is enabled, but needs to restarted due to
5029 * rx buffer overflow. If buffers are empty, restart receiver.
5031 if (info
->rx_buf_list
[EndIndex
].status
== 0xff) {
5032 spin_lock_irqsave(&info
->lock
,flags
);
5034 spin_unlock_irqrestore(&info
->lock
,flags
);
5041 /* load the transmit DMA buffer with data
5043 static void tx_load_dma_buffer(SLMP_INFO
*info
, const char *buf
, unsigned int count
)
5045 unsigned short copy_count
;
5048 SCADESC_EX
*desc_ex
;
5050 if ( debug_level
>= DEBUG_LEVEL_DATA
)
5051 trace_block(info
,buf
, min_t(int, count
,SCABUFSIZE
), 1);
5053 /* Copy source buffer to one or more DMA buffers, starting with
5054 * the first transmit dma buffer.
5058 copy_count
= min_t(unsigned short,count
,SCABUFSIZE
);
5060 desc
= &info
->tx_buf_list
[i
];
5061 desc_ex
= &info
->tx_buf_list_ex
[i
];
5063 load_pci_memory(info
, desc_ex
->virt_addr
,buf
,copy_count
);
5065 desc
->length
= copy_count
;
5069 count
-= copy_count
;
5075 if (i
>= info
->tx_buf_count
)
5079 info
->tx_buf_list
[i
].status
= 0x81; /* set EOM and EOT status */
5080 info
->last_tx_buf
= ++i
;
5083 static bool register_test(SLMP_INFO
*info
)
5085 static unsigned char testval
[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5086 static unsigned int count
= ARRAY_SIZE(testval
);
5089 unsigned long flags
;
5091 spin_lock_irqsave(&info
->lock
,flags
);
5094 /* assume failure */
5095 info
->init_error
= DiagStatus_AddressFailure
;
5097 /* Write bit patterns to various registers but do it out of */
5098 /* sync, then read back and verify values. */
5100 for (i
= 0 ; i
< count
; i
++) {
5101 write_reg(info
, TMC
, testval
[i
]);
5102 write_reg(info
, IDL
, testval
[(i
+1)%count
]);
5103 write_reg(info
, SA0
, testval
[(i
+2)%count
]);
5104 write_reg(info
, SA1
, testval
[(i
+3)%count
]);
5106 if ( (read_reg(info
, TMC
) != testval
[i
]) ||
5107 (read_reg(info
, IDL
) != testval
[(i
+1)%count
]) ||
5108 (read_reg(info
, SA0
) != testval
[(i
+2)%count
]) ||
5109 (read_reg(info
, SA1
) != testval
[(i
+3)%count
]) )
5117 spin_unlock_irqrestore(&info
->lock
,flags
);
5122 static bool irq_test(SLMP_INFO
*info
)
5124 unsigned long timeout
;
5125 unsigned long flags
;
5127 unsigned char timer
= (info
->port_num
& 1) ? TIMER2
: TIMER0
;
5129 spin_lock_irqsave(&info
->lock
,flags
);
5132 /* assume failure */
5133 info
->init_error
= DiagStatus_IrqFailure
;
5134 info
->irq_occurred
= false;
5136 /* setup timer0 on SCA0 to interrupt */
5138 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5139 write_reg(info
, IER2
, (unsigned char)((info
->port_num
& 1) ? BIT6
: BIT4
));
5141 write_reg(info
, (unsigned char)(timer
+ TEPR
), 0); /* timer expand prescale */
5142 write_reg16(info
, (unsigned char)(timer
+ TCONR
), 1); /* timer constant */
5145 /* TMCS, Timer Control/Status Register
5147 * 07 CMF, Compare match flag (read only) 1=match
5148 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5149 * 05 Reserved, must be 0
5150 * 04 TME, Timer Enable
5151 * 03..00 Reserved, must be 0
5155 write_reg(info
, (unsigned char)(timer
+ TMCS
), 0x50);
5157 spin_unlock_irqrestore(&info
->lock
,flags
);
5160 while( timeout
-- && !info
->irq_occurred
) {
5161 msleep_interruptible(10);
5164 spin_lock_irqsave(&info
->lock
,flags
);
5166 spin_unlock_irqrestore(&info
->lock
,flags
);
5168 return info
->irq_occurred
;
5171 /* initialize individual SCA device (2 ports)
5173 static bool sca_init(SLMP_INFO
*info
)
5175 /* set wait controller to single mem partition (low), no wait states */
5176 write_reg(info
, PABR0
, 0); /* wait controller addr boundary 0 */
5177 write_reg(info
, PABR1
, 0); /* wait controller addr boundary 1 */
5178 write_reg(info
, WCRL
, 0); /* wait controller low range */
5179 write_reg(info
, WCRM
, 0); /* wait controller mid range */
5180 write_reg(info
, WCRH
, 0); /* wait controller high range */
5182 /* DPCR, DMA Priority Control
5184 * 07..05 Not used, must be 0
5185 * 04 BRC, bus release condition: 0=all transfers complete
5186 * 03 CCC, channel change condition: 0=every cycle
5187 * 02..00 PR<2..0>, priority 100=round robin
5191 write_reg(info
, DPCR
, dma_priority
);
5193 /* DMA Master Enable, BIT7: 1=enable all channels */
5194 write_reg(info
, DMER
, 0x80);
5196 /* enable all interrupt classes */
5197 write_reg(info
, IER0
, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5198 write_reg(info
, IER1
, 0xff); /* DMIB,DMIA (channels 0-3) */
5199 write_reg(info
, IER2
, 0xf0); /* TIRQ (timers 0-3) */
5201 /* ITCR, interrupt control register
5202 * 07 IPC, interrupt priority, 0=MSCI->DMA
5203 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5204 * 04 VOS, Vector Output, 0=unmodified vector
5205 * 03..00 Reserved, must be 0
5207 write_reg(info
, ITCR
, 0);
5212 /* initialize adapter hardware
5214 static bool init_adapter(SLMP_INFO
*info
)
5218 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5219 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5222 info
->misc_ctrl_value
|= BIT30
;
5223 *MiscCtrl
= info
->misc_ctrl_value
;
5226 * Force at least 170ns delay before clearing
5227 * reset bit. Each read from LCR takes at least
5228 * 30ns so 10 times for 300ns to be safe.
5231 readval
= *MiscCtrl
;
5233 info
->misc_ctrl_value
&= ~BIT30
;
5234 *MiscCtrl
= info
->misc_ctrl_value
;
5236 /* init control reg (all DTRs off, all clksel=input) */
5237 info
->ctrlreg_value
= 0xaa;
5238 write_control_reg(info
);
5241 volatile u32
*LCR1BRDR
= (u32
*)(info
->lcr_base
+ 0x2c);
5242 lcr1_brdr_value
&= ~(BIT5
+ BIT4
+ BIT3
);
5244 switch(read_ahead_count
)
5247 lcr1_brdr_value
|= BIT5
+ BIT4
+ BIT3
;
5250 lcr1_brdr_value
|= BIT5
+ BIT4
;
5253 lcr1_brdr_value
|= BIT5
+ BIT3
;
5256 lcr1_brdr_value
|= BIT5
;
5260 *LCR1BRDR
= lcr1_brdr_value
;
5261 *MiscCtrl
= misc_ctrl_value
;
5264 sca_init(info
->port_array
[0]);
5265 sca_init(info
->port_array
[2]);
5270 /* Loopback an HDLC frame to test the hardware
5271 * interrupt and DMA functions.
5273 static bool loopback_test(SLMP_INFO
*info
)
5275 #define TESTFRAMESIZE 20
5277 unsigned long timeout
;
5278 u16 count
= TESTFRAMESIZE
;
5279 unsigned char buf
[TESTFRAMESIZE
];
5281 unsigned long flags
;
5283 struct tty_struct
*oldtty
= info
->port
.tty
;
5284 u32 speed
= info
->params
.clock_speed
;
5286 info
->params
.clock_speed
= 3686400;
5287 info
->port
.tty
= NULL
;
5289 /* assume failure */
5290 info
->init_error
= DiagStatus_DmaFailure
;
5292 /* build and send transmit frame */
5293 for (count
= 0; count
< TESTFRAMESIZE
;++count
)
5294 buf
[count
] = (unsigned char)count
;
5296 memset(info
->tmp_rx_buf
,0,TESTFRAMESIZE
);
5298 /* program hardware for HDLC and enabled receiver */
5299 spin_lock_irqsave(&info
->lock
,flags
);
5301 enable_loopback(info
,1);
5303 info
->tx_count
= count
;
5304 tx_load_dma_buffer(info
,buf
,count
);
5306 spin_unlock_irqrestore(&info
->lock
,flags
);
5308 /* wait for receive complete */
5309 /* Set a timeout for waiting for interrupt. */
5310 for ( timeout
= 100; timeout
; --timeout
) {
5311 msleep_interruptible(10);
5313 if (rx_get_frame(info
)) {
5319 /* verify received frame length and contents */
5321 ( info
->tmp_rx_buf_count
!= count
||
5322 memcmp(buf
, info
->tmp_rx_buf
,count
))) {
5326 spin_lock_irqsave(&info
->lock
,flags
);
5327 reset_adapter(info
);
5328 spin_unlock_irqrestore(&info
->lock
,flags
);
5330 info
->params
.clock_speed
= speed
;
5331 info
->port
.tty
= oldtty
;
5336 /* Perform diagnostics on hardware
5338 static int adapter_test( SLMP_INFO
*info
)
5340 unsigned long flags
;
5341 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5342 printk( "%s(%d):Testing device %s\n",
5343 __FILE__
,__LINE__
,info
->device_name
);
5345 spin_lock_irqsave(&info
->lock
,flags
);
5347 spin_unlock_irqrestore(&info
->lock
,flags
);
5349 info
->port_array
[0]->port_count
= 0;
5351 if ( register_test(info
->port_array
[0]) &&
5352 register_test(info
->port_array
[1])) {
5354 info
->port_array
[0]->port_count
= 2;
5356 if ( register_test(info
->port_array
[2]) &&
5357 register_test(info
->port_array
[3]) )
5358 info
->port_array
[0]->port_count
+= 2;
5361 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5362 __FILE__
,__LINE__
,info
->device_name
, (unsigned long)(info
->phys_sca_base
));
5366 if ( !irq_test(info
->port_array
[0]) ||
5367 !irq_test(info
->port_array
[1]) ||
5368 (info
->port_count
== 4 && !irq_test(info
->port_array
[2])) ||
5369 (info
->port_count
== 4 && !irq_test(info
->port_array
[3]))) {
5370 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5371 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
5375 if (!loopback_test(info
->port_array
[0]) ||
5376 !loopback_test(info
->port_array
[1]) ||
5377 (info
->port_count
== 4 && !loopback_test(info
->port_array
[2])) ||
5378 (info
->port_count
== 4 && !loopback_test(info
->port_array
[3]))) {
5379 printk( "%s(%d):DMA test failure for device %s\n",
5380 __FILE__
,__LINE__
,info
->device_name
);
5384 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5385 printk( "%s(%d):device %s passed diagnostics\n",
5386 __FILE__
,__LINE__
,info
->device_name
);
5388 info
->port_array
[0]->init_error
= 0;
5389 info
->port_array
[1]->init_error
= 0;
5390 if ( info
->port_count
> 2 ) {
5391 info
->port_array
[2]->init_error
= 0;
5392 info
->port_array
[3]->init_error
= 0;
5398 /* Test the shared memory on a PCI adapter.
5400 static bool memory_test(SLMP_INFO
*info
)
5402 static unsigned long testval
[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5403 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5404 unsigned long count
= ARRAY_SIZE(testval
);
5406 unsigned long limit
= SCA_MEM_SIZE
/sizeof(unsigned long);
5407 unsigned long * addr
= (unsigned long *)info
->memory_base
;
5409 /* Test data lines with test pattern at one location. */
5411 for ( i
= 0 ; i
< count
; i
++ ) {
5413 if ( *addr
!= testval
[i
] )
5417 /* Test address lines with incrementing pattern over */
5418 /* entire address range. */
5420 for ( i
= 0 ; i
< limit
; i
++ ) {
5425 addr
= (unsigned long *)info
->memory_base
;
5427 for ( i
= 0 ; i
< limit
; i
++ ) {
5428 if ( *addr
!= i
* 4 )
5433 memset( info
->memory_base
, 0, SCA_MEM_SIZE
);
5437 /* Load data into PCI adapter shared memory.
5439 * The PCI9050 releases control of the local bus
5440 * after completing the current read or write operation.
5442 * While the PCI9050 write FIFO not empty, the
5443 * PCI9050 treats all of the writes as a single transaction
5444 * and does not release the bus. This causes DMA latency problems
5445 * at high speeds when copying large data blocks to the shared memory.
5447 * This function breaks a write into multiple transations by
5448 * interleaving a read which flushes the write FIFO and 'completes'
5449 * the write transation. This allows any pending DMA request to gain control
5450 * of the local bus in a timely fasion.
5452 static void load_pci_memory(SLMP_INFO
*info
, char* dest
, const char* src
, unsigned short count
)
5454 /* A load interval of 16 allows for 4 32-bit writes at */
5455 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5457 unsigned short interval
= count
/ sca_pci_load_interval
;
5460 for ( i
= 0 ; i
< interval
; i
++ )
5462 memcpy(dest
, src
, sca_pci_load_interval
);
5463 read_status_reg(info
);
5464 dest
+= sca_pci_load_interval
;
5465 src
+= sca_pci_load_interval
;
5468 memcpy(dest
, src
, count
% sca_pci_load_interval
);
5471 static void trace_block(SLMP_INFO
*info
,const char* data
, int count
, int xmit
)
5476 printk("%s tx data:\n",info
->device_name
);
5478 printk("%s rx data:\n",info
->device_name
);
5486 for(i
=0;i
<linecount
;i
++)
5487 printk("%02X ",(unsigned char)data
[i
]);
5490 for(i
=0;i
<linecount
;i
++) {
5491 if (data
[i
]>=040 && data
[i
]<=0176)
5492 printk("%c",data
[i
]);
5501 } /* end of trace_block() */
5503 /* called when HDLC frame times out
5504 * update stats and do tx completion processing
5506 static void tx_timeout(unsigned long context
)
5508 SLMP_INFO
*info
= (SLMP_INFO
*)context
;
5509 unsigned long flags
;
5511 if ( debug_level
>= DEBUG_LEVEL_INFO
)
5512 printk( "%s(%d):%s tx_timeout()\n",
5513 __FILE__
,__LINE__
,info
->device_name
);
5514 if(info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
5515 info
->icount
.txtimeout
++;
5517 spin_lock_irqsave(&info
->lock
,flags
);
5518 info
->tx_active
= false;
5519 info
->tx_count
= info
->tx_put
= info
->tx_get
= 0;
5521 spin_unlock_irqrestore(&info
->lock
,flags
);
5523 #if SYNCLINK_GENERIC_HDLC
5525 hdlcdev_tx_done(info
);
5531 /* called to periodically check the DSR/RI modem signal input status
5533 static void status_timeout(unsigned long context
)
5536 SLMP_INFO
*info
= (SLMP_INFO
*)context
;
5537 unsigned long flags
;
5538 unsigned char delta
;
5541 spin_lock_irqsave(&info
->lock
,flags
);
5543 spin_unlock_irqrestore(&info
->lock
,flags
);
5545 /* check for DSR/RI state change */
5547 delta
= info
->old_signals
^ info
->serial_signals
;
5548 info
->old_signals
= info
->serial_signals
;
5550 if (delta
& SerialSignal_DSR
)
5551 status
|= MISCSTATUS_DSR_LATCHED
|(info
->serial_signals
&SerialSignal_DSR
);
5553 if (delta
& SerialSignal_RI
)
5554 status
|= MISCSTATUS_RI_LATCHED
|(info
->serial_signals
&SerialSignal_RI
);
5556 if (delta
& SerialSignal_DCD
)
5557 status
|= MISCSTATUS_DCD_LATCHED
|(info
->serial_signals
&SerialSignal_DCD
);
5559 if (delta
& SerialSignal_CTS
)
5560 status
|= MISCSTATUS_CTS_LATCHED
|(info
->serial_signals
&SerialSignal_CTS
);
5563 isr_io_pin(info
,status
);
5565 mod_timer(&info
->status_timer
, jiffies
+ msecs_to_jiffies(10));
5569 /* Register Access Routines -
5570 * All registers are memory mapped
5572 #define CALC_REGADDR() \
5573 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5574 if (info->port_num > 1) \
5575 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5576 if ( info->port_num & 1) { \
5578 RegAddr += 0x40; /* DMA access */ \
5579 else if (Addr > 0x1f && Addr < 0x60) \
5580 RegAddr += 0x20; /* MSCI access */ \
5584 static unsigned char read_reg(SLMP_INFO
* info
, unsigned char Addr
)
5589 static void write_reg(SLMP_INFO
* info
, unsigned char Addr
, unsigned char Value
)
5595 static u16
read_reg16(SLMP_INFO
* info
, unsigned char Addr
)
5598 return *((u16
*)RegAddr
);
5601 static void write_reg16(SLMP_INFO
* info
, unsigned char Addr
, u16 Value
)
5604 *((u16
*)RegAddr
) = Value
;
5607 static unsigned char read_status_reg(SLMP_INFO
* info
)
5609 unsigned char *RegAddr
= (unsigned char *)info
->statctrl_base
;
5613 static void write_control_reg(SLMP_INFO
* info
)
5615 unsigned char *RegAddr
= (unsigned char *)info
->statctrl_base
;
5616 *RegAddr
= info
->port_array
[0]->ctrlreg_value
;
5620 static int __devinit
synclinkmp_init_one (struct pci_dev
*dev
,
5621 const struct pci_device_id
*ent
)
5623 if (pci_enable_device(dev
)) {
5624 printk("error enabling pci device %p\n", dev
);
5627 device_init( ++synclinkmp_adapter_count
, dev
);
5631 static void __devexit
synclinkmp_remove_one (struct pci_dev
*dev
)