drivers/clk/at91/clk-main.c

   1 /*
   2  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  */
  10
  11 #include <linux/clk-provider.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/clk/at91_pmc.h>
  14 #include <linux/delay.h>
  15 #include <linux/of.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/regmap.h>
  18
  19 #include "pmc.h"
  20
  21 #define SLOW_CLOCK_FREQ         32768
  22 #define MAINF_DIV               16
  23 #define MAINFRDY_TIMEOUT        (((MAINF_DIV + 1) * USEC_PER_SEC) / \
  24                                  SLOW_CLOCK_FREQ)
  25 #define MAINF_LOOP_MIN_WAIT     (USEC_PER_SEC / SLOW_CLOCK_FREQ)
  26 #define MAINF_LOOP_MAX_WAIT     MAINFRDY_TIMEOUT
  27
  28 #define MOR_KEY_MASK            (0xff << 16)
  29
  30 #define clk_main_parent_select(s)       (((s) & \
  31                                         (AT91_PMC_MOSCEN | \
  32                                         AT91_PMC_OSCBYPASS)) ? 1 : 0)
  33
  34 struct clk_main_osc {
  35         struct clk_hw hw;
  36         struct regmap *regmap;
  37 };
  38
  39 #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
  40
  41 struct clk_main_rc_osc {
  42         struct clk_hw hw;
  43         struct regmap *regmap;
  44         unsigned long frequency;
  45         unsigned long accuracy;
  46 };
  47
  48 #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
  49
  50 struct clk_rm9200_main {
  51         struct clk_hw hw;
  52         struct regmap *regmap;
  53 };
  54
  55 #define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw)
  56
  57 struct clk_sam9x5_main {
  58         struct clk_hw hw;
  59         struct regmap *regmap;
  60         u8 parent;
  61 };
  62
  63 #define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw)
  64
  65 static inline bool clk_main_osc_ready(struct regmap *regmap)
  66 {
  67         unsigned int status;
  68
  69         regmap_read(regmap, AT91_PMC_SR, &status);
  70
  71         return status & AT91_PMC_MOSCS;
  72 }
  73
  74 static int clk_main_osc_prepare(struct clk_hw *hw)
  75 {
  76         struct clk_main_osc *osc = to_clk_main_osc(hw);
  77         struct regmap *regmap = osc->regmap;
  78         u32 tmp;
  79
  80         regmap_read(regmap, AT91_CKGR_MOR, &tmp);
  81         tmp &= ~MOR_KEY_MASK;
  82
  83         if (tmp & AT91_PMC_OSCBYPASS)
  84                 return 0;
  85
  86         if (!(tmp & AT91_PMC_MOSCEN)) {
  87                 tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY;
  88                 regmap_write(regmap, AT91_CKGR_MOR, tmp);
  89         }
  90
  91         while (!clk_main_osc_ready(regmap))
  92                 cpu_relax();
  93
  94         return 0;
  95 }
  96
  97 static void clk_main_osc_unprepare(struct clk_hw *hw)
  98 {
  99         struct clk_main_osc *osc = to_clk_main_osc(hw);
 100         struct regmap *regmap = osc->regmap;
 101         u32 tmp;
 102
 103         regmap_read(regmap, AT91_CKGR_MOR, &tmp);
 104         if (tmp & AT91_PMC_OSCBYPASS)
 105                 return;
 106
 107         if (!(tmp & AT91_PMC_MOSCEN))
 108                 return;
 109
 110         tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN);
 111         regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
 112 }
 113
 114 static int clk_main_osc_is_prepared(struct clk_hw *hw)
 115 {
 116         struct clk_main_osc *osc = to_clk_main_osc(hw);
 117         struct regmap *regmap = osc->regmap;
 118         u32 tmp, status;
 119
 120         regmap_read(regmap, AT91_CKGR_MOR, &tmp);
 121         if (tmp & AT91_PMC_OSCBYPASS)
 122                 return 1;
 123
 124         regmap_read(regmap, AT91_PMC_SR, &status);
 125
 126         return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);
 127 }
 128
 129 static const struct clk_ops main_osc_ops = {
 130         .prepare = clk_main_osc_prepare,
 131         .unprepare = clk_main_osc_unprepare,
 132         .is_prepared = clk_main_osc_is_prepared,
 133 };
 134
 135 static struct clk_hw * __init
 136 at91_clk_register_main_osc(struct regmap *regmap,
 137                            const char *name,
 138                            const char *parent_name,
 139                            bool bypass)
 140 {
 141         struct clk_main_osc *osc;
 142         struct clk_init_data init;
 143         struct clk_hw *hw;
 144         int ret;
 145
 146         if (!name || !parent_name)
 147                 return ERR_PTR(-EINVAL);
 148
 149         osc = kzalloc(sizeof(*osc), GFP_KERNEL);
 150         if (!osc)
 151                 return ERR_PTR(-ENOMEM);
 152
 153         init.name = name;
 154         init.ops = &main_osc_ops;
 155         init.parent_names = &parent_name;
 156         init.num_parents = 1;
 157         init.flags = CLK_IGNORE_UNUSED;
 158
 159         osc->hw.init = &init;
 160         osc->regmap = regmap;
 161
 162         if (bypass)
 163                 regmap_update_bits(regmap,
 164                                    AT91_CKGR_MOR, MOR_KEY_MASK |
 165                                    AT91_PMC_OSCBYPASS,
 166                                    AT91_PMC_OSCBYPASS | AT91_PMC_KEY);
 167
 168         hw = &osc->hw;
 169         ret = clk_hw_register(NULL, &osc->hw);
 170         if (ret) {
 171                 kfree(osc);
 172                 hw = ERR_PTR(ret);
 173         }
 174
 175         return hw;
 176 }
 177
 178 static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
 179 {
 180         struct clk_hw *hw;
 181         const char *name = np->name;
 182         const char *parent_name;
 183         struct regmap *regmap;
 184         bool bypass;
 185
 186         of_property_read_string(np, "clock-output-names", &name);
 187         bypass = of_property_read_bool(np, "atmel,osc-bypass");
 188         parent_name = of_clk_get_parent_name(np, 0);
 189
 190         regmap = syscon_node_to_regmap(of_get_parent(np));
 191         if (IS_ERR(regmap))
 192                 return;
 193
 194         hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass);
 195         if (IS_ERR(hw))
 196                 return;
 197
 198         of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
 199 }
 200 CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc",
 201                of_at91rm9200_clk_main_osc_setup);
 202
 203 static bool clk_main_rc_osc_ready(struct regmap *regmap)
 204 {
 205         unsigned int status;
 206
 207         regmap_read(regmap, AT91_PMC_SR, &status);
 208
 209         return status & AT91_PMC_MOSCRCS;
 210 }
 211
 212 static int clk_main_rc_osc_prepare(struct clk_hw *hw)
 213 {
 214         struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
 215         struct regmap *regmap = osc->regmap;
 216         unsigned int mor;
 217
 218         regmap_read(regmap, AT91_CKGR_MOR, &mor);
 219
 220         if (!(mor & AT91_PMC_MOSCRCEN))
 221                 regmap_update_bits(regmap, AT91_CKGR_MOR,
 222                                    MOR_KEY_MASK | AT91_PMC_MOSCRCEN,
 223                                    AT91_PMC_MOSCRCEN | AT91_PMC_KEY);
 224
 225         while (!clk_main_rc_osc_ready(regmap))
 226                 cpu_relax();
 227
 228         return 0;
 229 }
 230
 231 static void clk_main_rc_osc_unprepare(struct clk_hw *hw)
 232 {
 233         struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
 234         struct regmap *regmap = osc->regmap;
 235         unsigned int mor;
 236
 237         regmap_read(regmap, AT91_CKGR_MOR, &mor);
 238
 239         if (!(mor & AT91_PMC_MOSCRCEN))
 240                 return;
 241
 242         regmap_update_bits(regmap, AT91_CKGR_MOR,
 243                            MOR_KEY_MASK | AT91_PMC_MOSCRCEN, AT91_PMC_KEY);
 244 }
 245
 246 static int clk_main_rc_osc_is_prepared(struct clk_hw *hw)
 247 {
 248         struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
 249         struct regmap *regmap = osc->regmap;
 250         unsigned int mor, status;
 251
 252         regmap_read(regmap, AT91_CKGR_MOR, &mor);
 253         regmap_read(regmap, AT91_PMC_SR, &status);
 254
 255         return (mor & AT91_PMC_MOSCRCEN) && (status & AT91_PMC_MOSCRCS);
 256 }
 257
 258 static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw,
 259                                                  unsigned long parent_rate)
 260 {
 261         struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
 262
 263         return osc->frequency;
 264 }
 265
 266 static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
 267                                                      unsigned long parent_acc)
 268 {
 269         struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
 270
 271         return osc->accuracy;
 272 }
 273
 274 static const struct clk_ops main_rc_osc_ops = {
 275         .prepare = clk_main_rc_osc_prepare,
 276         .unprepare = clk_main_rc_osc_unprepare,
 277         .is_prepared = clk_main_rc_osc_is_prepared,
 278         .recalc_rate = clk_main_rc_osc_recalc_rate,
 279         .recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
 280 };
 281
 282 static struct clk_hw * __init
 283 at91_clk_register_main_rc_osc(struct regmap *regmap,
 284                               const char *name,
 285                               u32 frequency, u32 accuracy)
 286 {
 287         struct clk_main_rc_osc *osc;
 288         struct clk_init_data init;
 289         struct clk_hw *hw;
 290         int ret;
 291
 292         if (!name || !frequency)
 293                 return ERR_PTR(-EINVAL);
 294
 295         osc = kzalloc(sizeof(*osc), GFP_KERNEL);
 296         if (!osc)
 297                 return ERR_PTR(-ENOMEM);
 298
 299         init.name = name;
 300         init.ops = &main_rc_osc_ops;
 301         init.parent_names = NULL;
 302         init.num_parents = 0;
 303         init.flags = CLK_IGNORE_UNUSED;
 304
 305         osc->hw.init = &init;
 306         osc->regmap = regmap;
 307         osc->frequency = frequency;
 308         osc->accuracy = accuracy;
 309
 310         hw = &osc->hw;
 311         ret = clk_hw_register(NULL, hw);
 312         if (ret) {
 313                 kfree(osc);
 314                 hw = ERR_PTR(ret);
 315         }
 316
 317         return hw;
 318 }
 319
 320 static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
 321 {
 322         struct clk_hw *hw;
 323         u32 frequency = 0;
 324         u32 accuracy = 0;
 325         const char *name = np->name;
 326         struct regmap *regmap;
 327
 328         of_property_read_string(np, "clock-output-names", &name);
 329         of_property_read_u32(np, "clock-frequency", &frequency);
 330         of_property_read_u32(np, "clock-accuracy", &accuracy);
 331
 332         regmap = syscon_node_to_regmap(of_get_parent(np));
 333         if (IS_ERR(regmap))
 334                 return;
 335
 336         hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy);
 337         if (IS_ERR(hw))
 338                 return;
 339
 340         of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
 341 }
 342 CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc",
 343                of_at91sam9x5_clk_main_rc_osc_setup);
 344
 345
 346 static int clk_main_probe_frequency(struct regmap *regmap)
 347 {
 348         unsigned long prep_time, timeout;
 349         unsigned int mcfr;
 350
 351         timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
 352         do {
 353                 prep_time = jiffies;
 354                 regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
 355                 if (mcfr & AT91_PMC_MAINRDY)
 356                         return 0;
 357                 if (system_state < SYSTEM_RUNNING)
 358                         udelay(MAINF_LOOP_MIN_WAIT);
 359                 else
 360                         usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
 361         } while (time_before(prep_time, timeout));
 362
 363         return -ETIMEDOUT;
 364 }
 365
 366 static unsigned long clk_main_recalc_rate(struct regmap *regmap,
 367                                           unsigned long parent_rate)
 368 {
 369         unsigned int mcfr;
 370
 371         if (parent_rate)
 372                 return parent_rate;
 373
 374         pr_warn("Main crystal frequency not set, using approximate value\n");
 375         regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
 376         if (!(mcfr & AT91_PMC_MAINRDY))
 377                 return 0;
 378
 379         return ((mcfr & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV;
 380 }
 381
 382 static int clk_rm9200_main_prepare(struct clk_hw *hw)
 383 {
 384         struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
 385
 386         return clk_main_probe_frequency(clkmain->regmap);
 387 }
 388
 389 static int clk_rm9200_main_is_prepared(struct clk_hw *hw)
 390 {
 391         struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
 392         unsigned int status;
 393
 394         regmap_read(clkmain->regmap, AT91_CKGR_MCFR, &status);
 395
 396         return status & AT91_PMC_MAINRDY ? 1 : 0;
 397 }
 398
 399 static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw,
 400                                                  unsigned long parent_rate)
 401 {
 402         struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
 403
 404         return clk_main_recalc_rate(clkmain->regmap, parent_rate);
 405 }
 406
 407 static const struct clk_ops rm9200_main_ops = {
 408         .prepare = clk_rm9200_main_prepare,
 409         .is_prepared = clk_rm9200_main_is_prepared,
 410         .recalc_rate = clk_rm9200_main_recalc_rate,
 411 };
 412
 413 static struct clk_hw * __init
 414 at91_clk_register_rm9200_main(struct regmap *regmap,
 415                               const char *name,
 416                               const char *parent_name)
 417 {
 418         struct clk_rm9200_main *clkmain;
 419         struct clk_init_data init;
 420         struct clk_hw *hw;
 421         int ret;
 422
 423         if (!name)
 424                 return ERR_PTR(-EINVAL);
 425
 426         if (!parent_name)
 427                 return ERR_PTR(-EINVAL);
 428
 429         clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
 430         if (!clkmain)
 431                 return ERR_PTR(-ENOMEM);
 432
 433         init.name = name;
 434         init.ops = &rm9200_main_ops;
 435         init.parent_names = &parent_name;
 436         init.num_parents = 1;
 437         init.flags = 0;
 438
 439         clkmain->hw.init = &init;
 440         clkmain->regmap = regmap;
 441
 442         hw = &clkmain->hw;
 443         ret = clk_hw_register(NULL, &clkmain->hw);
 444         if (ret) {
 445                 kfree(clkmain);
 446                 hw = ERR_PTR(ret);
 447         }
 448
 449         return hw;
 450 }
 451
 452 static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
 453 {
 454         struct clk_hw *hw;
 455         const char *parent_name;
 456         const char *name = np->name;
 457         struct regmap *regmap;
 458
 459         parent_name = of_clk_get_parent_name(np, 0);
 460         of_property_read_string(np, "clock-output-names", &name);
 461
 462         regmap = syscon_node_to_regmap(of_get_parent(np));
 463         if (IS_ERR(regmap))
 464                 return;
 465
 466         hw = at91_clk_register_rm9200_main(regmap, name, parent_name);
 467         if (IS_ERR(hw))
 468                 return;
 469
 470         of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
 471 }
 472 CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
 473                of_at91rm9200_clk_main_setup);
 474
 475 static inline bool clk_sam9x5_main_ready(struct regmap *regmap)
 476 {
 477         unsigned int status;
 478
 479         regmap_read(regmap, AT91_PMC_SR, &status);
 480
 481         return status & AT91_PMC_MOSCSELS ? 1 : 0;
 482 }
 483
 484 static int clk_sam9x5_main_prepare(struct clk_hw *hw)
 485 {
 486         struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
 487         struct regmap *regmap = clkmain->regmap;
 488
 489         while (!clk_sam9x5_main_ready(regmap))
 490                 cpu_relax();
 491
 492         return clk_main_probe_frequency(regmap);
 493 }
 494
 495 static int clk_sam9x5_main_is_prepared(struct clk_hw *hw)
 496 {
 497         struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
 498
 499         return clk_sam9x5_main_ready(clkmain->regmap);
 500 }
 501
 502 static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw,
 503                                                  unsigned long parent_rate)
 504 {
 505         struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
 506
 507         return clk_main_recalc_rate(clkmain->regmap, parent_rate);
 508 }
 509
 510 static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
 511 {
 512         struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
 513         struct regmap *regmap = clkmain->regmap;
 514         unsigned int tmp;
 515
 516         if (index > 1)
 517                 return -EINVAL;
 518
 519         regmap_read(regmap, AT91_CKGR_MOR, &tmp);
 520         tmp &= ~MOR_KEY_MASK;
 521
 522         if (index && !(tmp & AT91_PMC_MOSCSEL))
 523                 regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_MOSCSEL);
 524         else if (!index && (tmp & AT91_PMC_MOSCSEL))
 525                 regmap_write(regmap, AT91_CKGR_MOR, tmp & ~AT91_PMC_MOSCSEL);
 526
 527         while (!clk_sam9x5_main_ready(regmap))
 528                 cpu_relax();
 529
 530         return 0;
 531 }
 532
 533 static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
 534 {
 535         struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
 536         unsigned int status;
 537
 538         regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
 539
 540         return clk_main_parent_select(status);
 541 }
 542
 543 static const struct clk_ops sam9x5_main_ops = {
 544         .prepare = clk_sam9x5_main_prepare,
 545         .is_prepared = clk_sam9x5_main_is_prepared,
 546         .recalc_rate = clk_sam9x5_main_recalc_rate,
 547         .set_parent = clk_sam9x5_main_set_parent,
 548         .get_parent = clk_sam9x5_main_get_parent,
 549 };
 550
 551 static struct clk_hw * __init
 552 at91_clk_register_sam9x5_main(struct regmap *regmap,
 553                               const char *name,
 554                               const char **parent_names,
 555                               int num_parents)
 556 {
 557         struct clk_sam9x5_main *clkmain;
 558         struct clk_init_data init;
 559         unsigned int status;
 560         struct clk_hw *hw;
 561         int ret;
 562
 563         if (!name)
 564                 return ERR_PTR(-EINVAL);
 565
 566         if (!parent_names || !num_parents)
 567                 return ERR_PTR(-EINVAL);
 568
 569         clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
 570         if (!clkmain)
 571                 return ERR_PTR(-ENOMEM);
 572
 573         init.name = name;
 574         init.ops = &sam9x5_main_ops;
 575         init.parent_names = parent_names;
 576         init.num_parents = num_parents;
 577         init.flags = CLK_SET_PARENT_GATE;
 578
 579         clkmain->hw.init = &init;
 580         clkmain->regmap = regmap;
 581         regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
 582         clkmain->parent = clk_main_parent_select(status);
 583
 584         hw = &clkmain->hw;
 585         ret = clk_hw_register(NULL, &clkmain->hw);
 586         if (ret) {
 587                 kfree(clkmain);
 588                 hw = ERR_PTR(ret);
 589         }
 590
 591         return hw;
 592 }
 593
 594 static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
 595 {
 596         struct clk_hw *hw;
 597         const char *parent_names[2];
 598         unsigned int num_parents;
 599         const char *name = np->name;
 600         struct regmap *regmap;
 601
 602         num_parents = of_clk_get_parent_count(np);
 603         if (num_parents == 0 || num_parents > 2)
 604                 return;
 605
 606         of_clk_parent_fill(np, parent_names, num_parents);
 607         regmap = syscon_node_to_regmap(of_get_parent(np));
 608         if (IS_ERR(regmap))
 609                 return;
 610
 611         of_property_read_string(np, "clock-output-names", &name);
 612
 613         hw = at91_clk_register_sam9x5_main(regmap, name, parent_names,
 614                                             num_parents);
 615         if (IS_ERR(hw))
 616                 return;
 617
 618         of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
 619 }
 620 CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main",
 621                of_at91sam9x5_clk_main_setup);