2 * Copyright (C) 2010,2015 Broadcom
3 * Copyright (C) 2012 Stephen Warren
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
18 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
20 * The clock tree on the 2835 has several levels. There's a root
21 * oscillator running at 19.2Mhz. After the oscillator there are 5
22 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
23 * and "HDMI displays". Those 5 PLLs each can divide their output to
24 * produce up to 4 channels. Finally, there is the level of clocks to
25 * be consumed by other hardware components (like "H264" or "HDMI
26 * state machine"), which divide off of some subset of the PLL
29 * All of the clocks in the tree are exposed in the DT, because the DT
30 * may want to make assignments of the final layer of clocks to the
31 * PLL channels, and some components of the hardware will actually
32 * skip layers of the tree (for example, the pixel clock comes
33 * directly from the PLLH PIX channel without using a CM_*CTL clock
37 #include <linux/clk-provider.h>
38 #include <linux/clkdev.h>
39 #include <linux/clk/bcm2835.h>
40 #include <linux/debugfs.h>
41 #include <linux/module.h>
43 #include <linux/platform_device.h>
44 #include <linux/slab.h>
45 #include <dt-bindings/clock/bcm2835.h>
47 #define CM_PASSWORD 0x5a000000
49 #define CM_GNRICCTL 0x000
50 #define CM_GNRICDIV 0x004
51 # define CM_DIV_FRAC_BITS 12
52 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
54 #define CM_VPUCTL 0x008
55 #define CM_VPUDIV 0x00c
56 #define CM_SYSCTL 0x010
57 #define CM_SYSDIV 0x014
58 #define CM_PERIACTL 0x018
59 #define CM_PERIADIV 0x01c
60 #define CM_PERIICTL 0x020
61 #define CM_PERIIDIV 0x024
62 #define CM_H264CTL 0x028
63 #define CM_H264DIV 0x02c
64 #define CM_ISPCTL 0x030
65 #define CM_ISPDIV 0x034
66 #define CM_V3DCTL 0x038
67 #define CM_V3DDIV 0x03c
68 #define CM_CAM0CTL 0x040
69 #define CM_CAM0DIV 0x044
70 #define CM_CAM1CTL 0x048
71 #define CM_CAM1DIV 0x04c
72 #define CM_CCP2CTL 0x050
73 #define CM_CCP2DIV 0x054
74 #define CM_DSI0ECTL 0x058
75 #define CM_DSI0EDIV 0x05c
76 #define CM_DSI0PCTL 0x060
77 #define CM_DSI0PDIV 0x064
78 #define CM_DPICTL 0x068
79 #define CM_DPIDIV 0x06c
80 #define CM_GP0CTL 0x070
81 #define CM_GP0DIV 0x074
82 #define CM_GP1CTL 0x078
83 #define CM_GP1DIV 0x07c
84 #define CM_GP2CTL 0x080
85 #define CM_GP2DIV 0x084
86 #define CM_HSMCTL 0x088
87 #define CM_HSMDIV 0x08c
88 #define CM_OTPCTL 0x090
89 #define CM_OTPDIV 0x094
90 #define CM_PCMCTL 0x098
91 #define CM_PCMDIV 0x09c
92 #define CM_PWMCTL 0x0a0
93 #define CM_PWMDIV 0x0a4
94 #define CM_SLIMCTL 0x0a8
95 #define CM_SLIMDIV 0x0ac
96 #define CM_SMICTL 0x0b0
97 #define CM_SMIDIV 0x0b4
98 /* no definition for 0x0b8 and 0x0bc */
99 #define CM_TCNTCTL 0x0c0
100 #define CM_TCNTDIV 0x0c4
101 #define CM_TECCTL 0x0c8
102 #define CM_TECDIV 0x0cc
103 #define CM_TD0CTL 0x0d0
104 #define CM_TD0DIV 0x0d4
105 #define CM_TD1CTL 0x0d8
106 #define CM_TD1DIV 0x0dc
107 #define CM_TSENSCTL 0x0e0
108 #define CM_TSENSDIV 0x0e4
109 #define CM_TIMERCTL 0x0e8
110 #define CM_TIMERDIV 0x0ec
111 #define CM_UARTCTL 0x0f0
112 #define CM_UARTDIV 0x0f4
113 #define CM_VECCTL 0x0f8
114 #define CM_VECDIV 0x0fc
115 #define CM_PULSECTL 0x190
116 #define CM_PULSEDIV 0x194
117 #define CM_SDCCTL 0x1a8
118 #define CM_SDCDIV 0x1ac
119 #define CM_ARMCTL 0x1b0
120 #define CM_AVEOCTL 0x1b8
121 #define CM_AVEODIV 0x1bc
122 #define CM_EMMCCTL 0x1c0
123 #define CM_EMMCDIV 0x1c4
125 /* General bits for the CM_*CTL regs */
126 # define CM_ENABLE BIT(4)
127 # define CM_KILL BIT(5)
128 # define CM_GATE_BIT 6
129 # define CM_GATE BIT(CM_GATE_BIT)
130 # define CM_BUSY BIT(7)
131 # define CM_BUSYD BIT(8)
132 # define CM_FRAC BIT(9)
133 # define CM_SRC_SHIFT 0
134 # define CM_SRC_BITS 4
135 # define CM_SRC_MASK 0xf
136 # define CM_SRC_GND 0
137 # define CM_SRC_OSC 1
138 # define CM_SRC_TESTDEBUG0 2
139 # define CM_SRC_TESTDEBUG1 3
140 # define CM_SRC_PLLA_CORE 4
141 # define CM_SRC_PLLA_PER 4
142 # define CM_SRC_PLLC_CORE0 5
143 # define CM_SRC_PLLC_PER 5
144 # define CM_SRC_PLLC_CORE1 8
145 # define CM_SRC_PLLD_CORE 6
146 # define CM_SRC_PLLD_PER 6
147 # define CM_SRC_PLLH_AUX 7
148 # define CM_SRC_PLLC_CORE1 8
149 # define CM_SRC_PLLC_CORE2 9
151 #define CM_OSCCOUNT 0x100
153 #define CM_PLLA 0x104
154 # define CM_PLL_ANARST BIT(8)
155 # define CM_PLLA_HOLDPER BIT(7)
156 # define CM_PLLA_LOADPER BIT(6)
157 # define CM_PLLA_HOLDCORE BIT(5)
158 # define CM_PLLA_LOADCORE BIT(4)
159 # define CM_PLLA_HOLDCCP2 BIT(3)
160 # define CM_PLLA_LOADCCP2 BIT(2)
161 # define CM_PLLA_HOLDDSI0 BIT(1)
162 # define CM_PLLA_LOADDSI0 BIT(0)
164 #define CM_PLLC 0x108
165 # define CM_PLLC_HOLDPER BIT(7)
166 # define CM_PLLC_LOADPER BIT(6)
167 # define CM_PLLC_HOLDCORE2 BIT(5)
168 # define CM_PLLC_LOADCORE2 BIT(4)
169 # define CM_PLLC_HOLDCORE1 BIT(3)
170 # define CM_PLLC_LOADCORE1 BIT(2)
171 # define CM_PLLC_HOLDCORE0 BIT(1)
172 # define CM_PLLC_LOADCORE0 BIT(0)
174 #define CM_PLLD 0x10c
175 # define CM_PLLD_HOLDPER BIT(7)
176 # define CM_PLLD_LOADPER BIT(6)
177 # define CM_PLLD_HOLDCORE BIT(5)
178 # define CM_PLLD_LOADCORE BIT(4)
179 # define CM_PLLD_HOLDDSI1 BIT(3)
180 # define CM_PLLD_LOADDSI1 BIT(2)
181 # define CM_PLLD_HOLDDSI0 BIT(1)
182 # define CM_PLLD_LOADDSI0 BIT(0)
184 #define CM_PLLH 0x110
185 # define CM_PLLH_LOADRCAL BIT(2)
186 # define CM_PLLH_LOADAUX BIT(1)
187 # define CM_PLLH_LOADPIX BIT(0)
189 #define CM_LOCK 0x114
190 # define CM_LOCK_FLOCKH BIT(12)
191 # define CM_LOCK_FLOCKD BIT(11)
192 # define CM_LOCK_FLOCKC BIT(10)
193 # define CM_LOCK_FLOCKB BIT(9)
194 # define CM_LOCK_FLOCKA BIT(8)
196 #define CM_EVENT 0x118
197 #define CM_DSI1ECTL 0x158
198 #define CM_DSI1EDIV 0x15c
199 #define CM_DSI1PCTL 0x160
200 #define CM_DSI1PDIV 0x164
201 #define CM_DFTCTL 0x168
202 #define CM_DFTDIV 0x16c
204 #define CM_PLLB 0x170
205 # define CM_PLLB_HOLDARM BIT(1)
206 # define CM_PLLB_LOADARM BIT(0)
208 #define A2W_PLLA_CTRL 0x1100
209 #define A2W_PLLC_CTRL 0x1120
210 #define A2W_PLLD_CTRL 0x1140
211 #define A2W_PLLH_CTRL 0x1160
212 #define A2W_PLLB_CTRL 0x11e0
213 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
214 # define A2W_PLL_CTRL_PWRDN BIT(16)
215 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000
216 # define A2W_PLL_CTRL_PDIV_SHIFT 12
217 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
218 # define A2W_PLL_CTRL_NDIV_SHIFT 0
220 #define A2W_PLLA_ANA0 0x1010
221 #define A2W_PLLC_ANA0 0x1030
222 #define A2W_PLLD_ANA0 0x1050
223 #define A2W_PLLH_ANA0 0x1070
224 #define A2W_PLLB_ANA0 0x10f0
226 #define A2W_PLL_KA_SHIFT 7
227 #define A2W_PLL_KA_MASK GENMASK(9, 7)
228 #define A2W_PLL_KI_SHIFT 19
229 #define A2W_PLL_KI_MASK GENMASK(21, 19)
230 #define A2W_PLL_KP_SHIFT 15
231 #define A2W_PLL_KP_MASK GENMASK(18, 15)
233 #define A2W_PLLH_KA_SHIFT 19
234 #define A2W_PLLH_KA_MASK GENMASK(21, 19)
235 #define A2W_PLLH_KI_LOW_SHIFT 22
236 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
237 #define A2W_PLLH_KI_HIGH_SHIFT 0
238 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
239 #define A2W_PLLH_KP_SHIFT 1
240 #define A2W_PLLH_KP_MASK GENMASK(4, 1)
242 #define A2W_XOSC_CTRL 0x1190
243 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
244 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
245 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
246 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
247 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
248 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
249 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
250 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
252 #define A2W_PLLA_FRAC 0x1200
253 #define A2W_PLLC_FRAC 0x1220
254 #define A2W_PLLD_FRAC 0x1240
255 #define A2W_PLLH_FRAC 0x1260
256 #define A2W_PLLB_FRAC 0x12e0
257 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
258 # define A2W_PLL_FRAC_BITS 20
260 #define A2W_PLL_CHANNEL_DISABLE BIT(8)
261 #define A2W_PLL_DIV_BITS 8
262 #define A2W_PLL_DIV_SHIFT 0
264 #define A2W_PLLA_DSI0 0x1300
265 #define A2W_PLLA_CORE 0x1400
266 #define A2W_PLLA_PER 0x1500
267 #define A2W_PLLA_CCP2 0x1600
269 #define A2W_PLLC_CORE2 0x1320
270 #define A2W_PLLC_CORE1 0x1420
271 #define A2W_PLLC_PER 0x1520
272 #define A2W_PLLC_CORE0 0x1620
274 #define A2W_PLLD_DSI0 0x1340
275 #define A2W_PLLD_CORE 0x1440
276 #define A2W_PLLD_PER 0x1540
277 #define A2W_PLLD_DSI1 0x1640
279 #define A2W_PLLH_AUX 0x1360
280 #define A2W_PLLH_RCAL 0x1460
281 #define A2W_PLLH_PIX 0x1560
282 #define A2W_PLLH_STS 0x1660
284 #define A2W_PLLH_CTRLR 0x1960
285 #define A2W_PLLH_FRACR 0x1a60
286 #define A2W_PLLH_AUXR 0x1b60
287 #define A2W_PLLH_RCALR 0x1c60
288 #define A2W_PLLH_PIXR 0x1d60
289 #define A2W_PLLH_STSR 0x1e60
291 #define A2W_PLLB_ARM 0x13e0
292 #define A2W_PLLB_SP0 0x14e0
293 #define A2W_PLLB_SP1 0x15e0
294 #define A2W_PLLB_SP2 0x16e0
296 #define LOCK_TIMEOUT_NS 100000000
297 #define BCM2835_MAX_FB_RATE 1750000000u
299 struct bcm2835_cprman
{
302 spinlock_t regs_lock
; /* spinlock for all clocks */
303 const char *osc_name
;
305 struct clk_onecell_data onecell
;
309 static inline void cprman_write(struct bcm2835_cprman
*cprman
, u32 reg
, u32 val
)
311 writel(CM_PASSWORD
| val
, cprman
->regs
+ reg
);
314 static inline u32
cprman_read(struct bcm2835_cprman
*cprman
, u32 reg
)
316 return readl(cprman
->regs
+ reg
);
319 static int bcm2835_debugfs_regset(struct bcm2835_cprman
*cprman
, u32 base
,
320 struct debugfs_reg32
*regs
, size_t nregs
,
321 struct dentry
*dentry
)
323 struct dentry
*regdump
;
324 struct debugfs_regset32
*regset
;
326 regset
= devm_kzalloc(cprman
->dev
, sizeof(*regset
), GFP_KERNEL
);
331 regset
->nregs
= nregs
;
332 regset
->base
= cprman
->regs
+ base
;
334 regdump
= debugfs_create_regset32("regdump", S_IRUGO
, dentry
,
337 return regdump
? 0 : -ENOMEM
;
341 * These are fixed clocks. They're probably not all root clocks and it may
342 * be possible to turn them on and off but until this is mapped out better
343 * it's the only way they can be used.
345 void __init
bcm2835_init_clocks(void)
350 clk
= clk_register_fixed_rate(NULL
, "apb_pclk", NULL
, 0, 126000000);
352 pr_err("apb_pclk not registered\n");
354 clk
= clk_register_fixed_rate(NULL
, "uart0_pclk", NULL
, 0, 3000000);
356 pr_err("uart0_pclk not registered\n");
357 ret
= clk_register_clkdev(clk
, NULL
, "20201000.uart");
359 pr_err("uart0_pclk alias not registered\n");
361 clk
= clk_register_fixed_rate(NULL
, "uart1_pclk", NULL
, 0, 125000000);
363 pr_err("uart1_pclk not registered\n");
364 ret
= clk_register_clkdev(clk
, NULL
, "20215000.uart");
366 pr_err("uart1_pclk alias not registered\n");
369 struct bcm2835_pll_data
{
375 u32 reference_enable_mask
;
376 /* Bit in CM_LOCK to indicate when the PLL has locked. */
379 const struct bcm2835_pll_ana_bits
*ana
;
381 unsigned long min_rate
;
382 unsigned long max_rate
;
384 * Highest rate for the VCO before we have to use the
387 unsigned long max_fb_rate
;
390 struct bcm2835_pll_ana_bits
{
400 static const struct bcm2835_pll_ana_bits bcm2835_ana_default
= {
403 .mask1
= (u32
)~(A2W_PLL_KI_MASK
| A2W_PLL_KP_MASK
),
404 .set1
= (2 << A2W_PLL_KI_SHIFT
) | (8 << A2W_PLL_KP_SHIFT
),
405 .mask3
= (u32
)~A2W_PLL_KA_MASK
,
406 .set3
= (2 << A2W_PLL_KA_SHIFT
),
407 .fb_prediv_mask
= BIT(14),
410 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh
= {
411 .mask0
= (u32
)~(A2W_PLLH_KA_MASK
| A2W_PLLH_KI_LOW_MASK
),
412 .set0
= (2 << A2W_PLLH_KA_SHIFT
) | (2 << A2W_PLLH_KI_LOW_SHIFT
),
413 .mask1
= (u32
)~(A2W_PLLH_KI_HIGH_MASK
| A2W_PLLH_KP_MASK
),
414 .set1
= (6 << A2W_PLLH_KP_SHIFT
),
417 .fb_prediv_mask
= BIT(11),
420 struct bcm2835_pll_divider_data
{
422 const char *source_pll
;
432 struct bcm2835_clock_data
{
435 const char *const *parents
;
441 /* Number of integer bits in the divider */
443 /* Number of fractional bits in the divider */
452 struct bcm2835_gate_data
{
461 struct bcm2835_cprman
*cprman
;
462 const struct bcm2835_pll_data
*data
;
465 static int bcm2835_pll_is_on(struct clk_hw
*hw
)
467 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
468 struct bcm2835_cprman
*cprman
= pll
->cprman
;
469 const struct bcm2835_pll_data
*data
= pll
->data
;
471 return cprman_read(cprman
, data
->a2w_ctrl_reg
) &
472 A2W_PLL_CTRL_PRST_DISABLE
;
475 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate
,
476 unsigned long parent_rate
,
477 u32
*ndiv
, u32
*fdiv
)
481 div
= (u64
)rate
<< A2W_PLL_FRAC_BITS
;
482 do_div(div
, parent_rate
);
484 *ndiv
= div
>> A2W_PLL_FRAC_BITS
;
485 *fdiv
= div
& ((1 << A2W_PLL_FRAC_BITS
) - 1);
488 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate
,
489 u32 ndiv
, u32 fdiv
, u32 pdiv
)
496 rate
= (u64
)parent_rate
* ((ndiv
<< A2W_PLL_FRAC_BITS
) + fdiv
);
498 return rate
>> A2W_PLL_FRAC_BITS
;
501 static long bcm2835_pll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
502 unsigned long *parent_rate
)
506 bcm2835_pll_choose_ndiv_and_fdiv(rate
, *parent_rate
, &ndiv
, &fdiv
);
508 return bcm2835_pll_rate_from_divisors(*parent_rate
, ndiv
, fdiv
, 1);
511 static unsigned long bcm2835_pll_get_rate(struct clk_hw
*hw
,
512 unsigned long parent_rate
)
514 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
515 struct bcm2835_cprman
*cprman
= pll
->cprman
;
516 const struct bcm2835_pll_data
*data
= pll
->data
;
517 u32 a2wctrl
= cprman_read(cprman
, data
->a2w_ctrl_reg
);
518 u32 ndiv
, pdiv
, fdiv
;
521 if (parent_rate
== 0)
524 fdiv
= cprman_read(cprman
, data
->frac_reg
) & A2W_PLL_FRAC_MASK
;
525 ndiv
= (a2wctrl
& A2W_PLL_CTRL_NDIV_MASK
) >> A2W_PLL_CTRL_NDIV_SHIFT
;
526 pdiv
= (a2wctrl
& A2W_PLL_CTRL_PDIV_MASK
) >> A2W_PLL_CTRL_PDIV_SHIFT
;
527 using_prediv
= cprman_read(cprman
, data
->ana_reg_base
+ 4) &
528 data
->ana
->fb_prediv_mask
;
533 return bcm2835_pll_rate_from_divisors(parent_rate
, ndiv
, fdiv
, pdiv
);
536 static void bcm2835_pll_off(struct clk_hw
*hw
)
538 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
539 struct bcm2835_cprman
*cprman
= pll
->cprman
;
540 const struct bcm2835_pll_data
*data
= pll
->data
;
542 spin_lock(&cprman
->regs_lock
);
543 cprman_write(cprman
, data
->cm_ctrl_reg
,
544 cprman_read(cprman
, data
->cm_ctrl_reg
) |
546 cprman_write(cprman
, data
->a2w_ctrl_reg
,
547 cprman_read(cprman
, data
->a2w_ctrl_reg
) |
549 spin_unlock(&cprman
->regs_lock
);
552 static int bcm2835_pll_on(struct clk_hw
*hw
)
554 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
555 struct bcm2835_cprman
*cprman
= pll
->cprman
;
556 const struct bcm2835_pll_data
*data
= pll
->data
;
559 cprman_write(cprman
, data
->a2w_ctrl_reg
,
560 cprman_read(cprman
, data
->a2w_ctrl_reg
) &
561 ~A2W_PLL_CTRL_PWRDN
);
563 /* Take the PLL out of reset. */
564 cprman_write(cprman
, data
->cm_ctrl_reg
,
565 cprman_read(cprman
, data
->cm_ctrl_reg
) & ~CM_PLL_ANARST
);
567 /* Wait for the PLL to lock. */
568 timeout
= ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS
);
569 while (!(cprman_read(cprman
, CM_LOCK
) & data
->lock_mask
)) {
570 if (ktime_after(ktime_get(), timeout
)) {
571 dev_err(cprman
->dev
, "%s: couldn't lock PLL\n",
572 clk_hw_get_name(hw
));
583 bcm2835_pll_write_ana(struct bcm2835_cprman
*cprman
, u32 ana_reg_base
, u32
*ana
)
588 * ANA register setup is done as a series of writes to
589 * ANA3-ANA0, in that order. This lets us write all 4
590 * registers as a single cycle of the serdes interface (taking
591 * 100 xosc clocks), whereas if we were to update ana0, 1, and
592 * 3 individually through their partial-write registers, each
593 * would be their own serdes cycle.
595 for (i
= 3; i
>= 0; i
--)
596 cprman_write(cprman
, ana_reg_base
+ i
* 4, ana
[i
]);
599 static int bcm2835_pll_set_rate(struct clk_hw
*hw
,
600 unsigned long rate
, unsigned long parent_rate
)
602 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
603 struct bcm2835_cprman
*cprman
= pll
->cprman
;
604 const struct bcm2835_pll_data
*data
= pll
->data
;
605 bool was_using_prediv
, use_fb_prediv
, do_ana_setup_first
;
606 u32 ndiv
, fdiv
, a2w_ctl
;
610 if (rate
< data
->min_rate
|| rate
> data
->max_rate
) {
611 dev_err(cprman
->dev
, "%s: rate out of spec: %lu vs (%lu, %lu)\n",
612 clk_hw_get_name(hw
), rate
,
613 data
->min_rate
, data
->max_rate
);
617 if (rate
> data
->max_fb_rate
) {
618 use_fb_prediv
= true;
621 use_fb_prediv
= false;
624 bcm2835_pll_choose_ndiv_and_fdiv(rate
, parent_rate
, &ndiv
, &fdiv
);
626 for (i
= 3; i
>= 0; i
--)
627 ana
[i
] = cprman_read(cprman
, data
->ana_reg_base
+ i
* 4);
629 was_using_prediv
= ana
[1] & data
->ana
->fb_prediv_mask
;
631 ana
[0] &= ~data
->ana
->mask0
;
632 ana
[0] |= data
->ana
->set0
;
633 ana
[1] &= ~data
->ana
->mask1
;
634 ana
[1] |= data
->ana
->set1
;
635 ana
[3] &= ~data
->ana
->mask3
;
636 ana
[3] |= data
->ana
->set3
;
638 if (was_using_prediv
&& !use_fb_prediv
) {
639 ana
[1] &= ~data
->ana
->fb_prediv_mask
;
640 do_ana_setup_first
= true;
641 } else if (!was_using_prediv
&& use_fb_prediv
) {
642 ana
[1] |= data
->ana
->fb_prediv_mask
;
643 do_ana_setup_first
= false;
645 do_ana_setup_first
= true;
648 /* Unmask the reference clock from the oscillator. */
649 cprman_write(cprman
, A2W_XOSC_CTRL
,
650 cprman_read(cprman
, A2W_XOSC_CTRL
) |
651 data
->reference_enable_mask
);
653 if (do_ana_setup_first
)
654 bcm2835_pll_write_ana(cprman
, data
->ana_reg_base
, ana
);
656 /* Set the PLL multiplier from the oscillator. */
657 cprman_write(cprman
, data
->frac_reg
, fdiv
);
659 a2w_ctl
= cprman_read(cprman
, data
->a2w_ctrl_reg
);
660 a2w_ctl
&= ~A2W_PLL_CTRL_NDIV_MASK
;
661 a2w_ctl
|= ndiv
<< A2W_PLL_CTRL_NDIV_SHIFT
;
662 a2w_ctl
&= ~A2W_PLL_CTRL_PDIV_MASK
;
663 a2w_ctl
|= 1 << A2W_PLL_CTRL_PDIV_SHIFT
;
664 cprman_write(cprman
, data
->a2w_ctrl_reg
, a2w_ctl
);
666 if (!do_ana_setup_first
)
667 bcm2835_pll_write_ana(cprman
, data
->ana_reg_base
, ana
);
672 static int bcm2835_pll_debug_init(struct clk_hw
*hw
,
673 struct dentry
*dentry
)
675 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
676 struct bcm2835_cprman
*cprman
= pll
->cprman
;
677 const struct bcm2835_pll_data
*data
= pll
->data
;
678 struct debugfs_reg32
*regs
;
680 regs
= devm_kzalloc(cprman
->dev
, 7 * sizeof(*regs
), GFP_KERNEL
);
684 regs
[0].name
= "cm_ctrl";
685 regs
[0].offset
= data
->cm_ctrl_reg
;
686 regs
[1].name
= "a2w_ctrl";
687 regs
[1].offset
= data
->a2w_ctrl_reg
;
688 regs
[2].name
= "frac";
689 regs
[2].offset
= data
->frac_reg
;
690 regs
[3].name
= "ana0";
691 regs
[3].offset
= data
->ana_reg_base
+ 0 * 4;
692 regs
[4].name
= "ana1";
693 regs
[4].offset
= data
->ana_reg_base
+ 1 * 4;
694 regs
[5].name
= "ana2";
695 regs
[5].offset
= data
->ana_reg_base
+ 2 * 4;
696 regs
[6].name
= "ana3";
697 regs
[6].offset
= data
->ana_reg_base
+ 3 * 4;
699 return bcm2835_debugfs_regset(cprman
, 0, regs
, 7, dentry
);
702 static const struct clk_ops bcm2835_pll_clk_ops
= {
703 .is_prepared
= bcm2835_pll_is_on
,
704 .prepare
= bcm2835_pll_on
,
705 .unprepare
= bcm2835_pll_off
,
706 .recalc_rate
= bcm2835_pll_get_rate
,
707 .set_rate
= bcm2835_pll_set_rate
,
708 .round_rate
= bcm2835_pll_round_rate
,
709 .debug_init
= bcm2835_pll_debug_init
,
712 struct bcm2835_pll_divider
{
713 struct clk_divider div
;
714 struct bcm2835_cprman
*cprman
;
715 const struct bcm2835_pll_divider_data
*data
;
718 static struct bcm2835_pll_divider
*
719 bcm2835_pll_divider_from_hw(struct clk_hw
*hw
)
721 return container_of(hw
, struct bcm2835_pll_divider
, div
.hw
);
724 static int bcm2835_pll_divider_is_on(struct clk_hw
*hw
)
726 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
727 struct bcm2835_cprman
*cprman
= divider
->cprman
;
728 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
730 return !(cprman_read(cprman
, data
->a2w_reg
) & A2W_PLL_CHANNEL_DISABLE
);
733 static long bcm2835_pll_divider_round_rate(struct clk_hw
*hw
,
735 unsigned long *parent_rate
)
737 return clk_divider_ops
.round_rate(hw
, rate
, parent_rate
);
740 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw
*hw
,
741 unsigned long parent_rate
)
743 return clk_divider_ops
.recalc_rate(hw
, parent_rate
);
746 static void bcm2835_pll_divider_off(struct clk_hw
*hw
)
748 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
749 struct bcm2835_cprman
*cprman
= divider
->cprman
;
750 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
752 spin_lock(&cprman
->regs_lock
);
753 cprman_write(cprman
, data
->cm_reg
,
754 (cprman_read(cprman
, data
->cm_reg
) &
755 ~data
->load_mask
) | data
->hold_mask
);
756 cprman_write(cprman
, data
->a2w_reg
, A2W_PLL_CHANNEL_DISABLE
);
757 spin_unlock(&cprman
->regs_lock
);
760 static int bcm2835_pll_divider_on(struct clk_hw
*hw
)
762 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
763 struct bcm2835_cprman
*cprman
= divider
->cprman
;
764 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
766 spin_lock(&cprman
->regs_lock
);
767 cprman_write(cprman
, data
->a2w_reg
,
768 cprman_read(cprman
, data
->a2w_reg
) &
769 ~A2W_PLL_CHANNEL_DISABLE
);
771 cprman_write(cprman
, data
->cm_reg
,
772 cprman_read(cprman
, data
->cm_reg
) & ~data
->hold_mask
);
773 spin_unlock(&cprman
->regs_lock
);
778 static int bcm2835_pll_divider_set_rate(struct clk_hw
*hw
,
780 unsigned long parent_rate
)
782 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
783 struct bcm2835_cprman
*cprman
= divider
->cprman
;
784 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
785 u32 cm
, div
, max_div
= 1 << A2W_PLL_DIV_BITS
;
787 div
= DIV_ROUND_UP_ULL(parent_rate
, rate
);
789 div
= min(div
, max_div
);
793 cprman_write(cprman
, data
->a2w_reg
, div
);
794 cm
= cprman_read(cprman
, data
->cm_reg
);
795 cprman_write(cprman
, data
->cm_reg
, cm
| data
->load_mask
);
796 cprman_write(cprman
, data
->cm_reg
, cm
& ~data
->load_mask
);
801 static int bcm2835_pll_divider_debug_init(struct clk_hw
*hw
,
802 struct dentry
*dentry
)
804 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
805 struct bcm2835_cprman
*cprman
= divider
->cprman
;
806 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
807 struct debugfs_reg32
*regs
;
809 regs
= devm_kzalloc(cprman
->dev
, 7 * sizeof(*regs
), GFP_KERNEL
);
814 regs
[0].offset
= data
->cm_reg
;
815 regs
[1].name
= "a2w";
816 regs
[1].offset
= data
->a2w_reg
;
818 return bcm2835_debugfs_regset(cprman
, 0, regs
, 2, dentry
);
821 static const struct clk_ops bcm2835_pll_divider_clk_ops
= {
822 .is_prepared
= bcm2835_pll_divider_is_on
,
823 .prepare
= bcm2835_pll_divider_on
,
824 .unprepare
= bcm2835_pll_divider_off
,
825 .recalc_rate
= bcm2835_pll_divider_get_rate
,
826 .set_rate
= bcm2835_pll_divider_set_rate
,
827 .round_rate
= bcm2835_pll_divider_round_rate
,
828 .debug_init
= bcm2835_pll_divider_debug_init
,
832 * The CM dividers do fixed-point division, so we can't use the
833 * generic integer divider code like the PLL dividers do (and we can't
834 * fake it by having some fixed shifts preceding it in the clock tree,
835 * because we'd run out of bits in a 32-bit unsigned long).
837 struct bcm2835_clock
{
839 struct bcm2835_cprman
*cprman
;
840 const struct bcm2835_clock_data
*data
;
843 static struct bcm2835_clock
*bcm2835_clock_from_hw(struct clk_hw
*hw
)
845 return container_of(hw
, struct bcm2835_clock
, hw
);
848 static int bcm2835_clock_is_on(struct clk_hw
*hw
)
850 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
851 struct bcm2835_cprman
*cprman
= clock
->cprman
;
852 const struct bcm2835_clock_data
*data
= clock
->data
;
854 return (cprman_read(cprman
, data
->ctl_reg
) & CM_ENABLE
) != 0;
857 static u32
bcm2835_clock_choose_div(struct clk_hw
*hw
,
859 unsigned long parent_rate
,
862 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
863 const struct bcm2835_clock_data
*data
= clock
->data
;
864 u32 unused_frac_mask
=
865 GENMASK(CM_DIV_FRAC_BITS
- data
->frac_bits
, 0) >> 1;
866 u64 temp
= (u64
)parent_rate
<< CM_DIV_FRAC_BITS
;
868 u32 div
, mindiv
, maxdiv
;
870 rem
= do_div(temp
, rate
);
873 /* Round up and mask off the unused bits */
874 if (round_up
&& ((div
& unused_frac_mask
) != 0 || rem
!= 0))
875 div
+= unused_frac_mask
+ 1;
876 div
&= ~unused_frac_mask
;
878 /* different clamping limits apply for a mash clock */
879 if (data
->is_mash_clock
) {
880 /* clamp to min divider of 2 */
881 mindiv
= 2 << CM_DIV_FRAC_BITS
;
882 /* clamp to the highest possible integer divider */
883 maxdiv
= (BIT(data
->int_bits
) - 1) << CM_DIV_FRAC_BITS
;
885 /* clamp to min divider of 1 */
886 mindiv
= 1 << CM_DIV_FRAC_BITS
;
887 /* clamp to the highest possible fractional divider */
888 maxdiv
= GENMASK(data
->int_bits
+ CM_DIV_FRAC_BITS
- 1,
889 CM_DIV_FRAC_BITS
- data
->frac_bits
);
892 /* apply the clamping limits */
893 div
= max_t(u32
, div
, mindiv
);
894 div
= min_t(u32
, div
, maxdiv
);
899 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock
*clock
,
900 unsigned long parent_rate
,
903 const struct bcm2835_clock_data
*data
= clock
->data
;
907 * The divisor is a 12.12 fixed point field, but only some of
908 * the bits are populated in any given clock.
910 div
>>= CM_DIV_FRAC_BITS
- data
->frac_bits
;
911 div
&= (1 << (data
->int_bits
+ data
->frac_bits
)) - 1;
916 temp
= (u64
)parent_rate
<< data
->frac_bits
;
923 static unsigned long bcm2835_clock_get_rate(struct clk_hw
*hw
,
924 unsigned long parent_rate
)
926 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
927 struct bcm2835_cprman
*cprman
= clock
->cprman
;
928 const struct bcm2835_clock_data
*data
= clock
->data
;
929 u32 div
= cprman_read(cprman
, data
->div_reg
);
931 return bcm2835_clock_rate_from_divisor(clock
, parent_rate
, div
);
934 static void bcm2835_clock_wait_busy(struct bcm2835_clock
*clock
)
936 struct bcm2835_cprman
*cprman
= clock
->cprman
;
937 const struct bcm2835_clock_data
*data
= clock
->data
;
938 ktime_t timeout
= ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS
);
940 while (cprman_read(cprman
, data
->ctl_reg
) & CM_BUSY
) {
941 if (ktime_after(ktime_get(), timeout
)) {
942 dev_err(cprman
->dev
, "%s: couldn't lock PLL\n",
943 clk_hw_get_name(&clock
->hw
));
950 static void bcm2835_clock_off(struct clk_hw
*hw
)
952 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
953 struct bcm2835_cprman
*cprman
= clock
->cprman
;
954 const struct bcm2835_clock_data
*data
= clock
->data
;
956 spin_lock(&cprman
->regs_lock
);
957 cprman_write(cprman
, data
->ctl_reg
,
958 cprman_read(cprman
, data
->ctl_reg
) & ~CM_ENABLE
);
959 spin_unlock(&cprman
->regs_lock
);
961 /* BUSY will remain high until the divider completes its cycle. */
962 bcm2835_clock_wait_busy(clock
);
965 static int bcm2835_clock_on(struct clk_hw
*hw
)
967 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
968 struct bcm2835_cprman
*cprman
= clock
->cprman
;
969 const struct bcm2835_clock_data
*data
= clock
->data
;
971 spin_lock(&cprman
->regs_lock
);
972 cprman_write(cprman
, data
->ctl_reg
,
973 cprman_read(cprman
, data
->ctl_reg
) |
976 spin_unlock(&cprman
->regs_lock
);
981 static int bcm2835_clock_set_rate(struct clk_hw
*hw
,
982 unsigned long rate
, unsigned long parent_rate
)
984 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
985 struct bcm2835_cprman
*cprman
= clock
->cprman
;
986 const struct bcm2835_clock_data
*data
= clock
->data
;
987 u32 div
= bcm2835_clock_choose_div(hw
, rate
, parent_rate
, false);
990 spin_lock(&cprman
->regs_lock
);
993 * Setting up frac support
995 * In principle it is recommended to stop/start the clock first,
996 * but as we set CLK_SET_RATE_GATE during registration of the
997 * clock this requirement should be take care of by the
1000 ctl
= cprman_read(cprman
, data
->ctl_reg
) & ~CM_FRAC
;
1001 ctl
|= (div
& CM_DIV_FRAC_MASK
) ? CM_FRAC
: 0;
1002 cprman_write(cprman
, data
->ctl_reg
, ctl
);
1004 cprman_write(cprman
, data
->div_reg
, div
);
1006 spin_unlock(&cprman
->regs_lock
);
1011 static int bcm2835_clock_determine_rate(struct clk_hw
*hw
,
1012 struct clk_rate_request
*req
)
1014 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1015 struct clk_hw
*parent
, *best_parent
= NULL
;
1016 unsigned long rate
, best_rate
= 0;
1017 unsigned long prate
, best_prate
= 0;
1022 * Select parent clock that results in the closest but lower rate
1024 for (i
= 0; i
< clk_hw_get_num_parents(hw
); ++i
) {
1025 parent
= clk_hw_get_parent_by_index(hw
, i
);
1028 prate
= clk_hw_get_rate(parent
);
1029 div
= bcm2835_clock_choose_div(hw
, req
->rate
, prate
, true);
1030 rate
= bcm2835_clock_rate_from_divisor(clock
, prate
, div
);
1031 if (rate
> best_rate
&& rate
<= req
->rate
) {
1032 best_parent
= parent
;
1041 req
->best_parent_hw
= best_parent
;
1042 req
->best_parent_rate
= best_prate
;
1044 req
->rate
= best_rate
;
1049 static int bcm2835_clock_set_parent(struct clk_hw
*hw
, u8 index
)
1051 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1052 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1053 const struct bcm2835_clock_data
*data
= clock
->data
;
1054 u8 src
= (index
<< CM_SRC_SHIFT
) & CM_SRC_MASK
;
1056 cprman_write(cprman
, data
->ctl_reg
, src
);
1060 static u8
bcm2835_clock_get_parent(struct clk_hw
*hw
)
1062 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1063 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1064 const struct bcm2835_clock_data
*data
= clock
->data
;
1065 u32 src
= cprman_read(cprman
, data
->ctl_reg
);
1067 return (src
& CM_SRC_MASK
) >> CM_SRC_SHIFT
;
1070 static struct debugfs_reg32 bcm2835_debugfs_clock_reg32
[] = {
1081 static int bcm2835_clock_debug_init(struct clk_hw
*hw
,
1082 struct dentry
*dentry
)
1084 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1085 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1086 const struct bcm2835_clock_data
*data
= clock
->data
;
1088 return bcm2835_debugfs_regset(
1089 cprman
, data
->ctl_reg
,
1090 bcm2835_debugfs_clock_reg32
,
1091 ARRAY_SIZE(bcm2835_debugfs_clock_reg32
),
1095 static const struct clk_ops bcm2835_clock_clk_ops
= {
1096 .is_prepared
= bcm2835_clock_is_on
,
1097 .prepare
= bcm2835_clock_on
,
1098 .unprepare
= bcm2835_clock_off
,
1099 .recalc_rate
= bcm2835_clock_get_rate
,
1100 .set_rate
= bcm2835_clock_set_rate
,
1101 .determine_rate
= bcm2835_clock_determine_rate
,
1102 .set_parent
= bcm2835_clock_set_parent
,
1103 .get_parent
= bcm2835_clock_get_parent
,
1104 .debug_init
= bcm2835_clock_debug_init
,
1107 static int bcm2835_vpu_clock_is_on(struct clk_hw
*hw
)
1113 * The VPU clock can never be disabled (it doesn't have an ENABLE
1114 * bit), so it gets its own set of clock ops.
1116 static const struct clk_ops bcm2835_vpu_clock_clk_ops
= {
1117 .is_prepared
= bcm2835_vpu_clock_is_on
,
1118 .recalc_rate
= bcm2835_clock_get_rate
,
1119 .set_rate
= bcm2835_clock_set_rate
,
1120 .determine_rate
= bcm2835_clock_determine_rate
,
1121 .set_parent
= bcm2835_clock_set_parent
,
1122 .get_parent
= bcm2835_clock_get_parent
,
1123 .debug_init
= bcm2835_clock_debug_init
,
1126 static struct clk
*bcm2835_register_pll(struct bcm2835_cprman
*cprman
,
1127 const struct bcm2835_pll_data
*data
)
1129 struct bcm2835_pll
*pll
;
1130 struct clk_init_data init
;
1132 memset(&init
, 0, sizeof(init
));
1134 /* All of the PLLs derive from the external oscillator. */
1135 init
.parent_names
= &cprman
->osc_name
;
1136 init
.num_parents
= 1;
1137 init
.name
= data
->name
;
1138 init
.ops
= &bcm2835_pll_clk_ops
;
1139 init
.flags
= CLK_IGNORE_UNUSED
;
1141 pll
= kzalloc(sizeof(*pll
), GFP_KERNEL
);
1145 pll
->cprman
= cprman
;
1147 pll
->hw
.init
= &init
;
1149 return devm_clk_register(cprman
->dev
, &pll
->hw
);
1153 bcm2835_register_pll_divider(struct bcm2835_cprman
*cprman
,
1154 const struct bcm2835_pll_divider_data
*data
)
1156 struct bcm2835_pll_divider
*divider
;
1157 struct clk_init_data init
;
1159 const char *divider_name
;
1161 if (data
->fixed_divider
!= 1) {
1162 divider_name
= devm_kasprintf(cprman
->dev
, GFP_KERNEL
,
1163 "%s_prediv", data
->name
);
1167 divider_name
= data
->name
;
1170 memset(&init
, 0, sizeof(init
));
1172 init
.parent_names
= &data
->source_pll
;
1173 init
.num_parents
= 1;
1174 init
.name
= divider_name
;
1175 init
.ops
= &bcm2835_pll_divider_clk_ops
;
1176 init
.flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
;
1178 divider
= devm_kzalloc(cprman
->dev
, sizeof(*divider
), GFP_KERNEL
);
1182 divider
->div
.reg
= cprman
->regs
+ data
->a2w_reg
;
1183 divider
->div
.shift
= A2W_PLL_DIV_SHIFT
;
1184 divider
->div
.width
= A2W_PLL_DIV_BITS
;
1185 divider
->div
.flags
= CLK_DIVIDER_MAX_AT_ZERO
;
1186 divider
->div
.lock
= &cprman
->regs_lock
;
1187 divider
->div
.hw
.init
= &init
;
1188 divider
->div
.table
= NULL
;
1190 divider
->cprman
= cprman
;
1191 divider
->data
= data
;
1193 clk
= devm_clk_register(cprman
->dev
, ÷r
->div
.hw
);
1198 * PLLH's channels have a fixed divide by 10 afterwards, which
1199 * is what our consumers are actually using.
1201 if (data
->fixed_divider
!= 1) {
1202 return clk_register_fixed_factor(cprman
->dev
, data
->name
,
1204 CLK_SET_RATE_PARENT
,
1206 data
->fixed_divider
);
1212 static struct clk
*bcm2835_register_clock(struct bcm2835_cprman
*cprman
,
1213 const struct bcm2835_clock_data
*data
)
1215 struct bcm2835_clock
*clock
;
1216 struct clk_init_data init
;
1217 const char *parents
[1 << CM_SRC_BITS
];
1221 * Replace our "xosc" references with the oscillator's
1224 for (i
= 0; i
< data
->num_mux_parents
; i
++) {
1225 if (strcmp(data
->parents
[i
], "xosc") == 0)
1226 parents
[i
] = cprman
->osc_name
;
1228 parents
[i
] = data
->parents
[i
];
1231 memset(&init
, 0, sizeof(init
));
1232 init
.parent_names
= parents
;
1233 init
.num_parents
= data
->num_mux_parents
;
1234 init
.name
= data
->name
;
1235 init
.flags
= data
->flags
| CLK_IGNORE_UNUSED
;
1237 if (data
->is_vpu_clock
) {
1238 init
.ops
= &bcm2835_vpu_clock_clk_ops
;
1240 init
.ops
= &bcm2835_clock_clk_ops
;
1241 init
.flags
|= CLK_SET_RATE_GATE
| CLK_SET_PARENT_GATE
;
1243 /* If the clock wasn't actually enabled at boot, it's not
1246 if (!(cprman_read(cprman
, data
->ctl_reg
) & CM_ENABLE
))
1247 init
.flags
&= ~CLK_IS_CRITICAL
;
1250 clock
= devm_kzalloc(cprman
->dev
, sizeof(*clock
), GFP_KERNEL
);
1254 clock
->cprman
= cprman
;
1256 clock
->hw
.init
= &init
;
1258 return devm_clk_register(cprman
->dev
, &clock
->hw
);
1261 static struct clk
*bcm2835_register_gate(struct bcm2835_cprman
*cprman
,
1262 const struct bcm2835_gate_data
*data
)
1264 return clk_register_gate(cprman
->dev
, data
->name
, data
->parent
,
1265 CLK_IGNORE_UNUSED
| CLK_SET_RATE_GATE
,
1266 cprman
->regs
+ data
->ctl_reg
,
1267 CM_GATE_BIT
, 0, &cprman
->regs_lock
);
1270 typedef struct clk
*(*bcm2835_clk_register
)(struct bcm2835_cprman
*cprman
,
1272 struct bcm2835_clk_desc
{
1273 bcm2835_clk_register clk_register
;
1277 /* assignment helper macros for different clock types */
1278 #define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
1279 .data = __VA_ARGS__ }
1280 #define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \
1281 &(struct bcm2835_pll_data) \
1283 #define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \
1284 &(struct bcm2835_pll_divider_data) \
1286 #define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \
1287 &(struct bcm2835_clock_data) \
1289 #define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \
1290 &(struct bcm2835_gate_data) \
1293 /* parent mux arrays plus helper macros */
1295 /* main oscillator parent mux */
1296 static const char *const bcm2835_clock_osc_parents
[] = {
1303 #define REGISTER_OSC_CLK(...) REGISTER_CLK( \
1304 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1305 .parents = bcm2835_clock_osc_parents, \
1308 /* main peripherial parent mux */
1309 static const char *const bcm2835_clock_per_parents
[] = {
1320 #define REGISTER_PER_CLK(...) REGISTER_CLK( \
1321 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1322 .parents = bcm2835_clock_per_parents, \
1325 /* main vpu parent mux */
1326 static const char *const bcm2835_clock_vpu_parents
[] = {
1339 #define REGISTER_VPU_CLK(...) REGISTER_CLK( \
1340 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1341 .parents = bcm2835_clock_vpu_parents, \
1345 * the real definition of all the pll, pll_dividers and clocks
1346 * these make use of the above REGISTER_* macros
1348 static const struct bcm2835_clk_desc clk_desc_array
[] = {
1349 /* the PLL + PLL dividers */
1352 * PLLA is the auxiliary PLL, used to drive the CCP2
1353 * (Compact Camera Port 2) transmitter clock.
1355 * It is in the PX LDO power domain, which is on when the
1356 * AUDIO domain is on.
1358 [BCM2835_PLLA
] = REGISTER_PLL(
1360 .cm_ctrl_reg
= CM_PLLA
,
1361 .a2w_ctrl_reg
= A2W_PLLA_CTRL
,
1362 .frac_reg
= A2W_PLLA_FRAC
,
1363 .ana_reg_base
= A2W_PLLA_ANA0
,
1364 .reference_enable_mask
= A2W_XOSC_CTRL_PLLA_ENABLE
,
1365 .lock_mask
= CM_LOCK_FLOCKA
,
1367 .ana
= &bcm2835_ana_default
,
1369 .min_rate
= 600000000u,
1370 .max_rate
= 2400000000u,
1371 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1372 [BCM2835_PLLA_CORE
] = REGISTER_PLL_DIV(
1373 .name
= "plla_core",
1374 .source_pll
= "plla",
1376 .a2w_reg
= A2W_PLLA_CORE
,
1377 .load_mask
= CM_PLLA_LOADCORE
,
1378 .hold_mask
= CM_PLLA_HOLDCORE
,
1379 .fixed_divider
= 1),
1380 [BCM2835_PLLA_PER
] = REGISTER_PLL_DIV(
1382 .source_pll
= "plla",
1384 .a2w_reg
= A2W_PLLA_PER
,
1385 .load_mask
= CM_PLLA_LOADPER
,
1386 .hold_mask
= CM_PLLA_HOLDPER
,
1387 .fixed_divider
= 1),
1388 [BCM2835_PLLA_DSI0
] = REGISTER_PLL_DIV(
1389 .name
= "plla_dsi0",
1390 .source_pll
= "plla",
1392 .a2w_reg
= A2W_PLLA_DSI0
,
1393 .load_mask
= CM_PLLA_LOADDSI0
,
1394 .hold_mask
= CM_PLLA_HOLDDSI0
,
1395 .fixed_divider
= 1),
1396 [BCM2835_PLLA_CCP2
] = REGISTER_PLL_DIV(
1397 .name
= "plla_ccp2",
1398 .source_pll
= "plla",
1400 .a2w_reg
= A2W_PLLA_CCP2
,
1401 .load_mask
= CM_PLLA_LOADCCP2
,
1402 .hold_mask
= CM_PLLA_HOLDCCP2
,
1403 .fixed_divider
= 1),
1405 /* PLLB is used for the ARM's clock. */
1406 [BCM2835_PLLB
] = REGISTER_PLL(
1408 .cm_ctrl_reg
= CM_PLLB
,
1409 .a2w_ctrl_reg
= A2W_PLLB_CTRL
,
1410 .frac_reg
= A2W_PLLB_FRAC
,
1411 .ana_reg_base
= A2W_PLLB_ANA0
,
1412 .reference_enable_mask
= A2W_XOSC_CTRL_PLLB_ENABLE
,
1413 .lock_mask
= CM_LOCK_FLOCKB
,
1415 .ana
= &bcm2835_ana_default
,
1417 .min_rate
= 600000000u,
1418 .max_rate
= 3000000000u,
1419 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1420 [BCM2835_PLLB_ARM
] = REGISTER_PLL_DIV(
1422 .source_pll
= "pllb",
1424 .a2w_reg
= A2W_PLLB_ARM
,
1425 .load_mask
= CM_PLLB_LOADARM
,
1426 .hold_mask
= CM_PLLB_HOLDARM
,
1427 .fixed_divider
= 1),
1430 * PLLC is the core PLL, used to drive the core VPU clock.
1432 * It is in the PX LDO power domain, which is on when the
1433 * AUDIO domain is on.
1435 [BCM2835_PLLC
] = REGISTER_PLL(
1437 .cm_ctrl_reg
= CM_PLLC
,
1438 .a2w_ctrl_reg
= A2W_PLLC_CTRL
,
1439 .frac_reg
= A2W_PLLC_FRAC
,
1440 .ana_reg_base
= A2W_PLLC_ANA0
,
1441 .reference_enable_mask
= A2W_XOSC_CTRL_PLLC_ENABLE
,
1442 .lock_mask
= CM_LOCK_FLOCKC
,
1444 .ana
= &bcm2835_ana_default
,
1446 .min_rate
= 600000000u,
1447 .max_rate
= 3000000000u,
1448 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1449 [BCM2835_PLLC_CORE0
] = REGISTER_PLL_DIV(
1450 .name
= "pllc_core0",
1451 .source_pll
= "pllc",
1453 .a2w_reg
= A2W_PLLC_CORE0
,
1454 .load_mask
= CM_PLLC_LOADCORE0
,
1455 .hold_mask
= CM_PLLC_HOLDCORE0
,
1456 .fixed_divider
= 1),
1457 [BCM2835_PLLC_CORE1
] = REGISTER_PLL_DIV(
1458 .name
= "pllc_core1",
1459 .source_pll
= "pllc",
1461 .a2w_reg
= A2W_PLLC_CORE1
,
1462 .load_mask
= CM_PLLC_LOADCORE1
,
1463 .hold_mask
= CM_PLLC_HOLDCORE1
,
1464 .fixed_divider
= 1),
1465 [BCM2835_PLLC_CORE2
] = REGISTER_PLL_DIV(
1466 .name
= "pllc_core2",
1467 .source_pll
= "pllc",
1469 .a2w_reg
= A2W_PLLC_CORE2
,
1470 .load_mask
= CM_PLLC_LOADCORE2
,
1471 .hold_mask
= CM_PLLC_HOLDCORE2
,
1472 .fixed_divider
= 1),
1473 [BCM2835_PLLC_PER
] = REGISTER_PLL_DIV(
1475 .source_pll
= "pllc",
1477 .a2w_reg
= A2W_PLLC_PER
,
1478 .load_mask
= CM_PLLC_LOADPER
,
1479 .hold_mask
= CM_PLLC_HOLDPER
,
1480 .fixed_divider
= 1),
1483 * PLLD is the display PLL, used to drive DSI display panels.
1485 * It is in the PX LDO power domain, which is on when the
1486 * AUDIO domain is on.
1488 [BCM2835_PLLD
] = REGISTER_PLL(
1490 .cm_ctrl_reg
= CM_PLLD
,
1491 .a2w_ctrl_reg
= A2W_PLLD_CTRL
,
1492 .frac_reg
= A2W_PLLD_FRAC
,
1493 .ana_reg_base
= A2W_PLLD_ANA0
,
1494 .reference_enable_mask
= A2W_XOSC_CTRL_DDR_ENABLE
,
1495 .lock_mask
= CM_LOCK_FLOCKD
,
1497 .ana
= &bcm2835_ana_default
,
1499 .min_rate
= 600000000u,
1500 .max_rate
= 2400000000u,
1501 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1502 [BCM2835_PLLD_CORE
] = REGISTER_PLL_DIV(
1503 .name
= "plld_core",
1504 .source_pll
= "plld",
1506 .a2w_reg
= A2W_PLLD_CORE
,
1507 .load_mask
= CM_PLLD_LOADCORE
,
1508 .hold_mask
= CM_PLLD_HOLDCORE
,
1509 .fixed_divider
= 1),
1510 [BCM2835_PLLD_PER
] = REGISTER_PLL_DIV(
1512 .source_pll
= "plld",
1514 .a2w_reg
= A2W_PLLD_PER
,
1515 .load_mask
= CM_PLLD_LOADPER
,
1516 .hold_mask
= CM_PLLD_HOLDPER
,
1517 .fixed_divider
= 1),
1518 [BCM2835_PLLD_DSI0
] = REGISTER_PLL_DIV(
1519 .name
= "plld_dsi0",
1520 .source_pll
= "plld",
1522 .a2w_reg
= A2W_PLLD_DSI0
,
1523 .load_mask
= CM_PLLD_LOADDSI0
,
1524 .hold_mask
= CM_PLLD_HOLDDSI0
,
1525 .fixed_divider
= 1),
1526 [BCM2835_PLLD_DSI1
] = REGISTER_PLL_DIV(
1527 .name
= "plld_dsi1",
1528 .source_pll
= "plld",
1530 .a2w_reg
= A2W_PLLD_DSI1
,
1531 .load_mask
= CM_PLLD_LOADDSI1
,
1532 .hold_mask
= CM_PLLD_HOLDDSI1
,
1533 .fixed_divider
= 1),
1536 * PLLH is used to supply the pixel clock or the AUX clock for the
1539 * It is in the HDMI power domain.
1541 [BCM2835_PLLH
] = REGISTER_PLL(
1543 .cm_ctrl_reg
= CM_PLLH
,
1544 .a2w_ctrl_reg
= A2W_PLLH_CTRL
,
1545 .frac_reg
= A2W_PLLH_FRAC
,
1546 .ana_reg_base
= A2W_PLLH_ANA0
,
1547 .reference_enable_mask
= A2W_XOSC_CTRL_PLLC_ENABLE
,
1548 .lock_mask
= CM_LOCK_FLOCKH
,
1550 .ana
= &bcm2835_ana_pllh
,
1552 .min_rate
= 600000000u,
1553 .max_rate
= 3000000000u,
1554 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1555 [BCM2835_PLLH_RCAL
] = REGISTER_PLL_DIV(
1556 .name
= "pllh_rcal",
1557 .source_pll
= "pllh",
1559 .a2w_reg
= A2W_PLLH_RCAL
,
1560 .load_mask
= CM_PLLH_LOADRCAL
,
1562 .fixed_divider
= 10),
1563 [BCM2835_PLLH_AUX
] = REGISTER_PLL_DIV(
1565 .source_pll
= "pllh",
1567 .a2w_reg
= A2W_PLLH_AUX
,
1568 .load_mask
= CM_PLLH_LOADAUX
,
1570 .fixed_divider
= 10),
1571 [BCM2835_PLLH_PIX
] = REGISTER_PLL_DIV(
1573 .source_pll
= "pllh",
1575 .a2w_reg
= A2W_PLLH_PIX
,
1576 .load_mask
= CM_PLLH_LOADPIX
,
1578 .fixed_divider
= 10),
1582 /* clocks with oscillator parent mux */
1584 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1585 [BCM2835_CLOCK_OTP
] = REGISTER_OSC_CLK(
1587 .ctl_reg
= CM_OTPCTL
,
1588 .div_reg
= CM_OTPDIV
,
1592 * Used for a 1Mhz clock for the system clocksource, and also used
1593 * bythe watchdog timer and the camera pulse generator.
1595 [BCM2835_CLOCK_TIMER
] = REGISTER_OSC_CLK(
1597 .ctl_reg
= CM_TIMERCTL
,
1598 .div_reg
= CM_TIMERDIV
,
1602 * Clock for the temperature sensor.
1603 * Generally run at 2Mhz, max 5Mhz.
1605 [BCM2835_CLOCK_TSENS
] = REGISTER_OSC_CLK(
1607 .ctl_reg
= CM_TSENSCTL
,
1608 .div_reg
= CM_TSENSDIV
,
1611 [BCM2835_CLOCK_TEC
] = REGISTER_OSC_CLK(
1613 .ctl_reg
= CM_TECCTL
,
1614 .div_reg
= CM_TECDIV
,
1618 /* clocks with vpu parent mux */
1619 [BCM2835_CLOCK_H264
] = REGISTER_VPU_CLK(
1621 .ctl_reg
= CM_H264CTL
,
1622 .div_reg
= CM_H264DIV
,
1625 [BCM2835_CLOCK_ISP
] = REGISTER_VPU_CLK(
1627 .ctl_reg
= CM_ISPCTL
,
1628 .div_reg
= CM_ISPDIV
,
1633 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
1634 * in the SDRAM controller can't be used.
1636 [BCM2835_CLOCK_SDRAM
] = REGISTER_VPU_CLK(
1638 .ctl_reg
= CM_SDCCTL
,
1639 .div_reg
= CM_SDCDIV
,
1642 [BCM2835_CLOCK_V3D
] = REGISTER_VPU_CLK(
1644 .ctl_reg
= CM_V3DCTL
,
1645 .div_reg
= CM_V3DDIV
,
1649 * VPU clock. This doesn't have an enable bit, since it drives
1650 * the bus for everything else, and is special so it doesn't need
1651 * to be gated for rate changes. It is also known as "clk_audio"
1652 * in various hardware documentation.
1654 [BCM2835_CLOCK_VPU
] = REGISTER_VPU_CLK(
1656 .ctl_reg
= CM_VPUCTL
,
1657 .div_reg
= CM_VPUDIV
,
1660 .flags
= CLK_IS_CRITICAL
,
1661 .is_vpu_clock
= true),
1663 /* clocks with per parent mux */
1664 [BCM2835_CLOCK_AVEO
] = REGISTER_PER_CLK(
1666 .ctl_reg
= CM_AVEOCTL
,
1667 .div_reg
= CM_AVEODIV
,
1670 [BCM2835_CLOCK_CAM0
] = REGISTER_PER_CLK(
1672 .ctl_reg
= CM_CAM0CTL
,
1673 .div_reg
= CM_CAM0DIV
,
1676 [BCM2835_CLOCK_CAM1
] = REGISTER_PER_CLK(
1678 .ctl_reg
= CM_CAM1CTL
,
1679 .div_reg
= CM_CAM1DIV
,
1682 [BCM2835_CLOCK_DFT
] = REGISTER_PER_CLK(
1684 .ctl_reg
= CM_DFTCTL
,
1685 .div_reg
= CM_DFTDIV
,
1688 [BCM2835_CLOCK_DPI
] = REGISTER_PER_CLK(
1690 .ctl_reg
= CM_DPICTL
,
1691 .div_reg
= CM_DPIDIV
,
1695 /* Arasan EMMC clock */
1696 [BCM2835_CLOCK_EMMC
] = REGISTER_PER_CLK(
1698 .ctl_reg
= CM_EMMCCTL
,
1699 .div_reg
= CM_EMMCDIV
,
1703 /* General purpose (GPIO) clocks */
1704 [BCM2835_CLOCK_GP0
] = REGISTER_PER_CLK(
1706 .ctl_reg
= CM_GP0CTL
,
1707 .div_reg
= CM_GP0DIV
,
1710 .is_mash_clock
= true),
1711 [BCM2835_CLOCK_GP1
] = REGISTER_PER_CLK(
1713 .ctl_reg
= CM_GP1CTL
,
1714 .div_reg
= CM_GP1DIV
,
1717 .flags
= CLK_IS_CRITICAL
,
1718 .is_mash_clock
= true),
1719 [BCM2835_CLOCK_GP2
] = REGISTER_PER_CLK(
1721 .ctl_reg
= CM_GP2CTL
,
1722 .div_reg
= CM_GP2DIV
,
1725 .flags
= CLK_IS_CRITICAL
),
1727 /* HDMI state machine */
1728 [BCM2835_CLOCK_HSM
] = REGISTER_PER_CLK(
1730 .ctl_reg
= CM_HSMCTL
,
1731 .div_reg
= CM_HSMDIV
,
1734 [BCM2835_CLOCK_PCM
] = REGISTER_PER_CLK(
1736 .ctl_reg
= CM_PCMCTL
,
1737 .div_reg
= CM_PCMDIV
,
1740 .is_mash_clock
= true),
1741 [BCM2835_CLOCK_PWM
] = REGISTER_PER_CLK(
1743 .ctl_reg
= CM_PWMCTL
,
1744 .div_reg
= CM_PWMDIV
,
1747 .is_mash_clock
= true),
1748 [BCM2835_CLOCK_SLIM
] = REGISTER_PER_CLK(
1750 .ctl_reg
= CM_SLIMCTL
,
1751 .div_reg
= CM_SLIMDIV
,
1754 .is_mash_clock
= true),
1755 [BCM2835_CLOCK_SMI
] = REGISTER_PER_CLK(
1757 .ctl_reg
= CM_SMICTL
,
1758 .div_reg
= CM_SMIDIV
,
1761 [BCM2835_CLOCK_UART
] = REGISTER_PER_CLK(
1763 .ctl_reg
= CM_UARTCTL
,
1764 .div_reg
= CM_UARTDIV
,
1768 /* TV encoder clock. Only operating frequency is 108Mhz. */
1769 [BCM2835_CLOCK_VEC
] = REGISTER_PER_CLK(
1771 .ctl_reg
= CM_VECCTL
,
1772 .div_reg
= CM_VECDIV
,
1777 [BCM2835_CLOCK_DSI0E
] = REGISTER_PER_CLK(
1779 .ctl_reg
= CM_DSI0ECTL
,
1780 .div_reg
= CM_DSI0EDIV
,
1783 [BCM2835_CLOCK_DSI1E
] = REGISTER_PER_CLK(
1785 .ctl_reg
= CM_DSI1ECTL
,
1786 .div_reg
= CM_DSI1EDIV
,
1793 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
1794 * you have the debug bit set in the power manager, which we
1795 * don't bother exposing) are individual gates off of the
1796 * non-stop vpu clock.
1798 [BCM2835_CLOCK_PERI_IMAGE
] = REGISTER_GATE(
1799 .name
= "peri_image",
1801 .ctl_reg
= CM_PERIICTL
),
1804 static int bcm2835_clk_probe(struct platform_device
*pdev
)
1806 struct device
*dev
= &pdev
->dev
;
1808 struct bcm2835_cprman
*cprman
;
1809 struct resource
*res
;
1810 const struct bcm2835_clk_desc
*desc
;
1811 const size_t asize
= ARRAY_SIZE(clk_desc_array
);
1814 cprman
= devm_kzalloc(dev
,
1815 sizeof(*cprman
) + asize
* sizeof(*clks
),
1820 spin_lock_init(&cprman
->regs_lock
);
1822 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1823 cprman
->regs
= devm_ioremap_resource(dev
, res
);
1824 if (IS_ERR(cprman
->regs
))
1825 return PTR_ERR(cprman
->regs
);
1827 cprman
->osc_name
= of_clk_get_parent_name(dev
->of_node
, 0);
1828 if (!cprman
->osc_name
)
1831 platform_set_drvdata(pdev
, cprman
);
1833 cprman
->onecell
.clk_num
= asize
;
1834 cprman
->onecell
.clks
= cprman
->clks
;
1835 clks
= cprman
->clks
;
1837 for (i
= 0; i
< asize
; i
++) {
1838 desc
= &clk_desc_array
[i
];
1839 if (desc
->clk_register
&& desc
->data
)
1840 clks
[i
] = desc
->clk_register(cprman
, desc
->data
);
1843 return of_clk_add_provider(dev
->of_node
, of_clk_src_onecell_get
,
1847 static const struct of_device_id bcm2835_clk_of_match
[] = {
1848 { .compatible
= "brcm,bcm2835-cprman", },
1851 MODULE_DEVICE_TABLE(of
, bcm2835_clk_of_match
);
1853 static struct platform_driver bcm2835_clk_driver
= {
1855 .name
= "bcm2835-clk",
1856 .of_match_table
= bcm2835_clk_of_match
,
1858 .probe
= bcm2835_clk_probe
,
1861 builtin_platform_driver(bcm2835_clk_driver
);
1863 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
1864 MODULE_DESCRIPTION("BCM2835 clock driver");
1865 MODULE_LICENSE("GPL v2");