2 * Copyright (C) 2010,2015 Broadcom
3 * Copyright (C) 2012 Stephen Warren
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
18 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
20 * The clock tree on the 2835 has several levels. There's a root
21 * oscillator running at 19.2Mhz. After the oscillator there are 5
22 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
23 * and "HDMI displays". Those 5 PLLs each can divide their output to
24 * produce up to 4 channels. Finally, there is the level of clocks to
25 * be consumed by other hardware components (like "H264" or "HDMI
26 * state machine"), which divide off of some subset of the PLL
29 * All of the clocks in the tree are exposed in the DT, because the DT
30 * may want to make assignments of the final layer of clocks to the
31 * PLL channels, and some components of the hardware will actually
32 * skip layers of the tree (for example, the pixel clock comes
33 * directly from the PLLH PIX channel without using a CM_*CTL clock
37 #include <linux/clk-provider.h>
38 #include <linux/clkdev.h>
39 #include <linux/clk/bcm2835.h>
40 #include <linux/debugfs.h>
41 #include <linux/module.h>
43 #include <linux/platform_device.h>
44 #include <linux/slab.h>
45 #include <dt-bindings/clock/bcm2835.h>
47 #define CM_PASSWORD 0x5a000000
49 #define CM_GNRICCTL 0x000
50 #define CM_GNRICDIV 0x004
51 # define CM_DIV_FRAC_BITS 12
52 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
54 #define CM_VPUCTL 0x008
55 #define CM_VPUDIV 0x00c
56 #define CM_SYSCTL 0x010
57 #define CM_SYSDIV 0x014
58 #define CM_PERIACTL 0x018
59 #define CM_PERIADIV 0x01c
60 #define CM_PERIICTL 0x020
61 #define CM_PERIIDIV 0x024
62 #define CM_H264CTL 0x028
63 #define CM_H264DIV 0x02c
64 #define CM_ISPCTL 0x030
65 #define CM_ISPDIV 0x034
66 #define CM_V3DCTL 0x038
67 #define CM_V3DDIV 0x03c
68 #define CM_CAM0CTL 0x040
69 #define CM_CAM0DIV 0x044
70 #define CM_CAM1CTL 0x048
71 #define CM_CAM1DIV 0x04c
72 #define CM_CCP2CTL 0x050
73 #define CM_CCP2DIV 0x054
74 #define CM_DSI0ECTL 0x058
75 #define CM_DSI0EDIV 0x05c
76 #define CM_DSI0PCTL 0x060
77 #define CM_DSI0PDIV 0x064
78 #define CM_DPICTL 0x068
79 #define CM_DPIDIV 0x06c
80 #define CM_GP0CTL 0x070
81 #define CM_GP0DIV 0x074
82 #define CM_GP1CTL 0x078
83 #define CM_GP1DIV 0x07c
84 #define CM_GP2CTL 0x080
85 #define CM_GP2DIV 0x084
86 #define CM_HSMCTL 0x088
87 #define CM_HSMDIV 0x08c
88 #define CM_OTPCTL 0x090
89 #define CM_OTPDIV 0x094
90 #define CM_PCMCTL 0x098
91 #define CM_PCMDIV 0x09c
92 #define CM_PWMCTL 0x0a0
93 #define CM_PWMDIV 0x0a4
94 #define CM_SLIMCTL 0x0a8
95 #define CM_SLIMDIV 0x0ac
96 #define CM_SMICTL 0x0b0
97 #define CM_SMIDIV 0x0b4
98 /* no definition for 0x0b8 and 0x0bc */
99 #define CM_TCNTCTL 0x0c0
100 #define CM_TCNTDIV 0x0c4
101 #define CM_TECCTL 0x0c8
102 #define CM_TECDIV 0x0cc
103 #define CM_TD0CTL 0x0d0
104 #define CM_TD0DIV 0x0d4
105 #define CM_TD1CTL 0x0d8
106 #define CM_TD1DIV 0x0dc
107 #define CM_TSENSCTL 0x0e0
108 #define CM_TSENSDIV 0x0e4
109 #define CM_TIMERCTL 0x0e8
110 #define CM_TIMERDIV 0x0ec
111 #define CM_UARTCTL 0x0f0
112 #define CM_UARTDIV 0x0f4
113 #define CM_VECCTL 0x0f8
114 #define CM_VECDIV 0x0fc
115 #define CM_PULSECTL 0x190
116 #define CM_PULSEDIV 0x194
117 #define CM_SDCCTL 0x1a8
118 #define CM_SDCDIV 0x1ac
119 #define CM_ARMCTL 0x1b0
120 #define CM_AVEOCTL 0x1b8
121 #define CM_AVEODIV 0x1bc
122 #define CM_EMMCCTL 0x1c0
123 #define CM_EMMCDIV 0x1c4
125 /* General bits for the CM_*CTL regs */
126 # define CM_ENABLE BIT(4)
127 # define CM_KILL BIT(5)
128 # define CM_GATE_BIT 6
129 # define CM_GATE BIT(CM_GATE_BIT)
130 # define CM_BUSY BIT(7)
131 # define CM_BUSYD BIT(8)
132 # define CM_FRAC BIT(9)
133 # define CM_SRC_SHIFT 0
134 # define CM_SRC_BITS 4
135 # define CM_SRC_MASK 0xf
136 # define CM_SRC_GND 0
137 # define CM_SRC_OSC 1
138 # define CM_SRC_TESTDEBUG0 2
139 # define CM_SRC_TESTDEBUG1 3
140 # define CM_SRC_PLLA_CORE 4
141 # define CM_SRC_PLLA_PER 4
142 # define CM_SRC_PLLC_CORE0 5
143 # define CM_SRC_PLLC_PER 5
144 # define CM_SRC_PLLC_CORE1 8
145 # define CM_SRC_PLLD_CORE 6
146 # define CM_SRC_PLLD_PER 6
147 # define CM_SRC_PLLH_AUX 7
148 # define CM_SRC_PLLC_CORE1 8
149 # define CM_SRC_PLLC_CORE2 9
151 #define CM_OSCCOUNT 0x100
153 #define CM_PLLA 0x104
154 # define CM_PLL_ANARST BIT(8)
155 # define CM_PLLA_HOLDPER BIT(7)
156 # define CM_PLLA_LOADPER BIT(6)
157 # define CM_PLLA_HOLDCORE BIT(5)
158 # define CM_PLLA_LOADCORE BIT(4)
159 # define CM_PLLA_HOLDCCP2 BIT(3)
160 # define CM_PLLA_LOADCCP2 BIT(2)
161 # define CM_PLLA_HOLDDSI0 BIT(1)
162 # define CM_PLLA_LOADDSI0 BIT(0)
164 #define CM_PLLC 0x108
165 # define CM_PLLC_HOLDPER BIT(7)
166 # define CM_PLLC_LOADPER BIT(6)
167 # define CM_PLLC_HOLDCORE2 BIT(5)
168 # define CM_PLLC_LOADCORE2 BIT(4)
169 # define CM_PLLC_HOLDCORE1 BIT(3)
170 # define CM_PLLC_LOADCORE1 BIT(2)
171 # define CM_PLLC_HOLDCORE0 BIT(1)
172 # define CM_PLLC_LOADCORE0 BIT(0)
174 #define CM_PLLD 0x10c
175 # define CM_PLLD_HOLDPER BIT(7)
176 # define CM_PLLD_LOADPER BIT(6)
177 # define CM_PLLD_HOLDCORE BIT(5)
178 # define CM_PLLD_LOADCORE BIT(4)
179 # define CM_PLLD_HOLDDSI1 BIT(3)
180 # define CM_PLLD_LOADDSI1 BIT(2)
181 # define CM_PLLD_HOLDDSI0 BIT(1)
182 # define CM_PLLD_LOADDSI0 BIT(0)
184 #define CM_PLLH 0x110
185 # define CM_PLLH_LOADRCAL BIT(2)
186 # define CM_PLLH_LOADAUX BIT(1)
187 # define CM_PLLH_LOADPIX BIT(0)
189 #define CM_LOCK 0x114
190 # define CM_LOCK_FLOCKH BIT(12)
191 # define CM_LOCK_FLOCKD BIT(11)
192 # define CM_LOCK_FLOCKC BIT(10)
193 # define CM_LOCK_FLOCKB BIT(9)
194 # define CM_LOCK_FLOCKA BIT(8)
196 #define CM_EVENT 0x118
197 #define CM_DSI1ECTL 0x158
198 #define CM_DSI1EDIV 0x15c
199 #define CM_DSI1PCTL 0x160
200 #define CM_DSI1PDIV 0x164
201 #define CM_DFTCTL 0x168
202 #define CM_DFTDIV 0x16c
204 #define CM_PLLB 0x170
205 # define CM_PLLB_HOLDARM BIT(1)
206 # define CM_PLLB_LOADARM BIT(0)
208 #define A2W_PLLA_CTRL 0x1100
209 #define A2W_PLLC_CTRL 0x1120
210 #define A2W_PLLD_CTRL 0x1140
211 #define A2W_PLLH_CTRL 0x1160
212 #define A2W_PLLB_CTRL 0x11e0
213 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
214 # define A2W_PLL_CTRL_PWRDN BIT(16)
215 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000
216 # define A2W_PLL_CTRL_PDIV_SHIFT 12
217 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
218 # define A2W_PLL_CTRL_NDIV_SHIFT 0
220 #define A2W_PLLA_ANA0 0x1010
221 #define A2W_PLLC_ANA0 0x1030
222 #define A2W_PLLD_ANA0 0x1050
223 #define A2W_PLLH_ANA0 0x1070
224 #define A2W_PLLB_ANA0 0x10f0
226 #define A2W_PLL_KA_SHIFT 7
227 #define A2W_PLL_KA_MASK GENMASK(9, 7)
228 #define A2W_PLL_KI_SHIFT 19
229 #define A2W_PLL_KI_MASK GENMASK(21, 19)
230 #define A2W_PLL_KP_SHIFT 15
231 #define A2W_PLL_KP_MASK GENMASK(18, 15)
233 #define A2W_PLLH_KA_SHIFT 19
234 #define A2W_PLLH_KA_MASK GENMASK(21, 19)
235 #define A2W_PLLH_KI_LOW_SHIFT 22
236 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
237 #define A2W_PLLH_KI_HIGH_SHIFT 0
238 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
239 #define A2W_PLLH_KP_SHIFT 1
240 #define A2W_PLLH_KP_MASK GENMASK(4, 1)
242 #define A2W_XOSC_CTRL 0x1190
243 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
244 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
245 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
246 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
247 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
248 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
249 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
250 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
252 #define A2W_PLLA_FRAC 0x1200
253 #define A2W_PLLC_FRAC 0x1220
254 #define A2W_PLLD_FRAC 0x1240
255 #define A2W_PLLH_FRAC 0x1260
256 #define A2W_PLLB_FRAC 0x12e0
257 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
258 # define A2W_PLL_FRAC_BITS 20
260 #define A2W_PLL_CHANNEL_DISABLE BIT(8)
261 #define A2W_PLL_DIV_BITS 8
262 #define A2W_PLL_DIV_SHIFT 0
264 #define A2W_PLLA_DSI0 0x1300
265 #define A2W_PLLA_CORE 0x1400
266 #define A2W_PLLA_PER 0x1500
267 #define A2W_PLLA_CCP2 0x1600
269 #define A2W_PLLC_CORE2 0x1320
270 #define A2W_PLLC_CORE1 0x1420
271 #define A2W_PLLC_PER 0x1520
272 #define A2W_PLLC_CORE0 0x1620
274 #define A2W_PLLD_DSI0 0x1340
275 #define A2W_PLLD_CORE 0x1440
276 #define A2W_PLLD_PER 0x1540
277 #define A2W_PLLD_DSI1 0x1640
279 #define A2W_PLLH_AUX 0x1360
280 #define A2W_PLLH_RCAL 0x1460
281 #define A2W_PLLH_PIX 0x1560
282 #define A2W_PLLH_STS 0x1660
284 #define A2W_PLLH_CTRLR 0x1960
285 #define A2W_PLLH_FRACR 0x1a60
286 #define A2W_PLLH_AUXR 0x1b60
287 #define A2W_PLLH_RCALR 0x1c60
288 #define A2W_PLLH_PIXR 0x1d60
289 #define A2W_PLLH_STSR 0x1e60
291 #define A2W_PLLB_ARM 0x13e0
292 #define A2W_PLLB_SP0 0x14e0
293 #define A2W_PLLB_SP1 0x15e0
294 #define A2W_PLLB_SP2 0x16e0
296 #define LOCK_TIMEOUT_NS 100000000
297 #define BCM2835_MAX_FB_RATE 1750000000u
299 struct bcm2835_cprman
{
302 spinlock_t regs_lock
; /* spinlock for all clocks */
303 const char *osc_name
;
305 struct clk_onecell_data onecell
;
309 static inline void cprman_write(struct bcm2835_cprman
*cprman
, u32 reg
, u32 val
)
311 writel(CM_PASSWORD
| val
, cprman
->regs
+ reg
);
314 static inline u32
cprman_read(struct bcm2835_cprman
*cprman
, u32 reg
)
316 return readl(cprman
->regs
+ reg
);
319 static int bcm2835_debugfs_regset(struct bcm2835_cprman
*cprman
, u32 base
,
320 struct debugfs_reg32
*regs
, size_t nregs
,
321 struct dentry
*dentry
)
323 struct dentry
*regdump
;
324 struct debugfs_regset32
*regset
;
326 regset
= devm_kzalloc(cprman
->dev
, sizeof(*regset
), GFP_KERNEL
);
331 regset
->nregs
= nregs
;
332 regset
->base
= cprman
->regs
+ base
;
334 regdump
= debugfs_create_regset32("regdump", S_IRUGO
, dentry
,
337 return regdump
? 0 : -ENOMEM
;
341 * These are fixed clocks. They're probably not all root clocks and it may
342 * be possible to turn them on and off but until this is mapped out better
343 * it's the only way they can be used.
345 void __init
bcm2835_init_clocks(void)
350 clk
= clk_register_fixed_rate(NULL
, "apb_pclk", NULL
, 0, 126000000);
352 pr_err("apb_pclk not registered\n");
354 clk
= clk_register_fixed_rate(NULL
, "uart0_pclk", NULL
, 0, 3000000);
356 pr_err("uart0_pclk not registered\n");
357 ret
= clk_register_clkdev(clk
, NULL
, "20201000.uart");
359 pr_err("uart0_pclk alias not registered\n");
361 clk
= clk_register_fixed_rate(NULL
, "uart1_pclk", NULL
, 0, 125000000);
363 pr_err("uart1_pclk not registered\n");
364 ret
= clk_register_clkdev(clk
, NULL
, "20215000.uart");
366 pr_err("uart1_pclk alias not registered\n");
369 struct bcm2835_pll_data
{
375 u32 reference_enable_mask
;
376 /* Bit in CM_LOCK to indicate when the PLL has locked. */
379 const struct bcm2835_pll_ana_bits
*ana
;
381 unsigned long min_rate
;
382 unsigned long max_rate
;
384 * Highest rate for the VCO before we have to use the
387 unsigned long max_fb_rate
;
390 struct bcm2835_pll_ana_bits
{
400 static const struct bcm2835_pll_ana_bits bcm2835_ana_default
= {
403 .mask1
= (u32
)~(A2W_PLL_KI_MASK
| A2W_PLL_KP_MASK
),
404 .set1
= (2 << A2W_PLL_KI_SHIFT
) | (8 << A2W_PLL_KP_SHIFT
),
405 .mask3
= (u32
)~A2W_PLL_KA_MASK
,
406 .set3
= (2 << A2W_PLL_KA_SHIFT
),
407 .fb_prediv_mask
= BIT(14),
410 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh
= {
411 .mask0
= (u32
)~(A2W_PLLH_KA_MASK
| A2W_PLLH_KI_LOW_MASK
),
412 .set0
= (2 << A2W_PLLH_KA_SHIFT
) | (2 << A2W_PLLH_KI_LOW_SHIFT
),
413 .mask1
= (u32
)~(A2W_PLLH_KI_HIGH_MASK
| A2W_PLLH_KP_MASK
),
414 .set1
= (6 << A2W_PLLH_KP_SHIFT
),
417 .fb_prediv_mask
= BIT(11),
420 struct bcm2835_pll_divider_data
{
422 const char *source_pll
;
432 struct bcm2835_clock_data
{
435 const char *const *parents
;
441 /* Number of integer bits in the divider */
443 /* Number of fractional bits in the divider */
450 struct bcm2835_gate_data
{
459 struct bcm2835_cprman
*cprman
;
460 const struct bcm2835_pll_data
*data
;
463 static int bcm2835_pll_is_on(struct clk_hw
*hw
)
465 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
466 struct bcm2835_cprman
*cprman
= pll
->cprman
;
467 const struct bcm2835_pll_data
*data
= pll
->data
;
469 return cprman_read(cprman
, data
->a2w_ctrl_reg
) &
470 A2W_PLL_CTRL_PRST_DISABLE
;
473 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate
,
474 unsigned long parent_rate
,
475 u32
*ndiv
, u32
*fdiv
)
479 div
= (u64
)rate
<< A2W_PLL_FRAC_BITS
;
480 do_div(div
, parent_rate
);
482 *ndiv
= div
>> A2W_PLL_FRAC_BITS
;
483 *fdiv
= div
& ((1 << A2W_PLL_FRAC_BITS
) - 1);
486 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate
,
487 u32 ndiv
, u32 fdiv
, u32 pdiv
)
494 rate
= (u64
)parent_rate
* ((ndiv
<< A2W_PLL_FRAC_BITS
) + fdiv
);
496 return rate
>> A2W_PLL_FRAC_BITS
;
499 static long bcm2835_pll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
500 unsigned long *parent_rate
)
504 bcm2835_pll_choose_ndiv_and_fdiv(rate
, *parent_rate
, &ndiv
, &fdiv
);
506 return bcm2835_pll_rate_from_divisors(*parent_rate
, ndiv
, fdiv
, 1);
509 static unsigned long bcm2835_pll_get_rate(struct clk_hw
*hw
,
510 unsigned long parent_rate
)
512 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
513 struct bcm2835_cprman
*cprman
= pll
->cprman
;
514 const struct bcm2835_pll_data
*data
= pll
->data
;
515 u32 a2wctrl
= cprman_read(cprman
, data
->a2w_ctrl_reg
);
516 u32 ndiv
, pdiv
, fdiv
;
519 if (parent_rate
== 0)
522 fdiv
= cprman_read(cprman
, data
->frac_reg
) & A2W_PLL_FRAC_MASK
;
523 ndiv
= (a2wctrl
& A2W_PLL_CTRL_NDIV_MASK
) >> A2W_PLL_CTRL_NDIV_SHIFT
;
524 pdiv
= (a2wctrl
& A2W_PLL_CTRL_PDIV_MASK
) >> A2W_PLL_CTRL_PDIV_SHIFT
;
525 using_prediv
= cprman_read(cprman
, data
->ana_reg_base
+ 4) &
526 data
->ana
->fb_prediv_mask
;
531 return bcm2835_pll_rate_from_divisors(parent_rate
, ndiv
, fdiv
, pdiv
);
534 static void bcm2835_pll_off(struct clk_hw
*hw
)
536 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
537 struct bcm2835_cprman
*cprman
= pll
->cprman
;
538 const struct bcm2835_pll_data
*data
= pll
->data
;
540 spin_lock(&cprman
->regs_lock
);
541 cprman_write(cprman
, data
->cm_ctrl_reg
,
542 cprman_read(cprman
, data
->cm_ctrl_reg
) |
544 cprman_write(cprman
, data
->a2w_ctrl_reg
,
545 cprman_read(cprman
, data
->a2w_ctrl_reg
) |
547 spin_unlock(&cprman
->regs_lock
);
550 static int bcm2835_pll_on(struct clk_hw
*hw
)
552 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
553 struct bcm2835_cprman
*cprman
= pll
->cprman
;
554 const struct bcm2835_pll_data
*data
= pll
->data
;
557 /* Take the PLL out of reset. */
558 cprman_write(cprman
, data
->cm_ctrl_reg
,
559 cprman_read(cprman
, data
->cm_ctrl_reg
) & ~CM_PLL_ANARST
);
561 /* Wait for the PLL to lock. */
562 timeout
= ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS
);
563 while (!(cprman_read(cprman
, CM_LOCK
) & data
->lock_mask
)) {
564 if (ktime_after(ktime_get(), timeout
)) {
565 dev_err(cprman
->dev
, "%s: couldn't lock PLL\n",
566 clk_hw_get_name(hw
));
577 bcm2835_pll_write_ana(struct bcm2835_cprman
*cprman
, u32 ana_reg_base
, u32
*ana
)
582 * ANA register setup is done as a series of writes to
583 * ANA3-ANA0, in that order. This lets us write all 4
584 * registers as a single cycle of the serdes interface (taking
585 * 100 xosc clocks), whereas if we were to update ana0, 1, and
586 * 3 individually through their partial-write registers, each
587 * would be their own serdes cycle.
589 for (i
= 3; i
>= 0; i
--)
590 cprman_write(cprman
, ana_reg_base
+ i
* 4, ana
[i
]);
593 static int bcm2835_pll_set_rate(struct clk_hw
*hw
,
594 unsigned long rate
, unsigned long parent_rate
)
596 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
597 struct bcm2835_cprman
*cprman
= pll
->cprman
;
598 const struct bcm2835_pll_data
*data
= pll
->data
;
599 bool was_using_prediv
, use_fb_prediv
, do_ana_setup_first
;
600 u32 ndiv
, fdiv
, a2w_ctl
;
604 if (rate
< data
->min_rate
|| rate
> data
->max_rate
) {
605 dev_err(cprman
->dev
, "%s: rate out of spec: %lu vs (%lu, %lu)\n",
606 clk_hw_get_name(hw
), rate
,
607 data
->min_rate
, data
->max_rate
);
611 if (rate
> data
->max_fb_rate
) {
612 use_fb_prediv
= true;
615 use_fb_prediv
= false;
618 bcm2835_pll_choose_ndiv_and_fdiv(rate
, parent_rate
, &ndiv
, &fdiv
);
620 for (i
= 3; i
>= 0; i
--)
621 ana
[i
] = cprman_read(cprman
, data
->ana_reg_base
+ i
* 4);
623 was_using_prediv
= ana
[1] & data
->ana
->fb_prediv_mask
;
625 ana
[0] &= ~data
->ana
->mask0
;
626 ana
[0] |= data
->ana
->set0
;
627 ana
[1] &= ~data
->ana
->mask1
;
628 ana
[1] |= data
->ana
->set1
;
629 ana
[3] &= ~data
->ana
->mask3
;
630 ana
[3] |= data
->ana
->set3
;
632 if (was_using_prediv
&& !use_fb_prediv
) {
633 ana
[1] &= ~data
->ana
->fb_prediv_mask
;
634 do_ana_setup_first
= true;
635 } else if (!was_using_prediv
&& use_fb_prediv
) {
636 ana
[1] |= data
->ana
->fb_prediv_mask
;
637 do_ana_setup_first
= false;
639 do_ana_setup_first
= true;
642 /* Unmask the reference clock from the oscillator. */
643 cprman_write(cprman
, A2W_XOSC_CTRL
,
644 cprman_read(cprman
, A2W_XOSC_CTRL
) |
645 data
->reference_enable_mask
);
647 if (do_ana_setup_first
)
648 bcm2835_pll_write_ana(cprman
, data
->ana_reg_base
, ana
);
650 /* Set the PLL multiplier from the oscillator. */
651 cprman_write(cprman
, data
->frac_reg
, fdiv
);
653 a2w_ctl
= cprman_read(cprman
, data
->a2w_ctrl_reg
);
654 a2w_ctl
&= ~A2W_PLL_CTRL_NDIV_MASK
;
655 a2w_ctl
|= ndiv
<< A2W_PLL_CTRL_NDIV_SHIFT
;
656 a2w_ctl
&= ~A2W_PLL_CTRL_PDIV_MASK
;
657 a2w_ctl
|= 1 << A2W_PLL_CTRL_PDIV_SHIFT
;
658 cprman_write(cprman
, data
->a2w_ctrl_reg
, a2w_ctl
);
660 if (!do_ana_setup_first
)
661 bcm2835_pll_write_ana(cprman
, data
->ana_reg_base
, ana
);
666 static int bcm2835_pll_debug_init(struct clk_hw
*hw
,
667 struct dentry
*dentry
)
669 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
670 struct bcm2835_cprman
*cprman
= pll
->cprman
;
671 const struct bcm2835_pll_data
*data
= pll
->data
;
672 struct debugfs_reg32
*regs
;
674 regs
= devm_kzalloc(cprman
->dev
, 7 * sizeof(*regs
), GFP_KERNEL
);
678 regs
[0].name
= "cm_ctrl";
679 regs
[0].offset
= data
->cm_ctrl_reg
;
680 regs
[1].name
= "a2w_ctrl";
681 regs
[1].offset
= data
->a2w_ctrl_reg
;
682 regs
[2].name
= "frac";
683 regs
[2].offset
= data
->frac_reg
;
684 regs
[3].name
= "ana0";
685 regs
[3].offset
= data
->ana_reg_base
+ 0 * 4;
686 regs
[4].name
= "ana1";
687 regs
[4].offset
= data
->ana_reg_base
+ 1 * 4;
688 regs
[5].name
= "ana2";
689 regs
[5].offset
= data
->ana_reg_base
+ 2 * 4;
690 regs
[6].name
= "ana3";
691 regs
[6].offset
= data
->ana_reg_base
+ 3 * 4;
693 return bcm2835_debugfs_regset(cprman
, 0, regs
, 7, dentry
);
696 static const struct clk_ops bcm2835_pll_clk_ops
= {
697 .is_prepared
= bcm2835_pll_is_on
,
698 .prepare
= bcm2835_pll_on
,
699 .unprepare
= bcm2835_pll_off
,
700 .recalc_rate
= bcm2835_pll_get_rate
,
701 .set_rate
= bcm2835_pll_set_rate
,
702 .round_rate
= bcm2835_pll_round_rate
,
703 .debug_init
= bcm2835_pll_debug_init
,
706 struct bcm2835_pll_divider
{
707 struct clk_divider div
;
708 struct bcm2835_cprman
*cprman
;
709 const struct bcm2835_pll_divider_data
*data
;
712 static struct bcm2835_pll_divider
*
713 bcm2835_pll_divider_from_hw(struct clk_hw
*hw
)
715 return container_of(hw
, struct bcm2835_pll_divider
, div
.hw
);
718 static int bcm2835_pll_divider_is_on(struct clk_hw
*hw
)
720 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
721 struct bcm2835_cprman
*cprman
= divider
->cprman
;
722 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
724 return !(cprman_read(cprman
, data
->a2w_reg
) & A2W_PLL_CHANNEL_DISABLE
);
727 static long bcm2835_pll_divider_round_rate(struct clk_hw
*hw
,
729 unsigned long *parent_rate
)
731 return clk_divider_ops
.round_rate(hw
, rate
, parent_rate
);
734 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw
*hw
,
735 unsigned long parent_rate
)
737 return clk_divider_ops
.recalc_rate(hw
, parent_rate
);
740 static void bcm2835_pll_divider_off(struct clk_hw
*hw
)
742 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
743 struct bcm2835_cprman
*cprman
= divider
->cprman
;
744 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
746 spin_lock(&cprman
->regs_lock
);
747 cprman_write(cprman
, data
->cm_reg
,
748 (cprman_read(cprman
, data
->cm_reg
) &
749 ~data
->load_mask
) | data
->hold_mask
);
750 cprman_write(cprman
, data
->a2w_reg
, A2W_PLL_CHANNEL_DISABLE
);
751 spin_unlock(&cprman
->regs_lock
);
754 static int bcm2835_pll_divider_on(struct clk_hw
*hw
)
756 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
757 struct bcm2835_cprman
*cprman
= divider
->cprman
;
758 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
760 spin_lock(&cprman
->regs_lock
);
761 cprman_write(cprman
, data
->a2w_reg
,
762 cprman_read(cprman
, data
->a2w_reg
) &
763 ~A2W_PLL_CHANNEL_DISABLE
);
765 cprman_write(cprman
, data
->cm_reg
,
766 cprman_read(cprman
, data
->cm_reg
) & ~data
->hold_mask
);
767 spin_unlock(&cprman
->regs_lock
);
772 static int bcm2835_pll_divider_set_rate(struct clk_hw
*hw
,
774 unsigned long parent_rate
)
776 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
777 struct bcm2835_cprman
*cprman
= divider
->cprman
;
778 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
779 u32 cm
, div
, max_div
= 1 << A2W_PLL_DIV_BITS
;
781 div
= DIV_ROUND_UP_ULL(parent_rate
, rate
);
783 div
= min(div
, max_div
);
787 cprman_write(cprman
, data
->a2w_reg
, div
);
788 cm
= cprman_read(cprman
, data
->cm_reg
);
789 cprman_write(cprman
, data
->cm_reg
, cm
| data
->load_mask
);
790 cprman_write(cprman
, data
->cm_reg
, cm
& ~data
->load_mask
);
795 static int bcm2835_pll_divider_debug_init(struct clk_hw
*hw
,
796 struct dentry
*dentry
)
798 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
799 struct bcm2835_cprman
*cprman
= divider
->cprman
;
800 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
801 struct debugfs_reg32
*regs
;
803 regs
= devm_kzalloc(cprman
->dev
, 7 * sizeof(*regs
), GFP_KERNEL
);
808 regs
[0].offset
= data
->cm_reg
;
809 regs
[1].name
= "a2w";
810 regs
[1].offset
= data
->a2w_reg
;
812 return bcm2835_debugfs_regset(cprman
, 0, regs
, 2, dentry
);
815 static const struct clk_ops bcm2835_pll_divider_clk_ops
= {
816 .is_prepared
= bcm2835_pll_divider_is_on
,
817 .prepare
= bcm2835_pll_divider_on
,
818 .unprepare
= bcm2835_pll_divider_off
,
819 .recalc_rate
= bcm2835_pll_divider_get_rate
,
820 .set_rate
= bcm2835_pll_divider_set_rate
,
821 .round_rate
= bcm2835_pll_divider_round_rate
,
822 .debug_init
= bcm2835_pll_divider_debug_init
,
826 * The CM dividers do fixed-point division, so we can't use the
827 * generic integer divider code like the PLL dividers do (and we can't
828 * fake it by having some fixed shifts preceding it in the clock tree,
829 * because we'd run out of bits in a 32-bit unsigned long).
831 struct bcm2835_clock
{
833 struct bcm2835_cprman
*cprman
;
834 const struct bcm2835_clock_data
*data
;
837 static struct bcm2835_clock
*bcm2835_clock_from_hw(struct clk_hw
*hw
)
839 return container_of(hw
, struct bcm2835_clock
, hw
);
842 static int bcm2835_clock_is_on(struct clk_hw
*hw
)
844 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
845 struct bcm2835_cprman
*cprman
= clock
->cprman
;
846 const struct bcm2835_clock_data
*data
= clock
->data
;
848 return (cprman_read(cprman
, data
->ctl_reg
) & CM_ENABLE
) != 0;
851 static u32
bcm2835_clock_choose_div(struct clk_hw
*hw
,
853 unsigned long parent_rate
,
856 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
857 const struct bcm2835_clock_data
*data
= clock
->data
;
858 u32 unused_frac_mask
=
859 GENMASK(CM_DIV_FRAC_BITS
- data
->frac_bits
, 0) >> 1;
860 u64 temp
= (u64
)parent_rate
<< CM_DIV_FRAC_BITS
;
862 u32 div
, mindiv
, maxdiv
;
864 rem
= do_div(temp
, rate
);
867 /* Round up and mask off the unused bits */
868 if (round_up
&& ((div
& unused_frac_mask
) != 0 || rem
!= 0))
869 div
+= unused_frac_mask
+ 1;
870 div
&= ~unused_frac_mask
;
872 /* different clamping limits apply for a mash clock */
873 if (data
->is_mash_clock
) {
874 /* clamp to min divider of 2 */
875 mindiv
= 2 << CM_DIV_FRAC_BITS
;
876 /* clamp to the highest possible integer divider */
877 maxdiv
= (BIT(data
->int_bits
) - 1) << CM_DIV_FRAC_BITS
;
879 /* clamp to min divider of 1 */
880 mindiv
= 1 << CM_DIV_FRAC_BITS
;
881 /* clamp to the highest possible fractional divider */
882 maxdiv
= GENMASK(data
->int_bits
+ CM_DIV_FRAC_BITS
- 1,
883 CM_DIV_FRAC_BITS
- data
->frac_bits
);
886 /* apply the clamping limits */
887 div
= max_t(u32
, div
, mindiv
);
888 div
= min_t(u32
, div
, maxdiv
);
893 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock
*clock
,
894 unsigned long parent_rate
,
897 const struct bcm2835_clock_data
*data
= clock
->data
;
901 * The divisor is a 12.12 fixed point field, but only some of
902 * the bits are populated in any given clock.
904 div
>>= CM_DIV_FRAC_BITS
- data
->frac_bits
;
905 div
&= (1 << (data
->int_bits
+ data
->frac_bits
)) - 1;
910 temp
= (u64
)parent_rate
<< data
->frac_bits
;
917 static unsigned long bcm2835_clock_get_rate(struct clk_hw
*hw
,
918 unsigned long parent_rate
)
920 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
921 struct bcm2835_cprman
*cprman
= clock
->cprman
;
922 const struct bcm2835_clock_data
*data
= clock
->data
;
923 u32 div
= cprman_read(cprman
, data
->div_reg
);
925 return bcm2835_clock_rate_from_divisor(clock
, parent_rate
, div
);
928 static void bcm2835_clock_wait_busy(struct bcm2835_clock
*clock
)
930 struct bcm2835_cprman
*cprman
= clock
->cprman
;
931 const struct bcm2835_clock_data
*data
= clock
->data
;
932 ktime_t timeout
= ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS
);
934 while (cprman_read(cprman
, data
->ctl_reg
) & CM_BUSY
) {
935 if (ktime_after(ktime_get(), timeout
)) {
936 dev_err(cprman
->dev
, "%s: couldn't lock PLL\n",
937 clk_hw_get_name(&clock
->hw
));
944 static void bcm2835_clock_off(struct clk_hw
*hw
)
946 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
947 struct bcm2835_cprman
*cprman
= clock
->cprman
;
948 const struct bcm2835_clock_data
*data
= clock
->data
;
950 spin_lock(&cprman
->regs_lock
);
951 cprman_write(cprman
, data
->ctl_reg
,
952 cprman_read(cprman
, data
->ctl_reg
) & ~CM_ENABLE
);
953 spin_unlock(&cprman
->regs_lock
);
955 /* BUSY will remain high until the divider completes its cycle. */
956 bcm2835_clock_wait_busy(clock
);
959 static int bcm2835_clock_on(struct clk_hw
*hw
)
961 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
962 struct bcm2835_cprman
*cprman
= clock
->cprman
;
963 const struct bcm2835_clock_data
*data
= clock
->data
;
965 spin_lock(&cprman
->regs_lock
);
966 cprman_write(cprman
, data
->ctl_reg
,
967 cprman_read(cprman
, data
->ctl_reg
) |
970 spin_unlock(&cprman
->regs_lock
);
975 static int bcm2835_clock_set_rate(struct clk_hw
*hw
,
976 unsigned long rate
, unsigned long parent_rate
)
978 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
979 struct bcm2835_cprman
*cprman
= clock
->cprman
;
980 const struct bcm2835_clock_data
*data
= clock
->data
;
981 u32 div
= bcm2835_clock_choose_div(hw
, rate
, parent_rate
, false);
984 spin_lock(&cprman
->regs_lock
);
987 * Setting up frac support
989 * In principle it is recommended to stop/start the clock first,
990 * but as we set CLK_SET_RATE_GATE during registration of the
991 * clock this requirement should be take care of by the
994 ctl
= cprman_read(cprman
, data
->ctl_reg
) & ~CM_FRAC
;
995 ctl
|= (div
& CM_DIV_FRAC_MASK
) ? CM_FRAC
: 0;
996 cprman_write(cprman
, data
->ctl_reg
, ctl
);
998 cprman_write(cprman
, data
->div_reg
, div
);
1000 spin_unlock(&cprman
->regs_lock
);
1005 static int bcm2835_clock_determine_rate(struct clk_hw
*hw
,
1006 struct clk_rate_request
*req
)
1008 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1009 struct clk_hw
*parent
, *best_parent
= NULL
;
1010 unsigned long rate
, best_rate
= 0;
1011 unsigned long prate
, best_prate
= 0;
1016 * Select parent clock that results in the closest but lower rate
1018 for (i
= 0; i
< clk_hw_get_num_parents(hw
); ++i
) {
1019 parent
= clk_hw_get_parent_by_index(hw
, i
);
1022 prate
= clk_hw_get_rate(parent
);
1023 div
= bcm2835_clock_choose_div(hw
, req
->rate
, prate
, true);
1024 rate
= bcm2835_clock_rate_from_divisor(clock
, prate
, div
);
1025 if (rate
> best_rate
&& rate
<= req
->rate
) {
1026 best_parent
= parent
;
1035 req
->best_parent_hw
= best_parent
;
1036 req
->best_parent_rate
= best_prate
;
1038 req
->rate
= best_rate
;
1043 static int bcm2835_clock_set_parent(struct clk_hw
*hw
, u8 index
)
1045 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1046 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1047 const struct bcm2835_clock_data
*data
= clock
->data
;
1048 u8 src
= (index
<< CM_SRC_SHIFT
) & CM_SRC_MASK
;
1050 cprman_write(cprman
, data
->ctl_reg
, src
);
1054 static u8
bcm2835_clock_get_parent(struct clk_hw
*hw
)
1056 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1057 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1058 const struct bcm2835_clock_data
*data
= clock
->data
;
1059 u32 src
= cprman_read(cprman
, data
->ctl_reg
);
1061 return (src
& CM_SRC_MASK
) >> CM_SRC_SHIFT
;
1064 static struct debugfs_reg32 bcm2835_debugfs_clock_reg32
[] = {
1075 static int bcm2835_clock_debug_init(struct clk_hw
*hw
,
1076 struct dentry
*dentry
)
1078 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1079 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1080 const struct bcm2835_clock_data
*data
= clock
->data
;
1082 return bcm2835_debugfs_regset(
1083 cprman
, data
->ctl_reg
,
1084 bcm2835_debugfs_clock_reg32
,
1085 ARRAY_SIZE(bcm2835_debugfs_clock_reg32
),
1089 static const struct clk_ops bcm2835_clock_clk_ops
= {
1090 .is_prepared
= bcm2835_clock_is_on
,
1091 .prepare
= bcm2835_clock_on
,
1092 .unprepare
= bcm2835_clock_off
,
1093 .recalc_rate
= bcm2835_clock_get_rate
,
1094 .set_rate
= bcm2835_clock_set_rate
,
1095 .determine_rate
= bcm2835_clock_determine_rate
,
1096 .set_parent
= bcm2835_clock_set_parent
,
1097 .get_parent
= bcm2835_clock_get_parent
,
1098 .debug_init
= bcm2835_clock_debug_init
,
1101 static int bcm2835_vpu_clock_is_on(struct clk_hw
*hw
)
1107 * The VPU clock can never be disabled (it doesn't have an ENABLE
1108 * bit), so it gets its own set of clock ops.
1110 static const struct clk_ops bcm2835_vpu_clock_clk_ops
= {
1111 .is_prepared
= bcm2835_vpu_clock_is_on
,
1112 .recalc_rate
= bcm2835_clock_get_rate
,
1113 .set_rate
= bcm2835_clock_set_rate
,
1114 .determine_rate
= bcm2835_clock_determine_rate
,
1115 .set_parent
= bcm2835_clock_set_parent
,
1116 .get_parent
= bcm2835_clock_get_parent
,
1117 .debug_init
= bcm2835_clock_debug_init
,
1120 static struct clk
*bcm2835_register_pll(struct bcm2835_cprman
*cprman
,
1121 const struct bcm2835_pll_data
*data
)
1123 struct bcm2835_pll
*pll
;
1124 struct clk_init_data init
;
1126 memset(&init
, 0, sizeof(init
));
1128 /* All of the PLLs derive from the external oscillator. */
1129 init
.parent_names
= &cprman
->osc_name
;
1130 init
.num_parents
= 1;
1131 init
.name
= data
->name
;
1132 init
.ops
= &bcm2835_pll_clk_ops
;
1133 init
.flags
= CLK_IGNORE_UNUSED
;
1135 pll
= kzalloc(sizeof(*pll
), GFP_KERNEL
);
1139 pll
->cprman
= cprman
;
1141 pll
->hw
.init
= &init
;
1143 return devm_clk_register(cprman
->dev
, &pll
->hw
);
1147 bcm2835_register_pll_divider(struct bcm2835_cprman
*cprman
,
1148 const struct bcm2835_pll_divider_data
*data
)
1150 struct bcm2835_pll_divider
*divider
;
1151 struct clk_init_data init
;
1153 const char *divider_name
;
1155 if (data
->fixed_divider
!= 1) {
1156 divider_name
= devm_kasprintf(cprman
->dev
, GFP_KERNEL
,
1157 "%s_prediv", data
->name
);
1161 divider_name
= data
->name
;
1164 memset(&init
, 0, sizeof(init
));
1166 init
.parent_names
= &data
->source_pll
;
1167 init
.num_parents
= 1;
1168 init
.name
= divider_name
;
1169 init
.ops
= &bcm2835_pll_divider_clk_ops
;
1170 init
.flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
;
1172 divider
= devm_kzalloc(cprman
->dev
, sizeof(*divider
), GFP_KERNEL
);
1176 divider
->div
.reg
= cprman
->regs
+ data
->a2w_reg
;
1177 divider
->div
.shift
= A2W_PLL_DIV_SHIFT
;
1178 divider
->div
.width
= A2W_PLL_DIV_BITS
;
1179 divider
->div
.flags
= CLK_DIVIDER_MAX_AT_ZERO
;
1180 divider
->div
.lock
= &cprman
->regs_lock
;
1181 divider
->div
.hw
.init
= &init
;
1182 divider
->div
.table
= NULL
;
1184 divider
->cprman
= cprman
;
1185 divider
->data
= data
;
1187 clk
= devm_clk_register(cprman
->dev
, ÷r
->div
.hw
);
1192 * PLLH's channels have a fixed divide by 10 afterwards, which
1193 * is what our consumers are actually using.
1195 if (data
->fixed_divider
!= 1) {
1196 return clk_register_fixed_factor(cprman
->dev
, data
->name
,
1198 CLK_SET_RATE_PARENT
,
1200 data
->fixed_divider
);
1206 static struct clk
*bcm2835_register_clock(struct bcm2835_cprman
*cprman
,
1207 const struct bcm2835_clock_data
*data
)
1209 struct bcm2835_clock
*clock
;
1210 struct clk_init_data init
;
1211 const char *parents
[1 << CM_SRC_BITS
];
1215 * Replace our "xosc" references with the oscillator's
1218 for (i
= 0; i
< data
->num_mux_parents
; i
++) {
1219 if (strcmp(data
->parents
[i
], "xosc") == 0)
1220 parents
[i
] = cprman
->osc_name
;
1222 parents
[i
] = data
->parents
[i
];
1225 memset(&init
, 0, sizeof(init
));
1226 init
.parent_names
= parents
;
1227 init
.num_parents
= data
->num_mux_parents
;
1228 init
.name
= data
->name
;
1229 init
.flags
= CLK_IGNORE_UNUSED
;
1231 if (data
->is_vpu_clock
) {
1232 init
.ops
= &bcm2835_vpu_clock_clk_ops
;
1234 init
.ops
= &bcm2835_clock_clk_ops
;
1235 init
.flags
|= CLK_SET_RATE_GATE
| CLK_SET_PARENT_GATE
;
1238 clock
= devm_kzalloc(cprman
->dev
, sizeof(*clock
), GFP_KERNEL
);
1242 clock
->cprman
= cprman
;
1244 clock
->hw
.init
= &init
;
1246 return devm_clk_register(cprman
->dev
, &clock
->hw
);
1249 static struct clk
*bcm2835_register_gate(struct bcm2835_cprman
*cprman
,
1250 const struct bcm2835_gate_data
*data
)
1252 return clk_register_gate(cprman
->dev
, data
->name
, data
->parent
,
1253 CLK_IGNORE_UNUSED
| CLK_SET_RATE_GATE
,
1254 cprman
->regs
+ data
->ctl_reg
,
1255 CM_GATE_BIT
, 0, &cprman
->regs_lock
);
1258 typedef struct clk
*(*bcm2835_clk_register
)(struct bcm2835_cprman
*cprman
,
1260 struct bcm2835_clk_desc
{
1261 bcm2835_clk_register clk_register
;
1265 /* assignment helper macros for different clock types */
1266 #define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
1267 .data = __VA_ARGS__ }
1268 #define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \
1269 &(struct bcm2835_pll_data) \
1271 #define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \
1272 &(struct bcm2835_pll_divider_data) \
1274 #define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \
1275 &(struct bcm2835_clock_data) \
1277 #define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \
1278 &(struct bcm2835_gate_data) \
1281 /* parent mux arrays plus helper macros */
1283 /* main oscillator parent mux */
1284 static const char *const bcm2835_clock_osc_parents
[] = {
1291 #define REGISTER_OSC_CLK(...) REGISTER_CLK( \
1292 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1293 .parents = bcm2835_clock_osc_parents, \
1296 /* main peripherial parent mux */
1297 static const char *const bcm2835_clock_per_parents
[] = {
1308 #define REGISTER_PER_CLK(...) REGISTER_CLK( \
1309 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1310 .parents = bcm2835_clock_per_parents, \
1313 /* main vpu parent mux */
1314 static const char *const bcm2835_clock_vpu_parents
[] = {
1327 #define REGISTER_VPU_CLK(...) REGISTER_CLK( \
1328 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1329 .parents = bcm2835_clock_vpu_parents, \
1333 * the real definition of all the pll, pll_dividers and clocks
1334 * these make use of the above REGISTER_* macros
1336 static const struct bcm2835_clk_desc clk_desc_array
[] = {
1337 /* the PLL + PLL dividers */
1340 * PLLA is the auxiliary PLL, used to drive the CCP2
1341 * (Compact Camera Port 2) transmitter clock.
1343 * It is in the PX LDO power domain, which is on when the
1344 * AUDIO domain is on.
1346 [BCM2835_PLLA
] = REGISTER_PLL(
1348 .cm_ctrl_reg
= CM_PLLA
,
1349 .a2w_ctrl_reg
= A2W_PLLA_CTRL
,
1350 .frac_reg
= A2W_PLLA_FRAC
,
1351 .ana_reg_base
= A2W_PLLA_ANA0
,
1352 .reference_enable_mask
= A2W_XOSC_CTRL_PLLA_ENABLE
,
1353 .lock_mask
= CM_LOCK_FLOCKA
,
1355 .ana
= &bcm2835_ana_default
,
1357 .min_rate
= 600000000u,
1358 .max_rate
= 2400000000u,
1359 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1360 [BCM2835_PLLA_CORE
] = REGISTER_PLL_DIV(
1361 .name
= "plla_core",
1362 .source_pll
= "plla",
1364 .a2w_reg
= A2W_PLLA_CORE
,
1365 .load_mask
= CM_PLLA_LOADCORE
,
1366 .hold_mask
= CM_PLLA_HOLDCORE
,
1367 .fixed_divider
= 1),
1368 [BCM2835_PLLA_PER
] = REGISTER_PLL_DIV(
1370 .source_pll
= "plla",
1372 .a2w_reg
= A2W_PLLA_PER
,
1373 .load_mask
= CM_PLLA_LOADPER
,
1374 .hold_mask
= CM_PLLA_HOLDPER
,
1375 .fixed_divider
= 1),
1376 [BCM2835_PLLA_DSI0
] = REGISTER_PLL_DIV(
1377 .name
= "plla_dsi0",
1378 .source_pll
= "plla",
1380 .a2w_reg
= A2W_PLLA_DSI0
,
1381 .load_mask
= CM_PLLA_LOADDSI0
,
1382 .hold_mask
= CM_PLLA_HOLDDSI0
,
1383 .fixed_divider
= 1),
1384 [BCM2835_PLLA_CCP2
] = REGISTER_PLL_DIV(
1385 .name
= "plla_ccp2",
1386 .source_pll
= "plla",
1388 .a2w_reg
= A2W_PLLA_CCP2
,
1389 .load_mask
= CM_PLLA_LOADCCP2
,
1390 .hold_mask
= CM_PLLA_HOLDCCP2
,
1391 .fixed_divider
= 1),
1393 /* PLLB is used for the ARM's clock. */
1394 [BCM2835_PLLB
] = REGISTER_PLL(
1396 .cm_ctrl_reg
= CM_PLLB
,
1397 .a2w_ctrl_reg
= A2W_PLLB_CTRL
,
1398 .frac_reg
= A2W_PLLB_FRAC
,
1399 .ana_reg_base
= A2W_PLLB_ANA0
,
1400 .reference_enable_mask
= A2W_XOSC_CTRL_PLLB_ENABLE
,
1401 .lock_mask
= CM_LOCK_FLOCKB
,
1403 .ana
= &bcm2835_ana_default
,
1405 .min_rate
= 600000000u,
1406 .max_rate
= 3000000000u,
1407 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1408 [BCM2835_PLLB_ARM
] = REGISTER_PLL_DIV(
1410 .source_pll
= "pllb",
1412 .a2w_reg
= A2W_PLLB_ARM
,
1413 .load_mask
= CM_PLLB_LOADARM
,
1414 .hold_mask
= CM_PLLB_HOLDARM
,
1415 .fixed_divider
= 1),
1418 * PLLC is the core PLL, used to drive the core VPU clock.
1420 * It is in the PX LDO power domain, which is on when the
1421 * AUDIO domain is on.
1423 [BCM2835_PLLC
] = REGISTER_PLL(
1425 .cm_ctrl_reg
= CM_PLLC
,
1426 .a2w_ctrl_reg
= A2W_PLLC_CTRL
,
1427 .frac_reg
= A2W_PLLC_FRAC
,
1428 .ana_reg_base
= A2W_PLLC_ANA0
,
1429 .reference_enable_mask
= A2W_XOSC_CTRL_PLLC_ENABLE
,
1430 .lock_mask
= CM_LOCK_FLOCKC
,
1432 .ana
= &bcm2835_ana_default
,
1434 .min_rate
= 600000000u,
1435 .max_rate
= 3000000000u,
1436 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1437 [BCM2835_PLLC_CORE0
] = REGISTER_PLL_DIV(
1438 .name
= "pllc_core0",
1439 .source_pll
= "pllc",
1441 .a2w_reg
= A2W_PLLC_CORE0
,
1442 .load_mask
= CM_PLLC_LOADCORE0
,
1443 .hold_mask
= CM_PLLC_HOLDCORE0
,
1444 .fixed_divider
= 1),
1445 [BCM2835_PLLC_CORE1
] = REGISTER_PLL_DIV(
1446 .name
= "pllc_core1",
1447 .source_pll
= "pllc",
1449 .a2w_reg
= A2W_PLLC_CORE1
,
1450 .load_mask
= CM_PLLC_LOADCORE1
,
1451 .hold_mask
= CM_PLLC_HOLDCORE1
,
1452 .fixed_divider
= 1),
1453 [BCM2835_PLLC_CORE2
] = REGISTER_PLL_DIV(
1454 .name
= "pllc_core2",
1455 .source_pll
= "pllc",
1457 .a2w_reg
= A2W_PLLC_CORE2
,
1458 .load_mask
= CM_PLLC_LOADCORE2
,
1459 .hold_mask
= CM_PLLC_HOLDCORE2
,
1460 .fixed_divider
= 1),
1461 [BCM2835_PLLC_PER
] = REGISTER_PLL_DIV(
1463 .source_pll
= "pllc",
1465 .a2w_reg
= A2W_PLLC_PER
,
1466 .load_mask
= CM_PLLC_LOADPER
,
1467 .hold_mask
= CM_PLLC_HOLDPER
,
1468 .fixed_divider
= 1),
1471 * PLLD is the display PLL, used to drive DSI display panels.
1473 * It is in the PX LDO power domain, which is on when the
1474 * AUDIO domain is on.
1476 [BCM2835_PLLD
] = REGISTER_PLL(
1478 .cm_ctrl_reg
= CM_PLLD
,
1479 .a2w_ctrl_reg
= A2W_PLLD_CTRL
,
1480 .frac_reg
= A2W_PLLD_FRAC
,
1481 .ana_reg_base
= A2W_PLLD_ANA0
,
1482 .reference_enable_mask
= A2W_XOSC_CTRL_DDR_ENABLE
,
1483 .lock_mask
= CM_LOCK_FLOCKD
,
1485 .ana
= &bcm2835_ana_default
,
1487 .min_rate
= 600000000u,
1488 .max_rate
= 2400000000u,
1489 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1490 [BCM2835_PLLD_CORE
] = REGISTER_PLL_DIV(
1491 .name
= "plld_core",
1492 .source_pll
= "plld",
1494 .a2w_reg
= A2W_PLLD_CORE
,
1495 .load_mask
= CM_PLLD_LOADCORE
,
1496 .hold_mask
= CM_PLLD_HOLDCORE
,
1497 .fixed_divider
= 1),
1498 [BCM2835_PLLD_PER
] = REGISTER_PLL_DIV(
1500 .source_pll
= "plld",
1502 .a2w_reg
= A2W_PLLD_PER
,
1503 .load_mask
= CM_PLLD_LOADPER
,
1504 .hold_mask
= CM_PLLD_HOLDPER
,
1505 .fixed_divider
= 1),
1506 [BCM2835_PLLD_DSI0
] = REGISTER_PLL_DIV(
1507 .name
= "plld_dsi0",
1508 .source_pll
= "plld",
1510 .a2w_reg
= A2W_PLLD_DSI0
,
1511 .load_mask
= CM_PLLD_LOADDSI0
,
1512 .hold_mask
= CM_PLLD_HOLDDSI0
,
1513 .fixed_divider
= 1),
1514 [BCM2835_PLLD_DSI1
] = REGISTER_PLL_DIV(
1515 .name
= "plld_dsi1",
1516 .source_pll
= "plld",
1518 .a2w_reg
= A2W_PLLD_DSI1
,
1519 .load_mask
= CM_PLLD_LOADDSI1
,
1520 .hold_mask
= CM_PLLD_HOLDDSI1
,
1521 .fixed_divider
= 1),
1524 * PLLH is used to supply the pixel clock or the AUX clock for the
1527 * It is in the HDMI power domain.
1529 [BCM2835_PLLH
] = REGISTER_PLL(
1531 .cm_ctrl_reg
= CM_PLLH
,
1532 .a2w_ctrl_reg
= A2W_PLLH_CTRL
,
1533 .frac_reg
= A2W_PLLH_FRAC
,
1534 .ana_reg_base
= A2W_PLLH_ANA0
,
1535 .reference_enable_mask
= A2W_XOSC_CTRL_PLLC_ENABLE
,
1536 .lock_mask
= CM_LOCK_FLOCKH
,
1538 .ana
= &bcm2835_ana_pllh
,
1540 .min_rate
= 600000000u,
1541 .max_rate
= 3000000000u,
1542 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1543 [BCM2835_PLLH_RCAL
] = REGISTER_PLL_DIV(
1544 .name
= "pllh_rcal",
1545 .source_pll
= "pllh",
1547 .a2w_reg
= A2W_PLLH_RCAL
,
1548 .load_mask
= CM_PLLH_LOADRCAL
,
1550 .fixed_divider
= 10),
1551 [BCM2835_PLLH_AUX
] = REGISTER_PLL_DIV(
1553 .source_pll
= "pllh",
1555 .a2w_reg
= A2W_PLLH_AUX
,
1556 .load_mask
= CM_PLLH_LOADAUX
,
1558 .fixed_divider
= 10),
1559 [BCM2835_PLLH_PIX
] = REGISTER_PLL_DIV(
1561 .source_pll
= "pllh",
1563 .a2w_reg
= A2W_PLLH_PIX
,
1564 .load_mask
= CM_PLLH_LOADPIX
,
1566 .fixed_divider
= 10),
1570 /* clocks with oscillator parent mux */
1572 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1573 [BCM2835_CLOCK_OTP
] = REGISTER_OSC_CLK(
1575 .ctl_reg
= CM_OTPCTL
,
1576 .div_reg
= CM_OTPDIV
,
1580 * Used for a 1Mhz clock for the system clocksource, and also used
1581 * bythe watchdog timer and the camera pulse generator.
1583 [BCM2835_CLOCK_TIMER
] = REGISTER_OSC_CLK(
1585 .ctl_reg
= CM_TIMERCTL
,
1586 .div_reg
= CM_TIMERDIV
,
1590 * Clock for the temperature sensor.
1591 * Generally run at 2Mhz, max 5Mhz.
1593 [BCM2835_CLOCK_TSENS
] = REGISTER_OSC_CLK(
1595 .ctl_reg
= CM_TSENSCTL
,
1596 .div_reg
= CM_TSENSDIV
,
1599 [BCM2835_CLOCK_TEC
] = REGISTER_OSC_CLK(
1601 .ctl_reg
= CM_TECCTL
,
1602 .div_reg
= CM_TECDIV
,
1606 /* clocks with vpu parent mux */
1607 [BCM2835_CLOCK_H264
] = REGISTER_VPU_CLK(
1609 .ctl_reg
= CM_H264CTL
,
1610 .div_reg
= CM_H264DIV
,
1613 [BCM2835_CLOCK_ISP
] = REGISTER_VPU_CLK(
1615 .ctl_reg
= CM_ISPCTL
,
1616 .div_reg
= CM_ISPDIV
,
1621 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
1622 * in the SDRAM controller can't be used.
1624 [BCM2835_CLOCK_SDRAM
] = REGISTER_VPU_CLK(
1626 .ctl_reg
= CM_SDCCTL
,
1627 .div_reg
= CM_SDCDIV
,
1630 [BCM2835_CLOCK_V3D
] = REGISTER_VPU_CLK(
1632 .ctl_reg
= CM_V3DCTL
,
1633 .div_reg
= CM_V3DDIV
,
1637 * VPU clock. This doesn't have an enable bit, since it drives
1638 * the bus for everything else, and is special so it doesn't need
1639 * to be gated for rate changes. It is also known as "clk_audio"
1640 * in various hardware documentation.
1642 [BCM2835_CLOCK_VPU
] = REGISTER_VPU_CLK(
1644 .ctl_reg
= CM_VPUCTL
,
1645 .div_reg
= CM_VPUDIV
,
1648 .is_vpu_clock
= true),
1650 /* clocks with per parent mux */
1651 [BCM2835_CLOCK_AVEO
] = REGISTER_PER_CLK(
1653 .ctl_reg
= CM_AVEOCTL
,
1654 .div_reg
= CM_AVEODIV
,
1657 [BCM2835_CLOCK_CAM0
] = REGISTER_PER_CLK(
1659 .ctl_reg
= CM_CAM0CTL
,
1660 .div_reg
= CM_CAM0DIV
,
1663 [BCM2835_CLOCK_CAM1
] = REGISTER_PER_CLK(
1665 .ctl_reg
= CM_CAM1CTL
,
1666 .div_reg
= CM_CAM1DIV
,
1669 [BCM2835_CLOCK_DFT
] = REGISTER_PER_CLK(
1671 .ctl_reg
= CM_DFTCTL
,
1672 .div_reg
= CM_DFTDIV
,
1675 [BCM2835_CLOCK_DPI
] = REGISTER_PER_CLK(
1677 .ctl_reg
= CM_DPICTL
,
1678 .div_reg
= CM_DPIDIV
,
1682 /* Arasan EMMC clock */
1683 [BCM2835_CLOCK_EMMC
] = REGISTER_PER_CLK(
1685 .ctl_reg
= CM_EMMCCTL
,
1686 .div_reg
= CM_EMMCDIV
,
1690 /* General purpose (GPIO) clocks */
1691 [BCM2835_CLOCK_GP0
] = REGISTER_PER_CLK(
1693 .ctl_reg
= CM_GP0CTL
,
1694 .div_reg
= CM_GP0DIV
,
1697 .is_mash_clock
= true),
1698 [BCM2835_CLOCK_GP1
] = REGISTER_PER_CLK(
1700 .ctl_reg
= CM_GP1CTL
,
1701 .div_reg
= CM_GP1DIV
,
1704 .is_mash_clock
= true),
1705 [BCM2835_CLOCK_GP2
] = REGISTER_PER_CLK(
1707 .ctl_reg
= CM_GP2CTL
,
1708 .div_reg
= CM_GP2DIV
,
1712 /* HDMI state machine */
1713 [BCM2835_CLOCK_HSM
] = REGISTER_PER_CLK(
1715 .ctl_reg
= CM_HSMCTL
,
1716 .div_reg
= CM_HSMDIV
,
1719 [BCM2835_CLOCK_PCM
] = REGISTER_PER_CLK(
1721 .ctl_reg
= CM_PCMCTL
,
1722 .div_reg
= CM_PCMDIV
,
1725 .is_mash_clock
= true),
1726 [BCM2835_CLOCK_PWM
] = REGISTER_PER_CLK(
1728 .ctl_reg
= CM_PWMCTL
,
1729 .div_reg
= CM_PWMDIV
,
1732 .is_mash_clock
= true),
1733 [BCM2835_CLOCK_SLIM
] = REGISTER_PER_CLK(
1735 .ctl_reg
= CM_SLIMCTL
,
1736 .div_reg
= CM_SLIMDIV
,
1739 .is_mash_clock
= true),
1740 [BCM2835_CLOCK_SMI
] = REGISTER_PER_CLK(
1742 .ctl_reg
= CM_SMICTL
,
1743 .div_reg
= CM_SMIDIV
,
1746 [BCM2835_CLOCK_UART
] = REGISTER_PER_CLK(
1748 .ctl_reg
= CM_UARTCTL
,
1749 .div_reg
= CM_UARTDIV
,
1753 /* TV encoder clock. Only operating frequency is 108Mhz. */
1754 [BCM2835_CLOCK_VEC
] = REGISTER_PER_CLK(
1756 .ctl_reg
= CM_VECCTL
,
1757 .div_reg
= CM_VECDIV
,
1762 [BCM2835_CLOCK_DSI0E
] = REGISTER_PER_CLK(
1764 .ctl_reg
= CM_DSI0ECTL
,
1765 .div_reg
= CM_DSI0EDIV
,
1768 [BCM2835_CLOCK_DSI1E
] = REGISTER_PER_CLK(
1770 .ctl_reg
= CM_DSI1ECTL
,
1771 .div_reg
= CM_DSI1EDIV
,
1778 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
1779 * you have the debug bit set in the power manager, which we
1780 * don't bother exposing) are individual gates off of the
1781 * non-stop vpu clock.
1783 [BCM2835_CLOCK_PERI_IMAGE
] = REGISTER_GATE(
1784 .name
= "peri_image",
1786 .ctl_reg
= CM_PERIICTL
),
1789 static int bcm2835_clk_probe(struct platform_device
*pdev
)
1791 struct device
*dev
= &pdev
->dev
;
1793 struct bcm2835_cprman
*cprman
;
1794 struct resource
*res
;
1795 const struct bcm2835_clk_desc
*desc
;
1796 const size_t asize
= ARRAY_SIZE(clk_desc_array
);
1799 cprman
= devm_kzalloc(dev
,
1800 sizeof(*cprman
) + asize
* sizeof(*clks
),
1805 spin_lock_init(&cprman
->regs_lock
);
1807 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1808 cprman
->regs
= devm_ioremap_resource(dev
, res
);
1809 if (IS_ERR(cprman
->regs
))
1810 return PTR_ERR(cprman
->regs
);
1812 cprman
->osc_name
= of_clk_get_parent_name(dev
->of_node
, 0);
1813 if (!cprman
->osc_name
)
1816 platform_set_drvdata(pdev
, cprman
);
1818 cprman
->onecell
.clk_num
= asize
;
1819 cprman
->onecell
.clks
= cprman
->clks
;
1820 clks
= cprman
->clks
;
1822 for (i
= 0; i
< asize
; i
++) {
1823 desc
= &clk_desc_array
[i
];
1824 if (desc
->clk_register
&& desc
->data
)
1825 clks
[i
] = desc
->clk_register(cprman
, desc
->data
);
1828 return of_clk_add_provider(dev
->of_node
, of_clk_src_onecell_get
,
1832 static const struct of_device_id bcm2835_clk_of_match
[] = {
1833 { .compatible
= "brcm,bcm2835-cprman", },
1836 MODULE_DEVICE_TABLE(of
, bcm2835_clk_of_match
);
1838 static struct platform_driver bcm2835_clk_driver
= {
1840 .name
= "bcm2835-clk",
1841 .of_match_table
= bcm2835_clk_of_match
,
1843 .probe
= bcm2835_clk_probe
,
1846 builtin_platform_driver(bcm2835_clk_driver
);
1848 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
1849 MODULE_DESCRIPTION("BCM2835 clock driver");
1850 MODULE_LICENSE("GPL v2");