2 * Copyright (C) 2010,2015 Broadcom
3 * Copyright (C) 2012 Stephen Warren
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
18 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
20 * The clock tree on the 2835 has several levels. There's a root
21 * oscillator running at 19.2Mhz. After the oscillator there are 5
22 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
23 * and "HDMI displays". Those 5 PLLs each can divide their output to
24 * produce up to 4 channels. Finally, there is the level of clocks to
25 * be consumed by other hardware components (like "H264" or "HDMI
26 * state machine"), which divide off of some subset of the PLL
29 * All of the clocks in the tree are exposed in the DT, because the DT
30 * may want to make assignments of the final layer of clocks to the
31 * PLL channels, and some components of the hardware will actually
32 * skip layers of the tree (for example, the pixel clock comes
33 * directly from the PLLH PIX channel without using a CM_*CTL clock
37 #include <linux/clk-provider.h>
38 #include <linux/clkdev.h>
39 #include <linux/clk.h>
40 #include <linux/clk/bcm2835.h>
41 #include <linux/debugfs.h>
42 #include <linux/module.h>
44 #include <linux/platform_device.h>
45 #include <linux/slab.h>
46 #include <dt-bindings/clock/bcm2835.h>
48 #define CM_PASSWORD 0x5a000000
50 #define CM_GNRICCTL 0x000
51 #define CM_GNRICDIV 0x004
52 # define CM_DIV_FRAC_BITS 12
53 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
55 #define CM_VPUCTL 0x008
56 #define CM_VPUDIV 0x00c
57 #define CM_SYSCTL 0x010
58 #define CM_SYSDIV 0x014
59 #define CM_PERIACTL 0x018
60 #define CM_PERIADIV 0x01c
61 #define CM_PERIICTL 0x020
62 #define CM_PERIIDIV 0x024
63 #define CM_H264CTL 0x028
64 #define CM_H264DIV 0x02c
65 #define CM_ISPCTL 0x030
66 #define CM_ISPDIV 0x034
67 #define CM_V3DCTL 0x038
68 #define CM_V3DDIV 0x03c
69 #define CM_CAM0CTL 0x040
70 #define CM_CAM0DIV 0x044
71 #define CM_CAM1CTL 0x048
72 #define CM_CAM1DIV 0x04c
73 #define CM_CCP2CTL 0x050
74 #define CM_CCP2DIV 0x054
75 #define CM_DSI0ECTL 0x058
76 #define CM_DSI0EDIV 0x05c
77 #define CM_DSI0PCTL 0x060
78 #define CM_DSI0PDIV 0x064
79 #define CM_DPICTL 0x068
80 #define CM_DPIDIV 0x06c
81 #define CM_GP0CTL 0x070
82 #define CM_GP0DIV 0x074
83 #define CM_GP1CTL 0x078
84 #define CM_GP1DIV 0x07c
85 #define CM_GP2CTL 0x080
86 #define CM_GP2DIV 0x084
87 #define CM_HSMCTL 0x088
88 #define CM_HSMDIV 0x08c
89 #define CM_OTPCTL 0x090
90 #define CM_OTPDIV 0x094
91 #define CM_PCMCTL 0x098
92 #define CM_PCMDIV 0x09c
93 #define CM_PWMCTL 0x0a0
94 #define CM_PWMDIV 0x0a4
95 #define CM_SLIMCTL 0x0a8
96 #define CM_SLIMDIV 0x0ac
97 #define CM_SMICTL 0x0b0
98 #define CM_SMIDIV 0x0b4
99 /* no definition for 0x0b8 and 0x0bc */
100 #define CM_TCNTCTL 0x0c0
101 #define CM_TCNTDIV 0x0c4
102 #define CM_TECCTL 0x0c8
103 #define CM_TECDIV 0x0cc
104 #define CM_TD0CTL 0x0d0
105 #define CM_TD0DIV 0x0d4
106 #define CM_TD1CTL 0x0d8
107 #define CM_TD1DIV 0x0dc
108 #define CM_TSENSCTL 0x0e0
109 #define CM_TSENSDIV 0x0e4
110 #define CM_TIMERCTL 0x0e8
111 #define CM_TIMERDIV 0x0ec
112 #define CM_UARTCTL 0x0f0
113 #define CM_UARTDIV 0x0f4
114 #define CM_VECCTL 0x0f8
115 #define CM_VECDIV 0x0fc
116 #define CM_PULSECTL 0x190
117 #define CM_PULSEDIV 0x194
118 #define CM_SDCCTL 0x1a8
119 #define CM_SDCDIV 0x1ac
120 #define CM_ARMCTL 0x1b0
121 #define CM_AVEOCTL 0x1b8
122 #define CM_AVEODIV 0x1bc
123 #define CM_EMMCCTL 0x1c0
124 #define CM_EMMCDIV 0x1c4
126 /* General bits for the CM_*CTL regs */
127 # define CM_ENABLE BIT(4)
128 # define CM_KILL BIT(5)
129 # define CM_GATE_BIT 6
130 # define CM_GATE BIT(CM_GATE_BIT)
131 # define CM_BUSY BIT(7)
132 # define CM_BUSYD BIT(8)
133 # define CM_FRAC BIT(9)
134 # define CM_SRC_SHIFT 0
135 # define CM_SRC_BITS 4
136 # define CM_SRC_MASK 0xf
137 # define CM_SRC_GND 0
138 # define CM_SRC_OSC 1
139 # define CM_SRC_TESTDEBUG0 2
140 # define CM_SRC_TESTDEBUG1 3
141 # define CM_SRC_PLLA_CORE 4
142 # define CM_SRC_PLLA_PER 4
143 # define CM_SRC_PLLC_CORE0 5
144 # define CM_SRC_PLLC_PER 5
145 # define CM_SRC_PLLC_CORE1 8
146 # define CM_SRC_PLLD_CORE 6
147 # define CM_SRC_PLLD_PER 6
148 # define CM_SRC_PLLH_AUX 7
149 # define CM_SRC_PLLC_CORE1 8
150 # define CM_SRC_PLLC_CORE2 9
152 #define CM_OSCCOUNT 0x100
154 #define CM_PLLA 0x104
155 # define CM_PLL_ANARST BIT(8)
156 # define CM_PLLA_HOLDPER BIT(7)
157 # define CM_PLLA_LOADPER BIT(6)
158 # define CM_PLLA_HOLDCORE BIT(5)
159 # define CM_PLLA_LOADCORE BIT(4)
160 # define CM_PLLA_HOLDCCP2 BIT(3)
161 # define CM_PLLA_LOADCCP2 BIT(2)
162 # define CM_PLLA_HOLDDSI0 BIT(1)
163 # define CM_PLLA_LOADDSI0 BIT(0)
165 #define CM_PLLC 0x108
166 # define CM_PLLC_HOLDPER BIT(7)
167 # define CM_PLLC_LOADPER BIT(6)
168 # define CM_PLLC_HOLDCORE2 BIT(5)
169 # define CM_PLLC_LOADCORE2 BIT(4)
170 # define CM_PLLC_HOLDCORE1 BIT(3)
171 # define CM_PLLC_LOADCORE1 BIT(2)
172 # define CM_PLLC_HOLDCORE0 BIT(1)
173 # define CM_PLLC_LOADCORE0 BIT(0)
175 #define CM_PLLD 0x10c
176 # define CM_PLLD_HOLDPER BIT(7)
177 # define CM_PLLD_LOADPER BIT(6)
178 # define CM_PLLD_HOLDCORE BIT(5)
179 # define CM_PLLD_LOADCORE BIT(4)
180 # define CM_PLLD_HOLDDSI1 BIT(3)
181 # define CM_PLLD_LOADDSI1 BIT(2)
182 # define CM_PLLD_HOLDDSI0 BIT(1)
183 # define CM_PLLD_LOADDSI0 BIT(0)
185 #define CM_PLLH 0x110
186 # define CM_PLLH_LOADRCAL BIT(2)
187 # define CM_PLLH_LOADAUX BIT(1)
188 # define CM_PLLH_LOADPIX BIT(0)
190 #define CM_LOCK 0x114
191 # define CM_LOCK_FLOCKH BIT(12)
192 # define CM_LOCK_FLOCKD BIT(11)
193 # define CM_LOCK_FLOCKC BIT(10)
194 # define CM_LOCK_FLOCKB BIT(9)
195 # define CM_LOCK_FLOCKA BIT(8)
197 #define CM_EVENT 0x118
198 #define CM_DSI1ECTL 0x158
199 #define CM_DSI1EDIV 0x15c
200 #define CM_DSI1PCTL 0x160
201 #define CM_DSI1PDIV 0x164
202 #define CM_DFTCTL 0x168
203 #define CM_DFTDIV 0x16c
205 #define CM_PLLB 0x170
206 # define CM_PLLB_HOLDARM BIT(1)
207 # define CM_PLLB_LOADARM BIT(0)
209 #define A2W_PLLA_CTRL 0x1100
210 #define A2W_PLLC_CTRL 0x1120
211 #define A2W_PLLD_CTRL 0x1140
212 #define A2W_PLLH_CTRL 0x1160
213 #define A2W_PLLB_CTRL 0x11e0
214 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
215 # define A2W_PLL_CTRL_PWRDN BIT(16)
216 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000
217 # define A2W_PLL_CTRL_PDIV_SHIFT 12
218 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
219 # define A2W_PLL_CTRL_NDIV_SHIFT 0
221 #define A2W_PLLA_ANA0 0x1010
222 #define A2W_PLLC_ANA0 0x1030
223 #define A2W_PLLD_ANA0 0x1050
224 #define A2W_PLLH_ANA0 0x1070
225 #define A2W_PLLB_ANA0 0x10f0
227 #define A2W_PLL_KA_SHIFT 7
228 #define A2W_PLL_KA_MASK GENMASK(9, 7)
229 #define A2W_PLL_KI_SHIFT 19
230 #define A2W_PLL_KI_MASK GENMASK(21, 19)
231 #define A2W_PLL_KP_SHIFT 15
232 #define A2W_PLL_KP_MASK GENMASK(18, 15)
234 #define A2W_PLLH_KA_SHIFT 19
235 #define A2W_PLLH_KA_MASK GENMASK(21, 19)
236 #define A2W_PLLH_KI_LOW_SHIFT 22
237 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
238 #define A2W_PLLH_KI_HIGH_SHIFT 0
239 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
240 #define A2W_PLLH_KP_SHIFT 1
241 #define A2W_PLLH_KP_MASK GENMASK(4, 1)
243 #define A2W_XOSC_CTRL 0x1190
244 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
245 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
246 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
247 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
248 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
249 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
250 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
251 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
253 #define A2W_PLLA_FRAC 0x1200
254 #define A2W_PLLC_FRAC 0x1220
255 #define A2W_PLLD_FRAC 0x1240
256 #define A2W_PLLH_FRAC 0x1260
257 #define A2W_PLLB_FRAC 0x12e0
258 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
259 # define A2W_PLL_FRAC_BITS 20
261 #define A2W_PLL_CHANNEL_DISABLE BIT(8)
262 #define A2W_PLL_DIV_BITS 8
263 #define A2W_PLL_DIV_SHIFT 0
265 #define A2W_PLLA_DSI0 0x1300
266 #define A2W_PLLA_CORE 0x1400
267 #define A2W_PLLA_PER 0x1500
268 #define A2W_PLLA_CCP2 0x1600
270 #define A2W_PLLC_CORE2 0x1320
271 #define A2W_PLLC_CORE1 0x1420
272 #define A2W_PLLC_PER 0x1520
273 #define A2W_PLLC_CORE0 0x1620
275 #define A2W_PLLD_DSI0 0x1340
276 #define A2W_PLLD_CORE 0x1440
277 #define A2W_PLLD_PER 0x1540
278 #define A2W_PLLD_DSI1 0x1640
280 #define A2W_PLLH_AUX 0x1360
281 #define A2W_PLLH_RCAL 0x1460
282 #define A2W_PLLH_PIX 0x1560
283 #define A2W_PLLH_STS 0x1660
285 #define A2W_PLLH_CTRLR 0x1960
286 #define A2W_PLLH_FRACR 0x1a60
287 #define A2W_PLLH_AUXR 0x1b60
288 #define A2W_PLLH_RCALR 0x1c60
289 #define A2W_PLLH_PIXR 0x1d60
290 #define A2W_PLLH_STSR 0x1e60
292 #define A2W_PLLB_ARM 0x13e0
293 #define A2W_PLLB_SP0 0x14e0
294 #define A2W_PLLB_SP1 0x15e0
295 #define A2W_PLLB_SP2 0x16e0
297 #define LOCK_TIMEOUT_NS 100000000
298 #define BCM2835_MAX_FB_RATE 1750000000u
300 struct bcm2835_cprman
{
303 spinlock_t regs_lock
; /* spinlock for all clocks */
304 const char *osc_name
;
307 struct clk_hw_onecell_data onecell
;
310 static inline void cprman_write(struct bcm2835_cprman
*cprman
, u32 reg
, u32 val
)
312 writel(CM_PASSWORD
| val
, cprman
->regs
+ reg
);
315 static inline u32
cprman_read(struct bcm2835_cprman
*cprman
, u32 reg
)
317 return readl(cprman
->regs
+ reg
);
320 static int bcm2835_debugfs_regset(struct bcm2835_cprman
*cprman
, u32 base
,
321 struct debugfs_reg32
*regs
, size_t nregs
,
322 struct dentry
*dentry
)
324 struct dentry
*regdump
;
325 struct debugfs_regset32
*regset
;
327 regset
= devm_kzalloc(cprman
->dev
, sizeof(*regset
), GFP_KERNEL
);
332 regset
->nregs
= nregs
;
333 regset
->base
= cprman
->regs
+ base
;
335 regdump
= debugfs_create_regset32("regdump", S_IRUGO
, dentry
,
338 return regdump
? 0 : -ENOMEM
;
342 * These are fixed clocks. They're probably not all root clocks and it may
343 * be possible to turn them on and off but until this is mapped out better
344 * it's the only way they can be used.
346 void __init
bcm2835_init_clocks(void)
351 hw
= clk_hw_register_fixed_rate(NULL
, "apb_pclk", NULL
, 0, 126000000);
353 pr_err("apb_pclk not registered\n");
355 hw
= clk_hw_register_fixed_rate(NULL
, "uart0_pclk", NULL
, 0, 3000000);
357 pr_err("uart0_pclk not registered\n");
358 ret
= clk_hw_register_clkdev(hw
, NULL
, "20201000.uart");
360 pr_err("uart0_pclk alias not registered\n");
362 hw
= clk_hw_register_fixed_rate(NULL
, "uart1_pclk", NULL
, 0, 125000000);
364 pr_err("uart1_pclk not registered\n");
365 ret
= clk_hw_register_clkdev(hw
, NULL
, "20215000.uart");
367 pr_err("uart1_pclk alias not registered\n");
370 struct bcm2835_pll_data
{
376 u32 reference_enable_mask
;
377 /* Bit in CM_LOCK to indicate when the PLL has locked. */
380 const struct bcm2835_pll_ana_bits
*ana
;
382 unsigned long min_rate
;
383 unsigned long max_rate
;
385 * Highest rate for the VCO before we have to use the
388 unsigned long max_fb_rate
;
391 struct bcm2835_pll_ana_bits
{
401 static const struct bcm2835_pll_ana_bits bcm2835_ana_default
= {
404 .mask1
= (u32
)~(A2W_PLL_KI_MASK
| A2W_PLL_KP_MASK
),
405 .set1
= (2 << A2W_PLL_KI_SHIFT
) | (8 << A2W_PLL_KP_SHIFT
),
406 .mask3
= (u32
)~A2W_PLL_KA_MASK
,
407 .set3
= (2 << A2W_PLL_KA_SHIFT
),
408 .fb_prediv_mask
= BIT(14),
411 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh
= {
412 .mask0
= (u32
)~(A2W_PLLH_KA_MASK
| A2W_PLLH_KI_LOW_MASK
),
413 .set0
= (2 << A2W_PLLH_KA_SHIFT
) | (2 << A2W_PLLH_KI_LOW_SHIFT
),
414 .mask1
= (u32
)~(A2W_PLLH_KI_HIGH_MASK
| A2W_PLLH_KP_MASK
),
415 .set1
= (6 << A2W_PLLH_KP_SHIFT
),
418 .fb_prediv_mask
= BIT(11),
421 struct bcm2835_pll_divider_data
{
423 const char *source_pll
;
433 struct bcm2835_clock_data
{
436 const char *const *parents
;
442 /* Number of integer bits in the divider */
444 /* Number of fractional bits in the divider */
453 struct bcm2835_gate_data
{
462 struct bcm2835_cprman
*cprman
;
463 const struct bcm2835_pll_data
*data
;
466 static int bcm2835_pll_is_on(struct clk_hw
*hw
)
468 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
469 struct bcm2835_cprman
*cprman
= pll
->cprman
;
470 const struct bcm2835_pll_data
*data
= pll
->data
;
472 return cprman_read(cprman
, data
->a2w_ctrl_reg
) &
473 A2W_PLL_CTRL_PRST_DISABLE
;
476 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate
,
477 unsigned long parent_rate
,
478 u32
*ndiv
, u32
*fdiv
)
482 div
= (u64
)rate
<< A2W_PLL_FRAC_BITS
;
483 do_div(div
, parent_rate
);
485 *ndiv
= div
>> A2W_PLL_FRAC_BITS
;
486 *fdiv
= div
& ((1 << A2W_PLL_FRAC_BITS
) - 1);
489 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate
,
490 u32 ndiv
, u32 fdiv
, u32 pdiv
)
497 rate
= (u64
)parent_rate
* ((ndiv
<< A2W_PLL_FRAC_BITS
) + fdiv
);
499 return rate
>> A2W_PLL_FRAC_BITS
;
502 static long bcm2835_pll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
503 unsigned long *parent_rate
)
505 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
506 const struct bcm2835_pll_data
*data
= pll
->data
;
509 rate
= clamp(rate
, data
->min_rate
, data
->max_rate
);
511 bcm2835_pll_choose_ndiv_and_fdiv(rate
, *parent_rate
, &ndiv
, &fdiv
);
513 return bcm2835_pll_rate_from_divisors(*parent_rate
, ndiv
, fdiv
, 1);
516 static unsigned long bcm2835_pll_get_rate(struct clk_hw
*hw
,
517 unsigned long parent_rate
)
519 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
520 struct bcm2835_cprman
*cprman
= pll
->cprman
;
521 const struct bcm2835_pll_data
*data
= pll
->data
;
522 u32 a2wctrl
= cprman_read(cprman
, data
->a2w_ctrl_reg
);
523 u32 ndiv
, pdiv
, fdiv
;
526 if (parent_rate
== 0)
529 fdiv
= cprman_read(cprman
, data
->frac_reg
) & A2W_PLL_FRAC_MASK
;
530 ndiv
= (a2wctrl
& A2W_PLL_CTRL_NDIV_MASK
) >> A2W_PLL_CTRL_NDIV_SHIFT
;
531 pdiv
= (a2wctrl
& A2W_PLL_CTRL_PDIV_MASK
) >> A2W_PLL_CTRL_PDIV_SHIFT
;
532 using_prediv
= cprman_read(cprman
, data
->ana_reg_base
+ 4) &
533 data
->ana
->fb_prediv_mask
;
538 return bcm2835_pll_rate_from_divisors(parent_rate
, ndiv
, fdiv
, pdiv
);
541 static void bcm2835_pll_off(struct clk_hw
*hw
)
543 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
544 struct bcm2835_cprman
*cprman
= pll
->cprman
;
545 const struct bcm2835_pll_data
*data
= pll
->data
;
547 spin_lock(&cprman
->regs_lock
);
548 cprman_write(cprman
, data
->cm_ctrl_reg
,
549 cprman_read(cprman
, data
->cm_ctrl_reg
) |
551 cprman_write(cprman
, data
->a2w_ctrl_reg
,
552 cprman_read(cprman
, data
->a2w_ctrl_reg
) |
554 spin_unlock(&cprman
->regs_lock
);
557 static int bcm2835_pll_on(struct clk_hw
*hw
)
559 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
560 struct bcm2835_cprman
*cprman
= pll
->cprman
;
561 const struct bcm2835_pll_data
*data
= pll
->data
;
564 cprman_write(cprman
, data
->a2w_ctrl_reg
,
565 cprman_read(cprman
, data
->a2w_ctrl_reg
) &
566 ~A2W_PLL_CTRL_PWRDN
);
568 /* Take the PLL out of reset. */
569 cprman_write(cprman
, data
->cm_ctrl_reg
,
570 cprman_read(cprman
, data
->cm_ctrl_reg
) & ~CM_PLL_ANARST
);
572 /* Wait for the PLL to lock. */
573 timeout
= ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS
);
574 while (!(cprman_read(cprman
, CM_LOCK
) & data
->lock_mask
)) {
575 if (ktime_after(ktime_get(), timeout
)) {
576 dev_err(cprman
->dev
, "%s: couldn't lock PLL\n",
577 clk_hw_get_name(hw
));
588 bcm2835_pll_write_ana(struct bcm2835_cprman
*cprman
, u32 ana_reg_base
, u32
*ana
)
593 * ANA register setup is done as a series of writes to
594 * ANA3-ANA0, in that order. This lets us write all 4
595 * registers as a single cycle of the serdes interface (taking
596 * 100 xosc clocks), whereas if we were to update ana0, 1, and
597 * 3 individually through their partial-write registers, each
598 * would be their own serdes cycle.
600 for (i
= 3; i
>= 0; i
--)
601 cprman_write(cprman
, ana_reg_base
+ i
* 4, ana
[i
]);
604 static int bcm2835_pll_set_rate(struct clk_hw
*hw
,
605 unsigned long rate
, unsigned long parent_rate
)
607 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
608 struct bcm2835_cprman
*cprman
= pll
->cprman
;
609 const struct bcm2835_pll_data
*data
= pll
->data
;
610 bool was_using_prediv
, use_fb_prediv
, do_ana_setup_first
;
611 u32 ndiv
, fdiv
, a2w_ctl
;
615 if (rate
> data
->max_fb_rate
) {
616 use_fb_prediv
= true;
619 use_fb_prediv
= false;
622 bcm2835_pll_choose_ndiv_and_fdiv(rate
, parent_rate
, &ndiv
, &fdiv
);
624 for (i
= 3; i
>= 0; i
--)
625 ana
[i
] = cprman_read(cprman
, data
->ana_reg_base
+ i
* 4);
627 was_using_prediv
= ana
[1] & data
->ana
->fb_prediv_mask
;
629 ana
[0] &= ~data
->ana
->mask0
;
630 ana
[0] |= data
->ana
->set0
;
631 ana
[1] &= ~data
->ana
->mask1
;
632 ana
[1] |= data
->ana
->set1
;
633 ana
[3] &= ~data
->ana
->mask3
;
634 ana
[3] |= data
->ana
->set3
;
636 if (was_using_prediv
&& !use_fb_prediv
) {
637 ana
[1] &= ~data
->ana
->fb_prediv_mask
;
638 do_ana_setup_first
= true;
639 } else if (!was_using_prediv
&& use_fb_prediv
) {
640 ana
[1] |= data
->ana
->fb_prediv_mask
;
641 do_ana_setup_first
= false;
643 do_ana_setup_first
= true;
646 /* Unmask the reference clock from the oscillator. */
647 cprman_write(cprman
, A2W_XOSC_CTRL
,
648 cprman_read(cprman
, A2W_XOSC_CTRL
) |
649 data
->reference_enable_mask
);
651 if (do_ana_setup_first
)
652 bcm2835_pll_write_ana(cprman
, data
->ana_reg_base
, ana
);
654 /* Set the PLL multiplier from the oscillator. */
655 cprman_write(cprman
, data
->frac_reg
, fdiv
);
657 a2w_ctl
= cprman_read(cprman
, data
->a2w_ctrl_reg
);
658 a2w_ctl
&= ~A2W_PLL_CTRL_NDIV_MASK
;
659 a2w_ctl
|= ndiv
<< A2W_PLL_CTRL_NDIV_SHIFT
;
660 a2w_ctl
&= ~A2W_PLL_CTRL_PDIV_MASK
;
661 a2w_ctl
|= 1 << A2W_PLL_CTRL_PDIV_SHIFT
;
662 cprman_write(cprman
, data
->a2w_ctrl_reg
, a2w_ctl
);
664 if (!do_ana_setup_first
)
665 bcm2835_pll_write_ana(cprman
, data
->ana_reg_base
, ana
);
670 static int bcm2835_pll_debug_init(struct clk_hw
*hw
,
671 struct dentry
*dentry
)
673 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
674 struct bcm2835_cprman
*cprman
= pll
->cprman
;
675 const struct bcm2835_pll_data
*data
= pll
->data
;
676 struct debugfs_reg32
*regs
;
678 regs
= devm_kzalloc(cprman
->dev
, 7 * sizeof(*regs
), GFP_KERNEL
);
682 regs
[0].name
= "cm_ctrl";
683 regs
[0].offset
= data
->cm_ctrl_reg
;
684 regs
[1].name
= "a2w_ctrl";
685 regs
[1].offset
= data
->a2w_ctrl_reg
;
686 regs
[2].name
= "frac";
687 regs
[2].offset
= data
->frac_reg
;
688 regs
[3].name
= "ana0";
689 regs
[3].offset
= data
->ana_reg_base
+ 0 * 4;
690 regs
[4].name
= "ana1";
691 regs
[4].offset
= data
->ana_reg_base
+ 1 * 4;
692 regs
[5].name
= "ana2";
693 regs
[5].offset
= data
->ana_reg_base
+ 2 * 4;
694 regs
[6].name
= "ana3";
695 regs
[6].offset
= data
->ana_reg_base
+ 3 * 4;
697 return bcm2835_debugfs_regset(cprman
, 0, regs
, 7, dentry
);
700 static const struct clk_ops bcm2835_pll_clk_ops
= {
701 .is_prepared
= bcm2835_pll_is_on
,
702 .prepare
= bcm2835_pll_on
,
703 .unprepare
= bcm2835_pll_off
,
704 .recalc_rate
= bcm2835_pll_get_rate
,
705 .set_rate
= bcm2835_pll_set_rate
,
706 .round_rate
= bcm2835_pll_round_rate
,
707 .debug_init
= bcm2835_pll_debug_init
,
710 struct bcm2835_pll_divider
{
711 struct clk_divider div
;
712 struct bcm2835_cprman
*cprman
;
713 const struct bcm2835_pll_divider_data
*data
;
716 static struct bcm2835_pll_divider
*
717 bcm2835_pll_divider_from_hw(struct clk_hw
*hw
)
719 return container_of(hw
, struct bcm2835_pll_divider
, div
.hw
);
722 static int bcm2835_pll_divider_is_on(struct clk_hw
*hw
)
724 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
725 struct bcm2835_cprman
*cprman
= divider
->cprman
;
726 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
728 return !(cprman_read(cprman
, data
->a2w_reg
) & A2W_PLL_CHANNEL_DISABLE
);
731 static long bcm2835_pll_divider_round_rate(struct clk_hw
*hw
,
733 unsigned long *parent_rate
)
735 return clk_divider_ops
.round_rate(hw
, rate
, parent_rate
);
738 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw
*hw
,
739 unsigned long parent_rate
)
741 return clk_divider_ops
.recalc_rate(hw
, parent_rate
);
744 static void bcm2835_pll_divider_off(struct clk_hw
*hw
)
746 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
747 struct bcm2835_cprman
*cprman
= divider
->cprman
;
748 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
750 spin_lock(&cprman
->regs_lock
);
751 cprman_write(cprman
, data
->cm_reg
,
752 (cprman_read(cprman
, data
->cm_reg
) &
753 ~data
->load_mask
) | data
->hold_mask
);
754 cprman_write(cprman
, data
->a2w_reg
, A2W_PLL_CHANNEL_DISABLE
);
755 spin_unlock(&cprman
->regs_lock
);
758 static int bcm2835_pll_divider_on(struct clk_hw
*hw
)
760 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
761 struct bcm2835_cprman
*cprman
= divider
->cprman
;
762 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
764 spin_lock(&cprman
->regs_lock
);
765 cprman_write(cprman
, data
->a2w_reg
,
766 cprman_read(cprman
, data
->a2w_reg
) &
767 ~A2W_PLL_CHANNEL_DISABLE
);
769 cprman_write(cprman
, data
->cm_reg
,
770 cprman_read(cprman
, data
->cm_reg
) & ~data
->hold_mask
);
771 spin_unlock(&cprman
->regs_lock
);
776 static int bcm2835_pll_divider_set_rate(struct clk_hw
*hw
,
778 unsigned long parent_rate
)
780 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
781 struct bcm2835_cprman
*cprman
= divider
->cprman
;
782 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
783 u32 cm
, div
, max_div
= 1 << A2W_PLL_DIV_BITS
;
785 div
= DIV_ROUND_UP_ULL(parent_rate
, rate
);
787 div
= min(div
, max_div
);
791 cprman_write(cprman
, data
->a2w_reg
, div
);
792 cm
= cprman_read(cprman
, data
->cm_reg
);
793 cprman_write(cprman
, data
->cm_reg
, cm
| data
->load_mask
);
794 cprman_write(cprman
, data
->cm_reg
, cm
& ~data
->load_mask
);
799 static int bcm2835_pll_divider_debug_init(struct clk_hw
*hw
,
800 struct dentry
*dentry
)
802 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
803 struct bcm2835_cprman
*cprman
= divider
->cprman
;
804 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
805 struct debugfs_reg32
*regs
;
807 regs
= devm_kzalloc(cprman
->dev
, 7 * sizeof(*regs
), GFP_KERNEL
);
812 regs
[0].offset
= data
->cm_reg
;
813 regs
[1].name
= "a2w";
814 regs
[1].offset
= data
->a2w_reg
;
816 return bcm2835_debugfs_regset(cprman
, 0, regs
, 2, dentry
);
819 static const struct clk_ops bcm2835_pll_divider_clk_ops
= {
820 .is_prepared
= bcm2835_pll_divider_is_on
,
821 .prepare
= bcm2835_pll_divider_on
,
822 .unprepare
= bcm2835_pll_divider_off
,
823 .recalc_rate
= bcm2835_pll_divider_get_rate
,
824 .set_rate
= bcm2835_pll_divider_set_rate
,
825 .round_rate
= bcm2835_pll_divider_round_rate
,
826 .debug_init
= bcm2835_pll_divider_debug_init
,
830 * The CM dividers do fixed-point division, so we can't use the
831 * generic integer divider code like the PLL dividers do (and we can't
832 * fake it by having some fixed shifts preceding it in the clock tree,
833 * because we'd run out of bits in a 32-bit unsigned long).
835 struct bcm2835_clock
{
837 struct bcm2835_cprman
*cprman
;
838 const struct bcm2835_clock_data
*data
;
841 static struct bcm2835_clock
*bcm2835_clock_from_hw(struct clk_hw
*hw
)
843 return container_of(hw
, struct bcm2835_clock
, hw
);
846 static int bcm2835_clock_is_on(struct clk_hw
*hw
)
848 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
849 struct bcm2835_cprman
*cprman
= clock
->cprman
;
850 const struct bcm2835_clock_data
*data
= clock
->data
;
852 return (cprman_read(cprman
, data
->ctl_reg
) & CM_ENABLE
) != 0;
855 static u32
bcm2835_clock_choose_div(struct clk_hw
*hw
,
857 unsigned long parent_rate
,
860 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
861 const struct bcm2835_clock_data
*data
= clock
->data
;
862 u32 unused_frac_mask
=
863 GENMASK(CM_DIV_FRAC_BITS
- data
->frac_bits
, 0) >> 1;
864 u64 temp
= (u64
)parent_rate
<< CM_DIV_FRAC_BITS
;
866 u32 div
, mindiv
, maxdiv
;
868 rem
= do_div(temp
, rate
);
871 /* Round up and mask off the unused bits */
872 if (round_up
&& ((div
& unused_frac_mask
) != 0 || rem
!= 0))
873 div
+= unused_frac_mask
+ 1;
874 div
&= ~unused_frac_mask
;
876 /* different clamping limits apply for a mash clock */
877 if (data
->is_mash_clock
) {
878 /* clamp to min divider of 2 */
879 mindiv
= 2 << CM_DIV_FRAC_BITS
;
880 /* clamp to the highest possible integer divider */
881 maxdiv
= (BIT(data
->int_bits
) - 1) << CM_DIV_FRAC_BITS
;
883 /* clamp to min divider of 1 */
884 mindiv
= 1 << CM_DIV_FRAC_BITS
;
885 /* clamp to the highest possible fractional divider */
886 maxdiv
= GENMASK(data
->int_bits
+ CM_DIV_FRAC_BITS
- 1,
887 CM_DIV_FRAC_BITS
- data
->frac_bits
);
890 /* apply the clamping limits */
891 div
= max_t(u32
, div
, mindiv
);
892 div
= min_t(u32
, div
, maxdiv
);
897 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock
*clock
,
898 unsigned long parent_rate
,
901 const struct bcm2835_clock_data
*data
= clock
->data
;
905 * The divisor is a 12.12 fixed point field, but only some of
906 * the bits are populated in any given clock.
908 div
>>= CM_DIV_FRAC_BITS
- data
->frac_bits
;
909 div
&= (1 << (data
->int_bits
+ data
->frac_bits
)) - 1;
914 temp
= (u64
)parent_rate
<< data
->frac_bits
;
921 static unsigned long bcm2835_clock_get_rate(struct clk_hw
*hw
,
922 unsigned long parent_rate
)
924 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
925 struct bcm2835_cprman
*cprman
= clock
->cprman
;
926 const struct bcm2835_clock_data
*data
= clock
->data
;
927 u32 div
= cprman_read(cprman
, data
->div_reg
);
929 return bcm2835_clock_rate_from_divisor(clock
, parent_rate
, div
);
932 static void bcm2835_clock_wait_busy(struct bcm2835_clock
*clock
)
934 struct bcm2835_cprman
*cprman
= clock
->cprman
;
935 const struct bcm2835_clock_data
*data
= clock
->data
;
936 ktime_t timeout
= ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS
);
938 while (cprman_read(cprman
, data
->ctl_reg
) & CM_BUSY
) {
939 if (ktime_after(ktime_get(), timeout
)) {
940 dev_err(cprman
->dev
, "%s: couldn't lock PLL\n",
941 clk_hw_get_name(&clock
->hw
));
948 static void bcm2835_clock_off(struct clk_hw
*hw
)
950 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
951 struct bcm2835_cprman
*cprman
= clock
->cprman
;
952 const struct bcm2835_clock_data
*data
= clock
->data
;
954 spin_lock(&cprman
->regs_lock
);
955 cprman_write(cprman
, data
->ctl_reg
,
956 cprman_read(cprman
, data
->ctl_reg
) & ~CM_ENABLE
);
957 spin_unlock(&cprman
->regs_lock
);
959 /* BUSY will remain high until the divider completes its cycle. */
960 bcm2835_clock_wait_busy(clock
);
963 static int bcm2835_clock_on(struct clk_hw
*hw
)
965 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
966 struct bcm2835_cprman
*cprman
= clock
->cprman
;
967 const struct bcm2835_clock_data
*data
= clock
->data
;
969 spin_lock(&cprman
->regs_lock
);
970 cprman_write(cprman
, data
->ctl_reg
,
971 cprman_read(cprman
, data
->ctl_reg
) |
974 spin_unlock(&cprman
->regs_lock
);
979 static int bcm2835_clock_set_rate(struct clk_hw
*hw
,
980 unsigned long rate
, unsigned long parent_rate
)
982 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
983 struct bcm2835_cprman
*cprman
= clock
->cprman
;
984 const struct bcm2835_clock_data
*data
= clock
->data
;
985 u32 div
= bcm2835_clock_choose_div(hw
, rate
, parent_rate
, false);
988 spin_lock(&cprman
->regs_lock
);
991 * Setting up frac support
993 * In principle it is recommended to stop/start the clock first,
994 * but as we set CLK_SET_RATE_GATE during registration of the
995 * clock this requirement should be take care of by the
998 ctl
= cprman_read(cprman
, data
->ctl_reg
) & ~CM_FRAC
;
999 ctl
|= (div
& CM_DIV_FRAC_MASK
) ? CM_FRAC
: 0;
1000 cprman_write(cprman
, data
->ctl_reg
, ctl
);
1002 cprman_write(cprman
, data
->div_reg
, div
);
1004 spin_unlock(&cprman
->regs_lock
);
1010 bcm2835_clk_is_pllc(struct clk_hw
*hw
)
1015 return strncmp(clk_hw_get_name(hw
), "pllc", 4) == 0;
1018 static int bcm2835_clock_determine_rate(struct clk_hw
*hw
,
1019 struct clk_rate_request
*req
)
1021 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1022 struct clk_hw
*parent
, *best_parent
= NULL
;
1023 bool current_parent_is_pllc
;
1024 unsigned long rate
, best_rate
= 0;
1025 unsigned long prate
, best_prate
= 0;
1029 current_parent_is_pllc
= bcm2835_clk_is_pllc(clk_hw_get_parent(hw
));
1032 * Select parent clock that results in the closest but lower rate
1034 for (i
= 0; i
< clk_hw_get_num_parents(hw
); ++i
) {
1035 parent
= clk_hw_get_parent_by_index(hw
, i
);
1040 * Don't choose a PLLC-derived clock as our parent
1041 * unless it had been manually set that way. PLLC's
1042 * frequency gets adjusted by the firmware due to
1043 * over-temp or under-voltage conditions, without
1044 * prior notification to our clock consumer.
1046 if (bcm2835_clk_is_pllc(parent
) && !current_parent_is_pllc
)
1049 prate
= clk_hw_get_rate(parent
);
1050 div
= bcm2835_clock_choose_div(hw
, req
->rate
, prate
, true);
1051 rate
= bcm2835_clock_rate_from_divisor(clock
, prate
, div
);
1052 if (rate
> best_rate
&& rate
<= req
->rate
) {
1053 best_parent
= parent
;
1062 req
->best_parent_hw
= best_parent
;
1063 req
->best_parent_rate
= best_prate
;
1065 req
->rate
= best_rate
;
1070 static int bcm2835_clock_set_parent(struct clk_hw
*hw
, u8 index
)
1072 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1073 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1074 const struct bcm2835_clock_data
*data
= clock
->data
;
1075 u8 src
= (index
<< CM_SRC_SHIFT
) & CM_SRC_MASK
;
1077 cprman_write(cprman
, data
->ctl_reg
, src
);
1081 static u8
bcm2835_clock_get_parent(struct clk_hw
*hw
)
1083 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1084 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1085 const struct bcm2835_clock_data
*data
= clock
->data
;
1086 u32 src
= cprman_read(cprman
, data
->ctl_reg
);
1088 return (src
& CM_SRC_MASK
) >> CM_SRC_SHIFT
;
1091 static struct debugfs_reg32 bcm2835_debugfs_clock_reg32
[] = {
1102 static int bcm2835_clock_debug_init(struct clk_hw
*hw
,
1103 struct dentry
*dentry
)
1105 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1106 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1107 const struct bcm2835_clock_data
*data
= clock
->data
;
1109 return bcm2835_debugfs_regset(
1110 cprman
, data
->ctl_reg
,
1111 bcm2835_debugfs_clock_reg32
,
1112 ARRAY_SIZE(bcm2835_debugfs_clock_reg32
),
1116 static const struct clk_ops bcm2835_clock_clk_ops
= {
1117 .is_prepared
= bcm2835_clock_is_on
,
1118 .prepare
= bcm2835_clock_on
,
1119 .unprepare
= bcm2835_clock_off
,
1120 .recalc_rate
= bcm2835_clock_get_rate
,
1121 .set_rate
= bcm2835_clock_set_rate
,
1122 .determine_rate
= bcm2835_clock_determine_rate
,
1123 .set_parent
= bcm2835_clock_set_parent
,
1124 .get_parent
= bcm2835_clock_get_parent
,
1125 .debug_init
= bcm2835_clock_debug_init
,
1128 static int bcm2835_vpu_clock_is_on(struct clk_hw
*hw
)
1134 * The VPU clock can never be disabled (it doesn't have an ENABLE
1135 * bit), so it gets its own set of clock ops.
1137 static const struct clk_ops bcm2835_vpu_clock_clk_ops
= {
1138 .is_prepared
= bcm2835_vpu_clock_is_on
,
1139 .recalc_rate
= bcm2835_clock_get_rate
,
1140 .set_rate
= bcm2835_clock_set_rate
,
1141 .determine_rate
= bcm2835_clock_determine_rate
,
1142 .set_parent
= bcm2835_clock_set_parent
,
1143 .get_parent
= bcm2835_clock_get_parent
,
1144 .debug_init
= bcm2835_clock_debug_init
,
1147 static struct clk_hw
*bcm2835_register_pll(struct bcm2835_cprman
*cprman
,
1148 const struct bcm2835_pll_data
*data
)
1150 struct bcm2835_pll
*pll
;
1151 struct clk_init_data init
;
1154 memset(&init
, 0, sizeof(init
));
1156 /* All of the PLLs derive from the external oscillator. */
1157 init
.parent_names
= &cprman
->osc_name
;
1158 init
.num_parents
= 1;
1159 init
.name
= data
->name
;
1160 init
.ops
= &bcm2835_pll_clk_ops
;
1161 init
.flags
= CLK_IGNORE_UNUSED
;
1163 pll
= kzalloc(sizeof(*pll
), GFP_KERNEL
);
1167 pll
->cprman
= cprman
;
1169 pll
->hw
.init
= &init
;
1171 ret
= devm_clk_hw_register(cprman
->dev
, &pll
->hw
);
1177 static struct clk_hw
*
1178 bcm2835_register_pll_divider(struct bcm2835_cprman
*cprman
,
1179 const struct bcm2835_pll_divider_data
*data
)
1181 struct bcm2835_pll_divider
*divider
;
1182 struct clk_init_data init
;
1183 const char *divider_name
;
1186 if (data
->fixed_divider
!= 1) {
1187 divider_name
= devm_kasprintf(cprman
->dev
, GFP_KERNEL
,
1188 "%s_prediv", data
->name
);
1192 divider_name
= data
->name
;
1195 memset(&init
, 0, sizeof(init
));
1197 init
.parent_names
= &data
->source_pll
;
1198 init
.num_parents
= 1;
1199 init
.name
= divider_name
;
1200 init
.ops
= &bcm2835_pll_divider_clk_ops
;
1201 init
.flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
;
1203 divider
= devm_kzalloc(cprman
->dev
, sizeof(*divider
), GFP_KERNEL
);
1207 divider
->div
.reg
= cprman
->regs
+ data
->a2w_reg
;
1208 divider
->div
.shift
= A2W_PLL_DIV_SHIFT
;
1209 divider
->div
.width
= A2W_PLL_DIV_BITS
;
1210 divider
->div
.flags
= CLK_DIVIDER_MAX_AT_ZERO
;
1211 divider
->div
.lock
= &cprman
->regs_lock
;
1212 divider
->div
.hw
.init
= &init
;
1213 divider
->div
.table
= NULL
;
1215 divider
->cprman
= cprman
;
1216 divider
->data
= data
;
1218 ret
= devm_clk_hw_register(cprman
->dev
, ÷r
->div
.hw
);
1220 return ERR_PTR(ret
);
1223 * PLLH's channels have a fixed divide by 10 afterwards, which
1224 * is what our consumers are actually using.
1226 if (data
->fixed_divider
!= 1) {
1227 return clk_hw_register_fixed_factor(cprman
->dev
, data
->name
,
1229 CLK_SET_RATE_PARENT
,
1231 data
->fixed_divider
);
1234 return ÷r
->div
.hw
;
1237 static struct clk_hw
*bcm2835_register_clock(struct bcm2835_cprman
*cprman
,
1238 const struct bcm2835_clock_data
*data
)
1240 struct bcm2835_clock
*clock
;
1241 struct clk_init_data init
;
1242 const char *parents
[1 << CM_SRC_BITS
];
1247 * Replace our "xosc" references with the oscillator's
1250 for (i
= 0; i
< data
->num_mux_parents
; i
++) {
1251 if (strcmp(data
->parents
[i
], "xosc") == 0)
1252 parents
[i
] = cprman
->osc_name
;
1254 parents
[i
] = data
->parents
[i
];
1257 memset(&init
, 0, sizeof(init
));
1258 init
.parent_names
= parents
;
1259 init
.num_parents
= data
->num_mux_parents
;
1260 init
.name
= data
->name
;
1261 init
.flags
= data
->flags
| CLK_IGNORE_UNUSED
;
1263 if (data
->is_vpu_clock
) {
1264 init
.ops
= &bcm2835_vpu_clock_clk_ops
;
1266 init
.ops
= &bcm2835_clock_clk_ops
;
1267 init
.flags
|= CLK_SET_RATE_GATE
| CLK_SET_PARENT_GATE
;
1269 /* If the clock wasn't actually enabled at boot, it's not
1272 if (!(cprman_read(cprman
, data
->ctl_reg
) & CM_ENABLE
))
1273 init
.flags
&= ~CLK_IS_CRITICAL
;
1276 clock
= devm_kzalloc(cprman
->dev
, sizeof(*clock
), GFP_KERNEL
);
1280 clock
->cprman
= cprman
;
1282 clock
->hw
.init
= &init
;
1284 ret
= devm_clk_hw_register(cprman
->dev
, &clock
->hw
);
1286 return ERR_PTR(ret
);
1290 static struct clk
*bcm2835_register_gate(struct bcm2835_cprman
*cprman
,
1291 const struct bcm2835_gate_data
*data
)
1293 return clk_register_gate(cprman
->dev
, data
->name
, data
->parent
,
1294 CLK_IGNORE_UNUSED
| CLK_SET_RATE_GATE
,
1295 cprman
->regs
+ data
->ctl_reg
,
1296 CM_GATE_BIT
, 0, &cprman
->regs_lock
);
1299 typedef struct clk_hw
*(*bcm2835_clk_register
)(struct bcm2835_cprman
*cprman
,
1301 struct bcm2835_clk_desc
{
1302 bcm2835_clk_register clk_register
;
1306 /* assignment helper macros for different clock types */
1307 #define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
1308 .data = __VA_ARGS__ }
1309 #define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \
1310 &(struct bcm2835_pll_data) \
1312 #define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \
1313 &(struct bcm2835_pll_divider_data) \
1315 #define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \
1316 &(struct bcm2835_clock_data) \
1318 #define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \
1319 &(struct bcm2835_gate_data) \
1322 /* parent mux arrays plus helper macros */
1324 /* main oscillator parent mux */
1325 static const char *const bcm2835_clock_osc_parents
[] = {
1332 #define REGISTER_OSC_CLK(...) REGISTER_CLK( \
1333 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1334 .parents = bcm2835_clock_osc_parents, \
1337 /* main peripherial parent mux */
1338 static const char *const bcm2835_clock_per_parents
[] = {
1349 #define REGISTER_PER_CLK(...) REGISTER_CLK( \
1350 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1351 .parents = bcm2835_clock_per_parents, \
1354 /* main vpu parent mux */
1355 static const char *const bcm2835_clock_vpu_parents
[] = {
1368 #define REGISTER_VPU_CLK(...) REGISTER_CLK( \
1369 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1370 .parents = bcm2835_clock_vpu_parents, \
1374 * the real definition of all the pll, pll_dividers and clocks
1375 * these make use of the above REGISTER_* macros
1377 static const struct bcm2835_clk_desc clk_desc_array
[] = {
1378 /* the PLL + PLL dividers */
1381 * PLLA is the auxiliary PLL, used to drive the CCP2
1382 * (Compact Camera Port 2) transmitter clock.
1384 * It is in the PX LDO power domain, which is on when the
1385 * AUDIO domain is on.
1387 [BCM2835_PLLA
] = REGISTER_PLL(
1389 .cm_ctrl_reg
= CM_PLLA
,
1390 .a2w_ctrl_reg
= A2W_PLLA_CTRL
,
1391 .frac_reg
= A2W_PLLA_FRAC
,
1392 .ana_reg_base
= A2W_PLLA_ANA0
,
1393 .reference_enable_mask
= A2W_XOSC_CTRL_PLLA_ENABLE
,
1394 .lock_mask
= CM_LOCK_FLOCKA
,
1396 .ana
= &bcm2835_ana_default
,
1398 .min_rate
= 600000000u,
1399 .max_rate
= 2400000000u,
1400 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1401 [BCM2835_PLLA_CORE
] = REGISTER_PLL_DIV(
1402 .name
= "plla_core",
1403 .source_pll
= "plla",
1405 .a2w_reg
= A2W_PLLA_CORE
,
1406 .load_mask
= CM_PLLA_LOADCORE
,
1407 .hold_mask
= CM_PLLA_HOLDCORE
,
1408 .fixed_divider
= 1),
1409 [BCM2835_PLLA_PER
] = REGISTER_PLL_DIV(
1411 .source_pll
= "plla",
1413 .a2w_reg
= A2W_PLLA_PER
,
1414 .load_mask
= CM_PLLA_LOADPER
,
1415 .hold_mask
= CM_PLLA_HOLDPER
,
1416 .fixed_divider
= 1),
1417 [BCM2835_PLLA_DSI0
] = REGISTER_PLL_DIV(
1418 .name
= "plla_dsi0",
1419 .source_pll
= "plla",
1421 .a2w_reg
= A2W_PLLA_DSI0
,
1422 .load_mask
= CM_PLLA_LOADDSI0
,
1423 .hold_mask
= CM_PLLA_HOLDDSI0
,
1424 .fixed_divider
= 1),
1425 [BCM2835_PLLA_CCP2
] = REGISTER_PLL_DIV(
1426 .name
= "plla_ccp2",
1427 .source_pll
= "plla",
1429 .a2w_reg
= A2W_PLLA_CCP2
,
1430 .load_mask
= CM_PLLA_LOADCCP2
,
1431 .hold_mask
= CM_PLLA_HOLDCCP2
,
1432 .fixed_divider
= 1),
1434 /* PLLB is used for the ARM's clock. */
1435 [BCM2835_PLLB
] = REGISTER_PLL(
1437 .cm_ctrl_reg
= CM_PLLB
,
1438 .a2w_ctrl_reg
= A2W_PLLB_CTRL
,
1439 .frac_reg
= A2W_PLLB_FRAC
,
1440 .ana_reg_base
= A2W_PLLB_ANA0
,
1441 .reference_enable_mask
= A2W_XOSC_CTRL_PLLB_ENABLE
,
1442 .lock_mask
= CM_LOCK_FLOCKB
,
1444 .ana
= &bcm2835_ana_default
,
1446 .min_rate
= 600000000u,
1447 .max_rate
= 3000000000u,
1448 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1449 [BCM2835_PLLB_ARM
] = REGISTER_PLL_DIV(
1451 .source_pll
= "pllb",
1453 .a2w_reg
= A2W_PLLB_ARM
,
1454 .load_mask
= CM_PLLB_LOADARM
,
1455 .hold_mask
= CM_PLLB_HOLDARM
,
1456 .fixed_divider
= 1),
1459 * PLLC is the core PLL, used to drive the core VPU clock.
1461 * It is in the PX LDO power domain, which is on when the
1462 * AUDIO domain is on.
1464 [BCM2835_PLLC
] = REGISTER_PLL(
1466 .cm_ctrl_reg
= CM_PLLC
,
1467 .a2w_ctrl_reg
= A2W_PLLC_CTRL
,
1468 .frac_reg
= A2W_PLLC_FRAC
,
1469 .ana_reg_base
= A2W_PLLC_ANA0
,
1470 .reference_enable_mask
= A2W_XOSC_CTRL_PLLC_ENABLE
,
1471 .lock_mask
= CM_LOCK_FLOCKC
,
1473 .ana
= &bcm2835_ana_default
,
1475 .min_rate
= 600000000u,
1476 .max_rate
= 3000000000u,
1477 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1478 [BCM2835_PLLC_CORE0
] = REGISTER_PLL_DIV(
1479 .name
= "pllc_core0",
1480 .source_pll
= "pllc",
1482 .a2w_reg
= A2W_PLLC_CORE0
,
1483 .load_mask
= CM_PLLC_LOADCORE0
,
1484 .hold_mask
= CM_PLLC_HOLDCORE0
,
1485 .fixed_divider
= 1),
1486 [BCM2835_PLLC_CORE1
] = REGISTER_PLL_DIV(
1487 .name
= "pllc_core1",
1488 .source_pll
= "pllc",
1490 .a2w_reg
= A2W_PLLC_CORE1
,
1491 .load_mask
= CM_PLLC_LOADCORE1
,
1492 .hold_mask
= CM_PLLC_HOLDCORE1
,
1493 .fixed_divider
= 1),
1494 [BCM2835_PLLC_CORE2
] = REGISTER_PLL_DIV(
1495 .name
= "pllc_core2",
1496 .source_pll
= "pllc",
1498 .a2w_reg
= A2W_PLLC_CORE2
,
1499 .load_mask
= CM_PLLC_LOADCORE2
,
1500 .hold_mask
= CM_PLLC_HOLDCORE2
,
1501 .fixed_divider
= 1),
1502 [BCM2835_PLLC_PER
] = REGISTER_PLL_DIV(
1504 .source_pll
= "pllc",
1506 .a2w_reg
= A2W_PLLC_PER
,
1507 .load_mask
= CM_PLLC_LOADPER
,
1508 .hold_mask
= CM_PLLC_HOLDPER
,
1509 .fixed_divider
= 1),
1512 * PLLD is the display PLL, used to drive DSI display panels.
1514 * It is in the PX LDO power domain, which is on when the
1515 * AUDIO domain is on.
1517 [BCM2835_PLLD
] = REGISTER_PLL(
1519 .cm_ctrl_reg
= CM_PLLD
,
1520 .a2w_ctrl_reg
= A2W_PLLD_CTRL
,
1521 .frac_reg
= A2W_PLLD_FRAC
,
1522 .ana_reg_base
= A2W_PLLD_ANA0
,
1523 .reference_enable_mask
= A2W_XOSC_CTRL_DDR_ENABLE
,
1524 .lock_mask
= CM_LOCK_FLOCKD
,
1526 .ana
= &bcm2835_ana_default
,
1528 .min_rate
= 600000000u,
1529 .max_rate
= 2400000000u,
1530 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1531 [BCM2835_PLLD_CORE
] = REGISTER_PLL_DIV(
1532 .name
= "plld_core",
1533 .source_pll
= "plld",
1535 .a2w_reg
= A2W_PLLD_CORE
,
1536 .load_mask
= CM_PLLD_LOADCORE
,
1537 .hold_mask
= CM_PLLD_HOLDCORE
,
1538 .fixed_divider
= 1),
1539 [BCM2835_PLLD_PER
] = REGISTER_PLL_DIV(
1541 .source_pll
= "plld",
1543 .a2w_reg
= A2W_PLLD_PER
,
1544 .load_mask
= CM_PLLD_LOADPER
,
1545 .hold_mask
= CM_PLLD_HOLDPER
,
1546 .fixed_divider
= 1),
1547 [BCM2835_PLLD_DSI0
] = REGISTER_PLL_DIV(
1548 .name
= "plld_dsi0",
1549 .source_pll
= "plld",
1551 .a2w_reg
= A2W_PLLD_DSI0
,
1552 .load_mask
= CM_PLLD_LOADDSI0
,
1553 .hold_mask
= CM_PLLD_HOLDDSI0
,
1554 .fixed_divider
= 1),
1555 [BCM2835_PLLD_DSI1
] = REGISTER_PLL_DIV(
1556 .name
= "plld_dsi1",
1557 .source_pll
= "plld",
1559 .a2w_reg
= A2W_PLLD_DSI1
,
1560 .load_mask
= CM_PLLD_LOADDSI1
,
1561 .hold_mask
= CM_PLLD_HOLDDSI1
,
1562 .fixed_divider
= 1),
1565 * PLLH is used to supply the pixel clock or the AUX clock for the
1568 * It is in the HDMI power domain.
1570 [BCM2835_PLLH
] = REGISTER_PLL(
1572 .cm_ctrl_reg
= CM_PLLH
,
1573 .a2w_ctrl_reg
= A2W_PLLH_CTRL
,
1574 .frac_reg
= A2W_PLLH_FRAC
,
1575 .ana_reg_base
= A2W_PLLH_ANA0
,
1576 .reference_enable_mask
= A2W_XOSC_CTRL_PLLC_ENABLE
,
1577 .lock_mask
= CM_LOCK_FLOCKH
,
1579 .ana
= &bcm2835_ana_pllh
,
1581 .min_rate
= 600000000u,
1582 .max_rate
= 3000000000u,
1583 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1584 [BCM2835_PLLH_RCAL
] = REGISTER_PLL_DIV(
1585 .name
= "pllh_rcal",
1586 .source_pll
= "pllh",
1588 .a2w_reg
= A2W_PLLH_RCAL
,
1589 .load_mask
= CM_PLLH_LOADRCAL
,
1591 .fixed_divider
= 10),
1592 [BCM2835_PLLH_AUX
] = REGISTER_PLL_DIV(
1594 .source_pll
= "pllh",
1596 .a2w_reg
= A2W_PLLH_AUX
,
1597 .load_mask
= CM_PLLH_LOADAUX
,
1599 .fixed_divider
= 1),
1600 [BCM2835_PLLH_PIX
] = REGISTER_PLL_DIV(
1602 .source_pll
= "pllh",
1604 .a2w_reg
= A2W_PLLH_PIX
,
1605 .load_mask
= CM_PLLH_LOADPIX
,
1607 .fixed_divider
= 10),
1611 /* clocks with oscillator parent mux */
1613 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1614 [BCM2835_CLOCK_OTP
] = REGISTER_OSC_CLK(
1616 .ctl_reg
= CM_OTPCTL
,
1617 .div_reg
= CM_OTPDIV
,
1621 * Used for a 1Mhz clock for the system clocksource, and also used
1622 * bythe watchdog timer and the camera pulse generator.
1624 [BCM2835_CLOCK_TIMER
] = REGISTER_OSC_CLK(
1626 .ctl_reg
= CM_TIMERCTL
,
1627 .div_reg
= CM_TIMERDIV
,
1631 * Clock for the temperature sensor.
1632 * Generally run at 2Mhz, max 5Mhz.
1634 [BCM2835_CLOCK_TSENS
] = REGISTER_OSC_CLK(
1636 .ctl_reg
= CM_TSENSCTL
,
1637 .div_reg
= CM_TSENSDIV
,
1640 [BCM2835_CLOCK_TEC
] = REGISTER_OSC_CLK(
1642 .ctl_reg
= CM_TECCTL
,
1643 .div_reg
= CM_TECDIV
,
1647 /* clocks with vpu parent mux */
1648 [BCM2835_CLOCK_H264
] = REGISTER_VPU_CLK(
1650 .ctl_reg
= CM_H264CTL
,
1651 .div_reg
= CM_H264DIV
,
1654 [BCM2835_CLOCK_ISP
] = REGISTER_VPU_CLK(
1656 .ctl_reg
= CM_ISPCTL
,
1657 .div_reg
= CM_ISPDIV
,
1662 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
1663 * in the SDRAM controller can't be used.
1665 [BCM2835_CLOCK_SDRAM
] = REGISTER_VPU_CLK(
1667 .ctl_reg
= CM_SDCCTL
,
1668 .div_reg
= CM_SDCDIV
,
1671 [BCM2835_CLOCK_V3D
] = REGISTER_VPU_CLK(
1673 .ctl_reg
= CM_V3DCTL
,
1674 .div_reg
= CM_V3DDIV
,
1678 * VPU clock. This doesn't have an enable bit, since it drives
1679 * the bus for everything else, and is special so it doesn't need
1680 * to be gated for rate changes. It is also known as "clk_audio"
1681 * in various hardware documentation.
1683 [BCM2835_CLOCK_VPU
] = REGISTER_VPU_CLK(
1685 .ctl_reg
= CM_VPUCTL
,
1686 .div_reg
= CM_VPUDIV
,
1689 .flags
= CLK_IS_CRITICAL
,
1690 .is_vpu_clock
= true),
1692 /* clocks with per parent mux */
1693 [BCM2835_CLOCK_AVEO
] = REGISTER_PER_CLK(
1695 .ctl_reg
= CM_AVEOCTL
,
1696 .div_reg
= CM_AVEODIV
,
1699 [BCM2835_CLOCK_CAM0
] = REGISTER_PER_CLK(
1701 .ctl_reg
= CM_CAM0CTL
,
1702 .div_reg
= CM_CAM0DIV
,
1705 [BCM2835_CLOCK_CAM1
] = REGISTER_PER_CLK(
1707 .ctl_reg
= CM_CAM1CTL
,
1708 .div_reg
= CM_CAM1DIV
,
1711 [BCM2835_CLOCK_DFT
] = REGISTER_PER_CLK(
1713 .ctl_reg
= CM_DFTCTL
,
1714 .div_reg
= CM_DFTDIV
,
1717 [BCM2835_CLOCK_DPI
] = REGISTER_PER_CLK(
1719 .ctl_reg
= CM_DPICTL
,
1720 .div_reg
= CM_DPIDIV
,
1724 /* Arasan EMMC clock */
1725 [BCM2835_CLOCK_EMMC
] = REGISTER_PER_CLK(
1727 .ctl_reg
= CM_EMMCCTL
,
1728 .div_reg
= CM_EMMCDIV
,
1732 /* General purpose (GPIO) clocks */
1733 [BCM2835_CLOCK_GP0
] = REGISTER_PER_CLK(
1735 .ctl_reg
= CM_GP0CTL
,
1736 .div_reg
= CM_GP0DIV
,
1739 .is_mash_clock
= true),
1740 [BCM2835_CLOCK_GP1
] = REGISTER_PER_CLK(
1742 .ctl_reg
= CM_GP1CTL
,
1743 .div_reg
= CM_GP1DIV
,
1746 .flags
= CLK_IS_CRITICAL
,
1747 .is_mash_clock
= true),
1748 [BCM2835_CLOCK_GP2
] = REGISTER_PER_CLK(
1750 .ctl_reg
= CM_GP2CTL
,
1751 .div_reg
= CM_GP2DIV
,
1754 .flags
= CLK_IS_CRITICAL
),
1756 /* HDMI state machine */
1757 [BCM2835_CLOCK_HSM
] = REGISTER_PER_CLK(
1759 .ctl_reg
= CM_HSMCTL
,
1760 .div_reg
= CM_HSMDIV
,
1763 [BCM2835_CLOCK_PCM
] = REGISTER_PER_CLK(
1765 .ctl_reg
= CM_PCMCTL
,
1766 .div_reg
= CM_PCMDIV
,
1769 .is_mash_clock
= true),
1770 [BCM2835_CLOCK_PWM
] = REGISTER_PER_CLK(
1772 .ctl_reg
= CM_PWMCTL
,
1773 .div_reg
= CM_PWMDIV
,
1776 .is_mash_clock
= true),
1777 [BCM2835_CLOCK_SLIM
] = REGISTER_PER_CLK(
1779 .ctl_reg
= CM_SLIMCTL
,
1780 .div_reg
= CM_SLIMDIV
,
1783 .is_mash_clock
= true),
1784 [BCM2835_CLOCK_SMI
] = REGISTER_PER_CLK(
1786 .ctl_reg
= CM_SMICTL
,
1787 .div_reg
= CM_SMIDIV
,
1790 [BCM2835_CLOCK_UART
] = REGISTER_PER_CLK(
1792 .ctl_reg
= CM_UARTCTL
,
1793 .div_reg
= CM_UARTDIV
,
1797 /* TV encoder clock. Only operating frequency is 108Mhz. */
1798 [BCM2835_CLOCK_VEC
] = REGISTER_PER_CLK(
1800 .ctl_reg
= CM_VECCTL
,
1801 .div_reg
= CM_VECDIV
,
1806 [BCM2835_CLOCK_DSI0E
] = REGISTER_PER_CLK(
1808 .ctl_reg
= CM_DSI0ECTL
,
1809 .div_reg
= CM_DSI0EDIV
,
1812 [BCM2835_CLOCK_DSI1E
] = REGISTER_PER_CLK(
1814 .ctl_reg
= CM_DSI1ECTL
,
1815 .div_reg
= CM_DSI1EDIV
,
1822 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
1823 * you have the debug bit set in the power manager, which we
1824 * don't bother exposing) are individual gates off of the
1825 * non-stop vpu clock.
1827 [BCM2835_CLOCK_PERI_IMAGE
] = REGISTER_GATE(
1828 .name
= "peri_image",
1830 .ctl_reg
= CM_PERIICTL
),
1834 * Permanently take a reference on the parent of the SDRAM clock.
1836 * While the SDRAM is being driven by its dedicated PLL most of the
1837 * time, there is a little loop running in the firmware that
1838 * periodically switches the SDRAM to using our CM clock to do PVT
1839 * recalibration, with the assumption that the previously configured
1840 * SDRAM parent is still enabled and running.
1842 static int bcm2835_mark_sdc_parent_critical(struct clk
*sdc
)
1844 struct clk
*parent
= clk_get_parent(sdc
);
1847 return PTR_ERR(parent
);
1849 return clk_prepare_enable(parent
);
1852 static int bcm2835_clk_probe(struct platform_device
*pdev
)
1854 struct device
*dev
= &pdev
->dev
;
1855 struct clk_hw
**hws
;
1856 struct bcm2835_cprman
*cprman
;
1857 struct resource
*res
;
1858 const struct bcm2835_clk_desc
*desc
;
1859 const size_t asize
= ARRAY_SIZE(clk_desc_array
);
1863 cprman
= devm_kzalloc(dev
, sizeof(*cprman
) +
1864 sizeof(*cprman
->onecell
.hws
) * asize
,
1869 spin_lock_init(&cprman
->regs_lock
);
1871 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1872 cprman
->regs
= devm_ioremap_resource(dev
, res
);
1873 if (IS_ERR(cprman
->regs
))
1874 return PTR_ERR(cprman
->regs
);
1876 cprman
->osc_name
= of_clk_get_parent_name(dev
->of_node
, 0);
1877 if (!cprman
->osc_name
)
1880 platform_set_drvdata(pdev
, cprman
);
1882 cprman
->onecell
.num
= asize
;
1883 hws
= cprman
->onecell
.hws
;
1885 for (i
= 0; i
< asize
; i
++) {
1886 desc
= &clk_desc_array
[i
];
1887 if (desc
->clk_register
&& desc
->data
)
1888 hws
[i
] = desc
->clk_register(cprman
, desc
->data
);
1891 ret
= bcm2835_mark_sdc_parent_critical(hws
[BCM2835_CLOCK_SDRAM
]->clk
);
1895 return of_clk_add_hw_provider(dev
->of_node
, of_clk_hw_onecell_get
,
1899 static const struct of_device_id bcm2835_clk_of_match
[] = {
1900 { .compatible
= "brcm,bcm2835-cprman", },
1903 MODULE_DEVICE_TABLE(of
, bcm2835_clk_of_match
);
1905 static struct platform_driver bcm2835_clk_driver
= {
1907 .name
= "bcm2835-clk",
1908 .of_match_table
= bcm2835_clk_of_match
,
1910 .probe
= bcm2835_clk_probe
,
1913 builtin_platform_driver(bcm2835_clk_driver
);
1915 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
1916 MODULE_DESCRIPTION("BCM2835 clock driver");
1917 MODULE_LICENSE("GPL v2");