2 * Copyright (C) 2010,2015 Broadcom
3 * Copyright (C) 2012 Stephen Warren
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
18 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
20 * The clock tree on the 2835 has several levels. There's a root
21 * oscillator running at 19.2Mhz. After the oscillator there are 5
22 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
23 * and "HDMI displays". Those 5 PLLs each can divide their output to
24 * produce up to 4 channels. Finally, there is the level of clocks to
25 * be consumed by other hardware components (like "H264" or "HDMI
26 * state machine"), which divide off of some subset of the PLL
29 * All of the clocks in the tree are exposed in the DT, because the DT
30 * may want to make assignments of the final layer of clocks to the
31 * PLL channels, and some components of the hardware will actually
32 * skip layers of the tree (for example, the pixel clock comes
33 * directly from the PLLH PIX channel without using a CM_*CTL clock
37 #include <linux/clk-provider.h>
38 #include <linux/clkdev.h>
39 #include <linux/clk.h>
40 #include <linux/clk/bcm2835.h>
41 #include <linux/debugfs.h>
42 #include <linux/module.h>
44 #include <linux/platform_device.h>
45 #include <linux/slab.h>
46 #include <dt-bindings/clock/bcm2835.h>
48 #define CM_PASSWORD 0x5a000000
50 #define CM_GNRICCTL 0x000
51 #define CM_GNRICDIV 0x004
52 # define CM_DIV_FRAC_BITS 12
53 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
55 #define CM_VPUCTL 0x008
56 #define CM_VPUDIV 0x00c
57 #define CM_SYSCTL 0x010
58 #define CM_SYSDIV 0x014
59 #define CM_PERIACTL 0x018
60 #define CM_PERIADIV 0x01c
61 #define CM_PERIICTL 0x020
62 #define CM_PERIIDIV 0x024
63 #define CM_H264CTL 0x028
64 #define CM_H264DIV 0x02c
65 #define CM_ISPCTL 0x030
66 #define CM_ISPDIV 0x034
67 #define CM_V3DCTL 0x038
68 #define CM_V3DDIV 0x03c
69 #define CM_CAM0CTL 0x040
70 #define CM_CAM0DIV 0x044
71 #define CM_CAM1CTL 0x048
72 #define CM_CAM1DIV 0x04c
73 #define CM_CCP2CTL 0x050
74 #define CM_CCP2DIV 0x054
75 #define CM_DSI0ECTL 0x058
76 #define CM_DSI0EDIV 0x05c
77 #define CM_DSI0PCTL 0x060
78 #define CM_DSI0PDIV 0x064
79 #define CM_DPICTL 0x068
80 #define CM_DPIDIV 0x06c
81 #define CM_GP0CTL 0x070
82 #define CM_GP0DIV 0x074
83 #define CM_GP1CTL 0x078
84 #define CM_GP1DIV 0x07c
85 #define CM_GP2CTL 0x080
86 #define CM_GP2DIV 0x084
87 #define CM_HSMCTL 0x088
88 #define CM_HSMDIV 0x08c
89 #define CM_OTPCTL 0x090
90 #define CM_OTPDIV 0x094
91 #define CM_PCMCTL 0x098
92 #define CM_PCMDIV 0x09c
93 #define CM_PWMCTL 0x0a0
94 #define CM_PWMDIV 0x0a4
95 #define CM_SLIMCTL 0x0a8
96 #define CM_SLIMDIV 0x0ac
97 #define CM_SMICTL 0x0b0
98 #define CM_SMIDIV 0x0b4
99 /* no definition for 0x0b8 and 0x0bc */
100 #define CM_TCNTCTL 0x0c0
101 #define CM_TCNTDIV 0x0c4
102 #define CM_TECCTL 0x0c8
103 #define CM_TECDIV 0x0cc
104 #define CM_TD0CTL 0x0d0
105 #define CM_TD0DIV 0x0d4
106 #define CM_TD1CTL 0x0d8
107 #define CM_TD1DIV 0x0dc
108 #define CM_TSENSCTL 0x0e0
109 #define CM_TSENSDIV 0x0e4
110 #define CM_TIMERCTL 0x0e8
111 #define CM_TIMERDIV 0x0ec
112 #define CM_UARTCTL 0x0f0
113 #define CM_UARTDIV 0x0f4
114 #define CM_VECCTL 0x0f8
115 #define CM_VECDIV 0x0fc
116 #define CM_PULSECTL 0x190
117 #define CM_PULSEDIV 0x194
118 #define CM_SDCCTL 0x1a8
119 #define CM_SDCDIV 0x1ac
120 #define CM_ARMCTL 0x1b0
121 #define CM_AVEOCTL 0x1b8
122 #define CM_AVEODIV 0x1bc
123 #define CM_EMMCCTL 0x1c0
124 #define CM_EMMCDIV 0x1c4
126 /* General bits for the CM_*CTL regs */
127 # define CM_ENABLE BIT(4)
128 # define CM_KILL BIT(5)
129 # define CM_GATE_BIT 6
130 # define CM_GATE BIT(CM_GATE_BIT)
131 # define CM_BUSY BIT(7)
132 # define CM_BUSYD BIT(8)
133 # define CM_FRAC BIT(9)
134 # define CM_SRC_SHIFT 0
135 # define CM_SRC_BITS 4
136 # define CM_SRC_MASK 0xf
137 # define CM_SRC_GND 0
138 # define CM_SRC_OSC 1
139 # define CM_SRC_TESTDEBUG0 2
140 # define CM_SRC_TESTDEBUG1 3
141 # define CM_SRC_PLLA_CORE 4
142 # define CM_SRC_PLLA_PER 4
143 # define CM_SRC_PLLC_CORE0 5
144 # define CM_SRC_PLLC_PER 5
145 # define CM_SRC_PLLC_CORE1 8
146 # define CM_SRC_PLLD_CORE 6
147 # define CM_SRC_PLLD_PER 6
148 # define CM_SRC_PLLH_AUX 7
149 # define CM_SRC_PLLC_CORE1 8
150 # define CM_SRC_PLLC_CORE2 9
152 #define CM_OSCCOUNT 0x100
154 #define CM_PLLA 0x104
155 # define CM_PLL_ANARST BIT(8)
156 # define CM_PLLA_HOLDPER BIT(7)
157 # define CM_PLLA_LOADPER BIT(6)
158 # define CM_PLLA_HOLDCORE BIT(5)
159 # define CM_PLLA_LOADCORE BIT(4)
160 # define CM_PLLA_HOLDCCP2 BIT(3)
161 # define CM_PLLA_LOADCCP2 BIT(2)
162 # define CM_PLLA_HOLDDSI0 BIT(1)
163 # define CM_PLLA_LOADDSI0 BIT(0)
165 #define CM_PLLC 0x108
166 # define CM_PLLC_HOLDPER BIT(7)
167 # define CM_PLLC_LOADPER BIT(6)
168 # define CM_PLLC_HOLDCORE2 BIT(5)
169 # define CM_PLLC_LOADCORE2 BIT(4)
170 # define CM_PLLC_HOLDCORE1 BIT(3)
171 # define CM_PLLC_LOADCORE1 BIT(2)
172 # define CM_PLLC_HOLDCORE0 BIT(1)
173 # define CM_PLLC_LOADCORE0 BIT(0)
175 #define CM_PLLD 0x10c
176 # define CM_PLLD_HOLDPER BIT(7)
177 # define CM_PLLD_LOADPER BIT(6)
178 # define CM_PLLD_HOLDCORE BIT(5)
179 # define CM_PLLD_LOADCORE BIT(4)
180 # define CM_PLLD_HOLDDSI1 BIT(3)
181 # define CM_PLLD_LOADDSI1 BIT(2)
182 # define CM_PLLD_HOLDDSI0 BIT(1)
183 # define CM_PLLD_LOADDSI0 BIT(0)
185 #define CM_PLLH 0x110
186 # define CM_PLLH_LOADRCAL BIT(2)
187 # define CM_PLLH_LOADAUX BIT(1)
188 # define CM_PLLH_LOADPIX BIT(0)
190 #define CM_LOCK 0x114
191 # define CM_LOCK_FLOCKH BIT(12)
192 # define CM_LOCK_FLOCKD BIT(11)
193 # define CM_LOCK_FLOCKC BIT(10)
194 # define CM_LOCK_FLOCKB BIT(9)
195 # define CM_LOCK_FLOCKA BIT(8)
197 #define CM_EVENT 0x118
198 #define CM_DSI1ECTL 0x158
199 #define CM_DSI1EDIV 0x15c
200 #define CM_DSI1PCTL 0x160
201 #define CM_DSI1PDIV 0x164
202 #define CM_DFTCTL 0x168
203 #define CM_DFTDIV 0x16c
205 #define CM_PLLB 0x170
206 # define CM_PLLB_HOLDARM BIT(1)
207 # define CM_PLLB_LOADARM BIT(0)
209 #define A2W_PLLA_CTRL 0x1100
210 #define A2W_PLLC_CTRL 0x1120
211 #define A2W_PLLD_CTRL 0x1140
212 #define A2W_PLLH_CTRL 0x1160
213 #define A2W_PLLB_CTRL 0x11e0
214 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
215 # define A2W_PLL_CTRL_PWRDN BIT(16)
216 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000
217 # define A2W_PLL_CTRL_PDIV_SHIFT 12
218 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
219 # define A2W_PLL_CTRL_NDIV_SHIFT 0
221 #define A2W_PLLA_ANA0 0x1010
222 #define A2W_PLLC_ANA0 0x1030
223 #define A2W_PLLD_ANA0 0x1050
224 #define A2W_PLLH_ANA0 0x1070
225 #define A2W_PLLB_ANA0 0x10f0
227 #define A2W_PLL_KA_SHIFT 7
228 #define A2W_PLL_KA_MASK GENMASK(9, 7)
229 #define A2W_PLL_KI_SHIFT 19
230 #define A2W_PLL_KI_MASK GENMASK(21, 19)
231 #define A2W_PLL_KP_SHIFT 15
232 #define A2W_PLL_KP_MASK GENMASK(18, 15)
234 #define A2W_PLLH_KA_SHIFT 19
235 #define A2W_PLLH_KA_MASK GENMASK(21, 19)
236 #define A2W_PLLH_KI_LOW_SHIFT 22
237 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
238 #define A2W_PLLH_KI_HIGH_SHIFT 0
239 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
240 #define A2W_PLLH_KP_SHIFT 1
241 #define A2W_PLLH_KP_MASK GENMASK(4, 1)
243 #define A2W_XOSC_CTRL 0x1190
244 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
245 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
246 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
247 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
248 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
249 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
250 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
251 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
253 #define A2W_PLLA_FRAC 0x1200
254 #define A2W_PLLC_FRAC 0x1220
255 #define A2W_PLLD_FRAC 0x1240
256 #define A2W_PLLH_FRAC 0x1260
257 #define A2W_PLLB_FRAC 0x12e0
258 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
259 # define A2W_PLL_FRAC_BITS 20
261 #define A2W_PLL_CHANNEL_DISABLE BIT(8)
262 #define A2W_PLL_DIV_BITS 8
263 #define A2W_PLL_DIV_SHIFT 0
265 #define A2W_PLLA_DSI0 0x1300
266 #define A2W_PLLA_CORE 0x1400
267 #define A2W_PLLA_PER 0x1500
268 #define A2W_PLLA_CCP2 0x1600
270 #define A2W_PLLC_CORE2 0x1320
271 #define A2W_PLLC_CORE1 0x1420
272 #define A2W_PLLC_PER 0x1520
273 #define A2W_PLLC_CORE0 0x1620
275 #define A2W_PLLD_DSI0 0x1340
276 #define A2W_PLLD_CORE 0x1440
277 #define A2W_PLLD_PER 0x1540
278 #define A2W_PLLD_DSI1 0x1640
280 #define A2W_PLLH_AUX 0x1360
281 #define A2W_PLLH_RCAL 0x1460
282 #define A2W_PLLH_PIX 0x1560
283 #define A2W_PLLH_STS 0x1660
285 #define A2W_PLLH_CTRLR 0x1960
286 #define A2W_PLLH_FRACR 0x1a60
287 #define A2W_PLLH_AUXR 0x1b60
288 #define A2W_PLLH_RCALR 0x1c60
289 #define A2W_PLLH_PIXR 0x1d60
290 #define A2W_PLLH_STSR 0x1e60
292 #define A2W_PLLB_ARM 0x13e0
293 #define A2W_PLLB_SP0 0x14e0
294 #define A2W_PLLB_SP1 0x15e0
295 #define A2W_PLLB_SP2 0x16e0
297 #define LOCK_TIMEOUT_NS 100000000
298 #define BCM2835_MAX_FB_RATE 1750000000u
300 struct bcm2835_cprman
{
303 spinlock_t regs_lock
; /* spinlock for all clocks */
304 const char *osc_name
;
307 struct clk_hw_onecell_data onecell
;
310 static inline void cprman_write(struct bcm2835_cprman
*cprman
, u32 reg
, u32 val
)
312 writel(CM_PASSWORD
| val
, cprman
->regs
+ reg
);
315 static inline u32
cprman_read(struct bcm2835_cprman
*cprman
, u32 reg
)
317 return readl(cprman
->regs
+ reg
);
320 static int bcm2835_debugfs_regset(struct bcm2835_cprman
*cprman
, u32 base
,
321 struct debugfs_reg32
*regs
, size_t nregs
,
322 struct dentry
*dentry
)
324 struct dentry
*regdump
;
325 struct debugfs_regset32
*regset
;
327 regset
= devm_kzalloc(cprman
->dev
, sizeof(*regset
), GFP_KERNEL
);
332 regset
->nregs
= nregs
;
333 regset
->base
= cprman
->regs
+ base
;
335 regdump
= debugfs_create_regset32("regdump", S_IRUGO
, dentry
,
338 return regdump
? 0 : -ENOMEM
;
342 * These are fixed clocks. They're probably not all root clocks and it may
343 * be possible to turn them on and off but until this is mapped out better
344 * it's the only way they can be used.
346 void __init
bcm2835_init_clocks(void)
351 hw
= clk_hw_register_fixed_rate(NULL
, "apb_pclk", NULL
, 0, 126000000);
353 pr_err("apb_pclk not registered\n");
355 hw
= clk_hw_register_fixed_rate(NULL
, "uart0_pclk", NULL
, 0, 3000000);
357 pr_err("uart0_pclk not registered\n");
358 ret
= clk_hw_register_clkdev(hw
, NULL
, "20201000.uart");
360 pr_err("uart0_pclk alias not registered\n");
362 hw
= clk_hw_register_fixed_rate(NULL
, "uart1_pclk", NULL
, 0, 125000000);
364 pr_err("uart1_pclk not registered\n");
365 ret
= clk_hw_register_clkdev(hw
, NULL
, "20215000.uart");
367 pr_err("uart1_pclk alias not registered\n");
370 struct bcm2835_pll_data
{
376 u32 reference_enable_mask
;
377 /* Bit in CM_LOCK to indicate when the PLL has locked. */
380 const struct bcm2835_pll_ana_bits
*ana
;
382 unsigned long min_rate
;
383 unsigned long max_rate
;
385 * Highest rate for the VCO before we have to use the
388 unsigned long max_fb_rate
;
391 struct bcm2835_pll_ana_bits
{
401 static const struct bcm2835_pll_ana_bits bcm2835_ana_default
= {
404 .mask1
= (u32
)~(A2W_PLL_KI_MASK
| A2W_PLL_KP_MASK
),
405 .set1
= (2 << A2W_PLL_KI_SHIFT
) | (8 << A2W_PLL_KP_SHIFT
),
406 .mask3
= (u32
)~A2W_PLL_KA_MASK
,
407 .set3
= (2 << A2W_PLL_KA_SHIFT
),
408 .fb_prediv_mask
= BIT(14),
411 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh
= {
412 .mask0
= (u32
)~(A2W_PLLH_KA_MASK
| A2W_PLLH_KI_LOW_MASK
),
413 .set0
= (2 << A2W_PLLH_KA_SHIFT
) | (2 << A2W_PLLH_KI_LOW_SHIFT
),
414 .mask1
= (u32
)~(A2W_PLLH_KI_HIGH_MASK
| A2W_PLLH_KP_MASK
),
415 .set1
= (6 << A2W_PLLH_KP_SHIFT
),
418 .fb_prediv_mask
= BIT(11),
421 struct bcm2835_pll_divider_data
{
423 const char *source_pll
;
433 struct bcm2835_clock_data
{
436 const char *const *parents
;
442 /* Number of integer bits in the divider */
444 /* Number of fractional bits in the divider */
453 struct bcm2835_gate_data
{
462 struct bcm2835_cprman
*cprman
;
463 const struct bcm2835_pll_data
*data
;
466 static int bcm2835_pll_is_on(struct clk_hw
*hw
)
468 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
469 struct bcm2835_cprman
*cprman
= pll
->cprman
;
470 const struct bcm2835_pll_data
*data
= pll
->data
;
472 return cprman_read(cprman
, data
->a2w_ctrl_reg
) &
473 A2W_PLL_CTRL_PRST_DISABLE
;
476 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate
,
477 unsigned long parent_rate
,
478 u32
*ndiv
, u32
*fdiv
)
482 div
= (u64
)rate
<< A2W_PLL_FRAC_BITS
;
483 do_div(div
, parent_rate
);
485 *ndiv
= div
>> A2W_PLL_FRAC_BITS
;
486 *fdiv
= div
& ((1 << A2W_PLL_FRAC_BITS
) - 1);
489 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate
,
490 u32 ndiv
, u32 fdiv
, u32 pdiv
)
497 rate
= (u64
)parent_rate
* ((ndiv
<< A2W_PLL_FRAC_BITS
) + fdiv
);
499 return rate
>> A2W_PLL_FRAC_BITS
;
502 static long bcm2835_pll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
503 unsigned long *parent_rate
)
507 bcm2835_pll_choose_ndiv_and_fdiv(rate
, *parent_rate
, &ndiv
, &fdiv
);
509 return bcm2835_pll_rate_from_divisors(*parent_rate
, ndiv
, fdiv
, 1);
512 static unsigned long bcm2835_pll_get_rate(struct clk_hw
*hw
,
513 unsigned long parent_rate
)
515 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
516 struct bcm2835_cprman
*cprman
= pll
->cprman
;
517 const struct bcm2835_pll_data
*data
= pll
->data
;
518 u32 a2wctrl
= cprman_read(cprman
, data
->a2w_ctrl_reg
);
519 u32 ndiv
, pdiv
, fdiv
;
522 if (parent_rate
== 0)
525 fdiv
= cprman_read(cprman
, data
->frac_reg
) & A2W_PLL_FRAC_MASK
;
526 ndiv
= (a2wctrl
& A2W_PLL_CTRL_NDIV_MASK
) >> A2W_PLL_CTRL_NDIV_SHIFT
;
527 pdiv
= (a2wctrl
& A2W_PLL_CTRL_PDIV_MASK
) >> A2W_PLL_CTRL_PDIV_SHIFT
;
528 using_prediv
= cprman_read(cprman
, data
->ana_reg_base
+ 4) &
529 data
->ana
->fb_prediv_mask
;
534 return bcm2835_pll_rate_from_divisors(parent_rate
, ndiv
, fdiv
, pdiv
);
537 static void bcm2835_pll_off(struct clk_hw
*hw
)
539 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
540 struct bcm2835_cprman
*cprman
= pll
->cprman
;
541 const struct bcm2835_pll_data
*data
= pll
->data
;
543 spin_lock(&cprman
->regs_lock
);
544 cprman_write(cprman
, data
->cm_ctrl_reg
,
545 cprman_read(cprman
, data
->cm_ctrl_reg
) |
547 cprman_write(cprman
, data
->a2w_ctrl_reg
,
548 cprman_read(cprman
, data
->a2w_ctrl_reg
) |
550 spin_unlock(&cprman
->regs_lock
);
553 static int bcm2835_pll_on(struct clk_hw
*hw
)
555 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
556 struct bcm2835_cprman
*cprman
= pll
->cprman
;
557 const struct bcm2835_pll_data
*data
= pll
->data
;
560 cprman_write(cprman
, data
->a2w_ctrl_reg
,
561 cprman_read(cprman
, data
->a2w_ctrl_reg
) &
562 ~A2W_PLL_CTRL_PWRDN
);
564 /* Take the PLL out of reset. */
565 cprman_write(cprman
, data
->cm_ctrl_reg
,
566 cprman_read(cprman
, data
->cm_ctrl_reg
) & ~CM_PLL_ANARST
);
568 /* Wait for the PLL to lock. */
569 timeout
= ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS
);
570 while (!(cprman_read(cprman
, CM_LOCK
) & data
->lock_mask
)) {
571 if (ktime_after(ktime_get(), timeout
)) {
572 dev_err(cprman
->dev
, "%s: couldn't lock PLL\n",
573 clk_hw_get_name(hw
));
584 bcm2835_pll_write_ana(struct bcm2835_cprman
*cprman
, u32 ana_reg_base
, u32
*ana
)
589 * ANA register setup is done as a series of writes to
590 * ANA3-ANA0, in that order. This lets us write all 4
591 * registers as a single cycle of the serdes interface (taking
592 * 100 xosc clocks), whereas if we were to update ana0, 1, and
593 * 3 individually through their partial-write registers, each
594 * would be their own serdes cycle.
596 for (i
= 3; i
>= 0; i
--)
597 cprman_write(cprman
, ana_reg_base
+ i
* 4, ana
[i
]);
600 static int bcm2835_pll_set_rate(struct clk_hw
*hw
,
601 unsigned long rate
, unsigned long parent_rate
)
603 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
604 struct bcm2835_cprman
*cprman
= pll
->cprman
;
605 const struct bcm2835_pll_data
*data
= pll
->data
;
606 bool was_using_prediv
, use_fb_prediv
, do_ana_setup_first
;
607 u32 ndiv
, fdiv
, a2w_ctl
;
611 if (rate
< data
->min_rate
|| rate
> data
->max_rate
) {
612 dev_err(cprman
->dev
, "%s: rate out of spec: %lu vs (%lu, %lu)\n",
613 clk_hw_get_name(hw
), rate
,
614 data
->min_rate
, data
->max_rate
);
618 if (rate
> data
->max_fb_rate
) {
619 use_fb_prediv
= true;
622 use_fb_prediv
= false;
625 bcm2835_pll_choose_ndiv_and_fdiv(rate
, parent_rate
, &ndiv
, &fdiv
);
627 for (i
= 3; i
>= 0; i
--)
628 ana
[i
] = cprman_read(cprman
, data
->ana_reg_base
+ i
* 4);
630 was_using_prediv
= ana
[1] & data
->ana
->fb_prediv_mask
;
632 ana
[0] &= ~data
->ana
->mask0
;
633 ana
[0] |= data
->ana
->set0
;
634 ana
[1] &= ~data
->ana
->mask1
;
635 ana
[1] |= data
->ana
->set1
;
636 ana
[3] &= ~data
->ana
->mask3
;
637 ana
[3] |= data
->ana
->set3
;
639 if (was_using_prediv
&& !use_fb_prediv
) {
640 ana
[1] &= ~data
->ana
->fb_prediv_mask
;
641 do_ana_setup_first
= true;
642 } else if (!was_using_prediv
&& use_fb_prediv
) {
643 ana
[1] |= data
->ana
->fb_prediv_mask
;
644 do_ana_setup_first
= false;
646 do_ana_setup_first
= true;
649 /* Unmask the reference clock from the oscillator. */
650 cprman_write(cprman
, A2W_XOSC_CTRL
,
651 cprman_read(cprman
, A2W_XOSC_CTRL
) |
652 data
->reference_enable_mask
);
654 if (do_ana_setup_first
)
655 bcm2835_pll_write_ana(cprman
, data
->ana_reg_base
, ana
);
657 /* Set the PLL multiplier from the oscillator. */
658 cprman_write(cprman
, data
->frac_reg
, fdiv
);
660 a2w_ctl
= cprman_read(cprman
, data
->a2w_ctrl_reg
);
661 a2w_ctl
&= ~A2W_PLL_CTRL_NDIV_MASK
;
662 a2w_ctl
|= ndiv
<< A2W_PLL_CTRL_NDIV_SHIFT
;
663 a2w_ctl
&= ~A2W_PLL_CTRL_PDIV_MASK
;
664 a2w_ctl
|= 1 << A2W_PLL_CTRL_PDIV_SHIFT
;
665 cprman_write(cprman
, data
->a2w_ctrl_reg
, a2w_ctl
);
667 if (!do_ana_setup_first
)
668 bcm2835_pll_write_ana(cprman
, data
->ana_reg_base
, ana
);
673 static int bcm2835_pll_debug_init(struct clk_hw
*hw
,
674 struct dentry
*dentry
)
676 struct bcm2835_pll
*pll
= container_of(hw
, struct bcm2835_pll
, hw
);
677 struct bcm2835_cprman
*cprman
= pll
->cprman
;
678 const struct bcm2835_pll_data
*data
= pll
->data
;
679 struct debugfs_reg32
*regs
;
681 regs
= devm_kzalloc(cprman
->dev
, 7 * sizeof(*regs
), GFP_KERNEL
);
685 regs
[0].name
= "cm_ctrl";
686 regs
[0].offset
= data
->cm_ctrl_reg
;
687 regs
[1].name
= "a2w_ctrl";
688 regs
[1].offset
= data
->a2w_ctrl_reg
;
689 regs
[2].name
= "frac";
690 regs
[2].offset
= data
->frac_reg
;
691 regs
[3].name
= "ana0";
692 regs
[3].offset
= data
->ana_reg_base
+ 0 * 4;
693 regs
[4].name
= "ana1";
694 regs
[4].offset
= data
->ana_reg_base
+ 1 * 4;
695 regs
[5].name
= "ana2";
696 regs
[5].offset
= data
->ana_reg_base
+ 2 * 4;
697 regs
[6].name
= "ana3";
698 regs
[6].offset
= data
->ana_reg_base
+ 3 * 4;
700 return bcm2835_debugfs_regset(cprman
, 0, regs
, 7, dentry
);
703 static const struct clk_ops bcm2835_pll_clk_ops
= {
704 .is_prepared
= bcm2835_pll_is_on
,
705 .prepare
= bcm2835_pll_on
,
706 .unprepare
= bcm2835_pll_off
,
707 .recalc_rate
= bcm2835_pll_get_rate
,
708 .set_rate
= bcm2835_pll_set_rate
,
709 .round_rate
= bcm2835_pll_round_rate
,
710 .debug_init
= bcm2835_pll_debug_init
,
713 struct bcm2835_pll_divider
{
714 struct clk_divider div
;
715 struct bcm2835_cprman
*cprman
;
716 const struct bcm2835_pll_divider_data
*data
;
719 static struct bcm2835_pll_divider
*
720 bcm2835_pll_divider_from_hw(struct clk_hw
*hw
)
722 return container_of(hw
, struct bcm2835_pll_divider
, div
.hw
);
725 static int bcm2835_pll_divider_is_on(struct clk_hw
*hw
)
727 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
728 struct bcm2835_cprman
*cprman
= divider
->cprman
;
729 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
731 return !(cprman_read(cprman
, data
->a2w_reg
) & A2W_PLL_CHANNEL_DISABLE
);
734 static long bcm2835_pll_divider_round_rate(struct clk_hw
*hw
,
736 unsigned long *parent_rate
)
738 return clk_divider_ops
.round_rate(hw
, rate
, parent_rate
);
741 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw
*hw
,
742 unsigned long parent_rate
)
744 return clk_divider_ops
.recalc_rate(hw
, parent_rate
);
747 static void bcm2835_pll_divider_off(struct clk_hw
*hw
)
749 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
750 struct bcm2835_cprman
*cprman
= divider
->cprman
;
751 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
753 spin_lock(&cprman
->regs_lock
);
754 cprman_write(cprman
, data
->cm_reg
,
755 (cprman_read(cprman
, data
->cm_reg
) &
756 ~data
->load_mask
) | data
->hold_mask
);
757 cprman_write(cprman
, data
->a2w_reg
, A2W_PLL_CHANNEL_DISABLE
);
758 spin_unlock(&cprman
->regs_lock
);
761 static int bcm2835_pll_divider_on(struct clk_hw
*hw
)
763 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
764 struct bcm2835_cprman
*cprman
= divider
->cprman
;
765 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
767 spin_lock(&cprman
->regs_lock
);
768 cprman_write(cprman
, data
->a2w_reg
,
769 cprman_read(cprman
, data
->a2w_reg
) &
770 ~A2W_PLL_CHANNEL_DISABLE
);
772 cprman_write(cprman
, data
->cm_reg
,
773 cprman_read(cprman
, data
->cm_reg
) & ~data
->hold_mask
);
774 spin_unlock(&cprman
->regs_lock
);
779 static int bcm2835_pll_divider_set_rate(struct clk_hw
*hw
,
781 unsigned long parent_rate
)
783 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
784 struct bcm2835_cprman
*cprman
= divider
->cprman
;
785 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
786 u32 cm
, div
, max_div
= 1 << A2W_PLL_DIV_BITS
;
788 div
= DIV_ROUND_UP_ULL(parent_rate
, rate
);
790 div
= min(div
, max_div
);
794 cprman_write(cprman
, data
->a2w_reg
, div
);
795 cm
= cprman_read(cprman
, data
->cm_reg
);
796 cprman_write(cprman
, data
->cm_reg
, cm
| data
->load_mask
);
797 cprman_write(cprman
, data
->cm_reg
, cm
& ~data
->load_mask
);
802 static int bcm2835_pll_divider_debug_init(struct clk_hw
*hw
,
803 struct dentry
*dentry
)
805 struct bcm2835_pll_divider
*divider
= bcm2835_pll_divider_from_hw(hw
);
806 struct bcm2835_cprman
*cprman
= divider
->cprman
;
807 const struct bcm2835_pll_divider_data
*data
= divider
->data
;
808 struct debugfs_reg32
*regs
;
810 regs
= devm_kzalloc(cprman
->dev
, 7 * sizeof(*regs
), GFP_KERNEL
);
815 regs
[0].offset
= data
->cm_reg
;
816 regs
[1].name
= "a2w";
817 regs
[1].offset
= data
->a2w_reg
;
819 return bcm2835_debugfs_regset(cprman
, 0, regs
, 2, dentry
);
822 static const struct clk_ops bcm2835_pll_divider_clk_ops
= {
823 .is_prepared
= bcm2835_pll_divider_is_on
,
824 .prepare
= bcm2835_pll_divider_on
,
825 .unprepare
= bcm2835_pll_divider_off
,
826 .recalc_rate
= bcm2835_pll_divider_get_rate
,
827 .set_rate
= bcm2835_pll_divider_set_rate
,
828 .round_rate
= bcm2835_pll_divider_round_rate
,
829 .debug_init
= bcm2835_pll_divider_debug_init
,
833 * The CM dividers do fixed-point division, so we can't use the
834 * generic integer divider code like the PLL dividers do (and we can't
835 * fake it by having some fixed shifts preceding it in the clock tree,
836 * because we'd run out of bits in a 32-bit unsigned long).
838 struct bcm2835_clock
{
840 struct bcm2835_cprman
*cprman
;
841 const struct bcm2835_clock_data
*data
;
844 static struct bcm2835_clock
*bcm2835_clock_from_hw(struct clk_hw
*hw
)
846 return container_of(hw
, struct bcm2835_clock
, hw
);
849 static int bcm2835_clock_is_on(struct clk_hw
*hw
)
851 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
852 struct bcm2835_cprman
*cprman
= clock
->cprman
;
853 const struct bcm2835_clock_data
*data
= clock
->data
;
855 return (cprman_read(cprman
, data
->ctl_reg
) & CM_ENABLE
) != 0;
858 static u32
bcm2835_clock_choose_div(struct clk_hw
*hw
,
860 unsigned long parent_rate
,
863 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
864 const struct bcm2835_clock_data
*data
= clock
->data
;
865 u32 unused_frac_mask
=
866 GENMASK(CM_DIV_FRAC_BITS
- data
->frac_bits
, 0) >> 1;
867 u64 temp
= (u64
)parent_rate
<< CM_DIV_FRAC_BITS
;
869 u32 div
, mindiv
, maxdiv
;
871 rem
= do_div(temp
, rate
);
874 /* Round up and mask off the unused bits */
875 if (round_up
&& ((div
& unused_frac_mask
) != 0 || rem
!= 0))
876 div
+= unused_frac_mask
+ 1;
877 div
&= ~unused_frac_mask
;
879 /* different clamping limits apply for a mash clock */
880 if (data
->is_mash_clock
) {
881 /* clamp to min divider of 2 */
882 mindiv
= 2 << CM_DIV_FRAC_BITS
;
883 /* clamp to the highest possible integer divider */
884 maxdiv
= (BIT(data
->int_bits
) - 1) << CM_DIV_FRAC_BITS
;
886 /* clamp to min divider of 1 */
887 mindiv
= 1 << CM_DIV_FRAC_BITS
;
888 /* clamp to the highest possible fractional divider */
889 maxdiv
= GENMASK(data
->int_bits
+ CM_DIV_FRAC_BITS
- 1,
890 CM_DIV_FRAC_BITS
- data
->frac_bits
);
893 /* apply the clamping limits */
894 div
= max_t(u32
, div
, mindiv
);
895 div
= min_t(u32
, div
, maxdiv
);
900 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock
*clock
,
901 unsigned long parent_rate
,
904 const struct bcm2835_clock_data
*data
= clock
->data
;
908 * The divisor is a 12.12 fixed point field, but only some of
909 * the bits are populated in any given clock.
911 div
>>= CM_DIV_FRAC_BITS
- data
->frac_bits
;
912 div
&= (1 << (data
->int_bits
+ data
->frac_bits
)) - 1;
917 temp
= (u64
)parent_rate
<< data
->frac_bits
;
924 static unsigned long bcm2835_clock_get_rate(struct clk_hw
*hw
,
925 unsigned long parent_rate
)
927 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
928 struct bcm2835_cprman
*cprman
= clock
->cprman
;
929 const struct bcm2835_clock_data
*data
= clock
->data
;
930 u32 div
= cprman_read(cprman
, data
->div_reg
);
932 return bcm2835_clock_rate_from_divisor(clock
, parent_rate
, div
);
935 static void bcm2835_clock_wait_busy(struct bcm2835_clock
*clock
)
937 struct bcm2835_cprman
*cprman
= clock
->cprman
;
938 const struct bcm2835_clock_data
*data
= clock
->data
;
939 ktime_t timeout
= ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS
);
941 while (cprman_read(cprman
, data
->ctl_reg
) & CM_BUSY
) {
942 if (ktime_after(ktime_get(), timeout
)) {
943 dev_err(cprman
->dev
, "%s: couldn't lock PLL\n",
944 clk_hw_get_name(&clock
->hw
));
951 static void bcm2835_clock_off(struct clk_hw
*hw
)
953 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
954 struct bcm2835_cprman
*cprman
= clock
->cprman
;
955 const struct bcm2835_clock_data
*data
= clock
->data
;
957 spin_lock(&cprman
->regs_lock
);
958 cprman_write(cprman
, data
->ctl_reg
,
959 cprman_read(cprman
, data
->ctl_reg
) & ~CM_ENABLE
);
960 spin_unlock(&cprman
->regs_lock
);
962 /* BUSY will remain high until the divider completes its cycle. */
963 bcm2835_clock_wait_busy(clock
);
966 static int bcm2835_clock_on(struct clk_hw
*hw
)
968 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
969 struct bcm2835_cprman
*cprman
= clock
->cprman
;
970 const struct bcm2835_clock_data
*data
= clock
->data
;
972 spin_lock(&cprman
->regs_lock
);
973 cprman_write(cprman
, data
->ctl_reg
,
974 cprman_read(cprman
, data
->ctl_reg
) |
977 spin_unlock(&cprman
->regs_lock
);
982 static int bcm2835_clock_set_rate(struct clk_hw
*hw
,
983 unsigned long rate
, unsigned long parent_rate
)
985 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
986 struct bcm2835_cprman
*cprman
= clock
->cprman
;
987 const struct bcm2835_clock_data
*data
= clock
->data
;
988 u32 div
= bcm2835_clock_choose_div(hw
, rate
, parent_rate
, false);
991 spin_lock(&cprman
->regs_lock
);
994 * Setting up frac support
996 * In principle it is recommended to stop/start the clock first,
997 * but as we set CLK_SET_RATE_GATE during registration of the
998 * clock this requirement should be take care of by the
1001 ctl
= cprman_read(cprman
, data
->ctl_reg
) & ~CM_FRAC
;
1002 ctl
|= (div
& CM_DIV_FRAC_MASK
) ? CM_FRAC
: 0;
1003 cprman_write(cprman
, data
->ctl_reg
, ctl
);
1005 cprman_write(cprman
, data
->div_reg
, div
);
1007 spin_unlock(&cprman
->regs_lock
);
1013 bcm2835_clk_is_pllc(struct clk_hw
*hw
)
1018 return strncmp(clk_hw_get_name(hw
), "pllc", 4) == 0;
1021 static int bcm2835_clock_determine_rate(struct clk_hw
*hw
,
1022 struct clk_rate_request
*req
)
1024 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1025 struct clk_hw
*parent
, *best_parent
= NULL
;
1026 bool current_parent_is_pllc
;
1027 unsigned long rate
, best_rate
= 0;
1028 unsigned long prate
, best_prate
= 0;
1032 current_parent_is_pllc
= bcm2835_clk_is_pllc(clk_hw_get_parent(hw
));
1035 * Select parent clock that results in the closest but lower rate
1037 for (i
= 0; i
< clk_hw_get_num_parents(hw
); ++i
) {
1038 parent
= clk_hw_get_parent_by_index(hw
, i
);
1043 * Don't choose a PLLC-derived clock as our parent
1044 * unless it had been manually set that way. PLLC's
1045 * frequency gets adjusted by the firmware due to
1046 * over-temp or under-voltage conditions, without
1047 * prior notification to our clock consumer.
1049 if (bcm2835_clk_is_pllc(parent
) && !current_parent_is_pllc
)
1052 prate
= clk_hw_get_rate(parent
);
1053 div
= bcm2835_clock_choose_div(hw
, req
->rate
, prate
, true);
1054 rate
= bcm2835_clock_rate_from_divisor(clock
, prate
, div
);
1055 if (rate
> best_rate
&& rate
<= req
->rate
) {
1056 best_parent
= parent
;
1065 req
->best_parent_hw
= best_parent
;
1066 req
->best_parent_rate
= best_prate
;
1068 req
->rate
= best_rate
;
1073 static int bcm2835_clock_set_parent(struct clk_hw
*hw
, u8 index
)
1075 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1076 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1077 const struct bcm2835_clock_data
*data
= clock
->data
;
1078 u8 src
= (index
<< CM_SRC_SHIFT
) & CM_SRC_MASK
;
1080 cprman_write(cprman
, data
->ctl_reg
, src
);
1084 static u8
bcm2835_clock_get_parent(struct clk_hw
*hw
)
1086 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1087 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1088 const struct bcm2835_clock_data
*data
= clock
->data
;
1089 u32 src
= cprman_read(cprman
, data
->ctl_reg
);
1091 return (src
& CM_SRC_MASK
) >> CM_SRC_SHIFT
;
1094 static struct debugfs_reg32 bcm2835_debugfs_clock_reg32
[] = {
1105 static int bcm2835_clock_debug_init(struct clk_hw
*hw
,
1106 struct dentry
*dentry
)
1108 struct bcm2835_clock
*clock
= bcm2835_clock_from_hw(hw
);
1109 struct bcm2835_cprman
*cprman
= clock
->cprman
;
1110 const struct bcm2835_clock_data
*data
= clock
->data
;
1112 return bcm2835_debugfs_regset(
1113 cprman
, data
->ctl_reg
,
1114 bcm2835_debugfs_clock_reg32
,
1115 ARRAY_SIZE(bcm2835_debugfs_clock_reg32
),
1119 static const struct clk_ops bcm2835_clock_clk_ops
= {
1120 .is_prepared
= bcm2835_clock_is_on
,
1121 .prepare
= bcm2835_clock_on
,
1122 .unprepare
= bcm2835_clock_off
,
1123 .recalc_rate
= bcm2835_clock_get_rate
,
1124 .set_rate
= bcm2835_clock_set_rate
,
1125 .determine_rate
= bcm2835_clock_determine_rate
,
1126 .set_parent
= bcm2835_clock_set_parent
,
1127 .get_parent
= bcm2835_clock_get_parent
,
1128 .debug_init
= bcm2835_clock_debug_init
,
1131 static int bcm2835_vpu_clock_is_on(struct clk_hw
*hw
)
1137 * The VPU clock can never be disabled (it doesn't have an ENABLE
1138 * bit), so it gets its own set of clock ops.
1140 static const struct clk_ops bcm2835_vpu_clock_clk_ops
= {
1141 .is_prepared
= bcm2835_vpu_clock_is_on
,
1142 .recalc_rate
= bcm2835_clock_get_rate
,
1143 .set_rate
= bcm2835_clock_set_rate
,
1144 .determine_rate
= bcm2835_clock_determine_rate
,
1145 .set_parent
= bcm2835_clock_set_parent
,
1146 .get_parent
= bcm2835_clock_get_parent
,
1147 .debug_init
= bcm2835_clock_debug_init
,
1150 static struct clk_hw
*bcm2835_register_pll(struct bcm2835_cprman
*cprman
,
1151 const struct bcm2835_pll_data
*data
)
1153 struct bcm2835_pll
*pll
;
1154 struct clk_init_data init
;
1157 memset(&init
, 0, sizeof(init
));
1159 /* All of the PLLs derive from the external oscillator. */
1160 init
.parent_names
= &cprman
->osc_name
;
1161 init
.num_parents
= 1;
1162 init
.name
= data
->name
;
1163 init
.ops
= &bcm2835_pll_clk_ops
;
1164 init
.flags
= CLK_IGNORE_UNUSED
;
1166 pll
= kzalloc(sizeof(*pll
), GFP_KERNEL
);
1170 pll
->cprman
= cprman
;
1172 pll
->hw
.init
= &init
;
1174 ret
= devm_clk_hw_register(cprman
->dev
, &pll
->hw
);
1180 static struct clk_hw
*
1181 bcm2835_register_pll_divider(struct bcm2835_cprman
*cprman
,
1182 const struct bcm2835_pll_divider_data
*data
)
1184 struct bcm2835_pll_divider
*divider
;
1185 struct clk_init_data init
;
1186 const char *divider_name
;
1189 if (data
->fixed_divider
!= 1) {
1190 divider_name
= devm_kasprintf(cprman
->dev
, GFP_KERNEL
,
1191 "%s_prediv", data
->name
);
1195 divider_name
= data
->name
;
1198 memset(&init
, 0, sizeof(init
));
1200 init
.parent_names
= &data
->source_pll
;
1201 init
.num_parents
= 1;
1202 init
.name
= divider_name
;
1203 init
.ops
= &bcm2835_pll_divider_clk_ops
;
1204 init
.flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
;
1206 divider
= devm_kzalloc(cprman
->dev
, sizeof(*divider
), GFP_KERNEL
);
1210 divider
->div
.reg
= cprman
->regs
+ data
->a2w_reg
;
1211 divider
->div
.shift
= A2W_PLL_DIV_SHIFT
;
1212 divider
->div
.width
= A2W_PLL_DIV_BITS
;
1213 divider
->div
.flags
= CLK_DIVIDER_MAX_AT_ZERO
;
1214 divider
->div
.lock
= &cprman
->regs_lock
;
1215 divider
->div
.hw
.init
= &init
;
1216 divider
->div
.table
= NULL
;
1218 divider
->cprman
= cprman
;
1219 divider
->data
= data
;
1221 ret
= devm_clk_hw_register(cprman
->dev
, ÷r
->div
.hw
);
1223 return ERR_PTR(ret
);
1226 * PLLH's channels have a fixed divide by 10 afterwards, which
1227 * is what our consumers are actually using.
1229 if (data
->fixed_divider
!= 1) {
1230 return clk_hw_register_fixed_factor(cprman
->dev
, data
->name
,
1232 CLK_SET_RATE_PARENT
,
1234 data
->fixed_divider
);
1237 return ÷r
->div
.hw
;
1240 static struct clk_hw
*bcm2835_register_clock(struct bcm2835_cprman
*cprman
,
1241 const struct bcm2835_clock_data
*data
)
1243 struct bcm2835_clock
*clock
;
1244 struct clk_init_data init
;
1245 const char *parents
[1 << CM_SRC_BITS
];
1250 * Replace our "xosc" references with the oscillator's
1253 for (i
= 0; i
< data
->num_mux_parents
; i
++) {
1254 if (strcmp(data
->parents
[i
], "xosc") == 0)
1255 parents
[i
] = cprman
->osc_name
;
1257 parents
[i
] = data
->parents
[i
];
1260 memset(&init
, 0, sizeof(init
));
1261 init
.parent_names
= parents
;
1262 init
.num_parents
= data
->num_mux_parents
;
1263 init
.name
= data
->name
;
1264 init
.flags
= data
->flags
| CLK_IGNORE_UNUSED
;
1266 if (data
->is_vpu_clock
) {
1267 init
.ops
= &bcm2835_vpu_clock_clk_ops
;
1269 init
.ops
= &bcm2835_clock_clk_ops
;
1270 init
.flags
|= CLK_SET_RATE_GATE
| CLK_SET_PARENT_GATE
;
1272 /* If the clock wasn't actually enabled at boot, it's not
1275 if (!(cprman_read(cprman
, data
->ctl_reg
) & CM_ENABLE
))
1276 init
.flags
&= ~CLK_IS_CRITICAL
;
1279 clock
= devm_kzalloc(cprman
->dev
, sizeof(*clock
), GFP_KERNEL
);
1283 clock
->cprman
= cprman
;
1285 clock
->hw
.init
= &init
;
1287 ret
= devm_clk_hw_register(cprman
->dev
, &clock
->hw
);
1289 return ERR_PTR(ret
);
1293 static struct clk
*bcm2835_register_gate(struct bcm2835_cprman
*cprman
,
1294 const struct bcm2835_gate_data
*data
)
1296 return clk_register_gate(cprman
->dev
, data
->name
, data
->parent
,
1297 CLK_IGNORE_UNUSED
| CLK_SET_RATE_GATE
,
1298 cprman
->regs
+ data
->ctl_reg
,
1299 CM_GATE_BIT
, 0, &cprman
->regs_lock
);
1302 typedef struct clk_hw
*(*bcm2835_clk_register
)(struct bcm2835_cprman
*cprman
,
1304 struct bcm2835_clk_desc
{
1305 bcm2835_clk_register clk_register
;
1309 /* assignment helper macros for different clock types */
1310 #define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
1311 .data = __VA_ARGS__ }
1312 #define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \
1313 &(struct bcm2835_pll_data) \
1315 #define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \
1316 &(struct bcm2835_pll_divider_data) \
1318 #define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \
1319 &(struct bcm2835_clock_data) \
1321 #define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \
1322 &(struct bcm2835_gate_data) \
1325 /* parent mux arrays plus helper macros */
1327 /* main oscillator parent mux */
1328 static const char *const bcm2835_clock_osc_parents
[] = {
1335 #define REGISTER_OSC_CLK(...) REGISTER_CLK( \
1336 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
1337 .parents = bcm2835_clock_osc_parents, \
1340 /* main peripherial parent mux */
1341 static const char *const bcm2835_clock_per_parents
[] = {
1352 #define REGISTER_PER_CLK(...) REGISTER_CLK( \
1353 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
1354 .parents = bcm2835_clock_per_parents, \
1357 /* main vpu parent mux */
1358 static const char *const bcm2835_clock_vpu_parents
[] = {
1371 #define REGISTER_VPU_CLK(...) REGISTER_CLK( \
1372 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
1373 .parents = bcm2835_clock_vpu_parents, \
1377 * the real definition of all the pll, pll_dividers and clocks
1378 * these make use of the above REGISTER_* macros
1380 static const struct bcm2835_clk_desc clk_desc_array
[] = {
1381 /* the PLL + PLL dividers */
1384 * PLLA is the auxiliary PLL, used to drive the CCP2
1385 * (Compact Camera Port 2) transmitter clock.
1387 * It is in the PX LDO power domain, which is on when the
1388 * AUDIO domain is on.
1390 [BCM2835_PLLA
] = REGISTER_PLL(
1392 .cm_ctrl_reg
= CM_PLLA
,
1393 .a2w_ctrl_reg
= A2W_PLLA_CTRL
,
1394 .frac_reg
= A2W_PLLA_FRAC
,
1395 .ana_reg_base
= A2W_PLLA_ANA0
,
1396 .reference_enable_mask
= A2W_XOSC_CTRL_PLLA_ENABLE
,
1397 .lock_mask
= CM_LOCK_FLOCKA
,
1399 .ana
= &bcm2835_ana_default
,
1401 .min_rate
= 600000000u,
1402 .max_rate
= 2400000000u,
1403 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1404 [BCM2835_PLLA_CORE
] = REGISTER_PLL_DIV(
1405 .name
= "plla_core",
1406 .source_pll
= "plla",
1408 .a2w_reg
= A2W_PLLA_CORE
,
1409 .load_mask
= CM_PLLA_LOADCORE
,
1410 .hold_mask
= CM_PLLA_HOLDCORE
,
1411 .fixed_divider
= 1),
1412 [BCM2835_PLLA_PER
] = REGISTER_PLL_DIV(
1414 .source_pll
= "plla",
1416 .a2w_reg
= A2W_PLLA_PER
,
1417 .load_mask
= CM_PLLA_LOADPER
,
1418 .hold_mask
= CM_PLLA_HOLDPER
,
1419 .fixed_divider
= 1),
1420 [BCM2835_PLLA_DSI0
] = REGISTER_PLL_DIV(
1421 .name
= "plla_dsi0",
1422 .source_pll
= "plla",
1424 .a2w_reg
= A2W_PLLA_DSI0
,
1425 .load_mask
= CM_PLLA_LOADDSI0
,
1426 .hold_mask
= CM_PLLA_HOLDDSI0
,
1427 .fixed_divider
= 1),
1428 [BCM2835_PLLA_CCP2
] = REGISTER_PLL_DIV(
1429 .name
= "plla_ccp2",
1430 .source_pll
= "plla",
1432 .a2w_reg
= A2W_PLLA_CCP2
,
1433 .load_mask
= CM_PLLA_LOADCCP2
,
1434 .hold_mask
= CM_PLLA_HOLDCCP2
,
1435 .fixed_divider
= 1),
1437 /* PLLB is used for the ARM's clock. */
1438 [BCM2835_PLLB
] = REGISTER_PLL(
1440 .cm_ctrl_reg
= CM_PLLB
,
1441 .a2w_ctrl_reg
= A2W_PLLB_CTRL
,
1442 .frac_reg
= A2W_PLLB_FRAC
,
1443 .ana_reg_base
= A2W_PLLB_ANA0
,
1444 .reference_enable_mask
= A2W_XOSC_CTRL_PLLB_ENABLE
,
1445 .lock_mask
= CM_LOCK_FLOCKB
,
1447 .ana
= &bcm2835_ana_default
,
1449 .min_rate
= 600000000u,
1450 .max_rate
= 3000000000u,
1451 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1452 [BCM2835_PLLB_ARM
] = REGISTER_PLL_DIV(
1454 .source_pll
= "pllb",
1456 .a2w_reg
= A2W_PLLB_ARM
,
1457 .load_mask
= CM_PLLB_LOADARM
,
1458 .hold_mask
= CM_PLLB_HOLDARM
,
1459 .fixed_divider
= 1),
1462 * PLLC is the core PLL, used to drive the core VPU clock.
1464 * It is in the PX LDO power domain, which is on when the
1465 * AUDIO domain is on.
1467 [BCM2835_PLLC
] = REGISTER_PLL(
1469 .cm_ctrl_reg
= CM_PLLC
,
1470 .a2w_ctrl_reg
= A2W_PLLC_CTRL
,
1471 .frac_reg
= A2W_PLLC_FRAC
,
1472 .ana_reg_base
= A2W_PLLC_ANA0
,
1473 .reference_enable_mask
= A2W_XOSC_CTRL_PLLC_ENABLE
,
1474 .lock_mask
= CM_LOCK_FLOCKC
,
1476 .ana
= &bcm2835_ana_default
,
1478 .min_rate
= 600000000u,
1479 .max_rate
= 3000000000u,
1480 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1481 [BCM2835_PLLC_CORE0
] = REGISTER_PLL_DIV(
1482 .name
= "pllc_core0",
1483 .source_pll
= "pllc",
1485 .a2w_reg
= A2W_PLLC_CORE0
,
1486 .load_mask
= CM_PLLC_LOADCORE0
,
1487 .hold_mask
= CM_PLLC_HOLDCORE0
,
1488 .fixed_divider
= 1),
1489 [BCM2835_PLLC_CORE1
] = REGISTER_PLL_DIV(
1490 .name
= "pllc_core1",
1491 .source_pll
= "pllc",
1493 .a2w_reg
= A2W_PLLC_CORE1
,
1494 .load_mask
= CM_PLLC_LOADCORE1
,
1495 .hold_mask
= CM_PLLC_HOLDCORE1
,
1496 .fixed_divider
= 1),
1497 [BCM2835_PLLC_CORE2
] = REGISTER_PLL_DIV(
1498 .name
= "pllc_core2",
1499 .source_pll
= "pllc",
1501 .a2w_reg
= A2W_PLLC_CORE2
,
1502 .load_mask
= CM_PLLC_LOADCORE2
,
1503 .hold_mask
= CM_PLLC_HOLDCORE2
,
1504 .fixed_divider
= 1),
1505 [BCM2835_PLLC_PER
] = REGISTER_PLL_DIV(
1507 .source_pll
= "pllc",
1509 .a2w_reg
= A2W_PLLC_PER
,
1510 .load_mask
= CM_PLLC_LOADPER
,
1511 .hold_mask
= CM_PLLC_HOLDPER
,
1512 .fixed_divider
= 1),
1515 * PLLD is the display PLL, used to drive DSI display panels.
1517 * It is in the PX LDO power domain, which is on when the
1518 * AUDIO domain is on.
1520 [BCM2835_PLLD
] = REGISTER_PLL(
1522 .cm_ctrl_reg
= CM_PLLD
,
1523 .a2w_ctrl_reg
= A2W_PLLD_CTRL
,
1524 .frac_reg
= A2W_PLLD_FRAC
,
1525 .ana_reg_base
= A2W_PLLD_ANA0
,
1526 .reference_enable_mask
= A2W_XOSC_CTRL_DDR_ENABLE
,
1527 .lock_mask
= CM_LOCK_FLOCKD
,
1529 .ana
= &bcm2835_ana_default
,
1531 .min_rate
= 600000000u,
1532 .max_rate
= 2400000000u,
1533 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1534 [BCM2835_PLLD_CORE
] = REGISTER_PLL_DIV(
1535 .name
= "plld_core",
1536 .source_pll
= "plld",
1538 .a2w_reg
= A2W_PLLD_CORE
,
1539 .load_mask
= CM_PLLD_LOADCORE
,
1540 .hold_mask
= CM_PLLD_HOLDCORE
,
1541 .fixed_divider
= 1),
1542 [BCM2835_PLLD_PER
] = REGISTER_PLL_DIV(
1544 .source_pll
= "plld",
1546 .a2w_reg
= A2W_PLLD_PER
,
1547 .load_mask
= CM_PLLD_LOADPER
,
1548 .hold_mask
= CM_PLLD_HOLDPER
,
1549 .fixed_divider
= 1),
1550 [BCM2835_PLLD_DSI0
] = REGISTER_PLL_DIV(
1551 .name
= "plld_dsi0",
1552 .source_pll
= "plld",
1554 .a2w_reg
= A2W_PLLD_DSI0
,
1555 .load_mask
= CM_PLLD_LOADDSI0
,
1556 .hold_mask
= CM_PLLD_HOLDDSI0
,
1557 .fixed_divider
= 1),
1558 [BCM2835_PLLD_DSI1
] = REGISTER_PLL_DIV(
1559 .name
= "plld_dsi1",
1560 .source_pll
= "plld",
1562 .a2w_reg
= A2W_PLLD_DSI1
,
1563 .load_mask
= CM_PLLD_LOADDSI1
,
1564 .hold_mask
= CM_PLLD_HOLDDSI1
,
1565 .fixed_divider
= 1),
1568 * PLLH is used to supply the pixel clock or the AUX clock for the
1571 * It is in the HDMI power domain.
1573 [BCM2835_PLLH
] = REGISTER_PLL(
1575 .cm_ctrl_reg
= CM_PLLH
,
1576 .a2w_ctrl_reg
= A2W_PLLH_CTRL
,
1577 .frac_reg
= A2W_PLLH_FRAC
,
1578 .ana_reg_base
= A2W_PLLH_ANA0
,
1579 .reference_enable_mask
= A2W_XOSC_CTRL_PLLC_ENABLE
,
1580 .lock_mask
= CM_LOCK_FLOCKH
,
1582 .ana
= &bcm2835_ana_pllh
,
1584 .min_rate
= 600000000u,
1585 .max_rate
= 3000000000u,
1586 .max_fb_rate
= BCM2835_MAX_FB_RATE
),
1587 [BCM2835_PLLH_RCAL
] = REGISTER_PLL_DIV(
1588 .name
= "pllh_rcal",
1589 .source_pll
= "pllh",
1591 .a2w_reg
= A2W_PLLH_RCAL
,
1592 .load_mask
= CM_PLLH_LOADRCAL
,
1594 .fixed_divider
= 10),
1595 [BCM2835_PLLH_AUX
] = REGISTER_PLL_DIV(
1597 .source_pll
= "pllh",
1599 .a2w_reg
= A2W_PLLH_AUX
,
1600 .load_mask
= CM_PLLH_LOADAUX
,
1602 .fixed_divider
= 10),
1603 [BCM2835_PLLH_PIX
] = REGISTER_PLL_DIV(
1605 .source_pll
= "pllh",
1607 .a2w_reg
= A2W_PLLH_PIX
,
1608 .load_mask
= CM_PLLH_LOADPIX
,
1610 .fixed_divider
= 10),
1614 /* clocks with oscillator parent mux */
1616 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1617 [BCM2835_CLOCK_OTP
] = REGISTER_OSC_CLK(
1619 .ctl_reg
= CM_OTPCTL
,
1620 .div_reg
= CM_OTPDIV
,
1624 * Used for a 1Mhz clock for the system clocksource, and also used
1625 * bythe watchdog timer and the camera pulse generator.
1627 [BCM2835_CLOCK_TIMER
] = REGISTER_OSC_CLK(
1629 .ctl_reg
= CM_TIMERCTL
,
1630 .div_reg
= CM_TIMERDIV
,
1634 * Clock for the temperature sensor.
1635 * Generally run at 2Mhz, max 5Mhz.
1637 [BCM2835_CLOCK_TSENS
] = REGISTER_OSC_CLK(
1639 .ctl_reg
= CM_TSENSCTL
,
1640 .div_reg
= CM_TSENSDIV
,
1643 [BCM2835_CLOCK_TEC
] = REGISTER_OSC_CLK(
1645 .ctl_reg
= CM_TECCTL
,
1646 .div_reg
= CM_TECDIV
,
1650 /* clocks with vpu parent mux */
1651 [BCM2835_CLOCK_H264
] = REGISTER_VPU_CLK(
1653 .ctl_reg
= CM_H264CTL
,
1654 .div_reg
= CM_H264DIV
,
1657 [BCM2835_CLOCK_ISP
] = REGISTER_VPU_CLK(
1659 .ctl_reg
= CM_ISPCTL
,
1660 .div_reg
= CM_ISPDIV
,
1665 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
1666 * in the SDRAM controller can't be used.
1668 [BCM2835_CLOCK_SDRAM
] = REGISTER_VPU_CLK(
1670 .ctl_reg
= CM_SDCCTL
,
1671 .div_reg
= CM_SDCDIV
,
1674 [BCM2835_CLOCK_V3D
] = REGISTER_VPU_CLK(
1676 .ctl_reg
= CM_V3DCTL
,
1677 .div_reg
= CM_V3DDIV
,
1681 * VPU clock. This doesn't have an enable bit, since it drives
1682 * the bus for everything else, and is special so it doesn't need
1683 * to be gated for rate changes. It is also known as "clk_audio"
1684 * in various hardware documentation.
1686 [BCM2835_CLOCK_VPU
] = REGISTER_VPU_CLK(
1688 .ctl_reg
= CM_VPUCTL
,
1689 .div_reg
= CM_VPUDIV
,
1692 .flags
= CLK_IS_CRITICAL
,
1693 .is_vpu_clock
= true),
1695 /* clocks with per parent mux */
1696 [BCM2835_CLOCK_AVEO
] = REGISTER_PER_CLK(
1698 .ctl_reg
= CM_AVEOCTL
,
1699 .div_reg
= CM_AVEODIV
,
1702 [BCM2835_CLOCK_CAM0
] = REGISTER_PER_CLK(
1704 .ctl_reg
= CM_CAM0CTL
,
1705 .div_reg
= CM_CAM0DIV
,
1708 [BCM2835_CLOCK_CAM1
] = REGISTER_PER_CLK(
1710 .ctl_reg
= CM_CAM1CTL
,
1711 .div_reg
= CM_CAM1DIV
,
1714 [BCM2835_CLOCK_DFT
] = REGISTER_PER_CLK(
1716 .ctl_reg
= CM_DFTCTL
,
1717 .div_reg
= CM_DFTDIV
,
1720 [BCM2835_CLOCK_DPI
] = REGISTER_PER_CLK(
1722 .ctl_reg
= CM_DPICTL
,
1723 .div_reg
= CM_DPIDIV
,
1727 /* Arasan EMMC clock */
1728 [BCM2835_CLOCK_EMMC
] = REGISTER_PER_CLK(
1730 .ctl_reg
= CM_EMMCCTL
,
1731 .div_reg
= CM_EMMCDIV
,
1735 /* General purpose (GPIO) clocks */
1736 [BCM2835_CLOCK_GP0
] = REGISTER_PER_CLK(
1738 .ctl_reg
= CM_GP0CTL
,
1739 .div_reg
= CM_GP0DIV
,
1742 .is_mash_clock
= true),
1743 [BCM2835_CLOCK_GP1
] = REGISTER_PER_CLK(
1745 .ctl_reg
= CM_GP1CTL
,
1746 .div_reg
= CM_GP1DIV
,
1749 .flags
= CLK_IS_CRITICAL
,
1750 .is_mash_clock
= true),
1751 [BCM2835_CLOCK_GP2
] = REGISTER_PER_CLK(
1753 .ctl_reg
= CM_GP2CTL
,
1754 .div_reg
= CM_GP2DIV
,
1757 .flags
= CLK_IS_CRITICAL
),
1759 /* HDMI state machine */
1760 [BCM2835_CLOCK_HSM
] = REGISTER_PER_CLK(
1762 .ctl_reg
= CM_HSMCTL
,
1763 .div_reg
= CM_HSMDIV
,
1766 [BCM2835_CLOCK_PCM
] = REGISTER_PER_CLK(
1768 .ctl_reg
= CM_PCMCTL
,
1769 .div_reg
= CM_PCMDIV
,
1772 .is_mash_clock
= true),
1773 [BCM2835_CLOCK_PWM
] = REGISTER_PER_CLK(
1775 .ctl_reg
= CM_PWMCTL
,
1776 .div_reg
= CM_PWMDIV
,
1779 .is_mash_clock
= true),
1780 [BCM2835_CLOCK_SLIM
] = REGISTER_PER_CLK(
1782 .ctl_reg
= CM_SLIMCTL
,
1783 .div_reg
= CM_SLIMDIV
,
1786 .is_mash_clock
= true),
1787 [BCM2835_CLOCK_SMI
] = REGISTER_PER_CLK(
1789 .ctl_reg
= CM_SMICTL
,
1790 .div_reg
= CM_SMIDIV
,
1793 [BCM2835_CLOCK_UART
] = REGISTER_PER_CLK(
1795 .ctl_reg
= CM_UARTCTL
,
1796 .div_reg
= CM_UARTDIV
,
1800 /* TV encoder clock. Only operating frequency is 108Mhz. */
1801 [BCM2835_CLOCK_VEC
] = REGISTER_PER_CLK(
1803 .ctl_reg
= CM_VECCTL
,
1804 .div_reg
= CM_VECDIV
,
1809 [BCM2835_CLOCK_DSI0E
] = REGISTER_PER_CLK(
1811 .ctl_reg
= CM_DSI0ECTL
,
1812 .div_reg
= CM_DSI0EDIV
,
1815 [BCM2835_CLOCK_DSI1E
] = REGISTER_PER_CLK(
1817 .ctl_reg
= CM_DSI1ECTL
,
1818 .div_reg
= CM_DSI1EDIV
,
1825 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
1826 * you have the debug bit set in the power manager, which we
1827 * don't bother exposing) are individual gates off of the
1828 * non-stop vpu clock.
1830 [BCM2835_CLOCK_PERI_IMAGE
] = REGISTER_GATE(
1831 .name
= "peri_image",
1833 .ctl_reg
= CM_PERIICTL
),
1837 * Permanently take a reference on the parent of the SDRAM clock.
1839 * While the SDRAM is being driven by its dedicated PLL most of the
1840 * time, there is a little loop running in the firmware that
1841 * periodically switches the SDRAM to using our CM clock to do PVT
1842 * recalibration, with the assumption that the previously configured
1843 * SDRAM parent is still enabled and running.
1845 static int bcm2835_mark_sdc_parent_critical(struct clk
*sdc
)
1847 struct clk
*parent
= clk_get_parent(sdc
);
1850 return PTR_ERR(parent
);
1852 return clk_prepare_enable(parent
);
1855 static int bcm2835_clk_probe(struct platform_device
*pdev
)
1857 struct device
*dev
= &pdev
->dev
;
1858 struct clk_hw
**hws
;
1859 struct bcm2835_cprman
*cprman
;
1860 struct resource
*res
;
1861 const struct bcm2835_clk_desc
*desc
;
1862 const size_t asize
= ARRAY_SIZE(clk_desc_array
);
1866 cprman
= devm_kzalloc(dev
, sizeof(*cprman
) +
1867 sizeof(*cprman
->onecell
.hws
) * asize
,
1872 spin_lock_init(&cprman
->regs_lock
);
1874 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1875 cprman
->regs
= devm_ioremap_resource(dev
, res
);
1876 if (IS_ERR(cprman
->regs
))
1877 return PTR_ERR(cprman
->regs
);
1879 cprman
->osc_name
= of_clk_get_parent_name(dev
->of_node
, 0);
1880 if (!cprman
->osc_name
)
1883 platform_set_drvdata(pdev
, cprman
);
1885 cprman
->onecell
.num
= asize
;
1886 hws
= cprman
->onecell
.hws
;
1888 for (i
= 0; i
< asize
; i
++) {
1889 desc
= &clk_desc_array
[i
];
1890 if (desc
->clk_register
&& desc
->data
)
1891 hws
[i
] = desc
->clk_register(cprman
, desc
->data
);
1894 ret
= bcm2835_mark_sdc_parent_critical(hws
[BCM2835_CLOCK_SDRAM
]->clk
);
1898 return of_clk_add_hw_provider(dev
->of_node
, of_clk_hw_onecell_get
,
1902 static const struct of_device_id bcm2835_clk_of_match
[] = {
1903 { .compatible
= "brcm,bcm2835-cprman", },
1906 MODULE_DEVICE_TABLE(of
, bcm2835_clk_of_match
);
1908 static struct platform_driver bcm2835_clk_driver
= {
1910 .name
= "bcm2835-clk",
1911 .of_match_table
= bcm2835_clk_of_match
,
1913 .probe
= bcm2835_clk_probe
,
1916 builtin_platform_driver(bcm2835_clk_driver
);
1918 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
1919 MODULE_DESCRIPTION("BCM2835 clock driver");
1920 MODULE_LICENSE("GPL v2");