drivers/clk/berlin/berlin2-pll.c

   1 /*
   2  * Copyright (c) 2014 Marvell Technology Group Ltd.
   3  *
   4  * Alexandre Belloni <alexandre.belloni@free-electrons.com>
   5  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <linux/clk-provider.h>
  20 #include <linux/io.h>
  21 #include <linux/kernel.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/slab.h>
  25 #include <asm/div64.h>
  26
  27 #include "berlin2-div.h"
  28
  29 struct berlin2_pll_map {
  30         const u8 vcodiv[16];
  31         u8 mult;
  32         u8 fbdiv_shift;
  33         u8 rfdiv_shift;
  34         u8 divsel_shift;
  35 };
  36
  37 struct berlin2_pll {
  38         struct clk_hw hw;
  39         void __iomem *base;
  40         struct berlin2_pll_map map;
  41 };
  42
  43 #define to_berlin2_pll(hw) container_of(hw, struct berlin2_pll, hw)
  44
  45 #define SPLL_CTRL0      0x00
  46 #define SPLL_CTRL1      0x04
  47 #define SPLL_CTRL2      0x08
  48 #define SPLL_CTRL3      0x0c
  49 #define SPLL_CTRL4      0x10
  50
  51 #define FBDIV_MASK      0x1ff
  52 #define RFDIV_MASK      0x1f
  53 #define DIVSEL_MASK     0xf
  54
  55 /*
  56  * The output frequency formula for the pll is:
  57  * clkout = fbdiv / refdiv * parent / vcodiv
  58  */
  59 static unsigned long
  60 berlin2_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
  61 {
  62         struct berlin2_pll *pll = to_berlin2_pll(hw);
  63         struct berlin2_pll_map *map = &pll->map;
  64         u32 val, fbdiv, rfdiv, vcodivsel, vcodiv;
  65         u64 rate = parent_rate;
  66
  67         val = readl_relaxed(pll->base + SPLL_CTRL0);
  68         fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK;
  69         rfdiv = (val >> map->rfdiv_shift) & RFDIV_MASK;
  70         if (rfdiv == 0) {
  71                 pr_warn("%s has zero rfdiv\n", __clk_get_name(hw->clk));
  72                 rfdiv = 1;
  73         }
  74
  75         val = readl_relaxed(pll->base + SPLL_CTRL1);
  76         vcodivsel = (val >> map->divsel_shift) & DIVSEL_MASK;
  77         vcodiv = map->vcodiv[vcodivsel];
  78         if (vcodiv == 0) {
  79                 pr_warn("%s has zero vcodiv (index %d)\n",
  80                         __clk_get_name(hw->clk), vcodivsel);
  81                 vcodiv = 1;
  82         }
  83
  84         rate *= fbdiv * map->mult;
  85         do_div(rate, rfdiv * vcodiv);
  86
  87         return (unsigned long)rate;
  88 }
  89
  90 static const struct clk_ops berlin2_pll_ops = {
  91         .recalc_rate    = berlin2_pll_recalc_rate,
  92 };
  93
  94 struct clk * __init
  95 berlin2_pll_register(const struct berlin2_pll_map *map,
  96                      void __iomem *base, const char *name,
  97                      const char *parent_name, unsigned long flags)
  98 {
  99         struct clk_init_data init;
 100         struct berlin2_pll *pll;
 101
 102         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 103         if (!pll)
 104                 return ERR_PTR(-ENOMEM);
 105
 106         /* copy pll_map to allow __initconst */
 107         memcpy(&pll->map, map, sizeof(*map));
 108         pll->base = base;
 109         pll->hw.init = &init;
 110         init.name = name;
 111         init.ops = &berlin2_pll_ops;
 112         init.parent_names = &parent_name;
 113         init.num_parents = 1;
 114         init.flags = flags;
 115
 116         return clk_register(NULL, &pll->hw);
 117 }