2 * Clock implementation for VIA/Wondermedia SoC's
3 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
18 #include <linux/slab.h>
19 #include <linux/bitops.h>
20 #include <linux/clkdev.h>
21 #include <linux/clk-provider.h>
23 /* All clocks share the same lock as none can be changed concurrently */
24 static DEFINE_SPINLOCK(_lock
);
28 void __iomem
*div_reg
;
29 unsigned int div_mask
;
36 * Add new PLL_TYPE_x definitions here as required. Use the first known model
37 * to support the new type as the name.
38 * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
39 * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
42 #define PLL_TYPE_VT8500 0
43 #define PLL_TYPE_WM8650 1
52 static void __iomem
*pmc_base
;
54 #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
56 #define VT8500_PMC_BUSY_MASK 0x18
58 static void vt8500_pmc_wait_busy(void)
60 while (readl(pmc_base
) & VT8500_PMC_BUSY_MASK
)
64 static int vt8500_dclk_enable(struct clk_hw
*hw
)
66 struct clk_device
*cdev
= to_clk_device(hw
);
68 unsigned long flags
= 0;
70 spin_lock_irqsave(cdev
->lock
, flags
);
72 en_val
= readl(cdev
->en_reg
);
73 en_val
|= BIT(cdev
->en_bit
);
74 writel(en_val
, cdev
->en_reg
);
76 spin_unlock_irqrestore(cdev
->lock
, flags
);
80 static void vt8500_dclk_disable(struct clk_hw
*hw
)
82 struct clk_device
*cdev
= to_clk_device(hw
);
84 unsigned long flags
= 0;
86 spin_lock_irqsave(cdev
->lock
, flags
);
88 en_val
= readl(cdev
->en_reg
);
89 en_val
&= ~BIT(cdev
->en_bit
);
90 writel(en_val
, cdev
->en_reg
);
92 spin_unlock_irqrestore(cdev
->lock
, flags
);
95 static int vt8500_dclk_is_enabled(struct clk_hw
*hw
)
97 struct clk_device
*cdev
= to_clk_device(hw
);
98 u32 en_val
= (readl(cdev
->en_reg
) & BIT(cdev
->en_bit
));
100 return en_val
? 1 : 0;
103 static unsigned long vt8500_dclk_recalc_rate(struct clk_hw
*hw
,
104 unsigned long parent_rate
)
106 struct clk_device
*cdev
= to_clk_device(hw
);
107 u32 div
= readl(cdev
->div_reg
) & cdev
->div_mask
;
109 /* Special case for SDMMC devices */
110 if ((cdev
->div_mask
== 0x3F) && (div
& BIT(5)))
111 div
= 64 * (div
& 0x1f);
113 /* div == 0 is actually the highest divisor */
115 div
= (cdev
->div_mask
+ 1);
117 return parent_rate
/ div
;
120 static long vt8500_dclk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
121 unsigned long *prate
)
123 u32 divisor
= *prate
/ rate
;
125 return *prate
/ divisor
;
128 static int vt8500_dclk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
129 unsigned long parent_rate
)
131 struct clk_device
*cdev
= to_clk_device(hw
);
132 u32 divisor
= parent_rate
/ rate
;
133 unsigned long flags
= 0;
135 if (divisor
== cdev
->div_mask
+ 1)
138 if (divisor
> cdev
->div_mask
) {
139 pr_err("%s: invalid divisor for clock\n", __func__
);
143 spin_lock_irqsave(cdev
->lock
, flags
);
145 vt8500_pmc_wait_busy();
146 writel(divisor
, cdev
->div_reg
);
147 vt8500_pmc_wait_busy();
149 spin_lock_irqsave(cdev
->lock
, flags
);
155 static const struct clk_ops vt8500_gated_clk_ops
= {
156 .enable
= vt8500_dclk_enable
,
157 .disable
= vt8500_dclk_disable
,
158 .is_enabled
= vt8500_dclk_is_enabled
,
161 static const struct clk_ops vt8500_divisor_clk_ops
= {
162 .round_rate
= vt8500_dclk_round_rate
,
163 .set_rate
= vt8500_dclk_set_rate
,
164 .recalc_rate
= vt8500_dclk_recalc_rate
,
167 static const struct clk_ops vt8500_gated_divisor_clk_ops
= {
168 .enable
= vt8500_dclk_enable
,
169 .disable
= vt8500_dclk_disable
,
170 .is_enabled
= vt8500_dclk_is_enabled
,
171 .round_rate
= vt8500_dclk_round_rate
,
172 .set_rate
= vt8500_dclk_set_rate
,
173 .recalc_rate
= vt8500_dclk_recalc_rate
,
176 #define CLK_INIT_GATED BIT(0)
177 #define CLK_INIT_DIVISOR BIT(1)
178 #define CLK_INIT_GATED_DIVISOR (CLK_INIT_DIVISOR | CLK_INIT_GATED)
180 static __init
void vtwm_device_clk_init(struct device_node
*node
)
184 struct clk_device
*dev_clk
;
185 const char *clk_name
= node
->name
;
186 const char *parent_name
;
187 struct clk_init_data init
;
189 int clk_init_flags
= 0;
191 dev_clk
= kzalloc(sizeof(*dev_clk
), GFP_KERNEL
);
192 if (WARN_ON(!dev_clk
))
195 dev_clk
->lock
= &_lock
;
197 rc
= of_property_read_u32(node
, "enable-reg", &en_reg
);
199 dev_clk
->en_reg
= pmc_base
+ en_reg
;
200 rc
= of_property_read_u32(node
, "enable-bit", &dev_clk
->en_bit
);
202 pr_err("%s: enable-bit property required for gated clock\n",
206 clk_init_flags
|= CLK_INIT_GATED
;
209 rc
= of_property_read_u32(node
, "divisor-reg", &div_reg
);
211 dev_clk
->div_reg
= pmc_base
+ div_reg
;
213 * use 0x1f as the default mask since it covers
214 * almost all the clocks and reduces dts properties
216 dev_clk
->div_mask
= 0x1f;
218 of_property_read_u32(node
, "divisor-mask", &dev_clk
->div_mask
);
219 clk_init_flags
|= CLK_INIT_DIVISOR
;
222 of_property_read_string(node
, "clock-output-names", &clk_name
);
224 switch (clk_init_flags
) {
226 init
.ops
= &vt8500_gated_clk_ops
;
228 case CLK_INIT_DIVISOR
:
229 init
.ops
= &vt8500_divisor_clk_ops
;
231 case CLK_INIT_GATED_DIVISOR
:
232 init
.ops
= &vt8500_gated_divisor_clk_ops
;
235 pr_err("%s: Invalid clock description in device tree\n",
241 init
.name
= clk_name
;
243 parent_name
= of_clk_get_parent_name(node
, 0);
244 init
.parent_names
= &parent_name
;
245 init
.num_parents
= 1;
247 dev_clk
->hw
.init
= &init
;
249 clk
= clk_register(NULL
, &dev_clk
->hw
);
250 if (WARN_ON(IS_ERR(clk
))) {
254 rc
= of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
255 clk_register_clkdev(clk
, clk_name
, NULL
);
259 /* PLL clock related functions */
261 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
263 /* Helper macros for PLL_VT8500 */
264 #define VT8500_PLL_MUL(x) ((x & 0x1F) << 1)
265 #define VT8500_PLL_DIV(x) ((x & 0x100) ? 1 : 2)
267 #define VT8500_BITS_TO_FREQ(r, m, d) \
270 #define VT8500_BITS_TO_VAL(m, d) \
271 ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
273 /* Helper macros for PLL_WM8650 */
274 #define WM8650_PLL_MUL(x) (x & 0x3FF)
275 #define WM8650_PLL_DIV(x) (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
277 #define WM8650_BITS_TO_FREQ(r, m, d1, d2) \
278 (r * m / (d1 * (1 << d2)))
280 #define WM8650_BITS_TO_VAL(m, d1, d2) \
281 ((d2 << 13) | (d1 << 10) | (m & 0x3FF))
284 static void vt8500_find_pll_bits(unsigned long rate
, unsigned long parent_rate
,
285 u32
*multiplier
, u32
*prediv
)
290 if ((rate
< parent_rate
* 4) || (rate
> parent_rate
* 62)) {
291 pr_err("%s: requested rate out of range\n", __func__
);
296 if (rate
<= parent_rate
* 31)
297 /* use the prediv to double the resolution */
302 *multiplier
= rate
/ (parent_rate
/ *prediv
);
303 tclk
= (parent_rate
/ *prediv
) * *multiplier
;
306 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__
,
310 static void wm8650_find_pll_bits(unsigned long rate
, unsigned long parent_rate
,
311 u32
*multiplier
, u32
*divisor1
, u32
*divisor2
)
314 u32 best_mul
, best_div1
, best_div2
;
315 unsigned long tclk
, rate_err
, best_err
;
317 best_err
= (unsigned long)-1;
319 /* Find the closest match (lower or equal to requested) */
320 for (div1
= 5; div1
>= 3; div1
--)
321 for (div2
= 3; div2
>= 0; div2
--)
322 for (mul
= 3; mul
<= 1023; mul
++) {
323 tclk
= parent_rate
* mul
/ (div1
* (1 << div2
));
326 /* error will always be +ve */
327 rate_err
= rate
- tclk
;
335 if (rate_err
< best_err
) {
343 /* if we got here, it wasn't an exact match */
344 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__
, rate
,
351 static int vtwm_pll_set_rate(struct clk_hw
*hw
, unsigned long rate
,
352 unsigned long parent_rate
)
354 struct clk_pll
*pll
= to_clk_pll(hw
);
357 unsigned long flags
= 0;
362 case PLL_TYPE_VT8500
:
363 vt8500_find_pll_bits(rate
, parent_rate
, &mul
, &div1
);
364 pll_val
= VT8500_BITS_TO_VAL(mul
, div1
);
366 case PLL_TYPE_WM8650
:
367 wm8650_find_pll_bits(rate
, parent_rate
, &mul
, &div1
, &div2
);
368 pll_val
= WM8650_BITS_TO_VAL(mul
, div1
, div2
);
371 pr_err("%s: invalid pll type\n", __func__
);
375 spin_lock_irqsave(pll
->lock
, flags
);
377 vt8500_pmc_wait_busy();
378 writel(pll_val
, pll
->reg
);
379 vt8500_pmc_wait_busy();
381 spin_unlock_irqrestore(pll
->lock
, flags
);
386 static long vtwm_pll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
387 unsigned long *prate
)
389 struct clk_pll
*pll
= to_clk_pll(hw
);
394 case PLL_TYPE_VT8500
:
395 vt8500_find_pll_bits(rate
, *prate
, &mul
, &div1
);
396 round_rate
= VT8500_BITS_TO_FREQ(*prate
, mul
, div1
);
398 case PLL_TYPE_WM8650
:
399 wm8650_find_pll_bits(rate
, *prate
, &mul
, &div1
, &div2
);
400 round_rate
= WM8650_BITS_TO_FREQ(*prate
, mul
, div1
, div2
);
409 static unsigned long vtwm_pll_recalc_rate(struct clk_hw
*hw
,
410 unsigned long parent_rate
)
412 struct clk_pll
*pll
= to_clk_pll(hw
);
413 u32 pll_val
= readl(pll
->reg
);
414 unsigned long pll_freq
;
417 case PLL_TYPE_VT8500
:
418 pll_freq
= parent_rate
* VT8500_PLL_MUL(pll_val
);
419 pll_freq
/= VT8500_PLL_DIV(pll_val
);
421 case PLL_TYPE_WM8650
:
422 pll_freq
= parent_rate
* WM8650_PLL_MUL(pll_val
);
423 pll_freq
/= WM8650_PLL_DIV(pll_val
);
432 const struct clk_ops vtwm_pll_ops
= {
433 .round_rate
= vtwm_pll_round_rate
,
434 .set_rate
= vtwm_pll_set_rate
,
435 .recalc_rate
= vtwm_pll_recalc_rate
,
438 static __init
void vtwm_pll_clk_init(struct device_node
*node
, int pll_type
)
442 struct clk_pll
*pll_clk
;
443 const char *clk_name
= node
->name
;
444 const char *parent_name
;
445 struct clk_init_data init
;
448 rc
= of_property_read_u32(node
, "reg", ®
);
452 pll_clk
= kzalloc(sizeof(*pll_clk
), GFP_KERNEL
);
453 if (WARN_ON(!pll_clk
))
456 pll_clk
->reg
= pmc_base
+ reg
;
457 pll_clk
->lock
= &_lock
;
458 pll_clk
->type
= pll_type
;
460 of_property_read_string(node
, "clock-output-names", &clk_name
);
462 init
.name
= clk_name
;
463 init
.ops
= &vtwm_pll_ops
;
465 parent_name
= of_clk_get_parent_name(node
, 0);
466 init
.parent_names
= &parent_name
;
467 init
.num_parents
= 1;
469 pll_clk
->hw
.init
= &init
;
471 clk
= clk_register(NULL
, &pll_clk
->hw
);
472 if (WARN_ON(IS_ERR(clk
))) {
476 rc
= of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
477 clk_register_clkdev(clk
, clk_name
, NULL
);
481 /* Wrappers for initialization functions */
483 static void __init
vt8500_pll_init(struct device_node
*node
)
485 vtwm_pll_clk_init(node
, PLL_TYPE_VT8500
);
488 static void __init
wm8650_pll_init(struct device_node
*node
)
490 vtwm_pll_clk_init(node
, PLL_TYPE_WM8650
);
493 static const __initconst
struct of_device_id clk_match
[] = {
494 { .compatible
= "fixed-clock", .data
= of_fixed_clk_setup
, },
495 { .compatible
= "via,vt8500-pll-clock", .data
= vt8500_pll_init
, },
496 { .compatible
= "wm,wm8650-pll-clock", .data
= wm8650_pll_init
, },
497 { .compatible
= "via,vt8500-device-clock",
498 .data
= vtwm_device_clk_init
, },
502 void __init
vtwm_clk_init(void __iomem
*base
)
509 of_clk_init(clk_match
);