drivers/clk/h8300/clk-div.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * H8/300 divide clock driver
   4  *
   5  * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
   6  */
   7
   8 #include <linux/clk-provider.h>
   9 #include <linux/err.h>
  10 #include <linux/of.h>
  11 #include <linux/of_address.h>
  12
  13 static DEFINE_SPINLOCK(clklock);
  14
  15 static void __init h8300_div_clk_setup(struct device_node *node)
  16 {
  17         unsigned int num_parents;
  18         struct clk_hw *hw;
  19         const char *clk_name = node->name;
  20         const char *parent_name;
  21         void __iomem *divcr = NULL;
  22         int width;
  23         int offset;
  24
  25         num_parents = of_clk_get_parent_count(node);
  26         if (!num_parents) {
  27                 pr_err("%s: no parent found", clk_name);
  28                 return;
  29         }
  30
  31         divcr = of_iomap(node, 0);
  32         if (divcr == NULL) {
  33                 pr_err("%s: failed to map divide register", clk_name);
  34                 goto error;
  35         }
  36         offset = (unsigned long)divcr & 3;
  37         offset = (3 - offset) * 8;
  38         divcr = (void __iomem *)((unsigned long)divcr & ~3);
  39
  40         parent_name = of_clk_get_parent_name(node, 0);
  41         of_property_read_u32(node, "renesas,width", &width);
  42         hw = clk_hw_register_divider(NULL, clk_name, parent_name,
  43                                    CLK_SET_RATE_GATE, divcr, offset, width,
  44                                    CLK_DIVIDER_POWER_OF_TWO, &clklock);
  45         if (!IS_ERR(hw)) {
  46                 of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
  47                 return;
  48         }
  49         pr_err("%s: failed to register %s div clock (%ld)\n",
  50                __func__, clk_name, PTR_ERR(hw));
  51 error:
  52         if (divcr)
  53                 iounmap(divcr);
  54 }
  55
  56 CLK_OF_DECLARE(h8300_div_clk, "renesas,h8300-div-clock", h8300_div_clk_setup);