1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Ingenic SoC CGU driver
5 * Copyright (c) 2013-2015 Imagination Technologies
6 * Author: Paul Burton <paul.burton@mips.com>
9 #ifndef __DRIVERS_CLK_INGENIC_CGU_H__
10 #define __DRIVERS_CLK_INGENIC_CGU_H__
12 #include <linux/bitops.h>
14 #include <linux/spinlock.h>
17 * struct ingenic_cgu_pll_info - information about a PLL
18 * @reg: the offset of the PLL's control register within the CGU
19 * @m_shift: the number of bits to shift the multiplier value by (ie. the
20 * index of the lowest bit of the multiplier value in the PLL's
22 * @m_bits: the size of the multiplier field in bits
23 * @m_offset: the multiplier value which encodes to 0 in the PLL's control
25 * @n_shift: the number of bits to shift the divider value by (ie. the
26 * index of the lowest bit of the divider value in the PLL's
28 * @n_bits: the size of the divider field in bits
29 * @n_offset: the divider value which encodes to 0 in the PLL's control
31 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
32 * the index of the lowest bit of the post-VCO divider value in
33 * the PLL's control register)
34 * @od_bits: the size of the post-VCO divider field in bits
35 * @od_max: the maximum post-VCO divider value
36 * @od_encoding: a pointer to an array mapping post-VCO divider values to
37 * their encoded values in the PLL control register, or -1 for
39 * @bypass_bit: the index of the bypass bit in the PLL control register
40 * @enable_bit: the index of the enable bit in the PLL control register
41 * @stable_bit: the index of the stable bit in the PLL control register
42 * @no_bypass_bit: if set, the PLL has no bypass functionality
44 struct ingenic_cgu_pll_info
{
46 const s8
*od_encoding
;
47 u8 m_shift
, m_bits
, m_offset
;
48 u8 n_shift
, n_bits
, n_offset
;
49 u8 od_shift
, od_bits
, od_max
;
57 * struct ingenic_cgu_mux_info - information about a clock mux
58 * @reg: offset of the mux control register within the CGU
59 * @shift: number of bits to shift the mux value by (ie. the index of
60 * the lowest bit of the mux value within its control register)
61 * @bits: the size of the mux value in bits
63 struct ingenic_cgu_mux_info
{
70 * struct ingenic_cgu_div_info - information about a divider
71 * @reg: offset of the divider control register within the CGU
72 * @shift: number of bits to left shift the divide value by (ie. the index of
73 * the lowest bit of the divide value within its control register)
74 * @div: number to divide the divider value by (i.e. if the
75 * effective divider value is the value written to the register
76 * multiplied by some constant)
77 * @bits: the size of the divide value in bits
78 * @ce_bit: the index of the change enable bit within reg, or -1 if there
80 * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one
81 * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one
83 struct ingenic_cgu_div_info
{
94 * struct ingenic_cgu_fixdiv_info - information about a fixed divider
95 * @div: the divider applied to the parent clock
97 struct ingenic_cgu_fixdiv_info
{
102 * struct ingenic_cgu_gate_info - information about a clock gate
103 * @reg: offset of the gate control register within the CGU
104 * @bit: offset of the bit in the register that controls the gate
105 * @clear_to_gate: if set, the clock is gated when the bit is cleared
106 * @delay_us: delay in microseconds after which the clock is considered stable
108 struct ingenic_cgu_gate_info
{
116 * struct ingenic_cgu_custom_info - information about a custom (SoC) clock
117 * @clk_ops: custom clock operation callbacks
119 struct ingenic_cgu_custom_info
{
120 const struct clk_ops
*clk_ops
;
124 * struct ingenic_cgu_clk_info - information about a clock
125 * @name: name of the clock
126 * @type: a bitmask formed from CGU_CLK_* values
127 * @parents: an array of the indices of potential parents of this clock
128 * within the clock_info array of the CGU, or -1 in entries
129 * which correspond to no valid parent
130 * @pll: information valid if type includes CGU_CLK_PLL
131 * @gate: information valid if type includes CGU_CLK_GATE
132 * @mux: information valid if type includes CGU_CLK_MUX
133 * @div: information valid if type includes CGU_CLK_DIV
134 * @fixdiv: information valid if type includes CGU_CLK_FIXDIV
135 * @custom: information valid if type includes CGU_CLK_CUSTOM
137 struct ingenic_cgu_clk_info
{
142 CGU_CLK_EXT
= BIT(0),
143 CGU_CLK_PLL
= BIT(1),
144 CGU_CLK_GATE
= BIT(2),
145 CGU_CLK_MUX
= BIT(3),
146 CGU_CLK_MUX_GLITCHFREE
= BIT(4),
147 CGU_CLK_DIV
= BIT(5),
148 CGU_CLK_FIXDIV
= BIT(6),
149 CGU_CLK_CUSTOM
= BIT(7),
155 struct ingenic_cgu_pll_info pll
;
158 struct ingenic_cgu_gate_info gate
;
159 struct ingenic_cgu_mux_info mux
;
160 struct ingenic_cgu_div_info div
;
161 struct ingenic_cgu_fixdiv_info fixdiv
;
164 struct ingenic_cgu_custom_info custom
;
169 * struct ingenic_cgu - data about the CGU
170 * @np: the device tree node that caused the CGU to be probed
171 * @base: the ioremap'ed base address of the CGU registers
172 * @clock_info: an array containing information about implemented clocks
173 * @clocks: used to provide clocks to DT, allows lookup of struct clk*
174 * @lock: lock to be held whilst manipulating CGU registers
177 struct device_node
*np
;
180 const struct ingenic_cgu_clk_info
*clock_info
;
181 struct clk_onecell_data clocks
;
187 * struct ingenic_clk - private data for a clock
188 * @hw: see Documentation/driver-api/clk.rst
189 * @cgu: a pointer to the CGU data
190 * @idx: the index of this clock in cgu->clock_info
194 struct ingenic_cgu
*cgu
;
198 #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw)
201 * ingenic_cgu_new() - create a new CGU instance
202 * @clock_info: an array of clock information structures describing the clocks
203 * which are implemented by the CGU
204 * @num_clocks: the number of entries in clock_info
205 * @np: the device tree node which causes this CGU to be probed
207 * Return: a pointer to the CGU instance if initialisation is successful,
211 ingenic_cgu_new(const struct ingenic_cgu_clk_info
*clock_info
,
212 unsigned num_clocks
, struct device_node
*np
);
215 * ingenic_cgu_register_clocks() - Registers the clocks
216 * @cgu: pointer to cgu data
218 * Register the clocks described by the CGU with the common clock framework.
220 * Return: 0 on success or -errno if unsuccesful.
222 int ingenic_cgu_register_clocks(struct ingenic_cgu
*cgu
);
224 #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */