2 * PLL clock driver for Keystone devices
4 * Copyright (C) 2013 Texas Instruments Inc.
5 * Murali Karicheri <m-karicheri2@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 #include <linux/clk-provider.h>
14 #include <linux/err.h>
16 #include <linux/slab.h>
17 #include <linux/of_address.h>
19 #include <linux/module.h>
21 #define PLLM_LOW_MASK 0x3f
22 #define PLLM_HIGH_MASK 0x7ffc0
23 #define MAIN_PLLM_HIGH_MASK 0x7f000
24 #define PLLM_HIGH_SHIFT 6
25 #define PLLD_MASK 0x3f
26 #define CLKOD_MASK 0x780000
27 #define CLKOD_SHIFT 19
30 * struct clk_pll_data - pll data structure
31 * @has_pllctrl: If set to non zero, lower 6 bits of multiplier is in pllm
32 * register of pll controller, else it is in the pll_ctrl0((bit 11-6)
33 * @phy_pllm: Physical address of PLLM in pll controller. Used when
34 * has_pllctrl is non zero.
35 * @phy_pll_ctl0: Physical address of PLL ctrl0. This could be that of
36 * Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL
37 * or PA PLL available on keystone2. These PLLs are controlled by
38 * this register. Main PLL is controlled by a PLL controller.
39 * @pllm: PLL register map address for multiplier bits
40 * @pllod: PLL register map address for post divider bits
41 * @pll_ctl0: PLL controller map address
42 * @pllm_lower_mask: multiplier lower mask
43 * @pllm_upper_mask: multiplier upper mask
44 * @pllm_upper_shift: multiplier upper shift
45 * @plld_mask: divider mask
46 * @clkod_mask: output divider mask
47 * @clkod_shift: output divider shift
48 * @plld_mask: divider mask
49 * @postdiv: Fixed post divider
57 void __iomem
*pll_ctl0
;
68 * struct clk_pll - Main pll clock
69 * @hw: clk_hw for the pll
70 * @pll_data: PLL driver specific data
74 struct clk_pll_data
*pll_data
;
77 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
79 static unsigned long clk_pllclk_recalc(struct clk_hw
*hw
,
80 unsigned long parent_rate
)
82 struct clk_pll
*pll
= to_clk_pll(hw
);
83 struct clk_pll_data
*pll_data
= pll
->pll_data
;
84 unsigned long rate
= parent_rate
;
85 u32 mult
= 0, prediv
, postdiv
, val
;
88 * get bits 0-5 of multiplier from pllctrl PLLM register
89 * if has_pllctrl is non zero
91 if (pll_data
->has_pllctrl
) {
92 val
= readl(pll_data
->pllm
);
93 mult
= (val
& pll_data
->pllm_lower_mask
);
96 /* bit6-12 of PLLM is in Main PLL control register */
97 val
= readl(pll_data
->pll_ctl0
);
98 mult
|= ((val
& pll_data
->pllm_upper_mask
)
99 >> pll_data
->pllm_upper_shift
);
100 prediv
= (val
& pll_data
->plld_mask
);
102 if (!pll_data
->has_pllctrl
)
103 /* read post divider from od bits*/
104 postdiv
= ((val
& pll_data
->clkod_mask
) >>
105 pll_data
->clkod_shift
) + 1;
106 else if (pll_data
->pllod
) {
107 postdiv
= readl(pll_data
->pllod
);
108 postdiv
= ((postdiv
& pll_data
->clkod_mask
) >>
109 pll_data
->clkod_shift
) + 1;
111 postdiv
= pll_data
->postdiv
;
113 rate
/= (prediv
+ 1);
114 rate
= (rate
* (mult
+ 1));
120 static const struct clk_ops clk_pll_ops
= {
121 .recalc_rate
= clk_pllclk_recalc
,
124 static struct clk
*clk_register_pll(struct device
*dev
,
126 const char *parent_name
,
127 struct clk_pll_data
*pll_data
)
129 struct clk_init_data init
;
133 pll
= kzalloc(sizeof(*pll
), GFP_KERNEL
);
135 return ERR_PTR(-ENOMEM
);
138 init
.ops
= &clk_pll_ops
;
140 init
.parent_names
= (parent_name
? &parent_name
: NULL
);
141 init
.num_parents
= (parent_name
? 1 : 0);
143 pll
->pll_data
= pll_data
;
144 pll
->hw
.init
= &init
;
146 clk
= clk_register(NULL
, &pll
->hw
);
157 * _of_clk_init - PLL initialisation via DT
158 * @node: device tree node for this clock
159 * @pllctrl: If true, lower 6 bits of multiplier is in pllm register of
160 * pll controller, else it is in the control regsiter0(bit 11-6)
162 static void __init
_of_pll_clk_init(struct device_node
*node
, bool pllctrl
)
164 struct clk_pll_data
*pll_data
;
165 const char *parent_name
;
169 pll_data
= kzalloc(sizeof(*pll_data
), GFP_KERNEL
);
171 pr_err("%s: Out of memory\n", __func__
);
175 parent_name
= of_clk_get_parent_name(node
, 0);
176 if (of_property_read_u32(node
, "fixed-postdiv", &pll_data
->postdiv
)) {
177 /* assume the PLL has output divider register bits */
178 pll_data
->clkod_mask
= CLKOD_MASK
;
179 pll_data
->clkod_shift
= CLKOD_SHIFT
;
182 * Check if there is an post-divider register. If not
183 * assume od bits are part of control register.
185 i
= of_property_match_string(node
, "reg-names",
187 pll_data
->pllod
= of_iomap(node
, i
);
190 i
= of_property_match_string(node
, "reg-names", "control");
191 pll_data
->pll_ctl0
= of_iomap(node
, i
);
192 if (!pll_data
->pll_ctl0
) {
193 pr_err("%s: ioremap failed\n", __func__
);
194 iounmap(pll_data
->pllod
);
198 pll_data
->pllm_lower_mask
= PLLM_LOW_MASK
;
199 pll_data
->pllm_upper_shift
= PLLM_HIGH_SHIFT
;
200 pll_data
->plld_mask
= PLLD_MASK
;
201 pll_data
->has_pllctrl
= pllctrl
;
202 if (!pll_data
->has_pllctrl
) {
203 pll_data
->pllm_upper_mask
= PLLM_HIGH_MASK
;
205 pll_data
->pllm_upper_mask
= MAIN_PLLM_HIGH_MASK
;
206 i
= of_property_match_string(node
, "reg-names", "multiplier");
207 pll_data
->pllm
= of_iomap(node
, i
);
208 if (!pll_data
->pllm
) {
209 iounmap(pll_data
->pll_ctl0
);
210 iounmap(pll_data
->pllod
);
215 clk
= clk_register_pll(NULL
, node
->name
, parent_name
, pll_data
);
217 of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
222 pr_err("%s: error initializing pll %s\n", __func__
, node
->name
);
227 * of_keystone_pll_clk_init - PLL initialisation DT wrapper
228 * @node: device tree node for this clock
230 static void __init
of_keystone_pll_clk_init(struct device_node
*node
)
232 _of_pll_clk_init(node
, false);
234 CLK_OF_DECLARE(keystone_pll_clock
, "ti,keystone,pll-clock",
235 of_keystone_pll_clk_init
);
238 * of_keystone_pll_main_clk_init - Main PLL initialisation DT wrapper
239 * @node: device tree node for this clock
241 static void __init
of_keystone_main_pll_clk_init(struct device_node
*node
)
243 _of_pll_clk_init(node
, true);
245 CLK_OF_DECLARE(keystone_main_pll_clock
, "ti,keystone,main-pll-clock",
246 of_keystone_main_pll_clk_init
);
249 * of_pll_div_clk_init - PLL divider setup function
250 * @node: device tree node for this clock
252 static void __init
of_pll_div_clk_init(struct device_node
*node
)
254 const char *parent_name
;
258 const char *clk_name
= node
->name
;
260 of_property_read_string(node
, "clock-output-names", &clk_name
);
261 reg
= of_iomap(node
, 0);
263 pr_err("%s: ioremap failed\n", __func__
);
267 parent_name
= of_clk_get_parent_name(node
, 0);
269 pr_err("%s: missing parent clock\n", __func__
);
273 if (of_property_read_u32(node
, "bit-shift", &shift
)) {
274 pr_err("%s: missing 'shift' property\n", __func__
);
278 if (of_property_read_u32(node
, "bit-mask", &mask
)) {
279 pr_err("%s: missing 'bit-mask' property\n", __func__
);
283 clk
= clk_register_divider(NULL
, clk_name
, parent_name
, 0, reg
, shift
,
286 of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
288 pr_err("%s: error registering divider %s\n", __func__
, clk_name
);
290 CLK_OF_DECLARE(pll_divider_clock
, "ti,keystone,pll-divider-clock", of_pll_div_clk_init
);
293 * of_pll_mux_clk_init - PLL mux setup function
294 * @node: device tree node for this clock
296 static void __init
of_pll_mux_clk_init(struct device_node
*node
)
301 const char *parents
[2];
302 const char *clk_name
= node
->name
;
304 of_property_read_string(node
, "clock-output-names", &clk_name
);
305 reg
= of_iomap(node
, 0);
307 pr_err("%s: ioremap failed\n", __func__
);
311 of_clk_parent_fill(node
, parents
, 2);
312 if (!parents
[0] || !parents
[1]) {
313 pr_err("%s: missing parent clocks\n", __func__
);
317 if (of_property_read_u32(node
, "bit-shift", &shift
)) {
318 pr_err("%s: missing 'shift' property\n", __func__
);
322 if (of_property_read_u32(node
, "bit-mask", &mask
)) {
323 pr_err("%s: missing 'bit-mask' property\n", __func__
);
327 clk
= clk_register_mux(NULL
, clk_name
, (const char **)&parents
,
328 ARRAY_SIZE(parents
) , 0, reg
, shift
, mask
,
331 of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
333 pr_err("%s: error registering mux %s\n", __func__
, clk_name
);
335 CLK_OF_DECLARE(pll_mux_clock
, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init
);