1 // SPDX-License-Identifier: GPL-2.0-only
3 // Copyright (c) 2021 MediaTek Inc.
4 // Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
7 #include <linux/delay.h>
8 #include <linux/mfd/syscon.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/slab.h>
19 #include <dt-bindings/clock/mt8192-clk.h>
21 static DEFINE_SPINLOCK(mt8192_clk_lock
);
23 static const struct mtk_fixed_clk top_fixed_clks
[] = {
24 FIXED_CLK(CLK_TOP_ULPOSC
, "ulposc", NULL
, 260000000),
27 static const struct mtk_fixed_factor top_early_divs
[] = {
28 FACTOR(CLK_TOP_CSW_F26M_D2
, "csw_f26m_d2", "clk26m", 1, 2),
31 static const struct mtk_fixed_factor top_divs
[] = {
32 FACTOR(CLK_TOP_MAINPLL_D3
, "mainpll_d3", "mainpll", 1, 3),
33 FACTOR(CLK_TOP_MAINPLL_D4
, "mainpll_d4", "mainpll", 1, 4),
34 FACTOR(CLK_TOP_MAINPLL_D4_D2
, "mainpll_d4_d2", "mainpll_d4", 1, 2),
35 FACTOR(CLK_TOP_MAINPLL_D4_D4
, "mainpll_d4_d4", "mainpll_d4", 1, 4),
36 FACTOR(CLK_TOP_MAINPLL_D4_D8
, "mainpll_d4_d8", "mainpll_d4", 1, 8),
37 FACTOR(CLK_TOP_MAINPLL_D4_D16
, "mainpll_d4_d16", "mainpll_d4", 1, 16),
38 FACTOR(CLK_TOP_MAINPLL_D5
, "mainpll_d5", "mainpll", 1, 5),
39 FACTOR(CLK_TOP_MAINPLL_D5_D2
, "mainpll_d5_d2", "mainpll_d5", 1, 2),
40 FACTOR(CLK_TOP_MAINPLL_D5_D4
, "mainpll_d5_d4", "mainpll_d5", 1, 4),
41 FACTOR(CLK_TOP_MAINPLL_D5_D8
, "mainpll_d5_d8", "mainpll_d5", 1, 8),
42 FACTOR(CLK_TOP_MAINPLL_D6
, "mainpll_d6", "mainpll", 1, 6),
43 FACTOR(CLK_TOP_MAINPLL_D6_D2
, "mainpll_d6_d2", "mainpll_d6", 1, 2),
44 FACTOR(CLK_TOP_MAINPLL_D6_D4
, "mainpll_d6_d4", "mainpll_d6", 1, 4),
45 FACTOR(CLK_TOP_MAINPLL_D7
, "mainpll_d7", "mainpll", 1, 7),
46 FACTOR(CLK_TOP_MAINPLL_D7_D2
, "mainpll_d7_d2", "mainpll_d7", 1, 2),
47 FACTOR(CLK_TOP_MAINPLL_D7_D4
, "mainpll_d7_d4", "mainpll_d7", 1, 4),
48 FACTOR(CLK_TOP_MAINPLL_D7_D8
, "mainpll_d7_d8", "mainpll_d7", 1, 8),
49 FACTOR(CLK_TOP_UNIVPLL_D3
, "univpll_d3", "univpll", 1, 3),
50 FACTOR(CLK_TOP_UNIVPLL_D4
, "univpll_d4", "univpll", 1, 4),
51 FACTOR(CLK_TOP_UNIVPLL_D4_D2
, "univpll_d4_d2", "univpll_d4", 1, 2),
52 FACTOR(CLK_TOP_UNIVPLL_D4_D4
, "univpll_d4_d4", "univpll_d4", 1, 4),
53 FACTOR(CLK_TOP_UNIVPLL_D4_D8
, "univpll_d4_d8", "univpll_d4", 1, 8),
54 FACTOR(CLK_TOP_UNIVPLL_D5
, "univpll_d5", "univpll", 1, 5),
55 FACTOR(CLK_TOP_UNIVPLL_D5_D2
, "univpll_d5_d2", "univpll_d5", 1, 2),
56 FACTOR(CLK_TOP_UNIVPLL_D5_D4
, "univpll_d5_d4", "univpll_d5", 1, 4),
57 FACTOR(CLK_TOP_UNIVPLL_D5_D8
, "univpll_d5_d8", "univpll_d5", 1, 8),
58 FACTOR(CLK_TOP_UNIVPLL_D6
, "univpll_d6", "univpll", 1, 6),
59 FACTOR(CLK_TOP_UNIVPLL_D6_D2
, "univpll_d6_d2", "univpll_d6", 1, 2),
60 FACTOR(CLK_TOP_UNIVPLL_D6_D4
, "univpll_d6_d4", "univpll_d6", 1, 4),
61 FACTOR(CLK_TOP_UNIVPLL_D6_D8
, "univpll_d6_d8", "univpll_d6", 1, 8),
62 FACTOR(CLK_TOP_UNIVPLL_D6_D16
, "univpll_d6_d16", "univpll_d6", 1, 16),
63 FACTOR(CLK_TOP_UNIVPLL_D7
, "univpll_d7", "univpll", 1, 7),
64 FACTOR(CLK_TOP_APLL1
, "apll1_ck", "apll1", 1, 1),
65 FACTOR(CLK_TOP_APLL1_D2
, "apll1_d2", "apll1", 1, 2),
66 FACTOR(CLK_TOP_APLL1_D4
, "apll1_d4", "apll1", 1, 4),
67 FACTOR(CLK_TOP_APLL1_D8
, "apll1_d8", "apll1", 1, 8),
68 FACTOR(CLK_TOP_APLL2
, "apll2_ck", "apll2", 1, 1),
69 FACTOR(CLK_TOP_APLL2_D2
, "apll2_d2", "apll2", 1, 2),
70 FACTOR(CLK_TOP_APLL2_D4
, "apll2_d4", "apll2", 1, 4),
71 FACTOR(CLK_TOP_APLL2_D8
, "apll2_d8", "apll2", 1, 8),
72 FACTOR(CLK_TOP_MMPLL_D4
, "mmpll_d4", "mmpll", 1, 4),
73 FACTOR(CLK_TOP_MMPLL_D4_D2
, "mmpll_d4_d2", "mmpll_d4", 1, 2),
74 FACTOR(CLK_TOP_MMPLL_D5
, "mmpll_d5", "mmpll", 1, 5),
75 FACTOR(CLK_TOP_MMPLL_D5_D2
, "mmpll_d5_d2", "mmpll_d5", 1, 2),
76 FACTOR(CLK_TOP_MMPLL_D6
, "mmpll_d6", "mmpll", 1, 6),
77 FACTOR(CLK_TOP_MMPLL_D6_D2
, "mmpll_d6_d2", "mmpll_d6", 1, 2),
78 FACTOR(CLK_TOP_MMPLL_D7
, "mmpll_d7", "mmpll", 1, 7),
79 FACTOR(CLK_TOP_MMPLL_D9
, "mmpll_d9", "mmpll", 1, 9),
80 FACTOR(CLK_TOP_APUPLL
, "apupll_ck", "apupll", 1, 2),
81 FACTOR(CLK_TOP_NPUPLL
, "npupll_ck", "npupll", 1, 1),
82 FACTOR(CLK_TOP_TVDPLL
, "tvdpll_ck", "tvdpll", 1, 1),
83 FACTOR(CLK_TOP_TVDPLL_D2
, "tvdpll_d2", "tvdpll", 1, 2),
84 FACTOR(CLK_TOP_TVDPLL_D4
, "tvdpll_d4", "tvdpll", 1, 4),
85 FACTOR(CLK_TOP_TVDPLL_D8
, "tvdpll_d8", "tvdpll", 1, 8),
86 FACTOR(CLK_TOP_TVDPLL_D16
, "tvdpll_d16", "tvdpll", 1, 16),
87 FACTOR(CLK_TOP_MSDCPLL
, "msdcpll_ck", "msdcpll", 1, 1),
88 FACTOR(CLK_TOP_MSDCPLL_D2
, "msdcpll_d2", "msdcpll", 1, 2),
89 FACTOR(CLK_TOP_MSDCPLL_D4
, "msdcpll_d4", "msdcpll", 1, 4),
90 FACTOR(CLK_TOP_OSC_D2
, "osc_d2", "ulposc", 1, 2),
91 FACTOR(CLK_TOP_OSC_D4
, "osc_d4", "ulposc", 1, 4),
92 FACTOR(CLK_TOP_OSC_D8
, "osc_d8", "ulposc", 1, 8),
93 FACTOR(CLK_TOP_OSC_D10
, "osc_d10", "ulposc", 1, 10),
94 FACTOR(CLK_TOP_OSC_D16
, "osc_d16", "ulposc", 1, 16),
95 FACTOR(CLK_TOP_OSC_D20
, "osc_d20", "ulposc", 1, 20),
96 FACTOR(CLK_TOP_ADSPPLL
, "adsppll_ck", "adsppll", 1, 1),
97 FACTOR(CLK_TOP_UNIVPLL_192M
, "univpll_192m", "univpll", 1, 13),
98 FACTOR(CLK_TOP_UNIVPLL_192M_D2
, "univpll_192m_d2", "univpll_192m", 1, 2),
99 FACTOR(CLK_TOP_UNIVPLL_192M_D4
, "univpll_192m_d4", "univpll_192m", 1, 4),
100 FACTOR(CLK_TOP_UNIVPLL_192M_D8
, "univpll_192m_d8", "univpll_192m", 1, 8),
101 FACTOR(CLK_TOP_UNIVPLL_192M_D16
, "univpll_192m_d16", "univpll_192m", 1, 16),
102 FACTOR(CLK_TOP_UNIVPLL_192M_D32
, "univpll_192m_d32", "univpll_192m", 1, 32),
105 static const char * const axi_parents
[] = {
115 static const char * const spm_parents
[] = {
122 static const char * const scp_parents
[] = {
133 static const char * const bus_aximem_parents
[] = {
141 static const char * const disp_parents
[] = {
154 static const char * const mdp_parents
[] = {
168 static const char * const img1_parents
[] = {
183 static const char * const img2_parents
[] = {
198 static const char * const ipe_parents
[] = {
210 static const char * const dpe_parents
[] = {
221 static const char * const cam_parents
[] = {
234 static const char * const ccu_parents
[] = {
247 static const char * const dsp7_parents
[] = {
258 static const char * const mfg_ref_parents
[] = {
265 static const char * const mfg_pll_parents
[] = {
270 static const char * const camtg_parents
[] = {
281 static const char * const camtg2_parents
[] = {
292 static const char * const camtg3_parents
[] = {
303 static const char * const camtg4_parents
[] = {
314 static const char * const camtg5_parents
[] = {
325 static const char * const camtg6_parents
[] = {
336 static const char * const uart_parents
[] = {
341 static const char * const spi_parents
[] = {
348 static const char * const msdc50_0_h_parents
[] = {
354 static const char * const msdc50_0_parents
[] = {
363 static const char * const msdc30_1_parents
[] = {
371 static const char * const msdc30_2_parents
[] = {
379 static const char * const audio_parents
[] = {
386 static const char * const aud_intbus_parents
[] = {
392 static const char * const pwrap_ulposc_parents
[] = {
400 static const char * const atb_parents
[] = {
406 static const char * const dpi_parents
[] = {
414 static const char * const scam_parents
[] = {
419 static const char * const disp_pwm_parents
[] = {
427 static const char * const usb_top_parents
[] = {
434 static const char * const ssusb_xhci_parents
[] = {
441 static const char * const i2c_parents
[] = {
447 static const char * const seninf_parents
[] = {
458 static const char * const seninf1_parents
[] = {
469 static const char * const seninf2_parents
[] = {
480 static const char * const seninf3_parents
[] = {
491 static const char * const tl_parents
[] = {
497 static const char * const dxcc_parents
[] = {
504 static const char * const aud_engen1_parents
[] = {
511 static const char * const aud_engen2_parents
[] = {
518 static const char * const aes_ufsfde_parents
[] = {
528 static const char * const ufs_parents
[] = {
538 static const char * const aud_1_parents
[] = {
543 static const char * const aud_2_parents
[] = {
548 static const char * const adsp_parents
[] = {
559 static const char * const dpmaif_main_parents
[] = {
567 static const char * const venc_parents
[] = {
586 static const char * const vdec_parents
[] = {
605 static const char * const camtm_parents
[] = {
612 static const char * const pwm_parents
[] = {
617 static const char * const audio_h_parents
[] = {
624 static const char * const spmi_mst_parents
[] = {
634 static const char * const aes_msdcfde_parents
[] = {
643 static const char * const sflash_parents
[] = {
650 static const char * const apll_i2s0_m_parents
[] = {
655 static const char * const apll_i2s1_m_parents
[] = {
660 static const char * const apll_i2s2_m_parents
[] = {
665 static const char * const apll_i2s3_m_parents
[] = {
670 static const char * const apll_i2s4_m_parents
[] = {
675 static const char * const apll_i2s5_m_parents
[] = {
680 static const char * const apll_i2s6_m_parents
[] = {
685 static const char * const apll_i2s7_m_parents
[] = {
690 static const char * const apll_i2s8_m_parents
[] = {
695 static const char * const apll_i2s9_m_parents
[] = {
702 * axi_sel is the main bus clock of whole SOC.
703 * spm_sel is the clock of the always-on co-processor.
704 * bus_aximem_sel is clock of the bus that access emi.
706 static const struct mtk_mux top_mtk_muxes
[] = {
708 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL
, "axi_sel",
709 axi_parents
, 0x010, 0x014, 0x018, 0, 3, 7, 0x004, 0,
711 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL
, "spm_sel",
712 spm_parents
, 0x010, 0x014, 0x018, 8, 2, 15, 0x004, 1,
714 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL
, "scp_sel",
715 scp_parents
, 0x010, 0x014, 0x018, 16, 3, 23, 0x004, 2),
716 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_BUS_AXIMEM_SEL
, "bus_aximem_sel",
717 bus_aximem_parents
, 0x010, 0x014, 0x018, 24, 3, 31, 0x004, 3,
720 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_SEL
, "disp_sel",
721 disp_parents
, 0x020, 0x024, 0x028, 0, 4, 7, 0x004, 4),
722 MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP_SEL
, "mdp_sel",
723 mdp_parents
, 0x020, 0x024, 0x028, 8, 4, 15, 0x004, 5),
724 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL
, "img1_sel",
725 img1_parents
, 0x020, 0x024, 0x028, 16, 4, 23, 0x004, 6),
726 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG2_SEL
, "img2_sel",
727 img2_parents
, 0x020, 0x024, 0x028, 24, 4, 31, 0x004, 7),
729 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL
, "ipe_sel",
730 ipe_parents
, 0x030, 0x034, 0x038, 0, 4, 7, 0x004, 8),
731 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE_SEL
, "dpe_sel",
732 dpe_parents
, 0x030, 0x034, 0x038, 8, 3, 15, 0x004, 9),
733 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL
, "cam_sel",
734 cam_parents
, 0x030, 0x034, 0x038, 16, 4, 23, 0x004, 10),
735 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU_SEL
, "ccu_sel",
736 ccu_parents
, 0x030, 0x034, 0x038, 24, 4, 31, 0x004, 11),
738 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP7_SEL
, "dsp7_sel",
739 dsp7_parents
, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16),
740 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL
, "mfg_ref_sel",
741 mfg_ref_parents
, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18),
742 MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL
, "mfg_pll_sel",
743 mfg_pll_parents
, 0x050, 0x054, 0x058, 18, 1, -1, -1),
744 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL
, "camtg_sel",
745 camtg_parents
, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19),
747 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL
, "camtg2_sel",
748 camtg2_parents
, 0x060, 0x064, 0x068, 0, 3, 7, 0x004, 20),
749 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL
, "camtg3_sel",
750 camtg3_parents
, 0x060, 0x064, 0x068, 8, 3, 15, 0x004, 21),
751 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4_SEL
, "camtg4_sel",
752 camtg4_parents
, 0x060, 0x064, 0x068, 16, 3, 23, 0x004, 22),
753 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5_SEL
, "camtg5_sel",
754 camtg5_parents
, 0x060, 0x064, 0x068, 24, 3, 31, 0x004, 23),
756 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6_SEL
, "camtg6_sel",
757 camtg6_parents
, 0x070, 0x074, 0x078, 0, 3, 7, 0x004, 24),
758 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL
, "uart_sel",
759 uart_parents
, 0x070, 0x074, 0x078, 8, 1, 15, 0x004, 25),
760 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL
, "spi_sel",
761 spi_parents
, 0x070, 0x074, 0x078, 16, 2, 23, 0x004, 26),
762 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_H_SEL
, "msdc50_0_h_sel",
763 msdc50_0_h_parents
, 0x070, 0x074, 0x078, 24, 2, 31, 0x004, 27),
765 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL
, "msdc50_0_sel",
766 msdc50_0_parents
, 0x080, 0x084, 0x088, 0, 3, 7, 0x004, 28),
767 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL
, "msdc30_1_sel",
768 msdc30_1_parents
, 0x080, 0x084, 0x088, 8, 3, 15, 0x004, 29),
769 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL
, "msdc30_2_sel",
770 msdc30_2_parents
, 0x080, 0x084, 0x088, 16, 3, 23, 0x004, 30),
771 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL
, "audio_sel",
772 audio_parents
, 0x080, 0x084, 0x088, 24, 2, 31, 0x008, 0),
774 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL
, "aud_intbus_sel",
775 aud_intbus_parents
, 0x090, 0x094, 0x098, 0, 2, 7, 0x008, 1),
776 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC_SEL
, "pwrap_ulposc_sel",
777 pwrap_ulposc_parents
, 0x090, 0x094, 0x098, 8, 3, 15, 0x008, 2),
778 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL
, "atb_sel",
779 atb_parents
, 0x090, 0x094, 0x098, 16, 2, 23, 0x008, 3),
781 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI_SEL
, "dpi_sel",
782 dpi_parents
, 0x0a0, 0x0a4, 0x0a8, 0, 3, 7, 0x008, 5),
783 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM_SEL
, "scam_sel",
784 scam_parents
, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, 0x008, 6),
785 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL
, "disp_pwm_sel",
786 disp_pwm_parents
, 0x0a0, 0x0a4, 0x0a8, 16, 3, 23, 0x008, 7),
787 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL
, "usb_top_sel",
788 usb_top_parents
, 0x0a0, 0x0a4, 0x0a8, 24, 2, 31, 0x008, 8),
790 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_SEL
, "ssusb_xhci_sel",
791 ssusb_xhci_parents
, 0x0b0, 0x0b4, 0x0b8, 0, 2, 7, 0x008, 9),
792 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL
, "i2c_sel",
793 i2c_parents
, 0x0b0, 0x0b4, 0x0b8, 8, 2, 15, 0x008, 10),
794 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL
, "seninf_sel",
795 seninf_parents
, 0x0b0, 0x0b4, 0x0b8, 16, 3, 23, 0x008, 11),
796 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL
, "seninf1_sel",
797 seninf1_parents
, 0x0b0, 0x0b4, 0x0b8, 24, 3, 31, 0x008, 12),
799 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2_SEL
, "seninf2_sel",
800 seninf2_parents
, 0x0c0, 0x0c4, 0x0c8, 0, 3, 7, 0x008, 13),
801 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3_SEL
, "seninf3_sel",
802 seninf3_parents
, 0x0c0, 0x0c4, 0x0c8, 8, 3, 15, 0x008, 14),
803 MUX_GATE_CLR_SET_UPD(CLK_TOP_TL_SEL
, "tl_sel",
804 tl_parents
, 0x0c0, 0x0c4, 0x0c8, 16, 2, 23, 0x008, 15),
805 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL
, "dxcc_sel",
806 dxcc_parents
, 0x0c0, 0x0c4, 0x0c8, 24, 2, 31, 0x008, 16),
808 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL
, "aud_engen1_sel",
809 aud_engen1_parents
, 0x0d0, 0x0d4, 0x0d8, 0, 2, 7, 0x008, 17),
810 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL
, "aud_engen2_sel",
811 aud_engen2_parents
, 0x0d0, 0x0d4, 0x0d8, 8, 2, 15, 0x008, 18),
812 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL
, "aes_ufsfde_sel",
813 aes_ufsfde_parents
, 0x0d0, 0x0d4, 0x0d8, 16, 3, 23, 0x008, 19),
814 MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS_SEL
, "ufs_sel",
815 ufs_parents
, 0x0d0, 0x0d4, 0x0d8, 24, 3, 31, 0x008, 20),
817 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL
, "aud_1_sel",
818 aud_1_parents
, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, 0x008, 21),
819 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL
, "aud_2_sel",
820 aud_2_parents
, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, 0x008, 22),
821 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_SEL
, "adsp_sel",
822 adsp_parents
, 0x0e0, 0x0e4, 0x0e8, 16, 3, 23, 0x008, 23),
823 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF_MAIN_SEL
, "dpmaif_main_sel",
824 dpmaif_main_parents
, 0x0e0, 0x0e4, 0x0e8, 24, 3, 31, 0x008, 24),
826 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL
, "venc_sel",
827 venc_parents
, 0x0f0, 0x0f4, 0x0f8, 0, 4, 7, 0x008, 25),
828 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL
, "vdec_sel",
829 vdec_parents
, 0x0f0, 0x0f4, 0x0f8, 8, 4, 15, 0x008, 26),
830 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL
, "camtm_sel",
831 camtm_parents
, 0x0f0, 0x0f4, 0x0f8, 16, 2, 23, 0x008, 27),
832 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL
, "pwm_sel",
833 pwm_parents
, 0x0f0, 0x0f4, 0x0f8, 24, 1, 31, 0x008, 28),
835 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL
, "audio_h_sel",
836 audio_h_parents
, 0x100, 0x104, 0x108, 0, 2, 7, 0x008, 29),
837 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST_SEL
, "spmi_mst_sel",
838 spmi_mst_parents
, 0x100, 0x104, 0x108, 8, 3, 15, 0x008, 30),
839 MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL
, "aes_msdcfde_sel",
840 aes_msdcfde_parents
, 0x100, 0x104, 0x108, 24, 3, 31, 0x00c, 1),
842 MUX_GATE_CLR_SET_UPD(CLK_TOP_SFLASH_SEL
, "sflash_sel",
843 sflash_parents
, 0x110, 0x114, 0x118, 8, 2, 15, 0x00c, 3),
846 static struct mtk_composite top_muxes
[] = {
848 MUX(CLK_TOP_APLL_I2S0_M_SEL
, "apll_i2s0_m_sel", apll_i2s0_m_parents
, 0x320, 16, 1),
849 MUX(CLK_TOP_APLL_I2S1_M_SEL
, "apll_i2s1_m_sel", apll_i2s1_m_parents
, 0x320, 17, 1),
850 MUX(CLK_TOP_APLL_I2S2_M_SEL
, "apll_i2s2_m_sel", apll_i2s2_m_parents
, 0x320, 18, 1),
851 MUX(CLK_TOP_APLL_I2S3_M_SEL
, "apll_i2s3_m_sel", apll_i2s3_m_parents
, 0x320, 19, 1),
852 MUX(CLK_TOP_APLL_I2S4_M_SEL
, "apll_i2s4_m_sel", apll_i2s4_m_parents
, 0x320, 20, 1),
853 MUX(CLK_TOP_APLL_I2S5_M_SEL
, "apll_i2s5_m_sel", apll_i2s5_m_parents
, 0x320, 21, 1),
854 MUX(CLK_TOP_APLL_I2S6_M_SEL
, "apll_i2s6_m_sel", apll_i2s6_m_parents
, 0x320, 22, 1),
855 MUX(CLK_TOP_APLL_I2S7_M_SEL
, "apll_i2s7_m_sel", apll_i2s7_m_parents
, 0x320, 23, 1),
856 MUX(CLK_TOP_APLL_I2S8_M_SEL
, "apll_i2s8_m_sel", apll_i2s8_m_parents
, 0x320, 24, 1),
857 MUX(CLK_TOP_APLL_I2S9_M_SEL
, "apll_i2s9_m_sel", apll_i2s9_m_parents
, 0x320, 25, 1),
860 static const struct mtk_composite top_adj_divs
[] = {
861 DIV_GATE(CLK_TOP_APLL12_DIV0
, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0),
862 DIV_GATE(CLK_TOP_APLL12_DIV1
, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1, 0x328, 8, 8),
863 DIV_GATE(CLK_TOP_APLL12_DIV2
, "apll12_div2", "apll_i2s2_m_sel", 0x320, 2, 0x328, 8, 16),
864 DIV_GATE(CLK_TOP_APLL12_DIV3
, "apll12_div3", "apll_i2s3_m_sel", 0x320, 3, 0x328, 8, 24),
865 DIV_GATE(CLK_TOP_APLL12_DIV4
, "apll12_div4", "apll_i2s4_m_sel", 0x320, 4, 0x334, 8, 0),
866 DIV_GATE(CLK_TOP_APLL12_DIVB
, "apll12_divb", "apll12_div4", 0x320, 5, 0x334, 8, 8),
867 DIV_GATE(CLK_TOP_APLL12_DIV5
, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16),
868 DIV_GATE(CLK_TOP_APLL12_DIV6
, "apll12_div6", "apll_i2s6_m_sel", 0x320, 7, 0x334, 8, 24),
869 DIV_GATE(CLK_TOP_APLL12_DIV7
, "apll12_div7", "apll_i2s7_m_sel", 0x320, 8, 0x338, 8, 0),
870 DIV_GATE(CLK_TOP_APLL12_DIV8
, "apll12_div8", "apll_i2s8_m_sel", 0x320, 9, 0x338, 8, 8),
871 DIV_GATE(CLK_TOP_APLL12_DIV9
, "apll12_div9", "apll_i2s9_m_sel", 0x320, 10, 0x338, 8, 16),
874 static const struct mtk_gate_regs apmixed_cg_regs
= {
880 #define GATE_APMIXED(_id, _name, _parent, _shift) \
881 GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
883 static const struct mtk_gate apmixed_clks
[] = {
884 GATE_APMIXED(CLK_APMIXED_MIPID26M
, "mipid26m", "clk26m", 16),
887 static const struct mtk_gate_regs infra0_cg_regs
= {
893 static const struct mtk_gate_regs infra1_cg_regs
= {
899 static const struct mtk_gate_regs infra2_cg_regs
= {
905 static const struct mtk_gate_regs infra3_cg_regs
= {
911 static const struct mtk_gate_regs infra4_cg_regs
= {
917 static const struct mtk_gate_regs infra5_cg_regs
= {
923 #define GATE_INFRA0(_id, _name, _parent, _shift) \
924 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
926 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag) \
927 GATE_MTK_FLAGS(_id, _name, _parent, &infra1_cg_regs, _shift, \
928 &mtk_clk_gate_ops_setclr, _flag)
930 #define GATE_INFRA1(_id, _name, _parent, _shift) \
931 GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
933 #define GATE_INFRA2(_id, _name, _parent, _shift) \
934 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
936 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \
937 GATE_MTK_FLAGS(_id, _name, _parent, &infra3_cg_regs, _shift, \
938 &mtk_clk_gate_ops_setclr, _flag)
940 #define GATE_INFRA3(_id, _name, _parent, _shift) \
941 GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
943 #define GATE_INFRA4(_id, _name, _parent, _shift) \
944 GATE_MTK(_id, _name, _parent, &infra4_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
946 #define GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, _flag) \
947 GATE_MTK_FLAGS(_id, _name, _parent, &infra5_cg_regs, _shift, \
948 &mtk_clk_gate_ops_setclr, _flag)
950 #define GATE_INFRA5(_id, _name, _parent, _shift) \
951 GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, 0)
955 * infra_133m and infra_66m are main peripheral bus clocks of SOC.
956 * infra_device_apc and infra_device_apc_sync are for device access permission control module.
958 static const struct mtk_gate infra_clks
[] = {
960 GATE_INFRA0(CLK_INFRA_PMIC_TMR
, "infra_pmic_tmr", "pwrap_ulposc_sel", 0),
961 GATE_INFRA0(CLK_INFRA_PMIC_AP
, "infra_pmic_ap", "pwrap_ulposc_sel", 1),
962 GATE_INFRA0(CLK_INFRA_PMIC_MD
, "infra_pmic_md", "pwrap_ulposc_sel", 2),
963 GATE_INFRA0(CLK_INFRA_PMIC_CONN
, "infra_pmic_conn", "pwrap_ulposc_sel", 3),
964 GATE_INFRA0(CLK_INFRA_SCPSYS
, "infra_scpsys", "scp_sel", 4),
965 GATE_INFRA0(CLK_INFRA_SEJ
, "infra_sej", "axi_sel", 5),
966 GATE_INFRA0(CLK_INFRA_APXGPT
, "infra_apxgpt", "axi_sel", 6),
967 GATE_INFRA0(CLK_INFRA_GCE
, "infra_gce", "axi_sel", 8),
968 GATE_INFRA0(CLK_INFRA_GCE2
, "infra_gce2", "axi_sel", 9),
969 GATE_INFRA0(CLK_INFRA_THERM
, "infra_therm", "axi_sel", 10),
970 GATE_INFRA0(CLK_INFRA_I2C0
, "infra_i2c0", "i2c_sel", 11),
971 GATE_INFRA0(CLK_INFRA_AP_DMA_PSEUDO
, "infra_ap_dma_pseudo", "axi_sel", 12),
972 GATE_INFRA0(CLK_INFRA_I2C2
, "infra_i2c2", "i2c_sel", 13),
973 GATE_INFRA0(CLK_INFRA_I2C3
, "infra_i2c3", "i2c_sel", 14),
974 GATE_INFRA0(CLK_INFRA_PWM_H
, "infra_pwm_h", "axi_sel", 15),
975 GATE_INFRA0(CLK_INFRA_PWM1
, "infra_pwm1", "pwm_sel", 16),
976 GATE_INFRA0(CLK_INFRA_PWM2
, "infra_pwm2", "pwm_sel", 17),
977 GATE_INFRA0(CLK_INFRA_PWM3
, "infra_pwm3", "pwm_sel", 18),
978 GATE_INFRA0(CLK_INFRA_PWM4
, "infra_pwm4", "pwm_sel", 19),
979 GATE_INFRA0(CLK_INFRA_PWM
, "infra_pwm", "pwm_sel", 21),
980 GATE_INFRA0(CLK_INFRA_UART0
, "infra_uart0", "uart_sel", 22),
981 GATE_INFRA0(CLK_INFRA_UART1
, "infra_uart1", "uart_sel", 23),
982 GATE_INFRA0(CLK_INFRA_UART2
, "infra_uart2", "uart_sel", 24),
983 GATE_INFRA0(CLK_INFRA_UART3
, "infra_uart3", "uart_sel", 25),
984 GATE_INFRA0(CLK_INFRA_GCE_26M
, "infra_gce_26m", "axi_sel", 27),
985 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC
, "infra_cq_dma_fpc", "axi_sel", 28),
986 GATE_INFRA0(CLK_INFRA_BTIF
, "infra_btif", "axi_sel", 31),
988 GATE_INFRA1(CLK_INFRA_SPI0
, "infra_spi0", "spi_sel", 1),
989 GATE_INFRA1(CLK_INFRA_MSDC0
, "infra_msdc0", "msdc50_0_h_sel", 2),
990 GATE_INFRA1(CLK_INFRA_MSDC1
, "infra_msdc1", "msdc50_0_h_sel", 4),
991 GATE_INFRA1(CLK_INFRA_MSDC2
, "infra_msdc2", "msdc50_0_h_sel", 5),
992 GATE_INFRA1(CLK_INFRA_MSDC0_SRC
, "infra_msdc0_src", "msdc50_0_sel", 6),
993 GATE_INFRA1(CLK_INFRA_GCPU
, "infra_gcpu", "axi_sel", 8),
994 GATE_INFRA1(CLK_INFRA_TRNG
, "infra_trng", "axi_sel", 9),
995 GATE_INFRA1(CLK_INFRA_AUXADC
, "infra_auxadc", "clk26m", 10),
996 GATE_INFRA1(CLK_INFRA_CPUM
, "infra_cpum", "axi_sel", 11),
997 GATE_INFRA1(CLK_INFRA_CCIF1_AP
, "infra_ccif1_ap", "axi_sel", 12),
998 GATE_INFRA1(CLK_INFRA_CCIF1_MD
, "infra_ccif1_md", "axi_sel", 13),
999 GATE_INFRA1(CLK_INFRA_AUXADC_MD
, "infra_auxadc_md", "clk26m", 14),
1000 GATE_INFRA1(CLK_INFRA_PCIE_TL_26M
, "infra_pcie_tl_26m", "axi_sel", 15),
1001 GATE_INFRA1(CLK_INFRA_MSDC1_SRC
, "infra_msdc1_src", "msdc30_1_sel", 16),
1002 GATE_INFRA1(CLK_INFRA_MSDC2_SRC
, "infra_msdc2_src", "msdc30_2_sel", 17),
1003 GATE_INFRA1(CLK_INFRA_PCIE_TL_96M
, "infra_pcie_tl_96m", "tl_sel", 18),
1004 GATE_INFRA1(CLK_INFRA_PCIE_PL_P_250M
, "infra_pcie_pl_p_250m", "axi_sel", 19),
1005 GATE_INFRA1_FLAGS(CLK_INFRA_DEVICE_APC
, "infra_device_apc", "axi_sel", 20, CLK_IS_CRITICAL
),
1006 GATE_INFRA1(CLK_INFRA_CCIF_AP
, "infra_ccif_ap", "axi_sel", 23),
1007 GATE_INFRA1(CLK_INFRA_DEBUGSYS
, "infra_debugsys", "axi_sel", 24),
1008 GATE_INFRA1(CLK_INFRA_AUDIO
, "infra_audio", "axi_sel", 25),
1009 GATE_INFRA1(CLK_INFRA_CCIF_MD
, "infra_ccif_md", "axi_sel", 26),
1010 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE
, "infra_dxcc_sec_core", "dxcc_sel", 27),
1011 GATE_INFRA1(CLK_INFRA_DXCC_AO
, "infra_dxcc_ao", "dxcc_sel", 28),
1012 GATE_INFRA1(CLK_INFRA_DBG_TRACE
, "infra_dbg_trace", "axi_sel", 29),
1013 GATE_INFRA1(CLK_INFRA_DEVMPU_B
, "infra_devmpu_b", "axi_sel", 30),
1014 GATE_INFRA1(CLK_INFRA_DRAMC_F26M
, "infra_dramc_f26m", "clk26m", 31),
1016 GATE_INFRA2(CLK_INFRA_IRTX
, "infra_irtx", "clk26m", 0),
1017 GATE_INFRA2(CLK_INFRA_SSUSB
, "infra_ssusb", "usb_top_sel", 1),
1018 GATE_INFRA2(CLK_INFRA_DISP_PWM
, "infra_disp_pwm", "axi_sel", 2),
1019 GATE_INFRA2(CLK_INFRA_CLDMA_B
, "infra_cldma_b", "axi_sel", 3),
1020 GATE_INFRA2(CLK_INFRA_AUDIO_26M_B
, "infra_audio_26m_b", "clk26m", 4),
1021 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE
, "infra_modem_temp_share", "clk26m", 5),
1022 GATE_INFRA2(CLK_INFRA_SPI1
, "infra_spi1", "spi_sel", 6),
1023 GATE_INFRA2(CLK_INFRA_I2C4
, "infra_i2c4", "i2c_sel", 7),
1024 GATE_INFRA2(CLK_INFRA_SPI2
, "infra_spi2", "spi_sel", 9),
1025 GATE_INFRA2(CLK_INFRA_SPI3
, "infra_spi3", "spi_sel", 10),
1026 GATE_INFRA2(CLK_INFRA_UNIPRO_SYS
, "infra_unipro_sys", "ufs_sel", 11),
1027 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK
, "infra_unipro_tick", "clk26m", 12),
1028 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_B
, "infra_ufs_mp_sap_b", "clk26m", 13),
1029 GATE_INFRA2(CLK_INFRA_MD32_B
, "infra_md32_b", "axi_sel", 14),
1030 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST
, "infra_unipro_mbist", "axi_sel", 16),
1031 GATE_INFRA2(CLK_INFRA_I2C5
, "infra_i2c5", "i2c_sel", 18),
1032 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER
, "infra_i2c5_arbiter", "i2c_sel", 19),
1033 GATE_INFRA2(CLK_INFRA_I2C5_IMM
, "infra_i2c5_imm", "i2c_sel", 20),
1034 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER
, "infra_i2c1_arbiter", "i2c_sel", 21),
1035 GATE_INFRA2(CLK_INFRA_I2C1_IMM
, "infra_i2c1_imm", "i2c_sel", 22),
1036 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER
, "infra_i2c2_arbiter", "i2c_sel", 23),
1037 GATE_INFRA2(CLK_INFRA_I2C2_IMM
, "infra_i2c2_imm", "i2c_sel", 24),
1038 GATE_INFRA2(CLK_INFRA_SPI4
, "infra_spi4", "spi_sel", 25),
1039 GATE_INFRA2(CLK_INFRA_SPI5
, "infra_spi5", "spi_sel", 26),
1040 GATE_INFRA2(CLK_INFRA_CQ_DMA
, "infra_cq_dma", "axi_sel", 27),
1041 GATE_INFRA2(CLK_INFRA_UFS
, "infra_ufs", "ufs_sel", 28),
1042 GATE_INFRA2(CLK_INFRA_AES_UFSFDE
, "infra_aes_ufsfde", "aes_ufsfde_sel", 29),
1043 GATE_INFRA2(CLK_INFRA_UFS_TICK
, "infra_ufs_tick", "ufs_sel", 30),
1044 GATE_INFRA2(CLK_INFRA_SSUSB_XHCI
, "infra_ssusb_xhci", "ssusb_xhci_sel", 31),
1046 GATE_INFRA3(CLK_INFRA_MSDC0_SELF
, "infra_msdc0_self", "msdc50_0_sel", 0),
1047 GATE_INFRA3(CLK_INFRA_MSDC1_SELF
, "infra_msdc1_self", "msdc50_0_sel", 1),
1048 GATE_INFRA3(CLK_INFRA_MSDC2_SELF
, "infra_msdc2_self", "msdc50_0_sel", 2),
1049 GATE_INFRA3(CLK_INFRA_UFS_AXI
, "infra_ufs_axi", "axi_sel", 5),
1050 GATE_INFRA3(CLK_INFRA_I2C6
, "infra_i2c6", "i2c_sel", 6),
1051 GATE_INFRA3(CLK_INFRA_AP_MSDC0
, "infra_ap_msdc0", "msdc50_0_sel", 7),
1052 GATE_INFRA3(CLK_INFRA_MD_MSDC0
, "infra_md_msdc0", "msdc50_0_sel", 8),
1053 GATE_INFRA3(CLK_INFRA_CCIF5_AP
, "infra_ccif5_ap", "axi_sel", 9),
1054 GATE_INFRA3(CLK_INFRA_CCIF5_MD
, "infra_ccif5_md", "axi_sel", 10),
1055 GATE_INFRA3(CLK_INFRA_PCIE_TOP_H_133M
, "infra_pcie_top_h_133m", "axi_sel", 11),
1056 GATE_INFRA3(CLK_INFRA_FLASHIF_TOP_H_133M
, "infra_flashif_top_h_133m", "axi_sel", 14),
1057 GATE_INFRA3(CLK_INFRA_PCIE_PERI_26M
, "infra_pcie_peri_26m", "axi_sel", 15),
1058 GATE_INFRA3(CLK_INFRA_CCIF2_AP
, "infra_ccif2_ap", "axi_sel", 16),
1059 GATE_INFRA3(CLK_INFRA_CCIF2_MD
, "infra_ccif2_md", "axi_sel", 17),
1060 GATE_INFRA3(CLK_INFRA_CCIF3_AP
, "infra_ccif3_ap", "axi_sel", 18),
1061 GATE_INFRA3(CLK_INFRA_CCIF3_MD
, "infra_ccif3_md", "axi_sel", 19),
1062 GATE_INFRA3(CLK_INFRA_SEJ_F13M
, "infra_sej_f13m", "clk26m", 20),
1063 GATE_INFRA3(CLK_INFRA_AES
, "infra_aes", "axi_sel", 21),
1064 GATE_INFRA3(CLK_INFRA_I2C7
, "infra_i2c7", "i2c_sel", 22),
1065 GATE_INFRA3(CLK_INFRA_I2C8
, "infra_i2c8", "i2c_sel", 23),
1066 GATE_INFRA3(CLK_INFRA_FBIST2FPC
, "infra_fbist2fpc", "msdc50_0_sel", 24),
1067 GATE_INFRA3_FLAGS(CLK_INFRA_DEVICE_APC_SYNC
, "infra_device_apc_sync", "axi_sel", 25,
1069 GATE_INFRA3(CLK_INFRA_DPMAIF_MAIN
, "infra_dpmaif_main", "dpmaif_main_sel", 26),
1070 GATE_INFRA3(CLK_INFRA_PCIE_TL_32K
, "infra_pcie_tl_32k", "axi_sel", 27),
1071 GATE_INFRA3(CLK_INFRA_CCIF4_AP
, "infra_ccif4_ap", "axi_sel", 28),
1072 GATE_INFRA3(CLK_INFRA_CCIF4_MD
, "infra_ccif4_md", "axi_sel", 29),
1073 GATE_INFRA3(CLK_INFRA_SPI6
, "infra_spi6", "spi_sel", 30),
1074 GATE_INFRA3(CLK_INFRA_SPI7
, "infra_spi7", "spi_sel", 31),
1076 GATE_INFRA4(CLK_INFRA_AP_DMA
, "infra_ap_dma", "infra_ap_dma_pseudo", 31),
1078 GATE_INFRA5_FLAGS(CLK_INFRA_133M
, "infra_133m", "axi_sel", 0, CLK_IS_CRITICAL
),
1079 GATE_INFRA5_FLAGS(CLK_INFRA_66M
, "infra_66m", "axi_sel", 1, CLK_IS_CRITICAL
),
1080 GATE_INFRA5(CLK_INFRA_66M_PERI_BUS
, "infra_66m_peri_bus", "axi_sel", 2),
1081 GATE_INFRA5(CLK_INFRA_FREE_DCM_133M
, "infra_free_dcm_133m", "axi_sel", 3),
1082 GATE_INFRA5(CLK_INFRA_FREE_DCM_66M
, "infra_free_dcm_66m", "axi_sel", 4),
1083 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_133M
, "infra_peri_bus_dcm_133m", "axi_sel", 5),
1084 GATE_INFRA5(CLK_INFRA_PERI_BUS_DCM_66M
, "infra_peri_bus_dcm_66m", "axi_sel", 6),
1085 GATE_INFRA5(CLK_INFRA_FLASHIF_PERI_26M
, "infra_flashif_peri_26m", "axi_sel", 30),
1086 GATE_INFRA5(CLK_INFRA_FLASHIF_SFLASH
, "infra_flashif_fsflash", "axi_sel", 31),
1089 static const struct mtk_gate_regs peri_cg_regs
= {
1095 #define GATE_PERI(_id, _name, _parent, _shift) \
1096 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1098 static const struct mtk_gate peri_clks
[] = {
1099 GATE_PERI(CLK_PERI_PERIAXI
, "peri_periaxi", "axi_sel", 31),
1102 static const struct mtk_gate_regs top_cg_regs
= {
1108 #define GATE_TOP(_id, _name, _parent, _shift) \
1109 GATE_MTK(_id, _name, _parent, &top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
1111 static const struct mtk_gate top_clks
[] = {
1112 GATE_TOP(CLK_TOP_SSUSB_TOP_REF
, "ssusb_top_ref", "clk26m", 24),
1113 GATE_TOP(CLK_TOP_SSUSB_PHY_REF
, "ssusb_phy_ref", "clk26m", 25),
1116 #define MT8192_PLL_FMAX (3800UL * MHZ)
1117 #define MT8192_PLL_FMIN (1500UL * MHZ)
1118 #define MT8192_INTEGER_BITS 8
1120 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1121 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
1122 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
1123 _pcw_reg, _pcw_shift, _pcw_chg_reg, \
1124 _en_reg, _pll_en_bit) { \
1128 .pwr_reg = _pwr_reg, \
1129 .en_mask = _en_mask, \
1131 .rst_bar_mask = _rst_bar_mask, \
1132 .fmax = MT8192_PLL_FMAX, \
1133 .fmin = MT8192_PLL_FMIN, \
1134 .pcwbits = _pcwbits, \
1135 .pcwibits = MT8192_INTEGER_BITS, \
1136 .pd_reg = _pd_reg, \
1137 .pd_shift = _pd_shift, \
1138 .tuner_reg = _tuner_reg, \
1139 .tuner_en_reg = _tuner_en_reg, \
1140 .tuner_en_bit = _tuner_en_bit, \
1141 .pcw_reg = _pcw_reg, \
1142 .pcw_shift = _pcw_shift, \
1143 .pcw_chg_reg = _pcw_chg_reg, \
1144 .en_reg = _en_reg, \
1145 .pll_en_bit = _pll_en_bit, \
1148 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1149 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
1150 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
1151 _pcw_reg, _pcw_shift) \
1152 PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1153 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
1154 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
1155 _pcw_reg, _pcw_shift, 0, 0, 0)
1157 static const struct mtk_pll_data plls
[] = {
1158 PLL_B(CLK_APMIXED_MAINPLL
, "mainpll", 0x0340, 0x034c, 0xff000000,
1159 HAVE_RST_BAR
, BIT(23), 22, 0x0344, 24, 0, 0, 0, 0x0344, 0),
1160 PLL_B(CLK_APMIXED_UNIVPLL
, "univpll", 0x0308, 0x0314, 0xff000000,
1161 HAVE_RST_BAR
, BIT(23), 22, 0x030c, 24, 0, 0, 0, 0x030c, 0),
1162 PLL(CLK_APMIXED_USBPLL
, "usbpll", 0x03c4, 0x03cc, 0x00000000,
1163 0, 0, 22, 0x03c4, 24, 0, 0, 0, 0x03c4, 0, 0x03c4, 0x03cc, 2),
1164 PLL_B(CLK_APMIXED_MSDCPLL
, "msdcpll", 0x0350, 0x035c, 0x00000000,
1165 0, 0, 22, 0x0354, 24, 0, 0, 0, 0x0354, 0),
1166 PLL_B(CLK_APMIXED_MMPLL
, "mmpll", 0x0360, 0x036c, 0xff000000,
1167 HAVE_RST_BAR
, BIT(23), 22, 0x0364, 24, 0, 0, 0, 0x0364, 0),
1168 PLL_B(CLK_APMIXED_ADSPPLL
, "adsppll", 0x0370, 0x037c, 0xff000000,
1169 HAVE_RST_BAR
, BIT(23), 22, 0x0374, 24, 0, 0, 0, 0x0374, 0),
1170 PLL_B(CLK_APMIXED_MFGPLL
, "mfgpll", 0x0268, 0x0274, 0x00000000,
1171 0, 0, 22, 0x026c, 24, 0, 0, 0, 0x026c, 0),
1172 PLL_B(CLK_APMIXED_TVDPLL
, "tvdpll", 0x0380, 0x038c, 0x00000000,
1173 0, 0, 22, 0x0384, 24, 0, 0, 0, 0x0384, 0),
1174 PLL_B(CLK_APMIXED_APLL1
, "apll1", 0x0318, 0x0328, 0x00000000,
1175 0, 0, 32, 0x031c, 24, 0x0040, 0x000c, 0, 0x0320, 0),
1176 PLL_B(CLK_APMIXED_APLL2
, "apll2", 0x032c, 0x033c, 0x00000000,
1177 0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0),
1180 static struct clk_onecell_data
*top_clk_data
;
1182 static void clk_mt8192_top_init_early(struct device_node
*node
)
1186 top_clk_data
= mtk_alloc_clk_data(CLK_TOP_NR_CLK
);
1190 for (i
= 0; i
< CLK_TOP_NR_CLK
; i
++)
1191 top_clk_data
->clks
[i
] = ERR_PTR(-EPROBE_DEFER
);
1193 mtk_clk_register_factors(top_early_divs
, ARRAY_SIZE(top_early_divs
), top_clk_data
);
1195 of_clk_add_provider(node
, of_clk_src_onecell_get
, top_clk_data
);
1198 CLK_OF_DECLARE_DRIVER(mt8192_topckgen
, "mediatek,mt8192-topckgen",
1199 clk_mt8192_top_init_early
);
1201 static int clk_mt8192_top_probe(struct platform_device
*pdev
)
1203 struct device_node
*node
= pdev
->dev
.of_node
;
1207 base
= devm_platform_ioremap_resource(pdev
, 0);
1209 return PTR_ERR(base
);
1211 mtk_clk_register_fixed_clks(top_fixed_clks
, ARRAY_SIZE(top_fixed_clks
), top_clk_data
);
1212 mtk_clk_register_factors(top_early_divs
, ARRAY_SIZE(top_early_divs
), top_clk_data
);
1213 mtk_clk_register_factors(top_divs
, ARRAY_SIZE(top_divs
), top_clk_data
);
1214 mtk_clk_register_muxes(top_mtk_muxes
, ARRAY_SIZE(top_mtk_muxes
), node
, &mt8192_clk_lock
,
1216 mtk_clk_register_composites(top_muxes
, ARRAY_SIZE(top_muxes
), base
, &mt8192_clk_lock
,
1218 mtk_clk_register_composites(top_adj_divs
, ARRAY_SIZE(top_adj_divs
), base
, &mt8192_clk_lock
,
1220 r
= mtk_clk_register_gates(node
, top_clks
, ARRAY_SIZE(top_clks
), top_clk_data
);
1224 return of_clk_add_provider(node
, of_clk_src_onecell_get
, top_clk_data
);
1227 static int clk_mt8192_infra_probe(struct platform_device
*pdev
)
1229 struct clk_onecell_data
*clk_data
;
1230 struct device_node
*node
= pdev
->dev
.of_node
;
1233 clk_data
= mtk_alloc_clk_data(CLK_INFRA_NR_CLK
);
1237 r
= mtk_clk_register_gates(node
, infra_clks
, ARRAY_SIZE(infra_clks
), clk_data
);
1241 return of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
1244 static int clk_mt8192_peri_probe(struct platform_device
*pdev
)
1246 struct clk_onecell_data
*clk_data
;
1247 struct device_node
*node
= pdev
->dev
.of_node
;
1250 clk_data
= mtk_alloc_clk_data(CLK_PERI_NR_CLK
);
1254 r
= mtk_clk_register_gates(node
, peri_clks
, ARRAY_SIZE(peri_clks
), clk_data
);
1258 return of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
1261 static int clk_mt8192_apmixed_probe(struct platform_device
*pdev
)
1263 struct clk_onecell_data
*clk_data
;
1264 struct device_node
*node
= pdev
->dev
.of_node
;
1267 clk_data
= mtk_alloc_clk_data(CLK_APMIXED_NR_CLK
);
1271 mtk_clk_register_plls(node
, plls
, ARRAY_SIZE(plls
), clk_data
);
1272 r
= mtk_clk_register_gates(node
, apmixed_clks
, ARRAY_SIZE(apmixed_clks
), clk_data
);
1276 return of_clk_add_provider(node
, of_clk_src_onecell_get
, clk_data
);
1279 static const struct of_device_id of_match_clk_mt8192
[] = {
1281 .compatible
= "mediatek,mt8192-apmixedsys",
1282 .data
= clk_mt8192_apmixed_probe
,
1284 .compatible
= "mediatek,mt8192-topckgen",
1285 .data
= clk_mt8192_top_probe
,
1287 .compatible
= "mediatek,mt8192-infracfg",
1288 .data
= clk_mt8192_infra_probe
,
1290 .compatible
= "mediatek,mt8192-pericfg",
1291 .data
= clk_mt8192_peri_probe
,
1297 static int clk_mt8192_probe(struct platform_device
*pdev
)
1299 int (*clk_probe
)(struct platform_device
*pdev
);
1302 clk_probe
= of_device_get_match_data(&pdev
->dev
);
1306 r
= clk_probe(pdev
);
1308 dev_err(&pdev
->dev
, "could not register clock provider: %s: %d\n", pdev
->name
, r
);
1313 static struct platform_driver clk_mt8192_drv
= {
1314 .probe
= clk_mt8192_probe
,
1316 .name
= "clk-mt8192",
1317 .of_match_table
= of_match_clk_mt8192
,
1321 static int __init
clk_mt8192_init(void)
1323 return platform_driver_register(&clk_mt8192_drv
);
1326 arch_initcall(clk_mt8192_init
);