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git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - drivers/clk/mediatek/clk-mtk.h
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: James Liao <jamesjj.liao@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef __DRV_CLK_MTK_H
16 #define __DRV_CLK_MTK_H
18 #include <linux/regmap.h>
19 #include <linux/bitops.h>
20 #include <linux/clk.h>
21 #include <linux/clk-provider.h>
23 #define MAX_MUX_GATE_BIT 31
24 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
26 #define MHZ (1000 * 1000)
28 struct mtk_fixed_factor
{
31 const char *parent_name
;
36 #define FACTOR(_id, _name, _parent, _mult, _div) { \
39 .parent_name = _parent, \
44 extern void mtk_clk_register_factors(const struct mtk_fixed_factor
*clks
,
45 int num
, struct clk_onecell_data
*clk_data
);
47 struct mtk_composite
{
50 const char * const *parent_names
;
58 signed char mux_shift
;
59 signed char mux_width
;
60 signed char gate_shift
;
62 signed char divider_shift
;
63 signed char divider_width
;
65 signed char num_parents
;
68 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) { \
72 .mux_shift = _shift, \
73 .mux_width = _width, \
75 .gate_shift = _gate, \
76 .divider_shift = -1, \
77 .parent_names = _parents, \
78 .num_parents = ARRAY_SIZE(_parents), \
79 .flags = CLK_SET_RATE_PARENT, \
82 #define MUX(_id, _name, _parents, _reg, _shift, _width) { \
86 .mux_shift = _shift, \
87 .mux_width = _width, \
89 .divider_shift = -1, \
90 .parent_names = _parents, \
91 .num_parents = ARRAY_SIZE(_parents), \
92 .flags = CLK_SET_RATE_PARENT, \
95 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \
99 .divider_reg = _div_reg, \
100 .divider_shift = _div_shift, \
101 .divider_width = _div_width, \
102 .gate_reg = _gate_reg, \
103 .gate_shift = _gate_shift, \
108 struct clk
*mtk_clk_register_composite(const struct mtk_composite
*mc
,
109 void __iomem
*base
, spinlock_t
*lock
);
111 void mtk_clk_register_composites(const struct mtk_composite
*mcs
,
112 int num
, void __iomem
*base
, spinlock_t
*lock
,
113 struct clk_onecell_data
*clk_data
);
115 struct mtk_gate_regs
{
124 const char *parent_name
;
125 const struct mtk_gate_regs
*regs
;
127 const struct clk_ops
*ops
;
130 int mtk_clk_register_gates(struct device_node
*node
, const struct mtk_gate
*clks
,
131 int num
, struct clk_onecell_data
*clk_data
);
133 struct clk_onecell_data
*mtk_alloc_clk_data(unsigned int clk_num
);
135 #define HAVE_RST_BAR BIT(0)
137 struct mtk_pll_data
{
147 const struct clk_ops
*ops
;
155 void __init
mtk_clk_register_plls(struct device_node
*node
,
156 const struct mtk_pll_data
*plls
, int num_plls
,
157 struct clk_onecell_data
*clk_data
);
159 #ifdef CONFIG_RESET_CONTROLLER
160 void mtk_register_reset_controller(struct device_node
*np
,
161 unsigned int num_regs
, int regofs
);
163 static inline void mtk_register_reset_controller(struct device_node
*np
,
164 unsigned int num_regs
, int regofs
)
169 #endif /* __DRV_CLK_MTK_H */