drivers/clk/mediatek/clk-mtk.h

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: James Liao <jamesjj.liao@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef __DRV_CLK_MTK_H
  16 #define __DRV_CLK_MTK_H
  17
  18 #include <linux/regmap.h>
  19 #include <linux/bitops.h>
  20 #include <linux/clk-provider.h>
  21
  22 struct clk;
  23
  24 #define MAX_MUX_GATE_BIT        31
  25 #define INVALID_MUX_GATE_BIT    (MAX_MUX_GATE_BIT + 1)
  26
  27 #define MHZ (1000 * 1000)
  28
  29 struct mtk_fixed_clk {
  30         int id;
  31         const char *name;
  32         const char *parent;
  33         unsigned long rate;
  34 };
  35
  36 #define FIXED_CLK(_id, _name, _parent, _rate) {         \
  37                 .id = _id,                              \
  38                 .name = _name,                          \
  39                 .parent = _parent,                      \
  40                 .rate = _rate,                          \
  41         }
  42
  43 void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
  44                 int num, struct clk_onecell_data *clk_data);
  45
  46 struct mtk_fixed_factor {
  47         int id;
  48         const char *name;
  49         const char *parent_name;
  50         int mult;
  51         int div;
  52 };
  53
  54 #define FACTOR(_id, _name, _parent, _mult, _div) {      \
  55                 .id = _id,                              \
  56                 .name = _name,                          \
  57                 .parent_name = _parent,                 \
  58                 .mult = _mult,                          \
  59                 .div = _div,                            \
  60         }
  61
  62 void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
  63                 int num, struct clk_onecell_data *clk_data);
  64
  65 struct mtk_composite {
  66         int id;
  67         const char *name;
  68         const char * const *parent_names;
  69         const char *parent;
  70         unsigned flags;
  71
  72         uint32_t mux_reg;
  73         uint32_t divider_reg;
  74         uint32_t gate_reg;
  75
  76         signed char mux_shift;
  77         signed char mux_width;
  78         signed char gate_shift;
  79
  80         signed char divider_shift;
  81         signed char divider_width;
  82
  83         signed char num_parents;
  84 };
  85
  86 /*
  87  * In case the rate change propagation to parent clocks is undesirable,
  88  * this macro allows to specify the clock flags manually.
  89  */
  90 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,      \
  91                         _gate, _flags) {                                \
  92                 .id = _id,                                              \
  93                 .name = _name,                                          \
  94                 .mux_reg = _reg,                                        \
  95                 .mux_shift = _shift,                                    \
  96                 .mux_width = _width,                                    \
  97                 .gate_reg = _reg,                                       \
  98                 .gate_shift = _gate,                                    \
  99                 .divider_shift = -1,                                    \
 100                 .parent_names = _parents,                               \
 101                 .num_parents = ARRAY_SIZE(_parents),                    \
 102                 .flags = _flags,                                        \
 103         }
 104
 105 /*
 106  * Unless necessary, all MUX_GATE clocks propagate rate changes to their
 107  * parent clock by default.
 108  */
 109 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate)     \
 110         MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,      \
 111                 _gate, CLK_SET_RATE_PARENT)
 112
 113 #define MUX(_id, _name, _parents, _reg, _shift, _width) {               \
 114                 .id = _id,                                              \
 115                 .name = _name,                                          \
 116                 .mux_reg = _reg,                                        \
 117                 .mux_shift = _shift,                                    \
 118                 .mux_width = _width,                                    \
 119                 .gate_shift = -1,                                       \
 120                 .divider_shift = -1,                                    \
 121                 .parent_names = _parents,                               \
 122                 .num_parents = ARRAY_SIZE(_parents),                    \
 123                 .flags = CLK_SET_RATE_PARENT,                           \
 124         }
 125
 126 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
 127                                         _div_width, _div_shift) {       \
 128                 .id = _id,                                              \
 129                 .parent = _parent,                                      \
 130                 .name = _name,                                          \
 131                 .divider_reg = _div_reg,                                \
 132                 .divider_shift = _div_shift,                            \
 133                 .divider_width = _div_width,                            \
 134                 .gate_reg = _gate_reg,                                  \
 135                 .gate_shift = _gate_shift,                              \
 136                 .mux_shift = -1,                                        \
 137                 .flags = 0,                                             \
 138         }
 139
 140 struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
 141                 void __iomem *base, spinlock_t *lock);
 142
 143 void mtk_clk_register_composites(const struct mtk_composite *mcs,
 144                 int num, void __iomem *base, spinlock_t *lock,
 145                 struct clk_onecell_data *clk_data);
 146
 147 struct mtk_gate_regs {
 148         u32 sta_ofs;
 149         u32 clr_ofs;
 150         u32 set_ofs;
 151 };
 152
 153 struct mtk_gate {
 154         int id;
 155         const char *name;
 156         const char *parent_name;
 157         const struct mtk_gate_regs *regs;
 158         int shift;
 159         const struct clk_ops *ops;
 160 };
 161
 162 int mtk_clk_register_gates(struct device_node *node,
 163                         const struct mtk_gate *clks, int num,
 164                         struct clk_onecell_data *clk_data);
 165
 166 struct mtk_clk_divider {
 167         int id;
 168         const char *name;
 169         const char *parent_name;
 170         unsigned long flags;
 171
 172         u32 div_reg;
 173         unsigned char div_shift;
 174         unsigned char div_width;
 175         unsigned char clk_divider_flags;
 176         const struct clk_div_table *clk_div_table;
 177 };
 178
 179 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) {    \
 180                 .id = _id,                                      \
 181                 .name = _name,                                  \
 182                 .parent_name = _parent,                         \
 183                 .div_reg = _reg,                                \
 184                 .div_shift = _shift,                            \
 185                 .div_width = _width,                            \
 186 }
 187
 188 void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
 189                         int num, void __iomem *base, spinlock_t *lock,
 190                                 struct clk_onecell_data *clk_data);
 191
 192 struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
 193
 194 #define HAVE_RST_BAR    BIT(0)
 195 #define PLL_AO          BIT(1)
 196
 197 struct mtk_pll_div_table {
 198         u32 div;
 199         unsigned long freq;
 200 };
 201
 202 struct mtk_pll_data {
 203         int id;
 204         const char *name;
 205         uint32_t reg;
 206         uint32_t pwr_reg;
 207         uint32_t en_mask;
 208         uint32_t pd_reg;
 209         uint32_t tuner_reg;
 210         int pd_shift;
 211         unsigned int flags;
 212         const struct clk_ops *ops;
 213         u32 rst_bar_mask;
 214         unsigned long fmax;
 215         int pcwbits;
 216         uint32_t pcw_reg;
 217         int pcw_shift;
 218         const struct mtk_pll_div_table *div_table;
 219 };
 220
 221 void mtk_clk_register_plls(struct device_node *node,
 222                 const struct mtk_pll_data *plls, int num_plls,
 223                 struct clk_onecell_data *clk_data);
 224
 225 struct clk *mtk_clk_register_ref2usb_tx(const char *name,
 226                         const char *parent_name, void __iomem *reg);
 227
 228 #ifdef CONFIG_RESET_CONTROLLER
 229 void mtk_register_reset_controller(struct device_node *np,
 230                         unsigned int num_regs, int regofs);
 231 #else
 232 static inline void mtk_register_reset_controller(struct device_node *np,
 233                         unsigned int num_regs, int regofs)
 234 {
 235 }
 236 #endif
 237
 238 #endif /* __DRV_CLK_MTK_H */