drivers/clk/meson/clk-pll.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 Endless Mobile, Inc.
   4  * Author: Carlo Caione <carlo@endlessm.com>
   5  *
   6  * Copyright (c) 2018 Baylibre, SAS.
   7  * Author: Jerome Brunet <jbrunet@baylibre.com>
   8  */
   9
  10 /*
  11  * In the most basic form, a Meson PLL is composed as follows:
  12  *
  13  *                     PLL
  14  *        +--------------------------------+
  15  *        |                                |
  16  *        |             +--+               |
  17  *  in >>-----[ /N ]--->|  |      +-----+  |
  18  *        |             |  |------| DCO |---->> out
  19  *        |  +--------->|  |      +--v--+  |
  20  *        |  |          +--+         |     |
  21  *        |  |                       |     |
  22  *        |  +--[ *(M + (F/Fmax) ]<--+     |
  23  *        |                                |
  24  *        +--------------------------------+
  25  *
  26  * out = in * (m + frac / frac_max) / n
  27  */
  28
  29 #include <linux/clk-provider.h>
  30 #include <linux/delay.h>
  31 #include <linux/err.h>
  32 #include <linux/io.h>
  33 #include <linux/math64.h>
  34 #include <linux/module.h>
  35 #include <linux/of_address.h>
  36 #include <linux/slab.h>
  37 #include <linux/string.h>
  38
  39 #include "clkc.h"
  40
  41 static inline struct meson_clk_pll_data *
  42 meson_clk_pll_data(struct clk_regmap *clk)
  43 {
  44         return (struct meson_clk_pll_data *)clk->data;
  45 }
  46
  47 static unsigned long __pll_params_to_rate(unsigned long parent_rate,
  48                                           const struct pll_params_table *pllt,
  49                                           u16 frac,
  50                                           struct meson_clk_pll_data *pll)
  51 {
  52         u64 rate = (u64)parent_rate * pllt->m;
  53
  54         if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
  55                 u64 frac_rate = (u64)parent_rate * frac;
  56
  57                 rate += DIV_ROUND_UP_ULL(frac_rate,
  58                                          (1 << pll->frac.width));
  59         }
  60
  61         return DIV_ROUND_UP_ULL(rate, pllt->n);
  62 }
  63
  64 static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
  65                                                 unsigned long parent_rate)
  66 {
  67         struct clk_regmap *clk = to_clk_regmap(hw);
  68         struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
  69         struct pll_params_table pllt;
  70         u16 frac;
  71
  72         pllt.n = meson_parm_read(clk->map, &pll->n);
  73         pllt.m = meson_parm_read(clk->map, &pll->m);
  74
  75         frac = MESON_PARM_APPLICABLE(&pll->frac) ?
  76                 meson_parm_read(clk->map, &pll->frac) :
  77                 0;
  78
  79         return __pll_params_to_rate(parent_rate, &pllt, frac, pll);
  80 }
  81
  82 static u16 __pll_params_with_frac(unsigned long rate,
  83                                   unsigned long parent_rate,
  84                                   const struct pll_params_table *pllt,
  85                                   struct meson_clk_pll_data *pll)
  86 {
  87         u16 frac_max = (1 << pll->frac.width);
  88         u64 val = (u64)rate * pllt->n;
  89
  90         if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)
  91                 val = DIV_ROUND_CLOSEST_ULL(val * frac_max, parent_rate);
  92         else
  93                 val = div_u64(val * frac_max, parent_rate);
  94
  95         val -= pllt->m * frac_max;
  96
  97         return min((u16)val, (u16)(frac_max - 1));
  98 }
  99
 100 static bool meson_clk_pll_is_better(unsigned long rate,
 101                                     unsigned long best,
 102                                     unsigned long now,
 103                                     struct meson_clk_pll_data *pll)
 104 {
 105         if (!(pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) ||
 106             MESON_PARM_APPLICABLE(&pll->frac)) {
 107                 /* Round down */
 108                 if (now < rate && best < now)
 109                         return true;
 110         } else {
 111                 /* Round Closest */
 112                 if (abs(now - rate) < abs(best - rate))
 113                         return true;
 114         }
 115
 116         return false;
 117 }
 118
 119 static const struct pll_params_table *
 120 meson_clk_get_pll_settings(unsigned long rate,
 121                            unsigned long parent_rate,
 122                            struct meson_clk_pll_data *pll)
 123 {
 124         const struct pll_params_table *table = pll->table;
 125         unsigned long best = 0, now = 0;
 126         unsigned int i, best_i = 0;
 127
 128         if (!table)
 129                 return NULL;
 130
 131         for (i = 0; table[i].n; i++) {
 132                 now = __pll_params_to_rate(parent_rate, &table[i], 0, pll);
 133
 134                 /* If we get an exact match, don't bother any further */
 135                 if (now == rate) {
 136                         return &table[i];
 137                 } else if (meson_clk_pll_is_better(rate, best, now, pll)) {
 138                         best = now;
 139                         best_i = i;
 140                 }
 141         }
 142
 143         return (struct pll_params_table *)&table[best_i];
 144 }
 145
 146 static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 147                                      unsigned long *parent_rate)
 148 {
 149         struct clk_regmap *clk = to_clk_regmap(hw);
 150         struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
 151         const struct pll_params_table *pllt =
 152                 meson_clk_get_pll_settings(rate, *parent_rate, pll);
 153         unsigned long round;
 154         u16 frac;
 155
 156         if (!pllt)
 157                 return meson_clk_pll_recalc_rate(hw, *parent_rate);
 158
 159         round = __pll_params_to_rate(*parent_rate, pllt, 0, pll);
 160
 161         if (!MESON_PARM_APPLICABLE(&pll->frac) || rate == round)
 162                 return round;
 163
 164         /*
 165          * The rate provided by the setting is not an exact match, let's
 166          * try to improve the result using the fractional parameter
 167          */
 168         frac = __pll_params_with_frac(rate, *parent_rate, pllt, pll);
 169
 170         return __pll_params_to_rate(*parent_rate, pllt, frac, pll);
 171 }
 172
 173 static int meson_clk_pll_wait_lock(struct clk_hw *hw)
 174 {
 175         struct clk_regmap *clk = to_clk_regmap(hw);
 176         struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
 177         int delay = 24000000;
 178
 179         do {
 180                 /* Is the clock locked now ? */
 181                 if (meson_parm_read(clk->map, &pll->l))
 182                         return 0;
 183
 184                 delay--;
 185         } while (delay > 0);
 186
 187         return -ETIMEDOUT;
 188 }
 189
 190 static void meson_clk_pll_init(struct clk_hw *hw)
 191 {
 192         struct clk_regmap *clk = to_clk_regmap(hw);
 193         struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
 194
 195         if (pll->init_count) {
 196                 meson_parm_write(clk->map, &pll->rst, 1);
 197                 regmap_multi_reg_write(clk->map, pll->init_regs,
 198                                        pll->init_count);
 199                 meson_parm_write(clk->map, &pll->rst, 0);
 200         }
 201 }
 202
 203 static int meson_clk_pll_is_enabled(struct clk_hw *hw)
 204 {
 205         struct clk_regmap *clk = to_clk_regmap(hw);
 206         struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
 207
 208         if (meson_parm_read(clk->map, &pll->rst) ||
 209             !meson_parm_read(clk->map, &pll->en) ||
 210             !meson_parm_read(clk->map, &pll->l))
 211                 return 0;
 212
 213         return 1;
 214 }
 215
 216 static int meson_clk_pll_enable(struct clk_hw *hw)
 217 {
 218         struct clk_regmap *clk = to_clk_regmap(hw);
 219         struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
 220
 221         /* do nothing if the PLL is already enabled */
 222         if (clk_hw_is_enabled(hw))
 223                 return 0;
 224
 225         /* Make sure the pll is in reset */
 226         meson_parm_write(clk->map, &pll->rst, 1);
 227
 228         /* Enable the pll */
 229         meson_parm_write(clk->map, &pll->en, 1);
 230
 231         /* Take the pll out reset */
 232         meson_parm_write(clk->map, &pll->rst, 0);
 233
 234         if (meson_clk_pll_wait_lock(hw))
 235                 return -EIO;
 236
 237         return 0;
 238 }
 239
 240 static void meson_clk_pll_disable(struct clk_hw *hw)
 241 {
 242         struct clk_regmap *clk = to_clk_regmap(hw);
 243         struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
 244
 245         /* Put the pll is in reset */
 246         meson_parm_write(clk->map, &pll->rst, 1);
 247
 248         /* Disable the pll */
 249         meson_parm_write(clk->map, &pll->en, 0);
 250 }
 251
 252 static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 253                                   unsigned long parent_rate)
 254 {
 255         struct clk_regmap *clk = to_clk_regmap(hw);
 256         struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
 257         const struct pll_params_table *pllt;
 258         unsigned int enabled;
 259         unsigned long old_rate;
 260         u16 frac = 0;
 261
 262         if (parent_rate == 0 || rate == 0)
 263                 return -EINVAL;
 264
 265         old_rate = rate;
 266
 267         pllt = meson_clk_get_pll_settings(rate, parent_rate, pll);
 268         if (!pllt)
 269                 return -EINVAL;
 270
 271         enabled = meson_parm_read(clk->map, &pll->en);
 272         if (enabled)
 273                 meson_clk_pll_disable(hw);
 274
 275         meson_parm_write(clk->map, &pll->n, pllt->n);
 276         meson_parm_write(clk->map, &pll->m, pllt->m);
 277
 278
 279         if (MESON_PARM_APPLICABLE(&pll->frac)) {
 280                 frac = __pll_params_with_frac(rate, parent_rate, pllt, pll);
 281                 meson_parm_write(clk->map, &pll->frac, frac);
 282         }
 283
 284         /* If the pll is stopped, bail out now */
 285         if (!enabled)
 286                 return 0;
 287
 288         if (meson_clk_pll_enable(hw)) {
 289                 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
 290                         __func__, old_rate);
 291                 /*
 292                  * FIXME: Do we really need/want this HACK ?
 293                  * It looks unsafe. what happens if the clock gets into a
 294                  * broken state and we can't lock back on the old_rate ? Looks
 295                  * like an infinite recursion is possible
 296                  */
 297                 meson_clk_pll_set_rate(hw, old_rate, parent_rate);
 298         }
 299
 300         return 0;
 301 }
 302
 303 const struct clk_ops meson_clk_pll_ops = {
 304         .init           = meson_clk_pll_init,
 305         .recalc_rate    = meson_clk_pll_recalc_rate,
 306         .round_rate     = meson_clk_pll_round_rate,
 307         .set_rate       = meson_clk_pll_set_rate,
 308         .is_enabled     = meson_clk_pll_is_enabled,
 309         .enable         = meson_clk_pll_enable,
 310         .disable        = meson_clk_pll_disable
 311 };
 312
 313 const struct clk_ops meson_clk_pll_ro_ops = {
 314         .recalc_rate    = meson_clk_pll_recalc_rate,
 315         .is_enabled     = meson_clk_pll_is_enabled,
 316 };