1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 AmLogic, Inc.
4 * Michael Turquette <mturquette@baylibre.com>
7 #include <linux/clk-provider.h>
8 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/platform_device.h>
13 #include "clk-regmap.h"
16 #include "meson-eeclk.h"
17 #include "vid-pll-div.h"
19 static DEFINE_SPINLOCK(meson_clk_lock
);
21 static const struct pll_params_table gxbb_gp0_pll_params_table
[] = {
56 static const struct pll_params_table gxl_gp0_pll_params_table
[] = {
85 static struct clk_regmap gxbb_fixed_pll_dco
= {
86 .data
= &(struct meson_clk_pll_data
){
88 .reg_off
= HHI_MPLL_CNTL
,
93 .reg_off
= HHI_MPLL_CNTL
,
98 .reg_off
= HHI_MPLL_CNTL
,
103 .reg_off
= HHI_MPLL_CNTL2
,
108 .reg_off
= HHI_MPLL_CNTL
,
113 .reg_off
= HHI_MPLL_CNTL
,
118 .hw
.init
= &(struct clk_init_data
){
119 .name
= "fixed_pll_dco",
120 .ops
= &meson_clk_pll_ro_ops
,
121 .parent_data
= &(const struct clk_parent_data
) {
128 static struct clk_regmap gxbb_fixed_pll
= {
129 .data
= &(struct clk_regmap_div_data
){
130 .offset
= HHI_MPLL_CNTL
,
133 .flags
= CLK_DIVIDER_POWER_OF_TWO
,
135 .hw
.init
= &(struct clk_init_data
){
137 .ops
= &clk_regmap_divider_ro_ops
,
138 .parent_hws
= (const struct clk_hw
*[]) {
139 &gxbb_fixed_pll_dco
.hw
143 * This clock won't ever change at runtime so
144 * CLK_SET_RATE_PARENT is not required
149 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult
= {
152 .hw
.init
= &(struct clk_init_data
){
153 .name
= "hdmi_pll_pre_mult",
154 .ops
= &clk_fixed_factor_ops
,
155 .parent_data
= &(const struct clk_parent_data
) {
162 static struct clk_regmap gxbb_hdmi_pll_dco
= {
163 .data
= &(struct meson_clk_pll_data
){
165 .reg_off
= HHI_HDMI_PLL_CNTL
,
170 .reg_off
= HHI_HDMI_PLL_CNTL
,
175 .reg_off
= HHI_HDMI_PLL_CNTL
,
180 .reg_off
= HHI_HDMI_PLL_CNTL2
,
185 .reg_off
= HHI_HDMI_PLL_CNTL
,
190 .reg_off
= HHI_HDMI_PLL_CNTL
,
195 .hw
.init
= &(struct clk_init_data
){
196 .name
= "hdmi_pll_dco",
197 .ops
= &meson_clk_pll_ro_ops
,
198 .parent_hws
= (const struct clk_hw
*[]) {
199 &gxbb_hdmi_pll_pre_mult
.hw
203 * Display directly handle hdmi pll registers ATM, we need
204 * NOCACHE to keep our view of the clock as accurate as possible
206 .flags
= CLK_GET_RATE_NOCACHE
,
210 static struct clk_regmap gxl_hdmi_pll_dco
= {
211 .data
= &(struct meson_clk_pll_data
){
213 .reg_off
= HHI_HDMI_PLL_CNTL
,
218 .reg_off
= HHI_HDMI_PLL_CNTL
,
223 .reg_off
= HHI_HDMI_PLL_CNTL
,
228 * On gxl, there is a register shift due to
229 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
230 * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
231 * instead which is defined at the same offset.
234 .reg_off
= HHI_HDMI_PLL_CNTL2
,
239 .reg_off
= HHI_HDMI_PLL_CNTL
,
244 .reg_off
= HHI_HDMI_PLL_CNTL
,
249 .hw
.init
= &(struct clk_init_data
){
250 .name
= "hdmi_pll_dco",
251 .ops
= &meson_clk_pll_ro_ops
,
252 .parent_data
= &(const struct clk_parent_data
) {
257 * Display directly handle hdmi pll registers ATM, we need
258 * NOCACHE to keep our view of the clock as accurate as possible
260 .flags
= CLK_GET_RATE_NOCACHE
,
264 static struct clk_regmap gxbb_hdmi_pll_od
= {
265 .data
= &(struct clk_regmap_div_data
){
266 .offset
= HHI_HDMI_PLL_CNTL2
,
269 .flags
= CLK_DIVIDER_POWER_OF_TWO
,
271 .hw
.init
= &(struct clk_init_data
){
272 .name
= "hdmi_pll_od",
273 .ops
= &clk_regmap_divider_ro_ops
,
274 .parent_hws
= (const struct clk_hw
*[]) {
275 &gxbb_hdmi_pll_dco
.hw
278 .flags
= CLK_GET_RATE_NOCACHE
| CLK_SET_RATE_PARENT
,
282 static struct clk_regmap gxbb_hdmi_pll_od2
= {
283 .data
= &(struct clk_regmap_div_data
){
284 .offset
= HHI_HDMI_PLL_CNTL2
,
287 .flags
= CLK_DIVIDER_POWER_OF_TWO
,
289 .hw
.init
= &(struct clk_init_data
){
290 .name
= "hdmi_pll_od2",
291 .ops
= &clk_regmap_divider_ro_ops
,
292 .parent_hws
= (const struct clk_hw
*[]) {
296 .flags
= CLK_GET_RATE_NOCACHE
| CLK_SET_RATE_PARENT
,
300 static struct clk_regmap gxbb_hdmi_pll
= {
301 .data
= &(struct clk_regmap_div_data
){
302 .offset
= HHI_HDMI_PLL_CNTL2
,
305 .flags
= CLK_DIVIDER_POWER_OF_TWO
,
307 .hw
.init
= &(struct clk_init_data
){
309 .ops
= &clk_regmap_divider_ro_ops
,
310 .parent_hws
= (const struct clk_hw
*[]) {
311 &gxbb_hdmi_pll_od2
.hw
314 .flags
= CLK_GET_RATE_NOCACHE
| CLK_SET_RATE_PARENT
,
318 static struct clk_regmap gxl_hdmi_pll_od
= {
319 .data
= &(struct clk_regmap_div_data
){
320 .offset
= HHI_HDMI_PLL_CNTL
+ 8,
323 .flags
= CLK_DIVIDER_POWER_OF_TWO
,
325 .hw
.init
= &(struct clk_init_data
){
326 .name
= "hdmi_pll_od",
327 .ops
= &clk_regmap_divider_ro_ops
,
328 .parent_hws
= (const struct clk_hw
*[]) {
332 .flags
= CLK_GET_RATE_NOCACHE
| CLK_SET_RATE_PARENT
,
336 static struct clk_regmap gxl_hdmi_pll_od2
= {
337 .data
= &(struct clk_regmap_div_data
){
338 .offset
= HHI_HDMI_PLL_CNTL
+ 8,
341 .flags
= CLK_DIVIDER_POWER_OF_TWO
,
343 .hw
.init
= &(struct clk_init_data
){
344 .name
= "hdmi_pll_od2",
345 .ops
= &clk_regmap_divider_ro_ops
,
346 .parent_hws
= (const struct clk_hw
*[]) {
350 .flags
= CLK_GET_RATE_NOCACHE
| CLK_SET_RATE_PARENT
,
354 static struct clk_regmap gxl_hdmi_pll
= {
355 .data
= &(struct clk_regmap_div_data
){
356 .offset
= HHI_HDMI_PLL_CNTL
+ 8,
359 .flags
= CLK_DIVIDER_POWER_OF_TWO
,
361 .hw
.init
= &(struct clk_init_data
){
363 .ops
= &clk_regmap_divider_ro_ops
,
364 .parent_hws
= (const struct clk_hw
*[]) {
368 .flags
= CLK_GET_RATE_NOCACHE
| CLK_SET_RATE_PARENT
,
372 static struct clk_regmap gxbb_sys_pll_dco
= {
373 .data
= &(struct meson_clk_pll_data
){
375 .reg_off
= HHI_SYS_PLL_CNTL
,
380 .reg_off
= HHI_SYS_PLL_CNTL
,
385 .reg_off
= HHI_SYS_PLL_CNTL
,
390 .reg_off
= HHI_SYS_PLL_CNTL
,
395 .reg_off
= HHI_SYS_PLL_CNTL
,
400 .hw
.init
= &(struct clk_init_data
){
401 .name
= "sys_pll_dco",
402 .ops
= &meson_clk_pll_ro_ops
,
403 .parent_data
= &(const struct clk_parent_data
) {
410 static struct clk_regmap gxbb_sys_pll
= {
411 .data
= &(struct clk_regmap_div_data
){
412 .offset
= HHI_SYS_PLL_CNTL
,
415 .flags
= CLK_DIVIDER_POWER_OF_TWO
,
417 .hw
.init
= &(struct clk_init_data
){
419 .ops
= &clk_regmap_divider_ro_ops
,
420 .parent_hws
= (const struct clk_hw
*[]) {
424 .flags
= CLK_SET_RATE_PARENT
,
428 static const struct reg_sequence gxbb_gp0_init_regs
[] = {
429 { .reg
= HHI_GP0_PLL_CNTL2
, .def
= 0x69c80000 },
430 { .reg
= HHI_GP0_PLL_CNTL3
, .def
= 0x0a5590c4 },
431 { .reg
= HHI_GP0_PLL_CNTL4
, .def
= 0x0000500d },
434 static struct clk_regmap gxbb_gp0_pll_dco
= {
435 .data
= &(struct meson_clk_pll_data
){
437 .reg_off
= HHI_GP0_PLL_CNTL
,
442 .reg_off
= HHI_GP0_PLL_CNTL
,
447 .reg_off
= HHI_GP0_PLL_CNTL
,
452 .reg_off
= HHI_GP0_PLL_CNTL
,
457 .reg_off
= HHI_GP0_PLL_CNTL
,
461 .table
= gxbb_gp0_pll_params_table
,
462 .init_regs
= gxbb_gp0_init_regs
,
463 .init_count
= ARRAY_SIZE(gxbb_gp0_init_regs
),
465 .hw
.init
= &(struct clk_init_data
){
466 .name
= "gp0_pll_dco",
467 .ops
= &meson_clk_pll_ops
,
468 .parent_data
= &(const struct clk_parent_data
) {
475 static const struct reg_sequence gxl_gp0_init_regs
[] = {
476 { .reg
= HHI_GP0_PLL_CNTL1
, .def
= 0xc084b000 },
477 { .reg
= HHI_GP0_PLL_CNTL2
, .def
= 0xb75020be },
478 { .reg
= HHI_GP0_PLL_CNTL3
, .def
= 0x0a59a288 },
479 { .reg
= HHI_GP0_PLL_CNTL4
, .def
= 0xc000004d },
480 { .reg
= HHI_GP0_PLL_CNTL5
, .def
= 0x00078000 },
483 static struct clk_regmap gxl_gp0_pll_dco
= {
484 .data
= &(struct meson_clk_pll_data
){
486 .reg_off
= HHI_GP0_PLL_CNTL
,
491 .reg_off
= HHI_GP0_PLL_CNTL
,
496 .reg_off
= HHI_GP0_PLL_CNTL
,
501 .reg_off
= HHI_GP0_PLL_CNTL1
,
506 .reg_off
= HHI_GP0_PLL_CNTL
,
511 .reg_off
= HHI_GP0_PLL_CNTL
,
515 .table
= gxl_gp0_pll_params_table
,
516 .init_regs
= gxl_gp0_init_regs
,
517 .init_count
= ARRAY_SIZE(gxl_gp0_init_regs
),
519 .hw
.init
= &(struct clk_init_data
){
520 .name
= "gp0_pll_dco",
521 .ops
= &meson_clk_pll_ops
,
522 .parent_data
= &(const struct clk_parent_data
) {
529 static struct clk_regmap gxbb_gp0_pll
= {
530 .data
= &(struct clk_regmap_div_data
){
531 .offset
= HHI_GP0_PLL_CNTL
,
534 .flags
= CLK_DIVIDER_POWER_OF_TWO
,
536 .hw
.init
= &(struct clk_init_data
){
538 .ops
= &clk_regmap_divider_ops
,
539 .parent_data
= &(const struct clk_parent_data
) {
542 * GXL and GXBB have different gp0_pll_dco (with
543 * different struct clk_hw). We fallback to the global
544 * naming string mechanism so gp0_pll picks up the
547 .name
= "gp0_pll_dco",
551 .flags
= CLK_SET_RATE_PARENT
,
555 static struct clk_fixed_factor gxbb_fclk_div2_div
= {
558 .hw
.init
= &(struct clk_init_data
){
559 .name
= "fclk_div2_div",
560 .ops
= &clk_fixed_factor_ops
,
561 .parent_hws
= (const struct clk_hw
*[]) {
568 static struct clk_regmap gxbb_fclk_div2
= {
569 .data
= &(struct clk_regmap_gate_data
){
570 .offset
= HHI_MPLL_CNTL6
,
573 .hw
.init
= &(struct clk_init_data
){
575 .ops
= &clk_regmap_gate_ops
,
576 .parent_hws
= (const struct clk_hw
*[]) {
577 &gxbb_fclk_div2_div
.hw
580 .flags
= CLK_IS_CRITICAL
,
584 static struct clk_fixed_factor gxbb_fclk_div3_div
= {
587 .hw
.init
= &(struct clk_init_data
){
588 .name
= "fclk_div3_div",
589 .ops
= &clk_fixed_factor_ops
,
590 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_fixed_pll
.hw
},
595 static struct clk_regmap gxbb_fclk_div3
= {
596 .data
= &(struct clk_regmap_gate_data
){
597 .offset
= HHI_MPLL_CNTL6
,
600 .hw
.init
= &(struct clk_init_data
){
602 .ops
= &clk_regmap_gate_ops
,
603 .parent_hws
= (const struct clk_hw
*[]) {
604 &gxbb_fclk_div3_div
.hw
609 * This clock, as fdiv2, is used by the SCPI FW and is required
610 * by the platform to operate correctly.
611 * Until the following condition are met, we need this clock to
612 * be marked as critical:
613 * a) The SCPI generic driver claims and enable all the clocks
615 * b) CCF has a clock hand-off mechanism to make the sure the
616 * clock stays on until the proper driver comes along
618 .flags
= CLK_IS_CRITICAL
,
622 static struct clk_fixed_factor gxbb_fclk_div4_div
= {
625 .hw
.init
= &(struct clk_init_data
){
626 .name
= "fclk_div4_div",
627 .ops
= &clk_fixed_factor_ops
,
628 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_fixed_pll
.hw
},
633 static struct clk_regmap gxbb_fclk_div4
= {
634 .data
= &(struct clk_regmap_gate_data
){
635 .offset
= HHI_MPLL_CNTL6
,
638 .hw
.init
= &(struct clk_init_data
){
640 .ops
= &clk_regmap_gate_ops
,
641 .parent_hws
= (const struct clk_hw
*[]) {
642 &gxbb_fclk_div4_div
.hw
648 static struct clk_fixed_factor gxbb_fclk_div5_div
= {
651 .hw
.init
= &(struct clk_init_data
){
652 .name
= "fclk_div5_div",
653 .ops
= &clk_fixed_factor_ops
,
654 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_fixed_pll
.hw
},
659 static struct clk_regmap gxbb_fclk_div5
= {
660 .data
= &(struct clk_regmap_gate_data
){
661 .offset
= HHI_MPLL_CNTL6
,
664 .hw
.init
= &(struct clk_init_data
){
666 .ops
= &clk_regmap_gate_ops
,
667 .parent_hws
= (const struct clk_hw
*[]) {
668 &gxbb_fclk_div5_div
.hw
674 static struct clk_fixed_factor gxbb_fclk_div7_div
= {
677 .hw
.init
= &(struct clk_init_data
){
678 .name
= "fclk_div7_div",
679 .ops
= &clk_fixed_factor_ops
,
680 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_fixed_pll
.hw
},
685 static struct clk_regmap gxbb_fclk_div7
= {
686 .data
= &(struct clk_regmap_gate_data
){
687 .offset
= HHI_MPLL_CNTL6
,
690 .hw
.init
= &(struct clk_init_data
){
692 .ops
= &clk_regmap_gate_ops
,
693 .parent_hws
= (const struct clk_hw
*[]) {
694 &gxbb_fclk_div7_div
.hw
700 static struct clk_regmap gxbb_mpll_prediv
= {
701 .data
= &(struct clk_regmap_div_data
){
702 .offset
= HHI_MPLL_CNTL5
,
706 .hw
.init
= &(struct clk_init_data
){
707 .name
= "mpll_prediv",
708 .ops
= &clk_regmap_divider_ro_ops
,
709 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_fixed_pll
.hw
},
714 static struct clk_regmap gxbb_mpll0_div
= {
715 .data
= &(struct meson_clk_mpll_data
){
717 .reg_off
= HHI_MPLL_CNTL7
,
722 .reg_off
= HHI_MPLL_CNTL7
,
727 .reg_off
= HHI_MPLL_CNTL7
,
731 .lock
= &meson_clk_lock
,
733 .hw
.init
= &(struct clk_init_data
){
735 .ops
= &meson_clk_mpll_ops
,
736 .parent_hws
= (const struct clk_hw
*[]) {
743 static struct clk_regmap gxbb_mpll0
= {
744 .data
= &(struct clk_regmap_gate_data
){
745 .offset
= HHI_MPLL_CNTL7
,
748 .hw
.init
= &(struct clk_init_data
){
750 .ops
= &clk_regmap_gate_ops
,
751 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_mpll0_div
.hw
},
753 .flags
= CLK_SET_RATE_PARENT
,
757 static struct clk_regmap gxbb_mpll1_div
= {
758 .data
= &(struct meson_clk_mpll_data
){
760 .reg_off
= HHI_MPLL_CNTL8
,
765 .reg_off
= HHI_MPLL_CNTL8
,
770 .reg_off
= HHI_MPLL_CNTL8
,
774 .lock
= &meson_clk_lock
,
776 .hw
.init
= &(struct clk_init_data
){
778 .ops
= &meson_clk_mpll_ops
,
779 .parent_hws
= (const struct clk_hw
*[]) {
786 static struct clk_regmap gxbb_mpll1
= {
787 .data
= &(struct clk_regmap_gate_data
){
788 .offset
= HHI_MPLL_CNTL8
,
791 .hw
.init
= &(struct clk_init_data
){
793 .ops
= &clk_regmap_gate_ops
,
794 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_mpll1_div
.hw
},
796 .flags
= CLK_SET_RATE_PARENT
,
800 static struct clk_regmap gxbb_mpll2_div
= {
801 .data
= &(struct meson_clk_mpll_data
){
803 .reg_off
= HHI_MPLL_CNTL9
,
808 .reg_off
= HHI_MPLL_CNTL9
,
813 .reg_off
= HHI_MPLL_CNTL9
,
817 .lock
= &meson_clk_lock
,
819 .hw
.init
= &(struct clk_init_data
){
821 .ops
= &meson_clk_mpll_ops
,
822 .parent_hws
= (const struct clk_hw
*[]) {
829 static struct clk_regmap gxbb_mpll2
= {
830 .data
= &(struct clk_regmap_gate_data
){
831 .offset
= HHI_MPLL_CNTL9
,
834 .hw
.init
= &(struct clk_init_data
){
836 .ops
= &clk_regmap_gate_ops
,
837 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_mpll2_div
.hw
},
839 .flags
= CLK_SET_RATE_PARENT
,
843 static u32 mux_table_clk81
[] = { 0, 2, 3, 4, 5, 6, 7 };
844 static const struct clk_parent_data clk81_parent_data
[] = {
845 { .fw_name
= "xtal", },
846 { .hw
= &gxbb_fclk_div7
.hw
},
847 { .hw
= &gxbb_mpll1
.hw
},
848 { .hw
= &gxbb_mpll2
.hw
},
849 { .hw
= &gxbb_fclk_div4
.hw
},
850 { .hw
= &gxbb_fclk_div3
.hw
},
851 { .hw
= &gxbb_fclk_div5
.hw
},
854 static struct clk_regmap gxbb_mpeg_clk_sel
= {
855 .data
= &(struct clk_regmap_mux_data
){
856 .offset
= HHI_MPEG_CLK_CNTL
,
859 .table
= mux_table_clk81
,
861 .hw
.init
= &(struct clk_init_data
){
862 .name
= "mpeg_clk_sel",
863 .ops
= &clk_regmap_mux_ro_ops
,
865 * bits 14:12 selects from 8 possible parents:
866 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
867 * fclk_div4, fclk_div3, fclk_div5
869 .parent_data
= clk81_parent_data
,
870 .num_parents
= ARRAY_SIZE(clk81_parent_data
),
874 static struct clk_regmap gxbb_mpeg_clk_div
= {
875 .data
= &(struct clk_regmap_div_data
){
876 .offset
= HHI_MPEG_CLK_CNTL
,
880 .hw
.init
= &(struct clk_init_data
){
881 .name
= "mpeg_clk_div",
882 .ops
= &clk_regmap_divider_ro_ops
,
883 .parent_hws
= (const struct clk_hw
*[]) {
884 &gxbb_mpeg_clk_sel
.hw
890 /* the mother of dragons gates */
891 static struct clk_regmap gxbb_clk81
= {
892 .data
= &(struct clk_regmap_gate_data
){
893 .offset
= HHI_MPEG_CLK_CNTL
,
896 .hw
.init
= &(struct clk_init_data
){
898 .ops
= &clk_regmap_gate_ops
,
899 .parent_hws
= (const struct clk_hw
*[]) {
900 &gxbb_mpeg_clk_div
.hw
903 .flags
= CLK_IS_CRITICAL
,
907 static struct clk_regmap gxbb_sar_adc_clk_sel
= {
908 .data
= &(struct clk_regmap_mux_data
){
909 .offset
= HHI_SAR_CLK_CNTL
,
913 .hw
.init
= &(struct clk_init_data
){
914 .name
= "sar_adc_clk_sel",
915 .ops
= &clk_regmap_mux_ops
,
916 /* NOTE: The datasheet doesn't list the parents for bit 10 */
917 .parent_data
= (const struct clk_parent_data
[]) {
918 { .fw_name
= "xtal", },
919 { .hw
= &gxbb_clk81
.hw
},
925 static struct clk_regmap gxbb_sar_adc_clk_div
= {
926 .data
= &(struct clk_regmap_div_data
){
927 .offset
= HHI_SAR_CLK_CNTL
,
931 .hw
.init
= &(struct clk_init_data
){
932 .name
= "sar_adc_clk_div",
933 .ops
= &clk_regmap_divider_ops
,
934 .parent_hws
= (const struct clk_hw
*[]) {
935 &gxbb_sar_adc_clk_sel
.hw
938 .flags
= CLK_SET_RATE_PARENT
,
942 static struct clk_regmap gxbb_sar_adc_clk
= {
943 .data
= &(struct clk_regmap_gate_data
){
944 .offset
= HHI_SAR_CLK_CNTL
,
947 .hw
.init
= &(struct clk_init_data
){
948 .name
= "sar_adc_clk",
949 .ops
= &clk_regmap_gate_ops
,
950 .parent_hws
= (const struct clk_hw
*[]) {
951 &gxbb_sar_adc_clk_div
.hw
954 .flags
= CLK_SET_RATE_PARENT
,
959 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
960 * muxed by a glitch-free switch.
963 static const struct clk_parent_data gxbb_mali_0_1_parent_data
[] = {
964 { .fw_name
= "xtal", },
965 { .hw
= &gxbb_gp0_pll
.hw
},
966 { .hw
= &gxbb_mpll2
.hw
},
967 { .hw
= &gxbb_mpll1
.hw
},
968 { .hw
= &gxbb_fclk_div7
.hw
},
969 { .hw
= &gxbb_fclk_div4
.hw
},
970 { .hw
= &gxbb_fclk_div3
.hw
},
971 { .hw
= &gxbb_fclk_div5
.hw
},
974 static struct clk_regmap gxbb_mali_0_sel
= {
975 .data
= &(struct clk_regmap_mux_data
){
976 .offset
= HHI_MALI_CLK_CNTL
,
980 .hw
.init
= &(struct clk_init_data
){
981 .name
= "mali_0_sel",
982 .ops
= &clk_regmap_mux_ops
,
984 * bits 10:9 selects from 8 possible parents:
985 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
986 * fclk_div4, fclk_div3, fclk_div5
988 .parent_data
= gxbb_mali_0_1_parent_data
,
990 .flags
= CLK_SET_RATE_NO_REPARENT
,
994 static struct clk_regmap gxbb_mali_0_div
= {
995 .data
= &(struct clk_regmap_div_data
){
996 .offset
= HHI_MALI_CLK_CNTL
,
1000 .hw
.init
= &(struct clk_init_data
){
1001 .name
= "mali_0_div",
1002 .ops
= &clk_regmap_divider_ops
,
1003 .parent_hws
= (const struct clk_hw
*[]) {
1007 .flags
= CLK_SET_RATE_NO_REPARENT
,
1011 static struct clk_regmap gxbb_mali_0
= {
1012 .data
= &(struct clk_regmap_gate_data
){
1013 .offset
= HHI_MALI_CLK_CNTL
,
1016 .hw
.init
= &(struct clk_init_data
){
1018 .ops
= &clk_regmap_gate_ops
,
1019 .parent_hws
= (const struct clk_hw
*[]) {
1023 .flags
= CLK_SET_RATE_PARENT
,
1027 static struct clk_regmap gxbb_mali_1_sel
= {
1028 .data
= &(struct clk_regmap_mux_data
){
1029 .offset
= HHI_MALI_CLK_CNTL
,
1033 .hw
.init
= &(struct clk_init_data
){
1034 .name
= "mali_1_sel",
1035 .ops
= &clk_regmap_mux_ops
,
1037 * bits 10:9 selects from 8 possible parents:
1038 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
1039 * fclk_div4, fclk_div3, fclk_div5
1041 .parent_data
= gxbb_mali_0_1_parent_data
,
1043 .flags
= CLK_SET_RATE_NO_REPARENT
,
1047 static struct clk_regmap gxbb_mali_1_div
= {
1048 .data
= &(struct clk_regmap_div_data
){
1049 .offset
= HHI_MALI_CLK_CNTL
,
1053 .hw
.init
= &(struct clk_init_data
){
1054 .name
= "mali_1_div",
1055 .ops
= &clk_regmap_divider_ops
,
1056 .parent_hws
= (const struct clk_hw
*[]) {
1060 .flags
= CLK_SET_RATE_NO_REPARENT
,
1064 static struct clk_regmap gxbb_mali_1
= {
1065 .data
= &(struct clk_regmap_gate_data
){
1066 .offset
= HHI_MALI_CLK_CNTL
,
1069 .hw
.init
= &(struct clk_init_data
){
1071 .ops
= &clk_regmap_gate_ops
,
1072 .parent_hws
= (const struct clk_hw
*[]) {
1076 .flags
= CLK_SET_RATE_PARENT
,
1080 static const struct clk_hw
*gxbb_mali_parent_hws
[] = {
1085 static struct clk_regmap gxbb_mali
= {
1086 .data
= &(struct clk_regmap_mux_data
){
1087 .offset
= HHI_MALI_CLK_CNTL
,
1091 .hw
.init
= &(struct clk_init_data
){
1093 .ops
= &clk_regmap_mux_ops
,
1094 .parent_hws
= gxbb_mali_parent_hws
,
1096 .flags
= CLK_SET_RATE_NO_REPARENT
,
1100 static struct clk_regmap gxbb_cts_amclk_sel
= {
1101 .data
= &(struct clk_regmap_mux_data
){
1102 .offset
= HHI_AUD_CLK_CNTL
,
1105 .table
= (u32
[]){ 1, 2, 3 },
1106 .flags
= CLK_MUX_ROUND_CLOSEST
,
1108 .hw
.init
= &(struct clk_init_data
){
1109 .name
= "cts_amclk_sel",
1110 .ops
= &clk_regmap_mux_ops
,
1111 .parent_hws
= (const struct clk_hw
*[]) {
1120 static struct clk_regmap gxbb_cts_amclk_div
= {
1121 .data
= &(struct clk_regmap_div_data
) {
1122 .offset
= HHI_AUD_CLK_CNTL
,
1125 .flags
= CLK_DIVIDER_ROUND_CLOSEST
,
1127 .hw
.init
= &(struct clk_init_data
){
1128 .name
= "cts_amclk_div",
1129 .ops
= &clk_regmap_divider_ops
,
1130 .parent_hws
= (const struct clk_hw
*[]) {
1131 &gxbb_cts_amclk_sel
.hw
1134 .flags
= CLK_SET_RATE_PARENT
,
1138 static struct clk_regmap gxbb_cts_amclk
= {
1139 .data
= &(struct clk_regmap_gate_data
){
1140 .offset
= HHI_AUD_CLK_CNTL
,
1143 .hw
.init
= &(struct clk_init_data
){
1144 .name
= "cts_amclk",
1145 .ops
= &clk_regmap_gate_ops
,
1146 .parent_hws
= (const struct clk_hw
*[]) {
1147 &gxbb_cts_amclk_div
.hw
1150 .flags
= CLK_SET_RATE_PARENT
,
1154 static struct clk_regmap gxbb_cts_mclk_i958_sel
= {
1155 .data
= &(struct clk_regmap_mux_data
){
1156 .offset
= HHI_AUD_CLK_CNTL2
,
1159 .table
= (u32
[]){ 1, 2, 3 },
1160 .flags
= CLK_MUX_ROUND_CLOSEST
,
1162 .hw
.init
= &(struct clk_init_data
) {
1163 .name
= "cts_mclk_i958_sel",
1164 .ops
= &clk_regmap_mux_ops
,
1165 .parent_hws
= (const struct clk_hw
*[]) {
1174 static struct clk_regmap gxbb_cts_mclk_i958_div
= {
1175 .data
= &(struct clk_regmap_div_data
){
1176 .offset
= HHI_AUD_CLK_CNTL2
,
1179 .flags
= CLK_DIVIDER_ROUND_CLOSEST
,
1181 .hw
.init
= &(struct clk_init_data
) {
1182 .name
= "cts_mclk_i958_div",
1183 .ops
= &clk_regmap_divider_ops
,
1184 .parent_hws
= (const struct clk_hw
*[]) {
1185 &gxbb_cts_mclk_i958_sel
.hw
1188 .flags
= CLK_SET_RATE_PARENT
,
1192 static struct clk_regmap gxbb_cts_mclk_i958
= {
1193 .data
= &(struct clk_regmap_gate_data
){
1194 .offset
= HHI_AUD_CLK_CNTL2
,
1197 .hw
.init
= &(struct clk_init_data
){
1198 .name
= "cts_mclk_i958",
1199 .ops
= &clk_regmap_gate_ops
,
1200 .parent_hws
= (const struct clk_hw
*[]) {
1201 &gxbb_cts_mclk_i958_div
.hw
1204 .flags
= CLK_SET_RATE_PARENT
,
1208 static struct clk_regmap gxbb_cts_i958
= {
1209 .data
= &(struct clk_regmap_mux_data
){
1210 .offset
= HHI_AUD_CLK_CNTL2
,
1214 .hw
.init
= &(struct clk_init_data
){
1216 .ops
= &clk_regmap_mux_ops
,
1217 .parent_hws
= (const struct clk_hw
*[]) {
1219 &gxbb_cts_mclk_i958
.hw
1223 *The parent is specific to origin of the audio data. Let the
1224 * consumer choose the appropriate parent
1226 .flags
= CLK_SET_RATE_PARENT
| CLK_SET_RATE_NO_REPARENT
,
1230 static const struct clk_parent_data gxbb_32k_clk_parent_data
[] = {
1231 { .fw_name
= "xtal", },
1233 * FIXME: This clock is provided by the ao clock controller but the
1234 * clock is not yet part of the binding of this controller, so string
1235 * name must be use to set this parent.
1237 { .name
= "cts_slow_oscin", .index
= -1 },
1238 { .hw
= &gxbb_fclk_div3
.hw
},
1239 { .hw
= &gxbb_fclk_div5
.hw
},
1242 static struct clk_regmap gxbb_32k_clk_sel
= {
1243 .data
= &(struct clk_regmap_mux_data
){
1244 .offset
= HHI_32K_CLK_CNTL
,
1248 .hw
.init
= &(struct clk_init_data
){
1249 .name
= "32k_clk_sel",
1250 .ops
= &clk_regmap_mux_ops
,
1251 .parent_data
= gxbb_32k_clk_parent_data
,
1253 .flags
= CLK_SET_RATE_PARENT
,
1257 static struct clk_regmap gxbb_32k_clk_div
= {
1258 .data
= &(struct clk_regmap_div_data
){
1259 .offset
= HHI_32K_CLK_CNTL
,
1263 .hw
.init
= &(struct clk_init_data
){
1264 .name
= "32k_clk_div",
1265 .ops
= &clk_regmap_divider_ops
,
1266 .parent_hws
= (const struct clk_hw
*[]) {
1267 &gxbb_32k_clk_sel
.hw
1270 .flags
= CLK_SET_RATE_PARENT
| CLK_DIVIDER_ROUND_CLOSEST
,
1274 static struct clk_regmap gxbb_32k_clk
= {
1275 .data
= &(struct clk_regmap_gate_data
){
1276 .offset
= HHI_32K_CLK_CNTL
,
1279 .hw
.init
= &(struct clk_init_data
){
1281 .ops
= &clk_regmap_gate_ops
,
1282 .parent_hws
= (const struct clk_hw
*[]) {
1283 &gxbb_32k_clk_div
.hw
1286 .flags
= CLK_SET_RATE_PARENT
,
1290 static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data
[] = {
1291 { .fw_name
= "xtal", },
1292 { .hw
= &gxbb_fclk_div2
.hw
},
1293 { .hw
= &gxbb_fclk_div3
.hw
},
1294 { .hw
= &gxbb_fclk_div5
.hw
},
1295 { .hw
= &gxbb_fclk_div7
.hw
},
1297 * Following these parent clocks, we should also have had mpll2, mpll3
1298 * and gp0_pll but these clocks are too precious to be used here. All
1299 * the necessary rates for MMC and NAND operation can be acheived using
1300 * xtal or fclk_div clocks
1305 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel
= {
1306 .data
= &(struct clk_regmap_mux_data
){
1307 .offset
= HHI_SD_EMMC_CLK_CNTL
,
1311 .hw
.init
= &(struct clk_init_data
) {
1312 .name
= "sd_emmc_a_clk0_sel",
1313 .ops
= &clk_regmap_mux_ops
,
1314 .parent_data
= gxbb_sd_emmc_clk0_parent_data
,
1315 .num_parents
= ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data
),
1316 .flags
= CLK_SET_RATE_PARENT
,
1320 static struct clk_regmap gxbb_sd_emmc_a_clk0_div
= {
1321 .data
= &(struct clk_regmap_div_data
){
1322 .offset
= HHI_SD_EMMC_CLK_CNTL
,
1325 .flags
= CLK_DIVIDER_ROUND_CLOSEST
,
1327 .hw
.init
= &(struct clk_init_data
) {
1328 .name
= "sd_emmc_a_clk0_div",
1329 .ops
= &clk_regmap_divider_ops
,
1330 .parent_hws
= (const struct clk_hw
*[]) {
1331 &gxbb_sd_emmc_a_clk0_sel
.hw
1334 .flags
= CLK_SET_RATE_PARENT
,
1338 static struct clk_regmap gxbb_sd_emmc_a_clk0
= {
1339 .data
= &(struct clk_regmap_gate_data
){
1340 .offset
= HHI_SD_EMMC_CLK_CNTL
,
1343 .hw
.init
= &(struct clk_init_data
){
1344 .name
= "sd_emmc_a_clk0",
1345 .ops
= &clk_regmap_gate_ops
,
1346 .parent_hws
= (const struct clk_hw
*[]) {
1347 &gxbb_sd_emmc_a_clk0_div
.hw
1350 .flags
= CLK_SET_RATE_PARENT
,
1355 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel
= {
1356 .data
= &(struct clk_regmap_mux_data
){
1357 .offset
= HHI_SD_EMMC_CLK_CNTL
,
1361 .hw
.init
= &(struct clk_init_data
) {
1362 .name
= "sd_emmc_b_clk0_sel",
1363 .ops
= &clk_regmap_mux_ops
,
1364 .parent_data
= gxbb_sd_emmc_clk0_parent_data
,
1365 .num_parents
= ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data
),
1366 .flags
= CLK_SET_RATE_PARENT
,
1370 static struct clk_regmap gxbb_sd_emmc_b_clk0_div
= {
1371 .data
= &(struct clk_regmap_div_data
){
1372 .offset
= HHI_SD_EMMC_CLK_CNTL
,
1375 .flags
= CLK_DIVIDER_ROUND_CLOSEST
,
1377 .hw
.init
= &(struct clk_init_data
) {
1378 .name
= "sd_emmc_b_clk0_div",
1379 .ops
= &clk_regmap_divider_ops
,
1380 .parent_hws
= (const struct clk_hw
*[]) {
1381 &gxbb_sd_emmc_b_clk0_sel
.hw
1384 .flags
= CLK_SET_RATE_PARENT
,
1388 static struct clk_regmap gxbb_sd_emmc_b_clk0
= {
1389 .data
= &(struct clk_regmap_gate_data
){
1390 .offset
= HHI_SD_EMMC_CLK_CNTL
,
1393 .hw
.init
= &(struct clk_init_data
){
1394 .name
= "sd_emmc_b_clk0",
1395 .ops
= &clk_regmap_gate_ops
,
1396 .parent_hws
= (const struct clk_hw
*[]) {
1397 &gxbb_sd_emmc_b_clk0_div
.hw
1400 .flags
= CLK_SET_RATE_PARENT
,
1404 /* EMMC/NAND clock */
1405 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel
= {
1406 .data
= &(struct clk_regmap_mux_data
){
1407 .offset
= HHI_NAND_CLK_CNTL
,
1411 .hw
.init
= &(struct clk_init_data
) {
1412 .name
= "sd_emmc_c_clk0_sel",
1413 .ops
= &clk_regmap_mux_ops
,
1414 .parent_data
= gxbb_sd_emmc_clk0_parent_data
,
1415 .num_parents
= ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data
),
1416 .flags
= CLK_SET_RATE_PARENT
,
1420 static struct clk_regmap gxbb_sd_emmc_c_clk0_div
= {
1421 .data
= &(struct clk_regmap_div_data
){
1422 .offset
= HHI_NAND_CLK_CNTL
,
1425 .flags
= CLK_DIVIDER_ROUND_CLOSEST
,
1427 .hw
.init
= &(struct clk_init_data
) {
1428 .name
= "sd_emmc_c_clk0_div",
1429 .ops
= &clk_regmap_divider_ops
,
1430 .parent_hws
= (const struct clk_hw
*[]) {
1431 &gxbb_sd_emmc_c_clk0_sel
.hw
1434 .flags
= CLK_SET_RATE_PARENT
,
1438 static struct clk_regmap gxbb_sd_emmc_c_clk0
= {
1439 .data
= &(struct clk_regmap_gate_data
){
1440 .offset
= HHI_NAND_CLK_CNTL
,
1443 .hw
.init
= &(struct clk_init_data
){
1444 .name
= "sd_emmc_c_clk0",
1445 .ops
= &clk_regmap_gate_ops
,
1446 .parent_hws
= (const struct clk_hw
*[]) {
1447 &gxbb_sd_emmc_c_clk0_div
.hw
1450 .flags
= CLK_SET_RATE_PARENT
,
1456 static const struct clk_hw
*gxbb_vpu_parent_hws
[] = {
1463 static struct clk_regmap gxbb_vpu_0_sel
= {
1464 .data
= &(struct clk_regmap_mux_data
){
1465 .offset
= HHI_VPU_CLK_CNTL
,
1469 .hw
.init
= &(struct clk_init_data
){
1470 .name
= "vpu_0_sel",
1471 .ops
= &clk_regmap_mux_ops
,
1473 * bits 9:10 selects from 4 possible parents:
1474 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1476 .parent_hws
= gxbb_vpu_parent_hws
,
1477 .num_parents
= ARRAY_SIZE(gxbb_vpu_parent_hws
),
1478 .flags
= CLK_SET_RATE_NO_REPARENT
,
1482 static struct clk_regmap gxbb_vpu_0_div
= {
1483 .data
= &(struct clk_regmap_div_data
){
1484 .offset
= HHI_VPU_CLK_CNTL
,
1488 .hw
.init
= &(struct clk_init_data
){
1489 .name
= "vpu_0_div",
1490 .ops
= &clk_regmap_divider_ops
,
1491 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vpu_0_sel
.hw
},
1493 .flags
= CLK_SET_RATE_PARENT
,
1497 static struct clk_regmap gxbb_vpu_0
= {
1498 .data
= &(struct clk_regmap_gate_data
){
1499 .offset
= HHI_VPU_CLK_CNTL
,
1502 .hw
.init
= &(struct clk_init_data
) {
1504 .ops
= &clk_regmap_gate_ops
,
1505 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vpu_0_div
.hw
},
1507 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1511 static struct clk_regmap gxbb_vpu_1_sel
= {
1512 .data
= &(struct clk_regmap_mux_data
){
1513 .offset
= HHI_VPU_CLK_CNTL
,
1517 .hw
.init
= &(struct clk_init_data
){
1518 .name
= "vpu_1_sel",
1519 .ops
= &clk_regmap_mux_ops
,
1521 * bits 25:26 selects from 4 possible parents:
1522 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1524 .parent_hws
= gxbb_vpu_parent_hws
,
1525 .num_parents
= ARRAY_SIZE(gxbb_vpu_parent_hws
),
1526 .flags
= CLK_SET_RATE_NO_REPARENT
,
1530 static struct clk_regmap gxbb_vpu_1_div
= {
1531 .data
= &(struct clk_regmap_div_data
){
1532 .offset
= HHI_VPU_CLK_CNTL
,
1536 .hw
.init
= &(struct clk_init_data
){
1537 .name
= "vpu_1_div",
1538 .ops
= &clk_regmap_divider_ops
,
1539 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vpu_1_sel
.hw
},
1541 .flags
= CLK_SET_RATE_PARENT
,
1545 static struct clk_regmap gxbb_vpu_1
= {
1546 .data
= &(struct clk_regmap_gate_data
){
1547 .offset
= HHI_VPU_CLK_CNTL
,
1550 .hw
.init
= &(struct clk_init_data
) {
1552 .ops
= &clk_regmap_gate_ops
,
1553 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vpu_1_div
.hw
},
1555 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1559 static struct clk_regmap gxbb_vpu
= {
1560 .data
= &(struct clk_regmap_mux_data
){
1561 .offset
= HHI_VPU_CLK_CNTL
,
1565 .hw
.init
= &(struct clk_init_data
){
1567 .ops
= &clk_regmap_mux_ops
,
1569 * bit 31 selects from 2 possible parents:
1572 .parent_hws
= (const struct clk_hw
*[]) {
1577 .flags
= CLK_SET_RATE_NO_REPARENT
,
1583 static const struct clk_hw
*gxbb_vapb_parent_hws
[] = {
1590 static struct clk_regmap gxbb_vapb_0_sel
= {
1591 .data
= &(struct clk_regmap_mux_data
){
1592 .offset
= HHI_VAPBCLK_CNTL
,
1596 .hw
.init
= &(struct clk_init_data
){
1597 .name
= "vapb_0_sel",
1598 .ops
= &clk_regmap_mux_ops
,
1600 * bits 9:10 selects from 4 possible parents:
1601 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1603 .parent_hws
= gxbb_vapb_parent_hws
,
1604 .num_parents
= ARRAY_SIZE(gxbb_vapb_parent_hws
),
1605 .flags
= CLK_SET_RATE_NO_REPARENT
,
1609 static struct clk_regmap gxbb_vapb_0_div
= {
1610 .data
= &(struct clk_regmap_div_data
){
1611 .offset
= HHI_VAPBCLK_CNTL
,
1615 .hw
.init
= &(struct clk_init_data
){
1616 .name
= "vapb_0_div",
1617 .ops
= &clk_regmap_divider_ops
,
1618 .parent_hws
= (const struct clk_hw
*[]) {
1622 .flags
= CLK_SET_RATE_PARENT
,
1626 static struct clk_regmap gxbb_vapb_0
= {
1627 .data
= &(struct clk_regmap_gate_data
){
1628 .offset
= HHI_VAPBCLK_CNTL
,
1631 .hw
.init
= &(struct clk_init_data
) {
1633 .ops
= &clk_regmap_gate_ops
,
1634 .parent_hws
= (const struct clk_hw
*[]) {
1638 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1642 static struct clk_regmap gxbb_vapb_1_sel
= {
1643 .data
= &(struct clk_regmap_mux_data
){
1644 .offset
= HHI_VAPBCLK_CNTL
,
1648 .hw
.init
= &(struct clk_init_data
){
1649 .name
= "vapb_1_sel",
1650 .ops
= &clk_regmap_mux_ops
,
1652 * bits 25:26 selects from 4 possible parents:
1653 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1655 .parent_hws
= gxbb_vapb_parent_hws
,
1656 .num_parents
= ARRAY_SIZE(gxbb_vapb_parent_hws
),
1657 .flags
= CLK_SET_RATE_NO_REPARENT
,
1661 static struct clk_regmap gxbb_vapb_1_div
= {
1662 .data
= &(struct clk_regmap_div_data
){
1663 .offset
= HHI_VAPBCLK_CNTL
,
1667 .hw
.init
= &(struct clk_init_data
){
1668 .name
= "vapb_1_div",
1669 .ops
= &clk_regmap_divider_ops
,
1670 .parent_hws
= (const struct clk_hw
*[]) {
1674 .flags
= CLK_SET_RATE_PARENT
,
1678 static struct clk_regmap gxbb_vapb_1
= {
1679 .data
= &(struct clk_regmap_gate_data
){
1680 .offset
= HHI_VAPBCLK_CNTL
,
1683 .hw
.init
= &(struct clk_init_data
) {
1685 .ops
= &clk_regmap_gate_ops
,
1686 .parent_hws
= (const struct clk_hw
*[]) {
1690 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1694 static struct clk_regmap gxbb_vapb_sel
= {
1695 .data
= &(struct clk_regmap_mux_data
){
1696 .offset
= HHI_VAPBCLK_CNTL
,
1700 .hw
.init
= &(struct clk_init_data
){
1702 .ops
= &clk_regmap_mux_ops
,
1704 * bit 31 selects from 2 possible parents:
1707 .parent_hws
= (const struct clk_hw
*[]) {
1712 .flags
= CLK_SET_RATE_NO_REPARENT
,
1716 static struct clk_regmap gxbb_vapb
= {
1717 .data
= &(struct clk_regmap_gate_data
){
1718 .offset
= HHI_VAPBCLK_CNTL
,
1721 .hw
.init
= &(struct clk_init_data
) {
1723 .ops
= &clk_regmap_gate_ops
,
1724 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vapb_sel
.hw
},
1726 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1732 static struct clk_regmap gxbb_vid_pll_div
= {
1733 .data
= &(struct meson_vid_pll_div_data
){
1735 .reg_off
= HHI_VID_PLL_CLK_DIV
,
1740 .reg_off
= HHI_VID_PLL_CLK_DIV
,
1745 .hw
.init
= &(struct clk_init_data
) {
1746 .name
= "vid_pll_div",
1747 .ops
= &meson_vid_pll_div_ro_ops
,
1748 .parent_data
= &(const struct clk_parent_data
) {
1751 * GXL and GXBB have different hdmi_plls (with
1752 * different struct clk_hw). We fallback to the global
1753 * naming string mechanism so vid_pll_div picks up the
1760 .flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
,
1764 static const struct clk_parent_data gxbb_vid_pll_parent_data
[] = {
1765 { .hw
= &gxbb_vid_pll_div
.hw
},
1768 * GXL and GXBB have different hdmi_plls (with
1769 * different struct clk_hw). We fallback to the global
1770 * naming string mechanism so vid_pll_div picks up the
1773 { .name
= "hdmi_pll", .index
= -1 },
1776 static struct clk_regmap gxbb_vid_pll_sel
= {
1777 .data
= &(struct clk_regmap_mux_data
){
1778 .offset
= HHI_VID_PLL_CLK_DIV
,
1782 .hw
.init
= &(struct clk_init_data
){
1783 .name
= "vid_pll_sel",
1784 .ops
= &clk_regmap_mux_ops
,
1786 * bit 18 selects from 2 possible parents:
1787 * vid_pll_div or hdmi_pll
1789 .parent_data
= gxbb_vid_pll_parent_data
,
1790 .num_parents
= ARRAY_SIZE(gxbb_vid_pll_parent_data
),
1791 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
1795 static struct clk_regmap gxbb_vid_pll
= {
1796 .data
= &(struct clk_regmap_gate_data
){
1797 .offset
= HHI_VID_PLL_CLK_DIV
,
1800 .hw
.init
= &(struct clk_init_data
) {
1802 .ops
= &clk_regmap_gate_ops
,
1803 .parent_hws
= (const struct clk_hw
*[]) {
1804 &gxbb_vid_pll_sel
.hw
1807 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1811 static const struct clk_hw
*gxbb_vclk_parent_hws
[] = {
1821 static struct clk_regmap gxbb_vclk_sel
= {
1822 .data
= &(struct clk_regmap_mux_data
){
1823 .offset
= HHI_VID_CLK_CNTL
,
1827 .hw
.init
= &(struct clk_init_data
){
1829 .ops
= &clk_regmap_mux_ops
,
1831 * bits 16:18 selects from 8 possible parents:
1832 * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1833 * vid_pll, fclk_div7, mp1
1835 .parent_hws
= gxbb_vclk_parent_hws
,
1836 .num_parents
= ARRAY_SIZE(gxbb_vclk_parent_hws
),
1837 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
1841 static struct clk_regmap gxbb_vclk2_sel
= {
1842 .data
= &(struct clk_regmap_mux_data
){
1843 .offset
= HHI_VIID_CLK_CNTL
,
1847 .hw
.init
= &(struct clk_init_data
){
1848 .name
= "vclk2_sel",
1849 .ops
= &clk_regmap_mux_ops
,
1851 * bits 16:18 selects from 8 possible parents:
1852 * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1853 * vid_pll, fclk_div7, mp1
1855 .parent_hws
= gxbb_vclk_parent_hws
,
1856 .num_parents
= ARRAY_SIZE(gxbb_vclk_parent_hws
),
1857 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
1861 static struct clk_regmap gxbb_vclk_input
= {
1862 .data
= &(struct clk_regmap_gate_data
){
1863 .offset
= HHI_VID_CLK_DIV
,
1866 .hw
.init
= &(struct clk_init_data
) {
1867 .name
= "vclk_input",
1868 .ops
= &clk_regmap_gate_ops
,
1869 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vclk_sel
.hw
},
1871 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1875 static struct clk_regmap gxbb_vclk2_input
= {
1876 .data
= &(struct clk_regmap_gate_data
){
1877 .offset
= HHI_VIID_CLK_DIV
,
1880 .hw
.init
= &(struct clk_init_data
) {
1881 .name
= "vclk2_input",
1882 .ops
= &clk_regmap_gate_ops
,
1883 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vclk2_sel
.hw
},
1885 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1889 static struct clk_regmap gxbb_vclk_div
= {
1890 .data
= &(struct clk_regmap_div_data
){
1891 .offset
= HHI_VID_CLK_DIV
,
1895 .hw
.init
= &(struct clk_init_data
){
1897 .ops
= &clk_regmap_divider_ops
,
1898 .parent_hws
= (const struct clk_hw
*[]) {
1902 .flags
= CLK_GET_RATE_NOCACHE
,
1906 static struct clk_regmap gxbb_vclk2_div
= {
1907 .data
= &(struct clk_regmap_div_data
){
1908 .offset
= HHI_VIID_CLK_DIV
,
1912 .hw
.init
= &(struct clk_init_data
){
1913 .name
= "vclk2_div",
1914 .ops
= &clk_regmap_divider_ops
,
1915 .parent_hws
= (const struct clk_hw
*[]) {
1916 &gxbb_vclk2_input
.hw
1919 .flags
= CLK_GET_RATE_NOCACHE
,
1923 static struct clk_regmap gxbb_vclk
= {
1924 .data
= &(struct clk_regmap_gate_data
){
1925 .offset
= HHI_VID_CLK_CNTL
,
1928 .hw
.init
= &(struct clk_init_data
) {
1930 .ops
= &clk_regmap_gate_ops
,
1931 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vclk_div
.hw
},
1933 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1937 static struct clk_regmap gxbb_vclk2
= {
1938 .data
= &(struct clk_regmap_gate_data
){
1939 .offset
= HHI_VIID_CLK_CNTL
,
1942 .hw
.init
= &(struct clk_init_data
) {
1944 .ops
= &clk_regmap_gate_ops
,
1945 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vclk2_div
.hw
},
1947 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1951 static struct clk_regmap gxbb_vclk_div1
= {
1952 .data
= &(struct clk_regmap_gate_data
){
1953 .offset
= HHI_VID_CLK_CNTL
,
1956 .hw
.init
= &(struct clk_init_data
) {
1957 .name
= "vclk_div1",
1958 .ops
= &clk_regmap_gate_ops
,
1959 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vclk
.hw
},
1961 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1965 static struct clk_regmap gxbb_vclk_div2_en
= {
1966 .data
= &(struct clk_regmap_gate_data
){
1967 .offset
= HHI_VID_CLK_CNTL
,
1970 .hw
.init
= &(struct clk_init_data
) {
1971 .name
= "vclk_div2_en",
1972 .ops
= &clk_regmap_gate_ops
,
1973 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vclk
.hw
},
1975 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1979 static struct clk_regmap gxbb_vclk_div4_en
= {
1980 .data
= &(struct clk_regmap_gate_data
){
1981 .offset
= HHI_VID_CLK_CNTL
,
1984 .hw
.init
= &(struct clk_init_data
) {
1985 .name
= "vclk_div4_en",
1986 .ops
= &clk_regmap_gate_ops
,
1987 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vclk
.hw
},
1989 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
1993 static struct clk_regmap gxbb_vclk_div6_en
= {
1994 .data
= &(struct clk_regmap_gate_data
){
1995 .offset
= HHI_VID_CLK_CNTL
,
1998 .hw
.init
= &(struct clk_init_data
) {
1999 .name
= "vclk_div6_en",
2000 .ops
= &clk_regmap_gate_ops
,
2001 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vclk
.hw
},
2003 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
2007 static struct clk_regmap gxbb_vclk_div12_en
= {
2008 .data
= &(struct clk_regmap_gate_data
){
2009 .offset
= HHI_VID_CLK_CNTL
,
2012 .hw
.init
= &(struct clk_init_data
) {
2013 .name
= "vclk_div12_en",
2014 .ops
= &clk_regmap_gate_ops
,
2015 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vclk
.hw
},
2017 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
2021 static struct clk_regmap gxbb_vclk2_div1
= {
2022 .data
= &(struct clk_regmap_gate_data
){
2023 .offset
= HHI_VIID_CLK_CNTL
,
2026 .hw
.init
= &(struct clk_init_data
) {
2027 .name
= "vclk2_div1",
2028 .ops
= &clk_regmap_gate_ops
,
2029 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vclk2
.hw
},
2031 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
2035 static struct clk_regmap gxbb_vclk2_div2_en
= {
2036 .data
= &(struct clk_regmap_gate_data
){
2037 .offset
= HHI_VIID_CLK_CNTL
,
2040 .hw
.init
= &(struct clk_init_data
) {
2041 .name
= "vclk2_div2_en",
2042 .ops
= &clk_regmap_gate_ops
,
2043 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vclk2
.hw
},
2045 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
2049 static struct clk_regmap gxbb_vclk2_div4_en
= {
2050 .data
= &(struct clk_regmap_gate_data
){
2051 .offset
= HHI_VIID_CLK_CNTL
,
2054 .hw
.init
= &(struct clk_init_data
) {
2055 .name
= "vclk2_div4_en",
2056 .ops
= &clk_regmap_gate_ops
,
2057 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vclk2
.hw
},
2059 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
2063 static struct clk_regmap gxbb_vclk2_div6_en
= {
2064 .data
= &(struct clk_regmap_gate_data
){
2065 .offset
= HHI_VIID_CLK_CNTL
,
2068 .hw
.init
= &(struct clk_init_data
) {
2069 .name
= "vclk2_div6_en",
2070 .ops
= &clk_regmap_gate_ops
,
2071 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vclk2
.hw
},
2073 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
2077 static struct clk_regmap gxbb_vclk2_div12_en
= {
2078 .data
= &(struct clk_regmap_gate_data
){
2079 .offset
= HHI_VIID_CLK_CNTL
,
2082 .hw
.init
= &(struct clk_init_data
) {
2083 .name
= "vclk2_div12_en",
2084 .ops
= &clk_regmap_gate_ops
,
2085 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_vclk2
.hw
},
2087 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
2091 static struct clk_fixed_factor gxbb_vclk_div2
= {
2094 .hw
.init
= &(struct clk_init_data
){
2095 .name
= "vclk_div2",
2096 .ops
= &clk_fixed_factor_ops
,
2097 .parent_hws
= (const struct clk_hw
*[]) {
2098 &gxbb_vclk_div2_en
.hw
2104 static struct clk_fixed_factor gxbb_vclk_div4
= {
2107 .hw
.init
= &(struct clk_init_data
){
2108 .name
= "vclk_div4",
2109 .ops
= &clk_fixed_factor_ops
,
2110 .parent_hws
= (const struct clk_hw
*[]) {
2111 &gxbb_vclk_div4_en
.hw
2117 static struct clk_fixed_factor gxbb_vclk_div6
= {
2120 .hw
.init
= &(struct clk_init_data
){
2121 .name
= "vclk_div6",
2122 .ops
= &clk_fixed_factor_ops
,
2123 .parent_hws
= (const struct clk_hw
*[]) {
2124 &gxbb_vclk_div6_en
.hw
2130 static struct clk_fixed_factor gxbb_vclk_div12
= {
2133 .hw
.init
= &(struct clk_init_data
){
2134 .name
= "vclk_div12",
2135 .ops
= &clk_fixed_factor_ops
,
2136 .parent_hws
= (const struct clk_hw
*[]) {
2137 &gxbb_vclk_div12_en
.hw
2143 static struct clk_fixed_factor gxbb_vclk2_div2
= {
2146 .hw
.init
= &(struct clk_init_data
){
2147 .name
= "vclk2_div2",
2148 .ops
= &clk_fixed_factor_ops
,
2149 .parent_hws
= (const struct clk_hw
*[]) {
2150 &gxbb_vclk2_div2_en
.hw
2156 static struct clk_fixed_factor gxbb_vclk2_div4
= {
2159 .hw
.init
= &(struct clk_init_data
){
2160 .name
= "vclk2_div4",
2161 .ops
= &clk_fixed_factor_ops
,
2162 .parent_hws
= (const struct clk_hw
*[]) {
2163 &gxbb_vclk2_div4_en
.hw
2169 static struct clk_fixed_factor gxbb_vclk2_div6
= {
2172 .hw
.init
= &(struct clk_init_data
){
2173 .name
= "vclk2_div6",
2174 .ops
= &clk_fixed_factor_ops
,
2175 .parent_hws
= (const struct clk_hw
*[]) {
2176 &gxbb_vclk2_div6_en
.hw
2182 static struct clk_fixed_factor gxbb_vclk2_div12
= {
2185 .hw
.init
= &(struct clk_init_data
){
2186 .name
= "vclk2_div12",
2187 .ops
= &clk_fixed_factor_ops
,
2188 .parent_hws
= (const struct clk_hw
*[]) {
2189 &gxbb_vclk2_div12_en
.hw
2195 static u32 mux_table_cts_sel
[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2196 static const struct clk_hw
*gxbb_cts_parent_hws
[] = {
2201 &gxbb_vclk_div12
.hw
,
2202 &gxbb_vclk2_div1
.hw
,
2203 &gxbb_vclk2_div2
.hw
,
2204 &gxbb_vclk2_div4
.hw
,
2205 &gxbb_vclk2_div6
.hw
,
2206 &gxbb_vclk2_div12
.hw
,
2209 static struct clk_regmap gxbb_cts_enci_sel
= {
2210 .data
= &(struct clk_regmap_mux_data
){
2211 .offset
= HHI_VID_CLK_DIV
,
2214 .table
= mux_table_cts_sel
,
2216 .hw
.init
= &(struct clk_init_data
){
2217 .name
= "cts_enci_sel",
2218 .ops
= &clk_regmap_mux_ops
,
2219 .parent_hws
= gxbb_cts_parent_hws
,
2220 .num_parents
= ARRAY_SIZE(gxbb_cts_parent_hws
),
2221 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
2225 static struct clk_regmap gxbb_cts_encp_sel
= {
2226 .data
= &(struct clk_regmap_mux_data
){
2227 .offset
= HHI_VID_CLK_DIV
,
2230 .table
= mux_table_cts_sel
,
2232 .hw
.init
= &(struct clk_init_data
){
2233 .name
= "cts_encp_sel",
2234 .ops
= &clk_regmap_mux_ops
,
2235 .parent_hws
= gxbb_cts_parent_hws
,
2236 .num_parents
= ARRAY_SIZE(gxbb_cts_parent_hws
),
2237 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
2241 static struct clk_regmap gxbb_cts_vdac_sel
= {
2242 .data
= &(struct clk_regmap_mux_data
){
2243 .offset
= HHI_VIID_CLK_DIV
,
2246 .table
= mux_table_cts_sel
,
2248 .hw
.init
= &(struct clk_init_data
){
2249 .name
= "cts_vdac_sel",
2250 .ops
= &clk_regmap_mux_ops
,
2251 .parent_hws
= gxbb_cts_parent_hws
,
2252 .num_parents
= ARRAY_SIZE(gxbb_cts_parent_hws
),
2253 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
2257 /* TOFIX: add support for cts_tcon */
2258 static u32 mux_table_hdmi_tx_sel
[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2259 static const struct clk_hw
*gxbb_cts_hdmi_tx_parent_hws
[] = {
2264 &gxbb_vclk_div12
.hw
,
2265 &gxbb_vclk2_div1
.hw
,
2266 &gxbb_vclk2_div2
.hw
,
2267 &gxbb_vclk2_div4
.hw
,
2268 &gxbb_vclk2_div6
.hw
,
2269 &gxbb_vclk2_div12
.hw
,
2272 static struct clk_regmap gxbb_hdmi_tx_sel
= {
2273 .data
= &(struct clk_regmap_mux_data
){
2274 .offset
= HHI_HDMI_CLK_CNTL
,
2277 .table
= mux_table_hdmi_tx_sel
,
2279 .hw
.init
= &(struct clk_init_data
){
2280 .name
= "hdmi_tx_sel",
2281 .ops
= &clk_regmap_mux_ops
,
2283 * bits 31:28 selects from 12 possible parents:
2284 * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
2285 * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2288 .parent_hws
= gxbb_cts_hdmi_tx_parent_hws
,
2289 .num_parents
= ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws
),
2290 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
2294 static struct clk_regmap gxbb_cts_enci
= {
2295 .data
= &(struct clk_regmap_gate_data
){
2296 .offset
= HHI_VID_CLK_CNTL2
,
2299 .hw
.init
= &(struct clk_init_data
) {
2301 .ops
= &clk_regmap_gate_ops
,
2302 .parent_hws
= (const struct clk_hw
*[]) {
2303 &gxbb_cts_enci_sel
.hw
2306 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
2310 static struct clk_regmap gxbb_cts_encp
= {
2311 .data
= &(struct clk_regmap_gate_data
){
2312 .offset
= HHI_VID_CLK_CNTL2
,
2315 .hw
.init
= &(struct clk_init_data
) {
2317 .ops
= &clk_regmap_gate_ops
,
2318 .parent_hws
= (const struct clk_hw
*[]) {
2319 &gxbb_cts_encp_sel
.hw
2322 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
2326 static struct clk_regmap gxbb_cts_vdac
= {
2327 .data
= &(struct clk_regmap_gate_data
){
2328 .offset
= HHI_VID_CLK_CNTL2
,
2331 .hw
.init
= &(struct clk_init_data
) {
2333 .ops
= &clk_regmap_gate_ops
,
2334 .parent_hws
= (const struct clk_hw
*[]) {
2335 &gxbb_cts_vdac_sel
.hw
2338 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
2342 static struct clk_regmap gxbb_hdmi_tx
= {
2343 .data
= &(struct clk_regmap_gate_data
){
2344 .offset
= HHI_VID_CLK_CNTL2
,
2347 .hw
.init
= &(struct clk_init_data
) {
2349 .ops
= &clk_regmap_gate_ops
,
2350 .parent_hws
= (const struct clk_hw
*[]) {
2351 &gxbb_hdmi_tx_sel
.hw
2354 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
2360 static const struct clk_parent_data gxbb_hdmi_parent_data
[] = {
2361 { .fw_name
= "xtal", },
2362 { .hw
= &gxbb_fclk_div4
.hw
},
2363 { .hw
= &gxbb_fclk_div3
.hw
},
2364 { .hw
= &gxbb_fclk_div5
.hw
},
2367 static struct clk_regmap gxbb_hdmi_sel
= {
2368 .data
= &(struct clk_regmap_mux_data
){
2369 .offset
= HHI_HDMI_CLK_CNTL
,
2372 .flags
= CLK_MUX_ROUND_CLOSEST
,
2374 .hw
.init
= &(struct clk_init_data
){
2376 .ops
= &clk_regmap_mux_ops
,
2377 .parent_data
= gxbb_hdmi_parent_data
,
2378 .num_parents
= ARRAY_SIZE(gxbb_hdmi_parent_data
),
2379 .flags
= CLK_SET_RATE_NO_REPARENT
| CLK_GET_RATE_NOCACHE
,
2383 static struct clk_regmap gxbb_hdmi_div
= {
2384 .data
= &(struct clk_regmap_div_data
){
2385 .offset
= HHI_HDMI_CLK_CNTL
,
2389 .hw
.init
= &(struct clk_init_data
){
2391 .ops
= &clk_regmap_divider_ops
,
2392 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_hdmi_sel
.hw
},
2394 .flags
= CLK_GET_RATE_NOCACHE
,
2398 static struct clk_regmap gxbb_hdmi
= {
2399 .data
= &(struct clk_regmap_gate_data
){
2400 .offset
= HHI_HDMI_CLK_CNTL
,
2403 .hw
.init
= &(struct clk_init_data
) {
2405 .ops
= &clk_regmap_gate_ops
,
2406 .parent_hws
= (const struct clk_hw
*[]) { &gxbb_hdmi_div
.hw
},
2408 .flags
= CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
2414 static const struct clk_hw
*gxbb_vdec_parent_hws
[] = {
2421 static struct clk_regmap gxbb_vdec_1_sel
= {
2422 .data
= &(struct clk_regmap_mux_data
){
2423 .offset
= HHI_VDEC_CLK_CNTL
,
2426 .flags
= CLK_MUX_ROUND_CLOSEST
,
2428 .hw
.init
= &(struct clk_init_data
){
2429 .name
= "vdec_1_sel",
2430 .ops
= &clk_regmap_mux_ops
,
2431 .parent_hws
= gxbb_vdec_parent_hws
,
2432 .num_parents
= ARRAY_SIZE(gxbb_vdec_parent_hws
),
2433 .flags
= CLK_SET_RATE_PARENT
,
2437 static struct clk_regmap gxbb_vdec_1_div
= {
2438 .data
= &(struct clk_regmap_div_data
){
2439 .offset
= HHI_VDEC_CLK_CNTL
,
2442 .flags
= CLK_DIVIDER_ROUND_CLOSEST
,
2444 .hw
.init
= &(struct clk_init_data
){
2445 .name
= "vdec_1_div",
2446 .ops
= &clk_regmap_divider_ops
,
2447 .parent_hws
= (const struct clk_hw
*[]) {
2451 .flags
= CLK_SET_RATE_PARENT
,
2455 static struct clk_regmap gxbb_vdec_1
= {
2456 .data
= &(struct clk_regmap_gate_data
){
2457 .offset
= HHI_VDEC_CLK_CNTL
,
2460 .hw
.init
= &(struct clk_init_data
) {
2462 .ops
= &clk_regmap_gate_ops
,
2463 .parent_hws
= (const struct clk_hw
*[]) {
2467 .flags
= CLK_SET_RATE_PARENT
,
2471 static struct clk_regmap gxbb_vdec_hevc_sel
= {
2472 .data
= &(struct clk_regmap_mux_data
){
2473 .offset
= HHI_VDEC2_CLK_CNTL
,
2476 .flags
= CLK_MUX_ROUND_CLOSEST
,
2478 .hw
.init
= &(struct clk_init_data
){
2479 .name
= "vdec_hevc_sel",
2480 .ops
= &clk_regmap_mux_ops
,
2481 .parent_hws
= gxbb_vdec_parent_hws
,
2482 .num_parents
= ARRAY_SIZE(gxbb_vdec_parent_hws
),
2483 .flags
= CLK_SET_RATE_PARENT
,
2487 static struct clk_regmap gxbb_vdec_hevc_div
= {
2488 .data
= &(struct clk_regmap_div_data
){
2489 .offset
= HHI_VDEC2_CLK_CNTL
,
2492 .flags
= CLK_DIVIDER_ROUND_CLOSEST
,
2494 .hw
.init
= &(struct clk_init_data
){
2495 .name
= "vdec_hevc_div",
2496 .ops
= &clk_regmap_divider_ops
,
2497 .parent_hws
= (const struct clk_hw
*[]) {
2498 &gxbb_vdec_hevc_sel
.hw
2501 .flags
= CLK_SET_RATE_PARENT
,
2505 static struct clk_regmap gxbb_vdec_hevc
= {
2506 .data
= &(struct clk_regmap_gate_data
){
2507 .offset
= HHI_VDEC2_CLK_CNTL
,
2510 .hw
.init
= &(struct clk_init_data
) {
2511 .name
= "vdec_hevc",
2512 .ops
= &clk_regmap_gate_ops
,
2513 .parent_hws
= (const struct clk_hw
*[]) {
2514 &gxbb_vdec_hevc_div
.hw
2517 .flags
= CLK_SET_RATE_PARENT
,
2521 static u32 mux_table_gen_clk
[] = { 0, 4, 5, 6, 7, 8,
2522 9, 10, 11, 13, 14, };
2523 static const struct clk_parent_data gen_clk_parent_data
[] = {
2524 { .fw_name
= "xtal", },
2525 { .hw
= &gxbb_vdec_1
.hw
},
2526 { .hw
= &gxbb_vdec_hevc
.hw
},
2527 { .hw
= &gxbb_mpll0
.hw
},
2528 { .hw
= &gxbb_mpll1
.hw
},
2529 { .hw
= &gxbb_mpll2
.hw
},
2530 { .hw
= &gxbb_fclk_div4
.hw
},
2531 { .hw
= &gxbb_fclk_div3
.hw
},
2532 { .hw
= &gxbb_fclk_div5
.hw
},
2533 { .hw
= &gxbb_fclk_div7
.hw
},
2534 { .hw
= &gxbb_gp0_pll
.hw
},
2537 static struct clk_regmap gxbb_gen_clk_sel
= {
2538 .data
= &(struct clk_regmap_mux_data
){
2539 .offset
= HHI_GEN_CLK_CNTL
,
2542 .table
= mux_table_gen_clk
,
2544 .hw
.init
= &(struct clk_init_data
){
2545 .name
= "gen_clk_sel",
2546 .ops
= &clk_regmap_mux_ops
,
2548 * bits 15:12 selects from 14 possible parents:
2549 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
2550 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
2551 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
2553 .parent_data
= gen_clk_parent_data
,
2554 .num_parents
= ARRAY_SIZE(gen_clk_parent_data
),
2558 static struct clk_regmap gxbb_gen_clk_div
= {
2559 .data
= &(struct clk_regmap_div_data
){
2560 .offset
= HHI_GEN_CLK_CNTL
,
2564 .hw
.init
= &(struct clk_init_data
){
2565 .name
= "gen_clk_div",
2566 .ops
= &clk_regmap_divider_ops
,
2567 .parent_hws
= (const struct clk_hw
*[]) {
2568 &gxbb_gen_clk_sel
.hw
2571 .flags
= CLK_SET_RATE_PARENT
,
2575 static struct clk_regmap gxbb_gen_clk
= {
2576 .data
= &(struct clk_regmap_gate_data
){
2577 .offset
= HHI_GEN_CLK_CNTL
,
2580 .hw
.init
= &(struct clk_init_data
){
2582 .ops
= &clk_regmap_gate_ops
,
2583 .parent_hws
= (const struct clk_hw
*[]) {
2584 &gxbb_gen_clk_div
.hw
2587 .flags
= CLK_SET_RATE_PARENT
,
2591 #define MESON_GATE(_name, _reg, _bit) \
2592 MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
2594 /* Everything Else (EE) domain gates */
2595 static MESON_GATE(gxbb_ddr
, HHI_GCLK_MPEG0
, 0);
2596 static MESON_GATE(gxbb_dos
, HHI_GCLK_MPEG0
, 1);
2597 static MESON_GATE(gxbb_isa
, HHI_GCLK_MPEG0
, 5);
2598 static MESON_GATE(gxbb_pl301
, HHI_GCLK_MPEG0
, 6);
2599 static MESON_GATE(gxbb_periphs
, HHI_GCLK_MPEG0
, 7);
2600 static MESON_GATE(gxbb_spicc
, HHI_GCLK_MPEG0
, 8);
2601 static MESON_GATE(gxbb_i2c
, HHI_GCLK_MPEG0
, 9);
2602 static MESON_GATE(gxbb_sana
, HHI_GCLK_MPEG0
, 10);
2603 static MESON_GATE(gxbb_smart_card
, HHI_GCLK_MPEG0
, 11);
2604 static MESON_GATE(gxbb_rng0
, HHI_GCLK_MPEG0
, 12);
2605 static MESON_GATE(gxbb_uart0
, HHI_GCLK_MPEG0
, 13);
2606 static MESON_GATE(gxbb_sdhc
, HHI_GCLK_MPEG0
, 14);
2607 static MESON_GATE(gxbb_stream
, HHI_GCLK_MPEG0
, 15);
2608 static MESON_GATE(gxbb_async_fifo
, HHI_GCLK_MPEG0
, 16);
2609 static MESON_GATE(gxbb_sdio
, HHI_GCLK_MPEG0
, 17);
2610 static MESON_GATE(gxbb_abuf
, HHI_GCLK_MPEG0
, 18);
2611 static MESON_GATE(gxbb_hiu_iface
, HHI_GCLK_MPEG0
, 19);
2612 static MESON_GATE(gxbb_assist_misc
, HHI_GCLK_MPEG0
, 23);
2613 static MESON_GATE(gxbb_emmc_a
, HHI_GCLK_MPEG0
, 24);
2614 static MESON_GATE(gxbb_emmc_b
, HHI_GCLK_MPEG0
, 25);
2615 static MESON_GATE(gxbb_emmc_c
, HHI_GCLK_MPEG0
, 26);
2616 static MESON_GATE(gxl_acodec
, HHI_GCLK_MPEG0
, 28);
2617 static MESON_GATE(gxbb_spi
, HHI_GCLK_MPEG0
, 30);
2619 static MESON_GATE(gxbb_i2s_spdif
, HHI_GCLK_MPEG1
, 2);
2620 static MESON_GATE(gxbb_eth
, HHI_GCLK_MPEG1
, 3);
2621 static MESON_GATE(gxbb_demux
, HHI_GCLK_MPEG1
, 4);
2622 static MESON_GATE(gxbb_blkmv
, HHI_GCLK_MPEG1
, 14);
2623 static MESON_GATE(gxbb_aiu
, HHI_GCLK_MPEG1
, 15);
2624 static MESON_GATE(gxbb_uart1
, HHI_GCLK_MPEG1
, 16);
2625 static MESON_GATE(gxbb_g2d
, HHI_GCLK_MPEG1
, 20);
2626 static MESON_GATE(gxbb_usb0
, HHI_GCLK_MPEG1
, 21);
2627 static MESON_GATE(gxbb_usb1
, HHI_GCLK_MPEG1
, 22);
2628 static MESON_GATE(gxbb_reset
, HHI_GCLK_MPEG1
, 23);
2629 static MESON_GATE(gxbb_nand
, HHI_GCLK_MPEG1
, 24);
2630 static MESON_GATE(gxbb_dos_parser
, HHI_GCLK_MPEG1
, 25);
2631 static MESON_GATE(gxbb_usb
, HHI_GCLK_MPEG1
, 26);
2632 static MESON_GATE(gxbb_vdin1
, HHI_GCLK_MPEG1
, 28);
2633 static MESON_GATE(gxbb_ahb_arb0
, HHI_GCLK_MPEG1
, 29);
2634 static MESON_GATE(gxbb_efuse
, HHI_GCLK_MPEG1
, 30);
2635 static MESON_GATE(gxbb_boot_rom
, HHI_GCLK_MPEG1
, 31);
2637 static MESON_GATE(gxbb_ahb_data_bus
, HHI_GCLK_MPEG2
, 1);
2638 static MESON_GATE(gxbb_ahb_ctrl_bus
, HHI_GCLK_MPEG2
, 2);
2639 static MESON_GATE(gxbb_hdmi_intr_sync
, HHI_GCLK_MPEG2
, 3);
2640 static MESON_GATE(gxbb_hdmi_pclk
, HHI_GCLK_MPEG2
, 4);
2641 static MESON_GATE(gxbb_usb1_ddr_bridge
, HHI_GCLK_MPEG2
, 8);
2642 static MESON_GATE(gxbb_usb0_ddr_bridge
, HHI_GCLK_MPEG2
, 9);
2643 static MESON_GATE(gxbb_mmc_pclk
, HHI_GCLK_MPEG2
, 11);
2644 static MESON_GATE(gxbb_dvin
, HHI_GCLK_MPEG2
, 12);
2645 static MESON_GATE(gxbb_uart2
, HHI_GCLK_MPEG2
, 15);
2646 static MESON_GATE(gxbb_sar_adc
, HHI_GCLK_MPEG2
, 22);
2647 static MESON_GATE(gxbb_vpu_intr
, HHI_GCLK_MPEG2
, 25);
2648 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge
, HHI_GCLK_MPEG2
, 26);
2649 static MESON_GATE(gxbb_clk81_a53
, HHI_GCLK_MPEG2
, 29);
2651 static MESON_GATE(gxbb_vclk2_venci0
, HHI_GCLK_OTHER
, 1);
2652 static MESON_GATE(gxbb_vclk2_venci1
, HHI_GCLK_OTHER
, 2);
2653 static MESON_GATE(gxbb_vclk2_vencp0
, HHI_GCLK_OTHER
, 3);
2654 static MESON_GATE(gxbb_vclk2_vencp1
, HHI_GCLK_OTHER
, 4);
2655 static MESON_GATE(gxbb_gclk_venci_int0
, HHI_GCLK_OTHER
, 8);
2656 static MESON_GATE(gxbb_gclk_vencp_int
, HHI_GCLK_OTHER
, 9);
2657 static MESON_GATE(gxbb_dac_clk
, HHI_GCLK_OTHER
, 10);
2658 static MESON_GATE(gxbb_aoclk_gate
, HHI_GCLK_OTHER
, 14);
2659 static MESON_GATE(gxbb_iec958_gate
, HHI_GCLK_OTHER
, 16);
2660 static MESON_GATE(gxbb_enc480p
, HHI_GCLK_OTHER
, 20);
2661 static MESON_GATE(gxbb_rng1
, HHI_GCLK_OTHER
, 21);
2662 static MESON_GATE(gxbb_gclk_venci_int1
, HHI_GCLK_OTHER
, 22);
2663 static MESON_GATE(gxbb_vclk2_venclmcc
, HHI_GCLK_OTHER
, 24);
2664 static MESON_GATE(gxbb_vclk2_vencl
, HHI_GCLK_OTHER
, 25);
2665 static MESON_GATE(gxbb_vclk_other
, HHI_GCLK_OTHER
, 26);
2666 static MESON_GATE(gxbb_edp
, HHI_GCLK_OTHER
, 31);
2668 /* Always On (AO) domain gates */
2670 static MESON_GATE(gxbb_ao_media_cpu
, HHI_GCLK_AO
, 0);
2671 static MESON_GATE(gxbb_ao_ahb_sram
, HHI_GCLK_AO
, 1);
2672 static MESON_GATE(gxbb_ao_ahb_bus
, HHI_GCLK_AO
, 2);
2673 static MESON_GATE(gxbb_ao_iface
, HHI_GCLK_AO
, 3);
2674 static MESON_GATE(gxbb_ao_i2c
, HHI_GCLK_AO
, 4);
2677 static MESON_PCLK(gxbb_aiu_glue
, HHI_GCLK_MPEG1
, 6, &gxbb_aiu
.hw
);
2678 static MESON_PCLK(gxbb_iec958
, HHI_GCLK_MPEG1
, 7, &gxbb_aiu_glue
.hw
);
2679 static MESON_PCLK(gxbb_i2s_out
, HHI_GCLK_MPEG1
, 8, &gxbb_aiu_glue
.hw
);
2680 static MESON_PCLK(gxbb_amclk
, HHI_GCLK_MPEG1
, 9, &gxbb_aiu_glue
.hw
);
2681 static MESON_PCLK(gxbb_aififo2
, HHI_GCLK_MPEG1
, 10, &gxbb_aiu_glue
.hw
);
2682 static MESON_PCLK(gxbb_mixer
, HHI_GCLK_MPEG1
, 11, &gxbb_aiu_glue
.hw
);
2683 static MESON_PCLK(gxbb_mixer_iface
, HHI_GCLK_MPEG1
, 12, &gxbb_aiu_glue
.hw
);
2684 static MESON_PCLK(gxbb_adc
, HHI_GCLK_MPEG1
, 13, &gxbb_aiu_glue
.hw
);
2686 /* Array of all clocks provided by this provider */
2688 static struct clk_hw_onecell_data gxbb_hw_onecell_data
= {
2690 [CLKID_SYS_PLL
] = &gxbb_sys_pll
.hw
,
2691 [CLKID_HDMI_PLL
] = &gxbb_hdmi_pll
.hw
,
2692 [CLKID_FIXED_PLL
] = &gxbb_fixed_pll
.hw
,
2693 [CLKID_FCLK_DIV2
] = &gxbb_fclk_div2
.hw
,
2694 [CLKID_FCLK_DIV3
] = &gxbb_fclk_div3
.hw
,
2695 [CLKID_FCLK_DIV4
] = &gxbb_fclk_div4
.hw
,
2696 [CLKID_FCLK_DIV5
] = &gxbb_fclk_div5
.hw
,
2697 [CLKID_FCLK_DIV7
] = &gxbb_fclk_div7
.hw
,
2698 [CLKID_GP0_PLL
] = &gxbb_gp0_pll
.hw
,
2699 [CLKID_MPEG_SEL
] = &gxbb_mpeg_clk_sel
.hw
,
2700 [CLKID_MPEG_DIV
] = &gxbb_mpeg_clk_div
.hw
,
2701 [CLKID_CLK81
] = &gxbb_clk81
.hw
,
2702 [CLKID_MPLL0
] = &gxbb_mpll0
.hw
,
2703 [CLKID_MPLL1
] = &gxbb_mpll1
.hw
,
2704 [CLKID_MPLL2
] = &gxbb_mpll2
.hw
,
2705 [CLKID_DDR
] = &gxbb_ddr
.hw
,
2706 [CLKID_DOS
] = &gxbb_dos
.hw
,
2707 [CLKID_ISA
] = &gxbb_isa
.hw
,
2708 [CLKID_PL301
] = &gxbb_pl301
.hw
,
2709 [CLKID_PERIPHS
] = &gxbb_periphs
.hw
,
2710 [CLKID_SPICC
] = &gxbb_spicc
.hw
,
2711 [CLKID_I2C
] = &gxbb_i2c
.hw
,
2712 [CLKID_SAR_ADC
] = &gxbb_sar_adc
.hw
,
2713 [CLKID_SMART_CARD
] = &gxbb_smart_card
.hw
,
2714 [CLKID_RNG0
] = &gxbb_rng0
.hw
,
2715 [CLKID_UART0
] = &gxbb_uart0
.hw
,
2716 [CLKID_SDHC
] = &gxbb_sdhc
.hw
,
2717 [CLKID_STREAM
] = &gxbb_stream
.hw
,
2718 [CLKID_ASYNC_FIFO
] = &gxbb_async_fifo
.hw
,
2719 [CLKID_SDIO
] = &gxbb_sdio
.hw
,
2720 [CLKID_ABUF
] = &gxbb_abuf
.hw
,
2721 [CLKID_HIU_IFACE
] = &gxbb_hiu_iface
.hw
,
2722 [CLKID_ASSIST_MISC
] = &gxbb_assist_misc
.hw
,
2723 [CLKID_SPI
] = &gxbb_spi
.hw
,
2724 [CLKID_I2S_SPDIF
] = &gxbb_i2s_spdif
.hw
,
2725 [CLKID_ETH
] = &gxbb_eth
.hw
,
2726 [CLKID_DEMUX
] = &gxbb_demux
.hw
,
2727 [CLKID_AIU_GLUE
] = &gxbb_aiu_glue
.hw
,
2728 [CLKID_IEC958
] = &gxbb_iec958
.hw
,
2729 [CLKID_I2S_OUT
] = &gxbb_i2s_out
.hw
,
2730 [CLKID_AMCLK
] = &gxbb_amclk
.hw
,
2731 [CLKID_AIFIFO2
] = &gxbb_aififo2
.hw
,
2732 [CLKID_MIXER
] = &gxbb_mixer
.hw
,
2733 [CLKID_MIXER_IFACE
] = &gxbb_mixer_iface
.hw
,
2734 [CLKID_ADC
] = &gxbb_adc
.hw
,
2735 [CLKID_BLKMV
] = &gxbb_blkmv
.hw
,
2736 [CLKID_AIU
] = &gxbb_aiu
.hw
,
2737 [CLKID_UART1
] = &gxbb_uart1
.hw
,
2738 [CLKID_G2D
] = &gxbb_g2d
.hw
,
2739 [CLKID_USB0
] = &gxbb_usb0
.hw
,
2740 [CLKID_USB1
] = &gxbb_usb1
.hw
,
2741 [CLKID_RESET
] = &gxbb_reset
.hw
,
2742 [CLKID_NAND
] = &gxbb_nand
.hw
,
2743 [CLKID_DOS_PARSER
] = &gxbb_dos_parser
.hw
,
2744 [CLKID_USB
] = &gxbb_usb
.hw
,
2745 [CLKID_VDIN1
] = &gxbb_vdin1
.hw
,
2746 [CLKID_AHB_ARB0
] = &gxbb_ahb_arb0
.hw
,
2747 [CLKID_EFUSE
] = &gxbb_efuse
.hw
,
2748 [CLKID_BOOT_ROM
] = &gxbb_boot_rom
.hw
,
2749 [CLKID_AHB_DATA_BUS
] = &gxbb_ahb_data_bus
.hw
,
2750 [CLKID_AHB_CTRL_BUS
] = &gxbb_ahb_ctrl_bus
.hw
,
2751 [CLKID_HDMI_INTR_SYNC
] = &gxbb_hdmi_intr_sync
.hw
,
2752 [CLKID_HDMI_PCLK
] = &gxbb_hdmi_pclk
.hw
,
2753 [CLKID_USB1_DDR_BRIDGE
] = &gxbb_usb1_ddr_bridge
.hw
,
2754 [CLKID_USB0_DDR_BRIDGE
] = &gxbb_usb0_ddr_bridge
.hw
,
2755 [CLKID_MMC_PCLK
] = &gxbb_mmc_pclk
.hw
,
2756 [CLKID_DVIN
] = &gxbb_dvin
.hw
,
2757 [CLKID_UART2
] = &gxbb_uart2
.hw
,
2758 [CLKID_SANA
] = &gxbb_sana
.hw
,
2759 [CLKID_VPU_INTR
] = &gxbb_vpu_intr
.hw
,
2760 [CLKID_SEC_AHB_AHB3_BRIDGE
] = &gxbb_sec_ahb_ahb3_bridge
.hw
,
2761 [CLKID_CLK81_A53
] = &gxbb_clk81_a53
.hw
,
2762 [CLKID_VCLK2_VENCI0
] = &gxbb_vclk2_venci0
.hw
,
2763 [CLKID_VCLK2_VENCI1
] = &gxbb_vclk2_venci1
.hw
,
2764 [CLKID_VCLK2_VENCP0
] = &gxbb_vclk2_vencp0
.hw
,
2765 [CLKID_VCLK2_VENCP1
] = &gxbb_vclk2_vencp1
.hw
,
2766 [CLKID_GCLK_VENCI_INT0
] = &gxbb_gclk_venci_int0
.hw
,
2767 [CLKID_GCLK_VENCI_INT
] = &gxbb_gclk_vencp_int
.hw
,
2768 [CLKID_DAC_CLK
] = &gxbb_dac_clk
.hw
,
2769 [CLKID_AOCLK_GATE
] = &gxbb_aoclk_gate
.hw
,
2770 [CLKID_IEC958_GATE
] = &gxbb_iec958_gate
.hw
,
2771 [CLKID_ENC480P
] = &gxbb_enc480p
.hw
,
2772 [CLKID_RNG1
] = &gxbb_rng1
.hw
,
2773 [CLKID_GCLK_VENCI_INT1
] = &gxbb_gclk_venci_int1
.hw
,
2774 [CLKID_VCLK2_VENCLMCC
] = &gxbb_vclk2_venclmcc
.hw
,
2775 [CLKID_VCLK2_VENCL
] = &gxbb_vclk2_vencl
.hw
,
2776 [CLKID_VCLK_OTHER
] = &gxbb_vclk_other
.hw
,
2777 [CLKID_EDP
] = &gxbb_edp
.hw
,
2778 [CLKID_AO_MEDIA_CPU
] = &gxbb_ao_media_cpu
.hw
,
2779 [CLKID_AO_AHB_SRAM
] = &gxbb_ao_ahb_sram
.hw
,
2780 [CLKID_AO_AHB_BUS
] = &gxbb_ao_ahb_bus
.hw
,
2781 [CLKID_AO_IFACE
] = &gxbb_ao_iface
.hw
,
2782 [CLKID_AO_I2C
] = &gxbb_ao_i2c
.hw
,
2783 [CLKID_SD_EMMC_A
] = &gxbb_emmc_a
.hw
,
2784 [CLKID_SD_EMMC_B
] = &gxbb_emmc_b
.hw
,
2785 [CLKID_SD_EMMC_C
] = &gxbb_emmc_c
.hw
,
2786 [CLKID_SAR_ADC_CLK
] = &gxbb_sar_adc_clk
.hw
,
2787 [CLKID_SAR_ADC_SEL
] = &gxbb_sar_adc_clk_sel
.hw
,
2788 [CLKID_SAR_ADC_DIV
] = &gxbb_sar_adc_clk_div
.hw
,
2789 [CLKID_MALI_0_SEL
] = &gxbb_mali_0_sel
.hw
,
2790 [CLKID_MALI_0_DIV
] = &gxbb_mali_0_div
.hw
,
2791 [CLKID_MALI_0
] = &gxbb_mali_0
.hw
,
2792 [CLKID_MALI_1_SEL
] = &gxbb_mali_1_sel
.hw
,
2793 [CLKID_MALI_1_DIV
] = &gxbb_mali_1_div
.hw
,
2794 [CLKID_MALI_1
] = &gxbb_mali_1
.hw
,
2795 [CLKID_MALI
] = &gxbb_mali
.hw
,
2796 [CLKID_CTS_AMCLK
] = &gxbb_cts_amclk
.hw
,
2797 [CLKID_CTS_AMCLK_SEL
] = &gxbb_cts_amclk_sel
.hw
,
2798 [CLKID_CTS_AMCLK_DIV
] = &gxbb_cts_amclk_div
.hw
,
2799 [CLKID_CTS_MCLK_I958
] = &gxbb_cts_mclk_i958
.hw
,
2800 [CLKID_CTS_MCLK_I958_SEL
] = &gxbb_cts_mclk_i958_sel
.hw
,
2801 [CLKID_CTS_MCLK_I958_DIV
] = &gxbb_cts_mclk_i958_div
.hw
,
2802 [CLKID_CTS_I958
] = &gxbb_cts_i958
.hw
,
2803 [CLKID_32K_CLK
] = &gxbb_32k_clk
.hw
,
2804 [CLKID_32K_CLK_SEL
] = &gxbb_32k_clk_sel
.hw
,
2805 [CLKID_32K_CLK_DIV
] = &gxbb_32k_clk_div
.hw
,
2806 [CLKID_SD_EMMC_A_CLK0_SEL
] = &gxbb_sd_emmc_a_clk0_sel
.hw
,
2807 [CLKID_SD_EMMC_A_CLK0_DIV
] = &gxbb_sd_emmc_a_clk0_div
.hw
,
2808 [CLKID_SD_EMMC_A_CLK0
] = &gxbb_sd_emmc_a_clk0
.hw
,
2809 [CLKID_SD_EMMC_B_CLK0_SEL
] = &gxbb_sd_emmc_b_clk0_sel
.hw
,
2810 [CLKID_SD_EMMC_B_CLK0_DIV
] = &gxbb_sd_emmc_b_clk0_div
.hw
,
2811 [CLKID_SD_EMMC_B_CLK0
] = &gxbb_sd_emmc_b_clk0
.hw
,
2812 [CLKID_SD_EMMC_C_CLK0_SEL
] = &gxbb_sd_emmc_c_clk0_sel
.hw
,
2813 [CLKID_SD_EMMC_C_CLK0_DIV
] = &gxbb_sd_emmc_c_clk0_div
.hw
,
2814 [CLKID_SD_EMMC_C_CLK0
] = &gxbb_sd_emmc_c_clk0
.hw
,
2815 [CLKID_VPU_0_SEL
] = &gxbb_vpu_0_sel
.hw
,
2816 [CLKID_VPU_0_DIV
] = &gxbb_vpu_0_div
.hw
,
2817 [CLKID_VPU_0
] = &gxbb_vpu_0
.hw
,
2818 [CLKID_VPU_1_SEL
] = &gxbb_vpu_1_sel
.hw
,
2819 [CLKID_VPU_1_DIV
] = &gxbb_vpu_1_div
.hw
,
2820 [CLKID_VPU_1
] = &gxbb_vpu_1
.hw
,
2821 [CLKID_VPU
] = &gxbb_vpu
.hw
,
2822 [CLKID_VAPB_0_SEL
] = &gxbb_vapb_0_sel
.hw
,
2823 [CLKID_VAPB_0_DIV
] = &gxbb_vapb_0_div
.hw
,
2824 [CLKID_VAPB_0
] = &gxbb_vapb_0
.hw
,
2825 [CLKID_VAPB_1_SEL
] = &gxbb_vapb_1_sel
.hw
,
2826 [CLKID_VAPB_1_DIV
] = &gxbb_vapb_1_div
.hw
,
2827 [CLKID_VAPB_1
] = &gxbb_vapb_1
.hw
,
2828 [CLKID_VAPB_SEL
] = &gxbb_vapb_sel
.hw
,
2829 [CLKID_VAPB
] = &gxbb_vapb
.hw
,
2830 [CLKID_HDMI_PLL_PRE_MULT
] = &gxbb_hdmi_pll_pre_mult
.hw
,
2831 [CLKID_MPLL0_DIV
] = &gxbb_mpll0_div
.hw
,
2832 [CLKID_MPLL1_DIV
] = &gxbb_mpll1_div
.hw
,
2833 [CLKID_MPLL2_DIV
] = &gxbb_mpll2_div
.hw
,
2834 [CLKID_MPLL_PREDIV
] = &gxbb_mpll_prediv
.hw
,
2835 [CLKID_FCLK_DIV2_DIV
] = &gxbb_fclk_div2_div
.hw
,
2836 [CLKID_FCLK_DIV3_DIV
] = &gxbb_fclk_div3_div
.hw
,
2837 [CLKID_FCLK_DIV4_DIV
] = &gxbb_fclk_div4_div
.hw
,
2838 [CLKID_FCLK_DIV5_DIV
] = &gxbb_fclk_div5_div
.hw
,
2839 [CLKID_FCLK_DIV7_DIV
] = &gxbb_fclk_div7_div
.hw
,
2840 [CLKID_VDEC_1_SEL
] = &gxbb_vdec_1_sel
.hw
,
2841 [CLKID_VDEC_1_DIV
] = &gxbb_vdec_1_div
.hw
,
2842 [CLKID_VDEC_1
] = &gxbb_vdec_1
.hw
,
2843 [CLKID_VDEC_HEVC_SEL
] = &gxbb_vdec_hevc_sel
.hw
,
2844 [CLKID_VDEC_HEVC_DIV
] = &gxbb_vdec_hevc_div
.hw
,
2845 [CLKID_VDEC_HEVC
] = &gxbb_vdec_hevc
.hw
,
2846 [CLKID_GEN_CLK_SEL
] = &gxbb_gen_clk_sel
.hw
,
2847 [CLKID_GEN_CLK_DIV
] = &gxbb_gen_clk_div
.hw
,
2848 [CLKID_GEN_CLK
] = &gxbb_gen_clk
.hw
,
2849 [CLKID_FIXED_PLL_DCO
] = &gxbb_fixed_pll_dco
.hw
,
2850 [CLKID_HDMI_PLL_DCO
] = &gxbb_hdmi_pll_dco
.hw
,
2851 [CLKID_HDMI_PLL_OD
] = &gxbb_hdmi_pll_od
.hw
,
2852 [CLKID_HDMI_PLL_OD2
] = &gxbb_hdmi_pll_od2
.hw
,
2853 [CLKID_SYS_PLL_DCO
] = &gxbb_sys_pll_dco
.hw
,
2854 [CLKID_GP0_PLL_DCO
] = &gxbb_gp0_pll_dco
.hw
,
2855 [CLKID_VID_PLL_DIV
] = &gxbb_vid_pll_div
.hw
,
2856 [CLKID_VID_PLL_SEL
] = &gxbb_vid_pll_sel
.hw
,
2857 [CLKID_VID_PLL
] = &gxbb_vid_pll
.hw
,
2858 [CLKID_VCLK_SEL
] = &gxbb_vclk_sel
.hw
,
2859 [CLKID_VCLK2_SEL
] = &gxbb_vclk2_sel
.hw
,
2860 [CLKID_VCLK_INPUT
] = &gxbb_vclk_input
.hw
,
2861 [CLKID_VCLK2_INPUT
] = &gxbb_vclk2_input
.hw
,
2862 [CLKID_VCLK_DIV
] = &gxbb_vclk_div
.hw
,
2863 [CLKID_VCLK2_DIV
] = &gxbb_vclk2_div
.hw
,
2864 [CLKID_VCLK
] = &gxbb_vclk
.hw
,
2865 [CLKID_VCLK2
] = &gxbb_vclk2
.hw
,
2866 [CLKID_VCLK_DIV1
] = &gxbb_vclk_div1
.hw
,
2867 [CLKID_VCLK_DIV2_EN
] = &gxbb_vclk_div2_en
.hw
,
2868 [CLKID_VCLK_DIV2
] = &gxbb_vclk_div2
.hw
,
2869 [CLKID_VCLK_DIV4_EN
] = &gxbb_vclk_div4_en
.hw
,
2870 [CLKID_VCLK_DIV4
] = &gxbb_vclk_div4
.hw
,
2871 [CLKID_VCLK_DIV6_EN
] = &gxbb_vclk_div6_en
.hw
,
2872 [CLKID_VCLK_DIV6
] = &gxbb_vclk_div6
.hw
,
2873 [CLKID_VCLK_DIV12_EN
] = &gxbb_vclk_div12_en
.hw
,
2874 [CLKID_VCLK_DIV12
] = &gxbb_vclk_div12
.hw
,
2875 [CLKID_VCLK2_DIV1
] = &gxbb_vclk2_div1
.hw
,
2876 [CLKID_VCLK2_DIV2_EN
] = &gxbb_vclk2_div2_en
.hw
,
2877 [CLKID_VCLK2_DIV2
] = &gxbb_vclk2_div2
.hw
,
2878 [CLKID_VCLK2_DIV4_EN
] = &gxbb_vclk2_div4_en
.hw
,
2879 [CLKID_VCLK2_DIV4
] = &gxbb_vclk2_div4
.hw
,
2880 [CLKID_VCLK2_DIV6_EN
] = &gxbb_vclk2_div6_en
.hw
,
2881 [CLKID_VCLK2_DIV6
] = &gxbb_vclk2_div6
.hw
,
2882 [CLKID_VCLK2_DIV12_EN
] = &gxbb_vclk2_div12_en
.hw
,
2883 [CLKID_VCLK2_DIV12
] = &gxbb_vclk2_div12
.hw
,
2884 [CLKID_CTS_ENCI_SEL
] = &gxbb_cts_enci_sel
.hw
,
2885 [CLKID_CTS_ENCP_SEL
] = &gxbb_cts_encp_sel
.hw
,
2886 [CLKID_CTS_VDAC_SEL
] = &gxbb_cts_vdac_sel
.hw
,
2887 [CLKID_HDMI_TX_SEL
] = &gxbb_hdmi_tx_sel
.hw
,
2888 [CLKID_CTS_ENCI
] = &gxbb_cts_enci
.hw
,
2889 [CLKID_CTS_ENCP
] = &gxbb_cts_encp
.hw
,
2890 [CLKID_CTS_VDAC
] = &gxbb_cts_vdac
.hw
,
2891 [CLKID_HDMI_TX
] = &gxbb_hdmi_tx
.hw
,
2892 [CLKID_HDMI_SEL
] = &gxbb_hdmi_sel
.hw
,
2893 [CLKID_HDMI_DIV
] = &gxbb_hdmi_div
.hw
,
2894 [CLKID_HDMI
] = &gxbb_hdmi
.hw
,
2900 static struct clk_hw_onecell_data gxl_hw_onecell_data
= {
2902 [CLKID_SYS_PLL
] = &gxbb_sys_pll
.hw
,
2903 [CLKID_HDMI_PLL
] = &gxl_hdmi_pll
.hw
,
2904 [CLKID_FIXED_PLL
] = &gxbb_fixed_pll
.hw
,
2905 [CLKID_FCLK_DIV2
] = &gxbb_fclk_div2
.hw
,
2906 [CLKID_FCLK_DIV3
] = &gxbb_fclk_div3
.hw
,
2907 [CLKID_FCLK_DIV4
] = &gxbb_fclk_div4
.hw
,
2908 [CLKID_FCLK_DIV5
] = &gxbb_fclk_div5
.hw
,
2909 [CLKID_FCLK_DIV7
] = &gxbb_fclk_div7
.hw
,
2910 [CLKID_GP0_PLL
] = &gxbb_gp0_pll
.hw
,
2911 [CLKID_MPEG_SEL
] = &gxbb_mpeg_clk_sel
.hw
,
2912 [CLKID_MPEG_DIV
] = &gxbb_mpeg_clk_div
.hw
,
2913 [CLKID_CLK81
] = &gxbb_clk81
.hw
,
2914 [CLKID_MPLL0
] = &gxbb_mpll0
.hw
,
2915 [CLKID_MPLL1
] = &gxbb_mpll1
.hw
,
2916 [CLKID_MPLL2
] = &gxbb_mpll2
.hw
,
2917 [CLKID_DDR
] = &gxbb_ddr
.hw
,
2918 [CLKID_DOS
] = &gxbb_dos
.hw
,
2919 [CLKID_ISA
] = &gxbb_isa
.hw
,
2920 [CLKID_PL301
] = &gxbb_pl301
.hw
,
2921 [CLKID_PERIPHS
] = &gxbb_periphs
.hw
,
2922 [CLKID_SPICC
] = &gxbb_spicc
.hw
,
2923 [CLKID_I2C
] = &gxbb_i2c
.hw
,
2924 [CLKID_SAR_ADC
] = &gxbb_sar_adc
.hw
,
2925 [CLKID_SMART_CARD
] = &gxbb_smart_card
.hw
,
2926 [CLKID_RNG0
] = &gxbb_rng0
.hw
,
2927 [CLKID_UART0
] = &gxbb_uart0
.hw
,
2928 [CLKID_SDHC
] = &gxbb_sdhc
.hw
,
2929 [CLKID_STREAM
] = &gxbb_stream
.hw
,
2930 [CLKID_ASYNC_FIFO
] = &gxbb_async_fifo
.hw
,
2931 [CLKID_SDIO
] = &gxbb_sdio
.hw
,
2932 [CLKID_ABUF
] = &gxbb_abuf
.hw
,
2933 [CLKID_HIU_IFACE
] = &gxbb_hiu_iface
.hw
,
2934 [CLKID_ASSIST_MISC
] = &gxbb_assist_misc
.hw
,
2935 [CLKID_SPI
] = &gxbb_spi
.hw
,
2936 [CLKID_I2S_SPDIF
] = &gxbb_i2s_spdif
.hw
,
2937 [CLKID_ETH
] = &gxbb_eth
.hw
,
2938 [CLKID_DEMUX
] = &gxbb_demux
.hw
,
2939 [CLKID_AIU_GLUE
] = &gxbb_aiu_glue
.hw
,
2940 [CLKID_IEC958
] = &gxbb_iec958
.hw
,
2941 [CLKID_I2S_OUT
] = &gxbb_i2s_out
.hw
,
2942 [CLKID_AMCLK
] = &gxbb_amclk
.hw
,
2943 [CLKID_AIFIFO2
] = &gxbb_aififo2
.hw
,
2944 [CLKID_MIXER
] = &gxbb_mixer
.hw
,
2945 [CLKID_MIXER_IFACE
] = &gxbb_mixer_iface
.hw
,
2946 [CLKID_ADC
] = &gxbb_adc
.hw
,
2947 [CLKID_BLKMV
] = &gxbb_blkmv
.hw
,
2948 [CLKID_AIU
] = &gxbb_aiu
.hw
,
2949 [CLKID_UART1
] = &gxbb_uart1
.hw
,
2950 [CLKID_G2D
] = &gxbb_g2d
.hw
,
2951 [CLKID_USB0
] = &gxbb_usb0
.hw
,
2952 [CLKID_USB1
] = &gxbb_usb1
.hw
,
2953 [CLKID_RESET
] = &gxbb_reset
.hw
,
2954 [CLKID_NAND
] = &gxbb_nand
.hw
,
2955 [CLKID_DOS_PARSER
] = &gxbb_dos_parser
.hw
,
2956 [CLKID_USB
] = &gxbb_usb
.hw
,
2957 [CLKID_VDIN1
] = &gxbb_vdin1
.hw
,
2958 [CLKID_AHB_ARB0
] = &gxbb_ahb_arb0
.hw
,
2959 [CLKID_EFUSE
] = &gxbb_efuse
.hw
,
2960 [CLKID_BOOT_ROM
] = &gxbb_boot_rom
.hw
,
2961 [CLKID_AHB_DATA_BUS
] = &gxbb_ahb_data_bus
.hw
,
2962 [CLKID_AHB_CTRL_BUS
] = &gxbb_ahb_ctrl_bus
.hw
,
2963 [CLKID_HDMI_INTR_SYNC
] = &gxbb_hdmi_intr_sync
.hw
,
2964 [CLKID_HDMI_PCLK
] = &gxbb_hdmi_pclk
.hw
,
2965 [CLKID_USB1_DDR_BRIDGE
] = &gxbb_usb1_ddr_bridge
.hw
,
2966 [CLKID_USB0_DDR_BRIDGE
] = &gxbb_usb0_ddr_bridge
.hw
,
2967 [CLKID_MMC_PCLK
] = &gxbb_mmc_pclk
.hw
,
2968 [CLKID_DVIN
] = &gxbb_dvin
.hw
,
2969 [CLKID_UART2
] = &gxbb_uart2
.hw
,
2970 [CLKID_SANA
] = &gxbb_sana
.hw
,
2971 [CLKID_VPU_INTR
] = &gxbb_vpu_intr
.hw
,
2972 [CLKID_SEC_AHB_AHB3_BRIDGE
] = &gxbb_sec_ahb_ahb3_bridge
.hw
,
2973 [CLKID_CLK81_A53
] = &gxbb_clk81_a53
.hw
,
2974 [CLKID_VCLK2_VENCI0
] = &gxbb_vclk2_venci0
.hw
,
2975 [CLKID_VCLK2_VENCI1
] = &gxbb_vclk2_venci1
.hw
,
2976 [CLKID_VCLK2_VENCP0
] = &gxbb_vclk2_vencp0
.hw
,
2977 [CLKID_VCLK2_VENCP1
] = &gxbb_vclk2_vencp1
.hw
,
2978 [CLKID_GCLK_VENCI_INT0
] = &gxbb_gclk_venci_int0
.hw
,
2979 [CLKID_GCLK_VENCI_INT
] = &gxbb_gclk_vencp_int
.hw
,
2980 [CLKID_DAC_CLK
] = &gxbb_dac_clk
.hw
,
2981 [CLKID_AOCLK_GATE
] = &gxbb_aoclk_gate
.hw
,
2982 [CLKID_IEC958_GATE
] = &gxbb_iec958_gate
.hw
,
2983 [CLKID_ENC480P
] = &gxbb_enc480p
.hw
,
2984 [CLKID_RNG1
] = &gxbb_rng1
.hw
,
2985 [CLKID_GCLK_VENCI_INT1
] = &gxbb_gclk_venci_int1
.hw
,
2986 [CLKID_VCLK2_VENCLMCC
] = &gxbb_vclk2_venclmcc
.hw
,
2987 [CLKID_VCLK2_VENCL
] = &gxbb_vclk2_vencl
.hw
,
2988 [CLKID_VCLK_OTHER
] = &gxbb_vclk_other
.hw
,
2989 [CLKID_EDP
] = &gxbb_edp
.hw
,
2990 [CLKID_AO_MEDIA_CPU
] = &gxbb_ao_media_cpu
.hw
,
2991 [CLKID_AO_AHB_SRAM
] = &gxbb_ao_ahb_sram
.hw
,
2992 [CLKID_AO_AHB_BUS
] = &gxbb_ao_ahb_bus
.hw
,
2993 [CLKID_AO_IFACE
] = &gxbb_ao_iface
.hw
,
2994 [CLKID_AO_I2C
] = &gxbb_ao_i2c
.hw
,
2995 [CLKID_SD_EMMC_A
] = &gxbb_emmc_a
.hw
,
2996 [CLKID_SD_EMMC_B
] = &gxbb_emmc_b
.hw
,
2997 [CLKID_SD_EMMC_C
] = &gxbb_emmc_c
.hw
,
2998 [CLKID_SAR_ADC_CLK
] = &gxbb_sar_adc_clk
.hw
,
2999 [CLKID_SAR_ADC_SEL
] = &gxbb_sar_adc_clk_sel
.hw
,
3000 [CLKID_SAR_ADC_DIV
] = &gxbb_sar_adc_clk_div
.hw
,
3001 [CLKID_MALI_0_SEL
] = &gxbb_mali_0_sel
.hw
,
3002 [CLKID_MALI_0_DIV
] = &gxbb_mali_0_div
.hw
,
3003 [CLKID_MALI_0
] = &gxbb_mali_0
.hw
,
3004 [CLKID_MALI_1_SEL
] = &gxbb_mali_1_sel
.hw
,
3005 [CLKID_MALI_1_DIV
] = &gxbb_mali_1_div
.hw
,
3006 [CLKID_MALI_1
] = &gxbb_mali_1
.hw
,
3007 [CLKID_MALI
] = &gxbb_mali
.hw
,
3008 [CLKID_CTS_AMCLK
] = &gxbb_cts_amclk
.hw
,
3009 [CLKID_CTS_AMCLK_SEL
] = &gxbb_cts_amclk_sel
.hw
,
3010 [CLKID_CTS_AMCLK_DIV
] = &gxbb_cts_amclk_div
.hw
,
3011 [CLKID_CTS_MCLK_I958
] = &gxbb_cts_mclk_i958
.hw
,
3012 [CLKID_CTS_MCLK_I958_SEL
] = &gxbb_cts_mclk_i958_sel
.hw
,
3013 [CLKID_CTS_MCLK_I958_DIV
] = &gxbb_cts_mclk_i958_div
.hw
,
3014 [CLKID_CTS_I958
] = &gxbb_cts_i958
.hw
,
3015 [CLKID_32K_CLK
] = &gxbb_32k_clk
.hw
,
3016 [CLKID_32K_CLK_SEL
] = &gxbb_32k_clk_sel
.hw
,
3017 [CLKID_32K_CLK_DIV
] = &gxbb_32k_clk_div
.hw
,
3018 [CLKID_SD_EMMC_A_CLK0_SEL
] = &gxbb_sd_emmc_a_clk0_sel
.hw
,
3019 [CLKID_SD_EMMC_A_CLK0_DIV
] = &gxbb_sd_emmc_a_clk0_div
.hw
,
3020 [CLKID_SD_EMMC_A_CLK0
] = &gxbb_sd_emmc_a_clk0
.hw
,
3021 [CLKID_SD_EMMC_B_CLK0_SEL
] = &gxbb_sd_emmc_b_clk0_sel
.hw
,
3022 [CLKID_SD_EMMC_B_CLK0_DIV
] = &gxbb_sd_emmc_b_clk0_div
.hw
,
3023 [CLKID_SD_EMMC_B_CLK0
] = &gxbb_sd_emmc_b_clk0
.hw
,
3024 [CLKID_SD_EMMC_C_CLK0_SEL
] = &gxbb_sd_emmc_c_clk0_sel
.hw
,
3025 [CLKID_SD_EMMC_C_CLK0_DIV
] = &gxbb_sd_emmc_c_clk0_div
.hw
,
3026 [CLKID_SD_EMMC_C_CLK0
] = &gxbb_sd_emmc_c_clk0
.hw
,
3027 [CLKID_VPU_0_SEL
] = &gxbb_vpu_0_sel
.hw
,
3028 [CLKID_VPU_0_DIV
] = &gxbb_vpu_0_div
.hw
,
3029 [CLKID_VPU_0
] = &gxbb_vpu_0
.hw
,
3030 [CLKID_VPU_1_SEL
] = &gxbb_vpu_1_sel
.hw
,
3031 [CLKID_VPU_1_DIV
] = &gxbb_vpu_1_div
.hw
,
3032 [CLKID_VPU_1
] = &gxbb_vpu_1
.hw
,
3033 [CLKID_VPU
] = &gxbb_vpu
.hw
,
3034 [CLKID_VAPB_0_SEL
] = &gxbb_vapb_0_sel
.hw
,
3035 [CLKID_VAPB_0_DIV
] = &gxbb_vapb_0_div
.hw
,
3036 [CLKID_VAPB_0
] = &gxbb_vapb_0
.hw
,
3037 [CLKID_VAPB_1_SEL
] = &gxbb_vapb_1_sel
.hw
,
3038 [CLKID_VAPB_1_DIV
] = &gxbb_vapb_1_div
.hw
,
3039 [CLKID_VAPB_1
] = &gxbb_vapb_1
.hw
,
3040 [CLKID_VAPB_SEL
] = &gxbb_vapb_sel
.hw
,
3041 [CLKID_VAPB
] = &gxbb_vapb
.hw
,
3042 [CLKID_MPLL0_DIV
] = &gxbb_mpll0_div
.hw
,
3043 [CLKID_MPLL1_DIV
] = &gxbb_mpll1_div
.hw
,
3044 [CLKID_MPLL2_DIV
] = &gxbb_mpll2_div
.hw
,
3045 [CLKID_MPLL_PREDIV
] = &gxbb_mpll_prediv
.hw
,
3046 [CLKID_FCLK_DIV2_DIV
] = &gxbb_fclk_div2_div
.hw
,
3047 [CLKID_FCLK_DIV3_DIV
] = &gxbb_fclk_div3_div
.hw
,
3048 [CLKID_FCLK_DIV4_DIV
] = &gxbb_fclk_div4_div
.hw
,
3049 [CLKID_FCLK_DIV5_DIV
] = &gxbb_fclk_div5_div
.hw
,
3050 [CLKID_FCLK_DIV7_DIV
] = &gxbb_fclk_div7_div
.hw
,
3051 [CLKID_VDEC_1_SEL
] = &gxbb_vdec_1_sel
.hw
,
3052 [CLKID_VDEC_1_DIV
] = &gxbb_vdec_1_div
.hw
,
3053 [CLKID_VDEC_1
] = &gxbb_vdec_1
.hw
,
3054 [CLKID_VDEC_HEVC_SEL
] = &gxbb_vdec_hevc_sel
.hw
,
3055 [CLKID_VDEC_HEVC_DIV
] = &gxbb_vdec_hevc_div
.hw
,
3056 [CLKID_VDEC_HEVC
] = &gxbb_vdec_hevc
.hw
,
3057 [CLKID_GEN_CLK_SEL
] = &gxbb_gen_clk_sel
.hw
,
3058 [CLKID_GEN_CLK_DIV
] = &gxbb_gen_clk_div
.hw
,
3059 [CLKID_GEN_CLK
] = &gxbb_gen_clk
.hw
,
3060 [CLKID_FIXED_PLL_DCO
] = &gxbb_fixed_pll_dco
.hw
,
3061 [CLKID_HDMI_PLL_DCO
] = &gxl_hdmi_pll_dco
.hw
,
3062 [CLKID_HDMI_PLL_OD
] = &gxl_hdmi_pll_od
.hw
,
3063 [CLKID_HDMI_PLL_OD2
] = &gxl_hdmi_pll_od2
.hw
,
3064 [CLKID_SYS_PLL_DCO
] = &gxbb_sys_pll_dco
.hw
,
3065 [CLKID_GP0_PLL_DCO
] = &gxl_gp0_pll_dco
.hw
,
3066 [CLKID_VID_PLL_DIV
] = &gxbb_vid_pll_div
.hw
,
3067 [CLKID_VID_PLL_SEL
] = &gxbb_vid_pll_sel
.hw
,
3068 [CLKID_VID_PLL
] = &gxbb_vid_pll
.hw
,
3069 [CLKID_VCLK_SEL
] = &gxbb_vclk_sel
.hw
,
3070 [CLKID_VCLK2_SEL
] = &gxbb_vclk2_sel
.hw
,
3071 [CLKID_VCLK_INPUT
] = &gxbb_vclk_input
.hw
,
3072 [CLKID_VCLK2_INPUT
] = &gxbb_vclk2_input
.hw
,
3073 [CLKID_VCLK_DIV
] = &gxbb_vclk_div
.hw
,
3074 [CLKID_VCLK2_DIV
] = &gxbb_vclk2_div
.hw
,
3075 [CLKID_VCLK
] = &gxbb_vclk
.hw
,
3076 [CLKID_VCLK2
] = &gxbb_vclk2
.hw
,
3077 [CLKID_VCLK_DIV1
] = &gxbb_vclk_div1
.hw
,
3078 [CLKID_VCLK_DIV2_EN
] = &gxbb_vclk_div2_en
.hw
,
3079 [CLKID_VCLK_DIV2
] = &gxbb_vclk_div2
.hw
,
3080 [CLKID_VCLK_DIV4_EN
] = &gxbb_vclk_div4_en
.hw
,
3081 [CLKID_VCLK_DIV4
] = &gxbb_vclk_div4
.hw
,
3082 [CLKID_VCLK_DIV6_EN
] = &gxbb_vclk_div6_en
.hw
,
3083 [CLKID_VCLK_DIV6
] = &gxbb_vclk_div6
.hw
,
3084 [CLKID_VCLK_DIV12_EN
] = &gxbb_vclk_div12_en
.hw
,
3085 [CLKID_VCLK_DIV12
] = &gxbb_vclk_div12
.hw
,
3086 [CLKID_VCLK2_DIV1
] = &gxbb_vclk2_div1
.hw
,
3087 [CLKID_VCLK2_DIV2_EN
] = &gxbb_vclk2_div2_en
.hw
,
3088 [CLKID_VCLK2_DIV2
] = &gxbb_vclk2_div2
.hw
,
3089 [CLKID_VCLK2_DIV4_EN
] = &gxbb_vclk2_div4_en
.hw
,
3090 [CLKID_VCLK2_DIV4
] = &gxbb_vclk2_div4
.hw
,
3091 [CLKID_VCLK2_DIV6_EN
] = &gxbb_vclk2_div6_en
.hw
,
3092 [CLKID_VCLK2_DIV6
] = &gxbb_vclk2_div6
.hw
,
3093 [CLKID_VCLK2_DIV12_EN
] = &gxbb_vclk2_div12_en
.hw
,
3094 [CLKID_VCLK2_DIV12
] = &gxbb_vclk2_div12
.hw
,
3095 [CLKID_CTS_ENCI_SEL
] = &gxbb_cts_enci_sel
.hw
,
3096 [CLKID_CTS_ENCP_SEL
] = &gxbb_cts_encp_sel
.hw
,
3097 [CLKID_CTS_VDAC_SEL
] = &gxbb_cts_vdac_sel
.hw
,
3098 [CLKID_HDMI_TX_SEL
] = &gxbb_hdmi_tx_sel
.hw
,
3099 [CLKID_CTS_ENCI
] = &gxbb_cts_enci
.hw
,
3100 [CLKID_CTS_ENCP
] = &gxbb_cts_encp
.hw
,
3101 [CLKID_CTS_VDAC
] = &gxbb_cts_vdac
.hw
,
3102 [CLKID_HDMI_TX
] = &gxbb_hdmi_tx
.hw
,
3103 [CLKID_HDMI_SEL
] = &gxbb_hdmi_sel
.hw
,
3104 [CLKID_HDMI_DIV
] = &gxbb_hdmi_div
.hw
,
3105 [CLKID_HDMI
] = &gxbb_hdmi
.hw
,
3106 [CLKID_ACODEC
] = &gxl_acodec
.hw
,
3112 static struct clk_regmap
*const gxbb_clk_regmaps
[] = {
3160 &gxbb_hdmi_intr_sync
,
3162 &gxbb_usb1_ddr_bridge
,
3163 &gxbb_usb0_ddr_bridge
,
3169 &gxbb_sec_ahb_ahb3_bridge
,
3175 &gxbb_gclk_venci_int0
,
3176 &gxbb_gclk_vencp_int
,
3182 &gxbb_gclk_venci_int1
,
3183 &gxbb_vclk2_venclmcc
,
3199 &gxbb_cts_mclk_i958
,
3201 &gxbb_sd_emmc_a_clk0
,
3202 &gxbb_sd_emmc_b_clk0
,
3203 &gxbb_sd_emmc_c_clk0
,
3210 &gxbb_sar_adc_clk_div
,
3213 &gxbb_cts_mclk_i958_div
,
3215 &gxbb_sd_emmc_a_clk0_div
,
3216 &gxbb_sd_emmc_b_clk0_div
,
3217 &gxbb_sd_emmc_c_clk0_div
,
3223 &gxbb_sar_adc_clk_sel
,
3227 &gxbb_cts_amclk_sel
,
3228 &gxbb_cts_mclk_i958_sel
,
3231 &gxbb_sd_emmc_a_clk0_sel
,
3232 &gxbb_sd_emmc_b_clk0_sel
,
3233 &gxbb_sd_emmc_c_clk0_sel
,
3246 &gxbb_cts_amclk_div
,
3258 &gxbb_vdec_hevc_sel
,
3259 &gxbb_vdec_hevc_div
,
3264 &gxbb_fixed_pll_dco
,
3278 &gxbb_vclk_div12_en
,
3284 &gxbb_vclk2_div2_en
,
3285 &gxbb_vclk2_div4_en
,
3286 &gxbb_vclk2_div6_en
,
3287 &gxbb_vclk2_div12_en
,
3306 static struct clk_regmap
*const gxl_clk_regmaps
[] = {
3354 &gxbb_hdmi_intr_sync
,
3356 &gxbb_usb1_ddr_bridge
,
3357 &gxbb_usb0_ddr_bridge
,
3363 &gxbb_sec_ahb_ahb3_bridge
,
3369 &gxbb_gclk_venci_int0
,
3370 &gxbb_gclk_vencp_int
,
3376 &gxbb_gclk_venci_int1
,
3377 &gxbb_vclk2_venclmcc
,
3393 &gxbb_cts_mclk_i958
,
3395 &gxbb_sd_emmc_a_clk0
,
3396 &gxbb_sd_emmc_b_clk0
,
3397 &gxbb_sd_emmc_c_clk0
,
3404 &gxbb_sar_adc_clk_div
,
3407 &gxbb_cts_mclk_i958_div
,
3409 &gxbb_sd_emmc_a_clk0_div
,
3410 &gxbb_sd_emmc_b_clk0_div
,
3411 &gxbb_sd_emmc_c_clk0_div
,
3417 &gxbb_sar_adc_clk_sel
,
3421 &gxbb_cts_amclk_sel
,
3422 &gxbb_cts_mclk_i958_sel
,
3425 &gxbb_sd_emmc_a_clk0_sel
,
3426 &gxbb_sd_emmc_b_clk0_sel
,
3427 &gxbb_sd_emmc_c_clk0_sel
,
3440 &gxbb_cts_amclk_div
,
3452 &gxbb_vdec_hevc_sel
,
3453 &gxbb_vdec_hevc_div
,
3458 &gxbb_fixed_pll_dco
,
3472 &gxbb_vclk_div12_en
,
3478 &gxbb_vclk2_div2_en
,
3479 &gxbb_vclk2_div4_en
,
3480 &gxbb_vclk2_div6_en
,
3481 &gxbb_vclk2_div12_en
,
3501 static const struct meson_eeclkc_data gxbb_clkc_data
= {
3502 .regmap_clks
= gxbb_clk_regmaps
,
3503 .regmap_clk_num
= ARRAY_SIZE(gxbb_clk_regmaps
),
3504 .hw_onecell_data
= &gxbb_hw_onecell_data
,
3507 static const struct meson_eeclkc_data gxl_clkc_data
= {
3508 .regmap_clks
= gxl_clk_regmaps
,
3509 .regmap_clk_num
= ARRAY_SIZE(gxl_clk_regmaps
),
3510 .hw_onecell_data
= &gxl_hw_onecell_data
,
3513 static const struct of_device_id clkc_match_table
[] = {
3514 { .compatible
= "amlogic,gxbb-clkc", .data
= &gxbb_clkc_data
},
3515 { .compatible
= "amlogic,gxl-clkc", .data
= &gxl_clkc_data
},
3519 static struct platform_driver gxbb_driver
= {
3520 .probe
= meson_eeclkc_probe
,
3522 .name
= "gxbb-clkc",
3523 .of_match_table
= clkc_match_table
,
3527 builtin_platform_driver(gxbb_driver
);