2 * AmLogic S905 / GXBB Clock Controller Driver
4 * Copyright (c) 2016 AmLogic, Inc.
5 * Michael Turquette <mturquette@baylibre.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include <linux/clk.h>
21 #include <linux/clk-provider.h>
22 #include <linux/of_address.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/init.h>
30 static DEFINE_SPINLOCK(clk_lock
);
32 static const struct pll_rate_table sys_pll_rate_table
[] = {
33 PLL_RATE(24000000, 56, 1, 2),
34 PLL_RATE(48000000, 64, 1, 2),
35 PLL_RATE(72000000, 72, 1, 2),
36 PLL_RATE(96000000, 64, 1, 2),
37 PLL_RATE(120000000, 80, 1, 2),
38 PLL_RATE(144000000, 96, 1, 2),
39 PLL_RATE(168000000, 56, 1, 1),
40 PLL_RATE(192000000, 64, 1, 1),
41 PLL_RATE(216000000, 72, 1, 1),
42 PLL_RATE(240000000, 80, 1, 1),
43 PLL_RATE(264000000, 88, 1, 1),
44 PLL_RATE(288000000, 96, 1, 1),
45 PLL_RATE(312000000, 52, 1, 2),
46 PLL_RATE(336000000, 56, 1, 2),
47 PLL_RATE(360000000, 60, 1, 2),
48 PLL_RATE(384000000, 64, 1, 2),
49 PLL_RATE(408000000, 68, 1, 2),
50 PLL_RATE(432000000, 72, 1, 2),
51 PLL_RATE(456000000, 76, 1, 2),
52 PLL_RATE(480000000, 80, 1, 2),
53 PLL_RATE(504000000, 84, 1, 2),
54 PLL_RATE(528000000, 88, 1, 2),
55 PLL_RATE(552000000, 92, 1, 2),
56 PLL_RATE(576000000, 96, 1, 2),
57 PLL_RATE(600000000, 50, 1, 1),
58 PLL_RATE(624000000, 52, 1, 1),
59 PLL_RATE(648000000, 54, 1, 1),
60 PLL_RATE(672000000, 56, 1, 1),
61 PLL_RATE(696000000, 58, 1, 1),
62 PLL_RATE(720000000, 60, 1, 1),
63 PLL_RATE(744000000, 62, 1, 1),
64 PLL_RATE(768000000, 64, 1, 1),
65 PLL_RATE(792000000, 66, 1, 1),
66 PLL_RATE(816000000, 68, 1, 1),
67 PLL_RATE(840000000, 70, 1, 1),
68 PLL_RATE(864000000, 72, 1, 1),
69 PLL_RATE(888000000, 74, 1, 1),
70 PLL_RATE(912000000, 76, 1, 1),
71 PLL_RATE(936000000, 78, 1, 1),
72 PLL_RATE(960000000, 80, 1, 1),
73 PLL_RATE(984000000, 82, 1, 1),
74 PLL_RATE(1008000000, 84, 1, 1),
75 PLL_RATE(1032000000, 86, 1, 1),
76 PLL_RATE(1056000000, 88, 1, 1),
77 PLL_RATE(1080000000, 90, 1, 1),
78 PLL_RATE(1104000000, 92, 1, 1),
79 PLL_RATE(1128000000, 94, 1, 1),
80 PLL_RATE(1152000000, 96, 1, 1),
81 PLL_RATE(1176000000, 98, 1, 1),
82 PLL_RATE(1200000000, 50, 1, 0),
83 PLL_RATE(1224000000, 51, 1, 0),
84 PLL_RATE(1248000000, 52, 1, 0),
85 PLL_RATE(1272000000, 53, 1, 0),
86 PLL_RATE(1296000000, 54, 1, 0),
87 PLL_RATE(1320000000, 55, 1, 0),
88 PLL_RATE(1344000000, 56, 1, 0),
89 PLL_RATE(1368000000, 57, 1, 0),
90 PLL_RATE(1392000000, 58, 1, 0),
91 PLL_RATE(1416000000, 59, 1, 0),
92 PLL_RATE(1440000000, 60, 1, 0),
93 PLL_RATE(1464000000, 61, 1, 0),
94 PLL_RATE(1488000000, 62, 1, 0),
95 PLL_RATE(1512000000, 63, 1, 0),
96 PLL_RATE(1536000000, 64, 1, 0),
97 PLL_RATE(1560000000, 65, 1, 0),
98 PLL_RATE(1584000000, 66, 1, 0),
99 PLL_RATE(1608000000, 67, 1, 0),
100 PLL_RATE(1632000000, 68, 1, 0),
101 PLL_RATE(1656000000, 68, 1, 0),
102 PLL_RATE(1680000000, 68, 1, 0),
103 PLL_RATE(1704000000, 68, 1, 0),
104 PLL_RATE(1728000000, 69, 1, 0),
105 PLL_RATE(1752000000, 69, 1, 0),
106 PLL_RATE(1776000000, 69, 1, 0),
107 PLL_RATE(1800000000, 69, 1, 0),
108 PLL_RATE(1824000000, 70, 1, 0),
109 PLL_RATE(1848000000, 70, 1, 0),
110 PLL_RATE(1872000000, 70, 1, 0),
111 PLL_RATE(1896000000, 70, 1, 0),
112 PLL_RATE(1920000000, 71, 1, 0),
113 PLL_RATE(1944000000, 71, 1, 0),
114 PLL_RATE(1968000000, 71, 1, 0),
115 PLL_RATE(1992000000, 71, 1, 0),
116 PLL_RATE(2016000000, 72, 1, 0),
117 PLL_RATE(2040000000, 72, 1, 0),
118 PLL_RATE(2064000000, 72, 1, 0),
119 PLL_RATE(2088000000, 72, 1, 0),
120 PLL_RATE(2112000000, 73, 1, 0),
124 static const struct pll_rate_table gxbb_gp0_pll_rate_table
[] = {
125 PLL_RATE(96000000, 32, 1, 3),
126 PLL_RATE(99000000, 33, 1, 3),
127 PLL_RATE(102000000, 34, 1, 3),
128 PLL_RATE(105000000, 35, 1, 3),
129 PLL_RATE(108000000, 36, 1, 3),
130 PLL_RATE(111000000, 37, 1, 3),
131 PLL_RATE(114000000, 38, 1, 3),
132 PLL_RATE(117000000, 39, 1, 3),
133 PLL_RATE(120000000, 40, 1, 3),
134 PLL_RATE(123000000, 41, 1, 3),
135 PLL_RATE(126000000, 42, 1, 3),
136 PLL_RATE(129000000, 43, 1, 3),
137 PLL_RATE(132000000, 44, 1, 3),
138 PLL_RATE(135000000, 45, 1, 3),
139 PLL_RATE(138000000, 46, 1, 3),
140 PLL_RATE(141000000, 47, 1, 3),
141 PLL_RATE(144000000, 48, 1, 3),
142 PLL_RATE(147000000, 49, 1, 3),
143 PLL_RATE(150000000, 50, 1, 3),
144 PLL_RATE(153000000, 51, 1, 3),
145 PLL_RATE(156000000, 52, 1, 3),
146 PLL_RATE(159000000, 53, 1, 3),
147 PLL_RATE(162000000, 54, 1, 3),
148 PLL_RATE(165000000, 55, 1, 3),
149 PLL_RATE(168000000, 56, 1, 3),
150 PLL_RATE(171000000, 57, 1, 3),
151 PLL_RATE(174000000, 58, 1, 3),
152 PLL_RATE(177000000, 59, 1, 3),
153 PLL_RATE(180000000, 60, 1, 3),
154 PLL_RATE(183000000, 61, 1, 3),
155 PLL_RATE(186000000, 62, 1, 3),
156 PLL_RATE(192000000, 32, 1, 2),
157 PLL_RATE(198000000, 33, 1, 2),
158 PLL_RATE(204000000, 34, 1, 2),
159 PLL_RATE(210000000, 35, 1, 2),
160 PLL_RATE(216000000, 36, 1, 2),
161 PLL_RATE(222000000, 37, 1, 2),
162 PLL_RATE(228000000, 38, 1, 2),
163 PLL_RATE(234000000, 39, 1, 2),
164 PLL_RATE(240000000, 40, 1, 2),
165 PLL_RATE(246000000, 41, 1, 2),
166 PLL_RATE(252000000, 42, 1, 2),
167 PLL_RATE(258000000, 43, 1, 2),
168 PLL_RATE(264000000, 44, 1, 2),
169 PLL_RATE(270000000, 45, 1, 2),
170 PLL_RATE(276000000, 46, 1, 2),
171 PLL_RATE(282000000, 47, 1, 2),
172 PLL_RATE(288000000, 48, 1, 2),
173 PLL_RATE(294000000, 49, 1, 2),
174 PLL_RATE(300000000, 50, 1, 2),
175 PLL_RATE(306000000, 51, 1, 2),
176 PLL_RATE(312000000, 52, 1, 2),
177 PLL_RATE(318000000, 53, 1, 2),
178 PLL_RATE(324000000, 54, 1, 2),
179 PLL_RATE(330000000, 55, 1, 2),
180 PLL_RATE(336000000, 56, 1, 2),
181 PLL_RATE(342000000, 57, 1, 2),
182 PLL_RATE(348000000, 58, 1, 2),
183 PLL_RATE(354000000, 59, 1, 2),
184 PLL_RATE(360000000, 60, 1, 2),
185 PLL_RATE(366000000, 61, 1, 2),
186 PLL_RATE(372000000, 62, 1, 2),
187 PLL_RATE(384000000, 32, 1, 1),
188 PLL_RATE(396000000, 33, 1, 1),
189 PLL_RATE(408000000, 34, 1, 1),
190 PLL_RATE(420000000, 35, 1, 1),
191 PLL_RATE(432000000, 36, 1, 1),
192 PLL_RATE(444000000, 37, 1, 1),
193 PLL_RATE(456000000, 38, 1, 1),
194 PLL_RATE(468000000, 39, 1, 1),
195 PLL_RATE(480000000, 40, 1, 1),
196 PLL_RATE(492000000, 41, 1, 1),
197 PLL_RATE(504000000, 42, 1, 1),
198 PLL_RATE(516000000, 43, 1, 1),
199 PLL_RATE(528000000, 44, 1, 1),
200 PLL_RATE(540000000, 45, 1, 1),
201 PLL_RATE(552000000, 46, 1, 1),
202 PLL_RATE(564000000, 47, 1, 1),
203 PLL_RATE(576000000, 48, 1, 1),
204 PLL_RATE(588000000, 49, 1, 1),
205 PLL_RATE(600000000, 50, 1, 1),
206 PLL_RATE(612000000, 51, 1, 1),
207 PLL_RATE(624000000, 52, 1, 1),
208 PLL_RATE(636000000, 53, 1, 1),
209 PLL_RATE(648000000, 54, 1, 1),
210 PLL_RATE(660000000, 55, 1, 1),
211 PLL_RATE(672000000, 56, 1, 1),
212 PLL_RATE(684000000, 57, 1, 1),
213 PLL_RATE(696000000, 58, 1, 1),
214 PLL_RATE(708000000, 59, 1, 1),
215 PLL_RATE(720000000, 60, 1, 1),
216 PLL_RATE(732000000, 61, 1, 1),
217 PLL_RATE(744000000, 62, 1, 1),
218 PLL_RATE(768000000, 32, 1, 0),
219 PLL_RATE(792000000, 33, 1, 0),
220 PLL_RATE(816000000, 34, 1, 0),
221 PLL_RATE(840000000, 35, 1, 0),
222 PLL_RATE(864000000, 36, 1, 0),
223 PLL_RATE(888000000, 37, 1, 0),
224 PLL_RATE(912000000, 38, 1, 0),
225 PLL_RATE(936000000, 39, 1, 0),
226 PLL_RATE(960000000, 40, 1, 0),
227 PLL_RATE(984000000, 41, 1, 0),
228 PLL_RATE(1008000000, 42, 1, 0),
229 PLL_RATE(1032000000, 43, 1, 0),
230 PLL_RATE(1056000000, 44, 1, 0),
231 PLL_RATE(1080000000, 45, 1, 0),
232 PLL_RATE(1104000000, 46, 1, 0),
233 PLL_RATE(1128000000, 47, 1, 0),
234 PLL_RATE(1152000000, 48, 1, 0),
235 PLL_RATE(1176000000, 49, 1, 0),
236 PLL_RATE(1200000000, 50, 1, 0),
237 PLL_RATE(1224000000, 51, 1, 0),
238 PLL_RATE(1248000000, 52, 1, 0),
239 PLL_RATE(1272000000, 53, 1, 0),
240 PLL_RATE(1296000000, 54, 1, 0),
241 PLL_RATE(1320000000, 55, 1, 0),
242 PLL_RATE(1344000000, 56, 1, 0),
243 PLL_RATE(1368000000, 57, 1, 0),
244 PLL_RATE(1392000000, 58, 1, 0),
245 PLL_RATE(1416000000, 59, 1, 0),
246 PLL_RATE(1440000000, 60, 1, 0),
247 PLL_RATE(1464000000, 61, 1, 0),
248 PLL_RATE(1488000000, 62, 1, 0),
252 static const struct pll_rate_table gxl_gp0_pll_rate_table
[] = {
253 PLL_RATE(504000000, 42, 1, 1),
254 PLL_RATE(516000000, 43, 1, 1),
255 PLL_RATE(528000000, 44, 1, 1),
256 PLL_RATE(540000000, 45, 1, 1),
257 PLL_RATE(552000000, 46, 1, 1),
258 PLL_RATE(564000000, 47, 1, 1),
259 PLL_RATE(576000000, 48, 1, 1),
260 PLL_RATE(588000000, 49, 1, 1),
261 PLL_RATE(600000000, 50, 1, 1),
262 PLL_RATE(612000000, 51, 1, 1),
263 PLL_RATE(624000000, 52, 1, 1),
264 PLL_RATE(636000000, 53, 1, 1),
265 PLL_RATE(648000000, 54, 1, 1),
266 PLL_RATE(660000000, 55, 1, 1),
267 PLL_RATE(672000000, 56, 1, 1),
268 PLL_RATE(684000000, 57, 1, 1),
269 PLL_RATE(696000000, 58, 1, 1),
270 PLL_RATE(708000000, 59, 1, 1),
271 PLL_RATE(720000000, 60, 1, 1),
272 PLL_RATE(732000000, 61, 1, 1),
273 PLL_RATE(744000000, 62, 1, 1),
274 PLL_RATE(756000000, 63, 1, 1),
275 PLL_RATE(768000000, 64, 1, 1),
276 PLL_RATE(780000000, 65, 1, 1),
277 PLL_RATE(792000000, 66, 1, 1),
281 static struct meson_clk_pll gxbb_fixed_pll
= {
283 .reg_off
= HHI_MPLL_CNTL
,
288 .reg_off
= HHI_MPLL_CNTL
,
293 .reg_off
= HHI_MPLL_CNTL
,
298 .hw
.init
= &(struct clk_init_data
){
300 .ops
= &meson_clk_pll_ro_ops
,
301 .parent_names
= (const char *[]){ "xtal" },
303 .flags
= CLK_GET_RATE_NOCACHE
,
307 static struct meson_clk_pll gxbb_hdmi_pll
= {
309 .reg_off
= HHI_HDMI_PLL_CNTL
,
314 .reg_off
= HHI_HDMI_PLL_CNTL
,
319 .reg_off
= HHI_HDMI_PLL_CNTL2
,
324 .reg_off
= HHI_HDMI_PLL_CNTL2
,
329 .reg_off
= HHI_HDMI_PLL_CNTL2
,
334 .hw
.init
= &(struct clk_init_data
){
336 .ops
= &meson_clk_pll_ro_ops
,
337 .parent_names
= (const char *[]){ "xtal" },
339 .flags
= CLK_GET_RATE_NOCACHE
,
343 static struct meson_clk_pll gxbb_sys_pll
= {
345 .reg_off
= HHI_SYS_PLL_CNTL
,
350 .reg_off
= HHI_SYS_PLL_CNTL
,
355 .reg_off
= HHI_SYS_PLL_CNTL
,
359 .rate_table
= sys_pll_rate_table
,
360 .rate_count
= ARRAY_SIZE(sys_pll_rate_table
),
362 .hw
.init
= &(struct clk_init_data
){
364 .ops
= &meson_clk_pll_ro_ops
,
365 .parent_names
= (const char *[]){ "xtal" },
367 .flags
= CLK_GET_RATE_NOCACHE
,
371 struct pll_params_table gxbb_gp0_params_table
[] = {
372 PLL_PARAM(HHI_GP0_PLL_CNTL
, 0x6a000228),
373 PLL_PARAM(HHI_GP0_PLL_CNTL2
, 0x69c80000),
374 PLL_PARAM(HHI_GP0_PLL_CNTL3
, 0x0a5590c4),
375 PLL_PARAM(HHI_GP0_PLL_CNTL4
, 0x0000500d),
378 static struct meson_clk_pll gxbb_gp0_pll
= {
380 .reg_off
= HHI_GP0_PLL_CNTL
,
385 .reg_off
= HHI_GP0_PLL_CNTL
,
390 .reg_off
= HHI_GP0_PLL_CNTL
,
395 .params_table
= gxbb_gp0_params_table
,
396 .params_count
= ARRAY_SIZE(gxbb_gp0_params_table
),
397 .no_init_reset
= true,
398 .clear_reset_for_lock
= true,
400 .rate_table
= gxbb_gp0_pll_rate_table
,
401 .rate_count
= ARRAY_SIZE(gxbb_gp0_pll_rate_table
),
403 .hw
.init
= &(struct clk_init_data
){
405 .ops
= &meson_clk_pll_ops
,
406 .parent_names
= (const char *[]){ "xtal" },
408 .flags
= CLK_GET_RATE_NOCACHE
,
412 struct pll_params_table gxl_gp0_params_table
[] = {
413 PLL_PARAM(HHI_GP0_PLL_CNTL
, 0x40010250),
414 PLL_PARAM(HHI_GP0_PLL_CNTL1
, 0xc084a000),
415 PLL_PARAM(HHI_GP0_PLL_CNTL2
, 0xb75020be),
416 PLL_PARAM(HHI_GP0_PLL_CNTL3
, 0x0a59a288),
417 PLL_PARAM(HHI_GP0_PLL_CNTL4
, 0xc000004d),
418 PLL_PARAM(HHI_GP0_PLL_CNTL5
, 0x00078000),
421 static struct meson_clk_pll gxl_gp0_pll
= {
423 .reg_off
= HHI_GP0_PLL_CNTL
,
428 .reg_off
= HHI_GP0_PLL_CNTL
,
433 .reg_off
= HHI_GP0_PLL_CNTL
,
438 .params_table
= gxl_gp0_params_table
,
439 .params_count
= ARRAY_SIZE(gxl_gp0_params_table
),
440 .no_init_reset
= true,
441 .reset_lock_loop
= true,
443 .rate_table
= gxl_gp0_pll_rate_table
,
444 .rate_count
= ARRAY_SIZE(gxl_gp0_pll_rate_table
),
446 .hw
.init
= &(struct clk_init_data
){
448 .ops
= &meson_clk_pll_ops
,
449 .parent_names
= (const char *[]){ "xtal" },
451 .flags
= CLK_GET_RATE_NOCACHE
,
455 static struct clk_fixed_factor gxbb_fclk_div2
= {
458 .hw
.init
= &(struct clk_init_data
){
460 .ops
= &clk_fixed_factor_ops
,
461 .parent_names
= (const char *[]){ "fixed_pll" },
466 static struct clk_fixed_factor gxbb_fclk_div3
= {
469 .hw
.init
= &(struct clk_init_data
){
471 .ops
= &clk_fixed_factor_ops
,
472 .parent_names
= (const char *[]){ "fixed_pll" },
477 static struct clk_fixed_factor gxbb_fclk_div4
= {
480 .hw
.init
= &(struct clk_init_data
){
482 .ops
= &clk_fixed_factor_ops
,
483 .parent_names
= (const char *[]){ "fixed_pll" },
488 static struct clk_fixed_factor gxbb_fclk_div5
= {
491 .hw
.init
= &(struct clk_init_data
){
493 .ops
= &clk_fixed_factor_ops
,
494 .parent_names
= (const char *[]){ "fixed_pll" },
499 static struct clk_fixed_factor gxbb_fclk_div7
= {
502 .hw
.init
= &(struct clk_init_data
){
504 .ops
= &clk_fixed_factor_ops
,
505 .parent_names
= (const char *[]){ "fixed_pll" },
510 static struct meson_clk_mpll gxbb_mpll0
= {
512 .reg_off
= HHI_MPLL_CNTL7
,
517 .reg_off
= HHI_MPLL_CNTL7
,
522 .reg_off
= HHI_MPLL_CNTL7
,
527 .reg_off
= HHI_MPLL_CNTL7
,
532 .reg_off
= HHI_MPLL_CNTL
,
537 .hw
.init
= &(struct clk_init_data
){
539 .ops
= &meson_clk_mpll_ops
,
540 .parent_names
= (const char *[]){ "fixed_pll" },
545 static struct meson_clk_mpll gxbb_mpll1
= {
547 .reg_off
= HHI_MPLL_CNTL8
,
552 .reg_off
= HHI_MPLL_CNTL8
,
557 .reg_off
= HHI_MPLL_CNTL8
,
562 .reg_off
= HHI_MPLL_CNTL8
,
567 .hw
.init
= &(struct clk_init_data
){
569 .ops
= &meson_clk_mpll_ops
,
570 .parent_names
= (const char *[]){ "fixed_pll" },
575 static struct meson_clk_mpll gxbb_mpll2
= {
577 .reg_off
= HHI_MPLL_CNTL9
,
582 .reg_off
= HHI_MPLL_CNTL9
,
587 .reg_off
= HHI_MPLL_CNTL9
,
592 .reg_off
= HHI_MPLL_CNTL9
,
597 .hw
.init
= &(struct clk_init_data
){
599 .ops
= &meson_clk_mpll_ops
,
600 .parent_names
= (const char *[]){ "fixed_pll" },
606 * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers
607 * and should be modeled with their respective PLLs via the forthcoming
608 * coordinated clock rates feature
611 static u32 mux_table_clk81
[] = { 0, 2, 3, 4, 5, 6, 7 };
612 static const char * const clk81_parent_names
[] = {
613 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
614 "fclk_div3", "fclk_div5"
617 static struct clk_mux gxbb_mpeg_clk_sel
= {
618 .reg
= (void *)HHI_MPEG_CLK_CNTL
,
621 .flags
= CLK_MUX_READ_ONLY
,
622 .table
= mux_table_clk81
,
624 .hw
.init
= &(struct clk_init_data
){
625 .name
= "mpeg_clk_sel",
626 .ops
= &clk_mux_ro_ops
,
628 * bits 14:12 selects from 8 possible parents:
629 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
630 * fclk_div4, fclk_div3, fclk_div5
632 .parent_names
= clk81_parent_names
,
633 .num_parents
= ARRAY_SIZE(clk81_parent_names
),
634 .flags
= (CLK_SET_RATE_NO_REPARENT
| CLK_IGNORE_UNUSED
),
638 static struct clk_divider gxbb_mpeg_clk_div
= {
639 .reg
= (void *)HHI_MPEG_CLK_CNTL
,
643 .hw
.init
= &(struct clk_init_data
){
644 .name
= "mpeg_clk_div",
645 .ops
= &clk_divider_ops
,
646 .parent_names
= (const char *[]){ "mpeg_clk_sel" },
648 .flags
= (CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
),
652 /* the mother of dragons^W gates */
653 static struct clk_gate gxbb_clk81
= {
654 .reg
= (void *)HHI_MPEG_CLK_CNTL
,
657 .hw
.init
= &(struct clk_init_data
){
659 .ops
= &clk_gate_ops
,
660 .parent_names
= (const char *[]){ "mpeg_clk_div" },
662 .flags
= (CLK_SET_RATE_PARENT
| CLK_IS_CRITICAL
),
666 static struct clk_mux gxbb_sar_adc_clk_sel
= {
667 .reg
= (void *)HHI_SAR_CLK_CNTL
,
671 .hw
.init
= &(struct clk_init_data
){
672 .name
= "sar_adc_clk_sel",
674 /* NOTE: The datasheet doesn't list the parents for bit 10 */
675 .parent_names
= (const char *[]){ "xtal", "clk81", },
680 static struct clk_divider gxbb_sar_adc_clk_div
= {
681 .reg
= (void *)HHI_SAR_CLK_CNTL
,
685 .hw
.init
= &(struct clk_init_data
){
686 .name
= "sar_adc_clk_div",
687 .ops
= &clk_divider_ops
,
688 .parent_names
= (const char *[]){ "sar_adc_clk_sel" },
693 static struct clk_gate gxbb_sar_adc_clk
= {
694 .reg
= (void *)HHI_SAR_CLK_CNTL
,
697 .hw
.init
= &(struct clk_init_data
){
698 .name
= "sar_adc_clk",
699 .ops
= &clk_gate_ops
,
700 .parent_names
= (const char *[]){ "sar_adc_clk_div" },
702 .flags
= CLK_SET_RATE_PARENT
,
707 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
708 * muxed by a glitch-free switch.
711 static u32 mux_table_mali_0_1
[] = {0, 1, 2, 3, 4, 5, 6, 7};
712 static const char * const gxbb_mali_0_1_parent_names
[] = {
713 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
714 "fclk_div4", "fclk_div3", "fclk_div5"
717 static struct clk_mux gxbb_mali_0_sel
= {
718 .reg
= (void *)HHI_MALI_CLK_CNTL
,
721 .table
= mux_table_mali_0_1
,
723 .hw
.init
= &(struct clk_init_data
){
724 .name
= "mali_0_sel",
727 * bits 10:9 selects from 8 possible parents:
728 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
729 * fclk_div4, fclk_div3, fclk_div5
731 .parent_names
= gxbb_mali_0_1_parent_names
,
733 .flags
= CLK_SET_RATE_NO_REPARENT
,
737 static struct clk_divider gxbb_mali_0_div
= {
738 .reg
= (void *)HHI_MALI_CLK_CNTL
,
742 .hw
.init
= &(struct clk_init_data
){
743 .name
= "mali_0_div",
744 .ops
= &clk_divider_ops
,
745 .parent_names
= (const char *[]){ "mali_0_sel" },
747 .flags
= CLK_SET_RATE_NO_REPARENT
,
751 static struct clk_gate gxbb_mali_0
= {
752 .reg
= (void *)HHI_MALI_CLK_CNTL
,
755 .hw
.init
= &(struct clk_init_data
){
757 .ops
= &clk_gate_ops
,
758 .parent_names
= (const char *[]){ "mali_0_div" },
760 .flags
= CLK_SET_RATE_PARENT
,
764 static struct clk_mux gxbb_mali_1_sel
= {
765 .reg
= (void *)HHI_MALI_CLK_CNTL
,
768 .table
= mux_table_mali_0_1
,
770 .hw
.init
= &(struct clk_init_data
){
771 .name
= "mali_1_sel",
774 * bits 10:9 selects from 8 possible parents:
775 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
776 * fclk_div4, fclk_div3, fclk_div5
778 .parent_names
= gxbb_mali_0_1_parent_names
,
780 .flags
= CLK_SET_RATE_NO_REPARENT
,
784 static struct clk_divider gxbb_mali_1_div
= {
785 .reg
= (void *)HHI_MALI_CLK_CNTL
,
789 .hw
.init
= &(struct clk_init_data
){
790 .name
= "mali_1_div",
791 .ops
= &clk_divider_ops
,
792 .parent_names
= (const char *[]){ "mali_1_sel" },
794 .flags
= CLK_SET_RATE_NO_REPARENT
,
798 static struct clk_gate gxbb_mali_1
= {
799 .reg
= (void *)HHI_MALI_CLK_CNTL
,
802 .hw
.init
= &(struct clk_init_data
){
804 .ops
= &clk_gate_ops
,
805 .parent_names
= (const char *[]){ "mali_1_div" },
807 .flags
= CLK_SET_RATE_PARENT
,
811 static u32 mux_table_mali
[] = {0, 1};
812 static const char * const gxbb_mali_parent_names
[] = {
816 static struct clk_mux gxbb_mali
= {
817 .reg
= (void *)HHI_MALI_CLK_CNTL
,
820 .table
= mux_table_mali
,
822 .hw
.init
= &(struct clk_init_data
){
825 .parent_names
= gxbb_mali_parent_names
,
827 .flags
= CLK_SET_RATE_NO_REPARENT
,
831 static struct clk_mux gxbb_cts_amclk_sel
= {
832 .reg
= (void *) HHI_AUD_CLK_CNTL
,
835 /* Default parent unknown (register reset value: 0) */
836 .table
= (u32
[]){ 1, 2, 3 },
838 .hw
.init
= &(struct clk_init_data
){
839 .name
= "cts_amclk_sel",
841 .parent_names
= (const char *[]){ "mpll0", "mpll1", "mpll2" },
843 .flags
= CLK_SET_RATE_PARENT
,
847 static struct meson_clk_audio_divider gxbb_cts_amclk_div
= {
849 .reg_off
= HHI_AUD_CLK_CNTL
,
854 .hw
.init
= &(struct clk_init_data
){
855 .name
= "cts_amclk_div",
856 .ops
= &meson_clk_audio_divider_ops
,
857 .parent_names
= (const char *[]){ "cts_amclk_sel" },
859 .flags
= CLK_SET_RATE_PARENT
| CLK_DIVIDER_ROUND_CLOSEST
,
863 static struct clk_gate gxbb_cts_amclk
= {
864 .reg
= (void *) HHI_AUD_CLK_CNTL
,
867 .hw
.init
= &(struct clk_init_data
){
869 .ops
= &clk_gate_ops
,
870 .parent_names
= (const char *[]){ "cts_amclk_div" },
872 .flags
= CLK_SET_RATE_PARENT
,
876 static struct clk_mux gxbb_cts_mclk_i958_sel
= {
877 .reg
= (void *)HHI_AUD_CLK_CNTL2
,
880 /* Default parent unknown (register reset value: 0) */
881 .table
= (u32
[]){ 1, 2, 3 },
883 .hw
.init
= &(struct clk_init_data
){
884 .name
= "cts_mclk_i958_sel",
886 .parent_names
= (const char *[]){ "mpll0", "mpll1", "mpll2" },
888 .flags
= CLK_SET_RATE_PARENT
,
892 static struct clk_divider gxbb_cts_mclk_i958_div
= {
893 .reg
= (void *)HHI_AUD_CLK_CNTL2
,
897 .hw
.init
= &(struct clk_init_data
){
898 .name
= "cts_mclk_i958_div",
899 .ops
= &clk_divider_ops
,
900 .parent_names
= (const char *[]){ "cts_mclk_i958_sel" },
902 .flags
= CLK_SET_RATE_PARENT
| CLK_DIVIDER_ROUND_CLOSEST
,
906 static struct clk_gate gxbb_cts_mclk_i958
= {
907 .reg
= (void *)HHI_AUD_CLK_CNTL2
,
910 .hw
.init
= &(struct clk_init_data
){
911 .name
= "cts_mclk_i958",
912 .ops
= &clk_gate_ops
,
913 .parent_names
= (const char *[]){ "cts_mclk_i958_div" },
915 .flags
= CLK_SET_RATE_PARENT
,
919 static struct clk_mux gxbb_cts_i958
= {
920 .reg
= (void *)HHI_AUD_CLK_CNTL2
,
924 .hw
.init
= &(struct clk_init_data
){
927 .parent_names
= (const char *[]){ "cts_amclk", "cts_mclk_i958" },
930 *The parent is specific to origin of the audio data. Let the
931 * consumer choose the appropriate parent
933 .flags
= CLK_SET_RATE_PARENT
| CLK_SET_RATE_NO_REPARENT
,
937 static struct clk_divider gxbb_32k_clk_div
= {
938 .reg
= (void *)HHI_32K_CLK_CNTL
,
942 .hw
.init
= &(struct clk_init_data
){
943 .name
= "32k_clk_div",
944 .ops
= &clk_divider_ops
,
945 .parent_names
= (const char *[]){ "32k_clk_sel" },
947 .flags
= CLK_SET_RATE_PARENT
| CLK_DIVIDER_ROUND_CLOSEST
,
951 static struct clk_gate gxbb_32k_clk
= {
952 .reg
= (void *)HHI_32K_CLK_CNTL
,
955 .hw
.init
= &(struct clk_init_data
){
957 .ops
= &clk_gate_ops
,
958 .parent_names
= (const char *[]){ "32k_clk_div" },
960 .flags
= CLK_SET_RATE_PARENT
,
964 static const char * const gxbb_32k_clk_parent_names
[] = {
965 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
968 static struct clk_mux gxbb_32k_clk_sel
= {
969 .reg
= (void *)HHI_32K_CLK_CNTL
,
973 .hw
.init
= &(struct clk_init_data
){
974 .name
= "32k_clk_sel",
976 .parent_names
= gxbb_32k_clk_parent_names
,
978 .flags
= CLK_SET_RATE_PARENT
,
982 /* Everything Else (EE) domain gates */
983 static MESON_GATE(gxbb_ddr
, HHI_GCLK_MPEG0
, 0);
984 static MESON_GATE(gxbb_dos
, HHI_GCLK_MPEG0
, 1);
985 static MESON_GATE(gxbb_isa
, HHI_GCLK_MPEG0
, 5);
986 static MESON_GATE(gxbb_pl301
, HHI_GCLK_MPEG0
, 6);
987 static MESON_GATE(gxbb_periphs
, HHI_GCLK_MPEG0
, 7);
988 static MESON_GATE(gxbb_spicc
, HHI_GCLK_MPEG0
, 8);
989 static MESON_GATE(gxbb_i2c
, HHI_GCLK_MPEG0
, 9);
990 static MESON_GATE(gxbb_sar_adc
, HHI_GCLK_MPEG0
, 10);
991 static MESON_GATE(gxbb_smart_card
, HHI_GCLK_MPEG0
, 11);
992 static MESON_GATE(gxbb_rng0
, HHI_GCLK_MPEG0
, 12);
993 static MESON_GATE(gxbb_uart0
, HHI_GCLK_MPEG0
, 13);
994 static MESON_GATE(gxbb_sdhc
, HHI_GCLK_MPEG0
, 14);
995 static MESON_GATE(gxbb_stream
, HHI_GCLK_MPEG0
, 15);
996 static MESON_GATE(gxbb_async_fifo
, HHI_GCLK_MPEG0
, 16);
997 static MESON_GATE(gxbb_sdio
, HHI_GCLK_MPEG0
, 17);
998 static MESON_GATE(gxbb_abuf
, HHI_GCLK_MPEG0
, 18);
999 static MESON_GATE(gxbb_hiu_iface
, HHI_GCLK_MPEG0
, 19);
1000 static MESON_GATE(gxbb_assist_misc
, HHI_GCLK_MPEG0
, 23);
1001 static MESON_GATE(gxbb_emmc_a
, HHI_GCLK_MPEG0
, 24);
1002 static MESON_GATE(gxbb_emmc_b
, HHI_GCLK_MPEG0
, 25);
1003 static MESON_GATE(gxbb_emmc_c
, HHI_GCLK_MPEG0
, 26);
1004 static MESON_GATE(gxbb_spi
, HHI_GCLK_MPEG0
, 30);
1006 static MESON_GATE(gxbb_i2s_spdif
, HHI_GCLK_MPEG1
, 2);
1007 static MESON_GATE(gxbb_eth
, HHI_GCLK_MPEG1
, 3);
1008 static MESON_GATE(gxbb_demux
, HHI_GCLK_MPEG1
, 4);
1009 static MESON_GATE(gxbb_aiu_glue
, HHI_GCLK_MPEG1
, 6);
1010 static MESON_GATE(gxbb_iec958
, HHI_GCLK_MPEG1
, 7);
1011 static MESON_GATE(gxbb_i2s_out
, HHI_GCLK_MPEG1
, 8);
1012 static MESON_GATE(gxbb_amclk
, HHI_GCLK_MPEG1
, 9);
1013 static MESON_GATE(gxbb_aififo2
, HHI_GCLK_MPEG1
, 10);
1014 static MESON_GATE(gxbb_mixer
, HHI_GCLK_MPEG1
, 11);
1015 static MESON_GATE(gxbb_mixer_iface
, HHI_GCLK_MPEG1
, 12);
1016 static MESON_GATE(gxbb_adc
, HHI_GCLK_MPEG1
, 13);
1017 static MESON_GATE(gxbb_blkmv
, HHI_GCLK_MPEG1
, 14);
1018 static MESON_GATE(gxbb_aiu
, HHI_GCLK_MPEG1
, 15);
1019 static MESON_GATE(gxbb_uart1
, HHI_GCLK_MPEG1
, 16);
1020 static MESON_GATE(gxbb_g2d
, HHI_GCLK_MPEG1
, 20);
1021 static MESON_GATE(gxbb_usb0
, HHI_GCLK_MPEG1
, 21);
1022 static MESON_GATE(gxbb_usb1
, HHI_GCLK_MPEG1
, 22);
1023 static MESON_GATE(gxbb_reset
, HHI_GCLK_MPEG1
, 23);
1024 static MESON_GATE(gxbb_nand
, HHI_GCLK_MPEG1
, 24);
1025 static MESON_GATE(gxbb_dos_parser
, HHI_GCLK_MPEG1
, 25);
1026 static MESON_GATE(gxbb_usb
, HHI_GCLK_MPEG1
, 26);
1027 static MESON_GATE(gxbb_vdin1
, HHI_GCLK_MPEG1
, 28);
1028 static MESON_GATE(gxbb_ahb_arb0
, HHI_GCLK_MPEG1
, 29);
1029 static MESON_GATE(gxbb_efuse
, HHI_GCLK_MPEG1
, 30);
1030 static MESON_GATE(gxbb_boot_rom
, HHI_GCLK_MPEG1
, 31);
1032 static MESON_GATE(gxbb_ahb_data_bus
, HHI_GCLK_MPEG2
, 1);
1033 static MESON_GATE(gxbb_ahb_ctrl_bus
, HHI_GCLK_MPEG2
, 2);
1034 static MESON_GATE(gxbb_hdmi_intr_sync
, HHI_GCLK_MPEG2
, 3);
1035 static MESON_GATE(gxbb_hdmi_pclk
, HHI_GCLK_MPEG2
, 4);
1036 static MESON_GATE(gxbb_usb1_ddr_bridge
, HHI_GCLK_MPEG2
, 8);
1037 static MESON_GATE(gxbb_usb0_ddr_bridge
, HHI_GCLK_MPEG2
, 9);
1038 static MESON_GATE(gxbb_mmc_pclk
, HHI_GCLK_MPEG2
, 11);
1039 static MESON_GATE(gxbb_dvin
, HHI_GCLK_MPEG2
, 12);
1040 static MESON_GATE(gxbb_uart2
, HHI_GCLK_MPEG2
, 15);
1041 static MESON_GATE(gxbb_sana
, HHI_GCLK_MPEG2
, 22);
1042 static MESON_GATE(gxbb_vpu_intr
, HHI_GCLK_MPEG2
, 25);
1043 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge
, HHI_GCLK_MPEG2
, 26);
1044 static MESON_GATE(gxbb_clk81_a53
, HHI_GCLK_MPEG2
, 29);
1046 static MESON_GATE(gxbb_vclk2_venci0
, HHI_GCLK_OTHER
, 1);
1047 static MESON_GATE(gxbb_vclk2_venci1
, HHI_GCLK_OTHER
, 2);
1048 static MESON_GATE(gxbb_vclk2_vencp0
, HHI_GCLK_OTHER
, 3);
1049 static MESON_GATE(gxbb_vclk2_vencp1
, HHI_GCLK_OTHER
, 4);
1050 static MESON_GATE(gxbb_gclk_venci_int0
, HHI_GCLK_OTHER
, 8);
1051 static MESON_GATE(gxbb_gclk_vencp_int
, HHI_GCLK_OTHER
, 9);
1052 static MESON_GATE(gxbb_dac_clk
, HHI_GCLK_OTHER
, 10);
1053 static MESON_GATE(gxbb_aoclk_gate
, HHI_GCLK_OTHER
, 14);
1054 static MESON_GATE(gxbb_iec958_gate
, HHI_GCLK_OTHER
, 16);
1055 static MESON_GATE(gxbb_enc480p
, HHI_GCLK_OTHER
, 20);
1056 static MESON_GATE(gxbb_rng1
, HHI_GCLK_OTHER
, 21);
1057 static MESON_GATE(gxbb_gclk_venci_int1
, HHI_GCLK_OTHER
, 22);
1058 static MESON_GATE(gxbb_vclk2_venclmcc
, HHI_GCLK_OTHER
, 24);
1059 static MESON_GATE(gxbb_vclk2_vencl
, HHI_GCLK_OTHER
, 25);
1060 static MESON_GATE(gxbb_vclk_other
, HHI_GCLK_OTHER
, 26);
1061 static MESON_GATE(gxbb_edp
, HHI_GCLK_OTHER
, 31);
1063 /* Always On (AO) domain gates */
1065 static MESON_GATE(gxbb_ao_media_cpu
, HHI_GCLK_AO
, 0);
1066 static MESON_GATE(gxbb_ao_ahb_sram
, HHI_GCLK_AO
, 1);
1067 static MESON_GATE(gxbb_ao_ahb_bus
, HHI_GCLK_AO
, 2);
1068 static MESON_GATE(gxbb_ao_iface
, HHI_GCLK_AO
, 3);
1069 static MESON_GATE(gxbb_ao_i2c
, HHI_GCLK_AO
, 4);
1071 /* Array of all clocks provided by this provider */
1073 static struct clk_hw_onecell_data gxbb_hw_onecell_data
= {
1075 [CLKID_SYS_PLL
] = &gxbb_sys_pll
.hw
,
1076 [CLKID_HDMI_PLL
] = &gxbb_hdmi_pll
.hw
,
1077 [CLKID_FIXED_PLL
] = &gxbb_fixed_pll
.hw
,
1078 [CLKID_FCLK_DIV2
] = &gxbb_fclk_div2
.hw
,
1079 [CLKID_FCLK_DIV3
] = &gxbb_fclk_div3
.hw
,
1080 [CLKID_FCLK_DIV4
] = &gxbb_fclk_div4
.hw
,
1081 [CLKID_FCLK_DIV5
] = &gxbb_fclk_div5
.hw
,
1082 [CLKID_FCLK_DIV7
] = &gxbb_fclk_div7
.hw
,
1083 [CLKID_GP0_PLL
] = &gxbb_gp0_pll
.hw
,
1084 [CLKID_MPEG_SEL
] = &gxbb_mpeg_clk_sel
.hw
,
1085 [CLKID_MPEG_DIV
] = &gxbb_mpeg_clk_div
.hw
,
1086 [CLKID_CLK81
] = &gxbb_clk81
.hw
,
1087 [CLKID_MPLL0
] = &gxbb_mpll0
.hw
,
1088 [CLKID_MPLL1
] = &gxbb_mpll1
.hw
,
1089 [CLKID_MPLL2
] = &gxbb_mpll2
.hw
,
1090 [CLKID_DDR
] = &gxbb_ddr
.hw
,
1091 [CLKID_DOS
] = &gxbb_dos
.hw
,
1092 [CLKID_ISA
] = &gxbb_isa
.hw
,
1093 [CLKID_PL301
] = &gxbb_pl301
.hw
,
1094 [CLKID_PERIPHS
] = &gxbb_periphs
.hw
,
1095 [CLKID_SPICC
] = &gxbb_spicc
.hw
,
1096 [CLKID_I2C
] = &gxbb_i2c
.hw
,
1097 [CLKID_SAR_ADC
] = &gxbb_sar_adc
.hw
,
1098 [CLKID_SMART_CARD
] = &gxbb_smart_card
.hw
,
1099 [CLKID_RNG0
] = &gxbb_rng0
.hw
,
1100 [CLKID_UART0
] = &gxbb_uart0
.hw
,
1101 [CLKID_SDHC
] = &gxbb_sdhc
.hw
,
1102 [CLKID_STREAM
] = &gxbb_stream
.hw
,
1103 [CLKID_ASYNC_FIFO
] = &gxbb_async_fifo
.hw
,
1104 [CLKID_SDIO
] = &gxbb_sdio
.hw
,
1105 [CLKID_ABUF
] = &gxbb_abuf
.hw
,
1106 [CLKID_HIU_IFACE
] = &gxbb_hiu_iface
.hw
,
1107 [CLKID_ASSIST_MISC
] = &gxbb_assist_misc
.hw
,
1108 [CLKID_SPI
] = &gxbb_spi
.hw
,
1109 [CLKID_I2S_SPDIF
] = &gxbb_i2s_spdif
.hw
,
1110 [CLKID_ETH
] = &gxbb_eth
.hw
,
1111 [CLKID_DEMUX
] = &gxbb_demux
.hw
,
1112 [CLKID_AIU_GLUE
] = &gxbb_aiu_glue
.hw
,
1113 [CLKID_IEC958
] = &gxbb_iec958
.hw
,
1114 [CLKID_I2S_OUT
] = &gxbb_i2s_out
.hw
,
1115 [CLKID_AMCLK
] = &gxbb_amclk
.hw
,
1116 [CLKID_AIFIFO2
] = &gxbb_aififo2
.hw
,
1117 [CLKID_MIXER
] = &gxbb_mixer
.hw
,
1118 [CLKID_MIXER_IFACE
] = &gxbb_mixer_iface
.hw
,
1119 [CLKID_ADC
] = &gxbb_adc
.hw
,
1120 [CLKID_BLKMV
] = &gxbb_blkmv
.hw
,
1121 [CLKID_AIU
] = &gxbb_aiu
.hw
,
1122 [CLKID_UART1
] = &gxbb_uart1
.hw
,
1123 [CLKID_G2D
] = &gxbb_g2d
.hw
,
1124 [CLKID_USB0
] = &gxbb_usb0
.hw
,
1125 [CLKID_USB1
] = &gxbb_usb1
.hw
,
1126 [CLKID_RESET
] = &gxbb_reset
.hw
,
1127 [CLKID_NAND
] = &gxbb_nand
.hw
,
1128 [CLKID_DOS_PARSER
] = &gxbb_dos_parser
.hw
,
1129 [CLKID_USB
] = &gxbb_usb
.hw
,
1130 [CLKID_VDIN1
] = &gxbb_vdin1
.hw
,
1131 [CLKID_AHB_ARB0
] = &gxbb_ahb_arb0
.hw
,
1132 [CLKID_EFUSE
] = &gxbb_efuse
.hw
,
1133 [CLKID_BOOT_ROM
] = &gxbb_boot_rom
.hw
,
1134 [CLKID_AHB_DATA_BUS
] = &gxbb_ahb_data_bus
.hw
,
1135 [CLKID_AHB_CTRL_BUS
] = &gxbb_ahb_ctrl_bus
.hw
,
1136 [CLKID_HDMI_INTR_SYNC
] = &gxbb_hdmi_intr_sync
.hw
,
1137 [CLKID_HDMI_PCLK
] = &gxbb_hdmi_pclk
.hw
,
1138 [CLKID_USB1_DDR_BRIDGE
] = &gxbb_usb1_ddr_bridge
.hw
,
1139 [CLKID_USB0_DDR_BRIDGE
] = &gxbb_usb0_ddr_bridge
.hw
,
1140 [CLKID_MMC_PCLK
] = &gxbb_mmc_pclk
.hw
,
1141 [CLKID_DVIN
] = &gxbb_dvin
.hw
,
1142 [CLKID_UART2
] = &gxbb_uart2
.hw
,
1143 [CLKID_SANA
] = &gxbb_sana
.hw
,
1144 [CLKID_VPU_INTR
] = &gxbb_vpu_intr
.hw
,
1145 [CLKID_SEC_AHB_AHB3_BRIDGE
] = &gxbb_sec_ahb_ahb3_bridge
.hw
,
1146 [CLKID_CLK81_A53
] = &gxbb_clk81_a53
.hw
,
1147 [CLKID_VCLK2_VENCI0
] = &gxbb_vclk2_venci0
.hw
,
1148 [CLKID_VCLK2_VENCI1
] = &gxbb_vclk2_venci1
.hw
,
1149 [CLKID_VCLK2_VENCP0
] = &gxbb_vclk2_vencp0
.hw
,
1150 [CLKID_VCLK2_VENCP1
] = &gxbb_vclk2_vencp1
.hw
,
1151 [CLKID_GCLK_VENCI_INT0
] = &gxbb_gclk_venci_int0
.hw
,
1152 [CLKID_GCLK_VENCI_INT
] = &gxbb_gclk_vencp_int
.hw
,
1153 [CLKID_DAC_CLK
] = &gxbb_dac_clk
.hw
,
1154 [CLKID_AOCLK_GATE
] = &gxbb_aoclk_gate
.hw
,
1155 [CLKID_IEC958_GATE
] = &gxbb_iec958_gate
.hw
,
1156 [CLKID_ENC480P
] = &gxbb_enc480p
.hw
,
1157 [CLKID_RNG1
] = &gxbb_rng1
.hw
,
1158 [CLKID_GCLK_VENCI_INT1
] = &gxbb_gclk_venci_int1
.hw
,
1159 [CLKID_VCLK2_VENCLMCC
] = &gxbb_vclk2_venclmcc
.hw
,
1160 [CLKID_VCLK2_VENCL
] = &gxbb_vclk2_vencl
.hw
,
1161 [CLKID_VCLK_OTHER
] = &gxbb_vclk_other
.hw
,
1162 [CLKID_EDP
] = &gxbb_edp
.hw
,
1163 [CLKID_AO_MEDIA_CPU
] = &gxbb_ao_media_cpu
.hw
,
1164 [CLKID_AO_AHB_SRAM
] = &gxbb_ao_ahb_sram
.hw
,
1165 [CLKID_AO_AHB_BUS
] = &gxbb_ao_ahb_bus
.hw
,
1166 [CLKID_AO_IFACE
] = &gxbb_ao_iface
.hw
,
1167 [CLKID_AO_I2C
] = &gxbb_ao_i2c
.hw
,
1168 [CLKID_SD_EMMC_A
] = &gxbb_emmc_a
.hw
,
1169 [CLKID_SD_EMMC_B
] = &gxbb_emmc_b
.hw
,
1170 [CLKID_SD_EMMC_C
] = &gxbb_emmc_c
.hw
,
1171 [CLKID_SAR_ADC_CLK
] = &gxbb_sar_adc_clk
.hw
,
1172 [CLKID_SAR_ADC_SEL
] = &gxbb_sar_adc_clk_sel
.hw
,
1173 [CLKID_SAR_ADC_DIV
] = &gxbb_sar_adc_clk_div
.hw
,
1174 [CLKID_MALI_0_SEL
] = &gxbb_mali_0_sel
.hw
,
1175 [CLKID_MALI_0_DIV
] = &gxbb_mali_0_div
.hw
,
1176 [CLKID_MALI_0
] = &gxbb_mali_0
.hw
,
1177 [CLKID_MALI_1_SEL
] = &gxbb_mali_1_sel
.hw
,
1178 [CLKID_MALI_1_DIV
] = &gxbb_mali_1_div
.hw
,
1179 [CLKID_MALI_1
] = &gxbb_mali_1
.hw
,
1180 [CLKID_MALI
] = &gxbb_mali
.hw
,
1181 [CLKID_CTS_AMCLK
] = &gxbb_cts_amclk
.hw
,
1182 [CLKID_CTS_AMCLK_SEL
] = &gxbb_cts_amclk_sel
.hw
,
1183 [CLKID_CTS_AMCLK_DIV
] = &gxbb_cts_amclk_div
.hw
,
1184 [CLKID_CTS_MCLK_I958
] = &gxbb_cts_mclk_i958
.hw
,
1185 [CLKID_CTS_MCLK_I958_SEL
] = &gxbb_cts_mclk_i958_sel
.hw
,
1186 [CLKID_CTS_MCLK_I958_DIV
] = &gxbb_cts_mclk_i958_div
.hw
,
1187 [CLKID_CTS_I958
] = &gxbb_cts_i958
.hw
,
1188 [CLKID_32K_CLK
] = &gxbb_32k_clk
.hw
,
1189 [CLKID_32K_CLK_SEL
] = &gxbb_32k_clk_sel
.hw
,
1190 [CLKID_32K_CLK_DIV
] = &gxbb_32k_clk_div
.hw
,
1195 static struct clk_hw_onecell_data gxl_hw_onecell_data
= {
1197 [CLKID_SYS_PLL
] = &gxbb_sys_pll
.hw
,
1198 [CLKID_HDMI_PLL
] = &gxbb_hdmi_pll
.hw
,
1199 [CLKID_FIXED_PLL
] = &gxbb_fixed_pll
.hw
,
1200 [CLKID_FCLK_DIV2
] = &gxbb_fclk_div2
.hw
,
1201 [CLKID_FCLK_DIV3
] = &gxbb_fclk_div3
.hw
,
1202 [CLKID_FCLK_DIV4
] = &gxbb_fclk_div4
.hw
,
1203 [CLKID_FCLK_DIV5
] = &gxbb_fclk_div5
.hw
,
1204 [CLKID_FCLK_DIV7
] = &gxbb_fclk_div7
.hw
,
1205 [CLKID_GP0_PLL
] = &gxl_gp0_pll
.hw
,
1206 [CLKID_MPEG_SEL
] = &gxbb_mpeg_clk_sel
.hw
,
1207 [CLKID_MPEG_DIV
] = &gxbb_mpeg_clk_div
.hw
,
1208 [CLKID_CLK81
] = &gxbb_clk81
.hw
,
1209 [CLKID_MPLL0
] = &gxbb_mpll0
.hw
,
1210 [CLKID_MPLL1
] = &gxbb_mpll1
.hw
,
1211 [CLKID_MPLL2
] = &gxbb_mpll2
.hw
,
1212 [CLKID_DDR
] = &gxbb_ddr
.hw
,
1213 [CLKID_DOS
] = &gxbb_dos
.hw
,
1214 [CLKID_ISA
] = &gxbb_isa
.hw
,
1215 [CLKID_PL301
] = &gxbb_pl301
.hw
,
1216 [CLKID_PERIPHS
] = &gxbb_periphs
.hw
,
1217 [CLKID_SPICC
] = &gxbb_spicc
.hw
,
1218 [CLKID_I2C
] = &gxbb_i2c
.hw
,
1219 [CLKID_SAR_ADC
] = &gxbb_sar_adc
.hw
,
1220 [CLKID_SMART_CARD
] = &gxbb_smart_card
.hw
,
1221 [CLKID_RNG0
] = &gxbb_rng0
.hw
,
1222 [CLKID_UART0
] = &gxbb_uart0
.hw
,
1223 [CLKID_SDHC
] = &gxbb_sdhc
.hw
,
1224 [CLKID_STREAM
] = &gxbb_stream
.hw
,
1225 [CLKID_ASYNC_FIFO
] = &gxbb_async_fifo
.hw
,
1226 [CLKID_SDIO
] = &gxbb_sdio
.hw
,
1227 [CLKID_ABUF
] = &gxbb_abuf
.hw
,
1228 [CLKID_HIU_IFACE
] = &gxbb_hiu_iface
.hw
,
1229 [CLKID_ASSIST_MISC
] = &gxbb_assist_misc
.hw
,
1230 [CLKID_SPI
] = &gxbb_spi
.hw
,
1231 [CLKID_I2S_SPDIF
] = &gxbb_i2s_spdif
.hw
,
1232 [CLKID_ETH
] = &gxbb_eth
.hw
,
1233 [CLKID_DEMUX
] = &gxbb_demux
.hw
,
1234 [CLKID_AIU_GLUE
] = &gxbb_aiu_glue
.hw
,
1235 [CLKID_IEC958
] = &gxbb_iec958
.hw
,
1236 [CLKID_I2S_OUT
] = &gxbb_i2s_out
.hw
,
1237 [CLKID_AMCLK
] = &gxbb_amclk
.hw
,
1238 [CLKID_AIFIFO2
] = &gxbb_aififo2
.hw
,
1239 [CLKID_MIXER
] = &gxbb_mixer
.hw
,
1240 [CLKID_MIXER_IFACE
] = &gxbb_mixer_iface
.hw
,
1241 [CLKID_ADC
] = &gxbb_adc
.hw
,
1242 [CLKID_BLKMV
] = &gxbb_blkmv
.hw
,
1243 [CLKID_AIU
] = &gxbb_aiu
.hw
,
1244 [CLKID_UART1
] = &gxbb_uart1
.hw
,
1245 [CLKID_G2D
] = &gxbb_g2d
.hw
,
1246 [CLKID_USB0
] = &gxbb_usb0
.hw
,
1247 [CLKID_USB1
] = &gxbb_usb1
.hw
,
1248 [CLKID_RESET
] = &gxbb_reset
.hw
,
1249 [CLKID_NAND
] = &gxbb_nand
.hw
,
1250 [CLKID_DOS_PARSER
] = &gxbb_dos_parser
.hw
,
1251 [CLKID_USB
] = &gxbb_usb
.hw
,
1252 [CLKID_VDIN1
] = &gxbb_vdin1
.hw
,
1253 [CLKID_AHB_ARB0
] = &gxbb_ahb_arb0
.hw
,
1254 [CLKID_EFUSE
] = &gxbb_efuse
.hw
,
1255 [CLKID_BOOT_ROM
] = &gxbb_boot_rom
.hw
,
1256 [CLKID_AHB_DATA_BUS
] = &gxbb_ahb_data_bus
.hw
,
1257 [CLKID_AHB_CTRL_BUS
] = &gxbb_ahb_ctrl_bus
.hw
,
1258 [CLKID_HDMI_INTR_SYNC
] = &gxbb_hdmi_intr_sync
.hw
,
1259 [CLKID_HDMI_PCLK
] = &gxbb_hdmi_pclk
.hw
,
1260 [CLKID_USB1_DDR_BRIDGE
] = &gxbb_usb1_ddr_bridge
.hw
,
1261 [CLKID_USB0_DDR_BRIDGE
] = &gxbb_usb0_ddr_bridge
.hw
,
1262 [CLKID_MMC_PCLK
] = &gxbb_mmc_pclk
.hw
,
1263 [CLKID_DVIN
] = &gxbb_dvin
.hw
,
1264 [CLKID_UART2
] = &gxbb_uart2
.hw
,
1265 [CLKID_SANA
] = &gxbb_sana
.hw
,
1266 [CLKID_VPU_INTR
] = &gxbb_vpu_intr
.hw
,
1267 [CLKID_SEC_AHB_AHB3_BRIDGE
] = &gxbb_sec_ahb_ahb3_bridge
.hw
,
1268 [CLKID_CLK81_A53
] = &gxbb_clk81_a53
.hw
,
1269 [CLKID_VCLK2_VENCI0
] = &gxbb_vclk2_venci0
.hw
,
1270 [CLKID_VCLK2_VENCI1
] = &gxbb_vclk2_venci1
.hw
,
1271 [CLKID_VCLK2_VENCP0
] = &gxbb_vclk2_vencp0
.hw
,
1272 [CLKID_VCLK2_VENCP1
] = &gxbb_vclk2_vencp1
.hw
,
1273 [CLKID_GCLK_VENCI_INT0
] = &gxbb_gclk_venci_int0
.hw
,
1274 [CLKID_GCLK_VENCI_INT
] = &gxbb_gclk_vencp_int
.hw
,
1275 [CLKID_DAC_CLK
] = &gxbb_dac_clk
.hw
,
1276 [CLKID_AOCLK_GATE
] = &gxbb_aoclk_gate
.hw
,
1277 [CLKID_IEC958_GATE
] = &gxbb_iec958_gate
.hw
,
1278 [CLKID_ENC480P
] = &gxbb_enc480p
.hw
,
1279 [CLKID_RNG1
] = &gxbb_rng1
.hw
,
1280 [CLKID_GCLK_VENCI_INT1
] = &gxbb_gclk_venci_int1
.hw
,
1281 [CLKID_VCLK2_VENCLMCC
] = &gxbb_vclk2_venclmcc
.hw
,
1282 [CLKID_VCLK2_VENCL
] = &gxbb_vclk2_vencl
.hw
,
1283 [CLKID_VCLK_OTHER
] = &gxbb_vclk_other
.hw
,
1284 [CLKID_EDP
] = &gxbb_edp
.hw
,
1285 [CLKID_AO_MEDIA_CPU
] = &gxbb_ao_media_cpu
.hw
,
1286 [CLKID_AO_AHB_SRAM
] = &gxbb_ao_ahb_sram
.hw
,
1287 [CLKID_AO_AHB_BUS
] = &gxbb_ao_ahb_bus
.hw
,
1288 [CLKID_AO_IFACE
] = &gxbb_ao_iface
.hw
,
1289 [CLKID_AO_I2C
] = &gxbb_ao_i2c
.hw
,
1290 [CLKID_SD_EMMC_A
] = &gxbb_emmc_a
.hw
,
1291 [CLKID_SD_EMMC_B
] = &gxbb_emmc_b
.hw
,
1292 [CLKID_SD_EMMC_C
] = &gxbb_emmc_c
.hw
,
1293 [CLKID_SAR_ADC_CLK
] = &gxbb_sar_adc_clk
.hw
,
1294 [CLKID_SAR_ADC_SEL
] = &gxbb_sar_adc_clk_sel
.hw
,
1295 [CLKID_SAR_ADC_DIV
] = &gxbb_sar_adc_clk_div
.hw
,
1296 [CLKID_MALI_0_SEL
] = &gxbb_mali_0_sel
.hw
,
1297 [CLKID_MALI_0_DIV
] = &gxbb_mali_0_div
.hw
,
1298 [CLKID_MALI_0
] = &gxbb_mali_0
.hw
,
1299 [CLKID_MALI_1_SEL
] = &gxbb_mali_1_sel
.hw
,
1300 [CLKID_MALI_1_DIV
] = &gxbb_mali_1_div
.hw
,
1301 [CLKID_MALI_1
] = &gxbb_mali_1
.hw
,
1302 [CLKID_MALI
] = &gxbb_mali
.hw
,
1303 [CLKID_CTS_AMCLK
] = &gxbb_cts_amclk
.hw
,
1304 [CLKID_CTS_AMCLK_SEL
] = &gxbb_cts_amclk_sel
.hw
,
1305 [CLKID_CTS_AMCLK_DIV
] = &gxbb_cts_amclk_div
.hw
,
1306 [CLKID_CTS_MCLK_I958
] = &gxbb_cts_mclk_i958
.hw
,
1307 [CLKID_CTS_MCLK_I958_SEL
] = &gxbb_cts_mclk_i958_sel
.hw
,
1308 [CLKID_CTS_MCLK_I958_DIV
] = &gxbb_cts_mclk_i958_div
.hw
,
1309 [CLKID_CTS_I958
] = &gxbb_cts_i958
.hw
,
1310 [CLKID_32K_CLK
] = &gxbb_32k_clk
.hw
,
1311 [CLKID_32K_CLK_SEL
] = &gxbb_32k_clk_sel
.hw
,
1312 [CLKID_32K_CLK_DIV
] = &gxbb_32k_clk_div
.hw
,
1317 /* Convenience tables to populate base addresses in .probe */
1319 static struct meson_clk_pll
*const gxbb_clk_plls
[] = {
1326 static struct meson_clk_pll
*const gxl_clk_plls
[] = {
1333 static struct meson_clk_mpll
*const gxbb_clk_mplls
[] = {
1339 static struct clk_gate
*const gxbb_clk_gates
[] = {
1387 &gxbb_hdmi_intr_sync
,
1389 &gxbb_usb1_ddr_bridge
,
1390 &gxbb_usb0_ddr_bridge
,
1396 &gxbb_sec_ahb_ahb3_bridge
,
1402 &gxbb_gclk_venci_int0
,
1403 &gxbb_gclk_vencp_int
,
1409 &gxbb_gclk_venci_int1
,
1410 &gxbb_vclk2_venclmcc
,
1426 &gxbb_cts_mclk_i958
,
1430 static struct clk_mux
*const gxbb_clk_muxes
[] = {
1432 &gxbb_sar_adc_clk_sel
,
1436 &gxbb_cts_amclk_sel
,
1437 &gxbb_cts_mclk_i958_sel
,
1442 static struct clk_divider
*const gxbb_clk_dividers
[] = {
1444 &gxbb_sar_adc_clk_div
,
1447 &gxbb_cts_mclk_i958_div
,
1451 static struct meson_clk_audio_divider
*const gxbb_audio_dividers
[] = {
1452 &gxbb_cts_amclk_div
,
1456 struct clk_gate
*const *clk_gates
;
1457 unsigned int clk_gates_count
;
1458 struct meson_clk_mpll
*const *clk_mplls
;
1459 unsigned int clk_mplls_count
;
1460 struct meson_clk_pll
*const *clk_plls
;
1461 unsigned int clk_plls_count
;
1462 struct clk_mux
*const *clk_muxes
;
1463 unsigned int clk_muxes_count
;
1464 struct clk_divider
*const *clk_dividers
;
1465 unsigned int clk_dividers_count
;
1466 struct meson_clk_audio_divider
*const *clk_audio_dividers
;
1467 unsigned int clk_audio_dividers_count
;
1468 struct clk_hw_onecell_data
*hw_onecell_data
;
1471 static const struct clkc_data gxbb_clkc_data
= {
1472 .clk_gates
= gxbb_clk_gates
,
1473 .clk_gates_count
= ARRAY_SIZE(gxbb_clk_gates
),
1474 .clk_mplls
= gxbb_clk_mplls
,
1475 .clk_mplls_count
= ARRAY_SIZE(gxbb_clk_mplls
),
1476 .clk_plls
= gxbb_clk_plls
,
1477 .clk_plls_count
= ARRAY_SIZE(gxbb_clk_plls
),
1478 .clk_muxes
= gxbb_clk_muxes
,
1479 .clk_muxes_count
= ARRAY_SIZE(gxbb_clk_muxes
),
1480 .clk_dividers
= gxbb_clk_dividers
,
1481 .clk_dividers_count
= ARRAY_SIZE(gxbb_clk_dividers
),
1482 .clk_audio_dividers
= gxbb_audio_dividers
,
1483 .clk_audio_dividers_count
= ARRAY_SIZE(gxbb_audio_dividers
),
1484 .hw_onecell_data
= &gxbb_hw_onecell_data
,
1487 static const struct clkc_data gxl_clkc_data
= {
1488 .clk_gates
= gxbb_clk_gates
,
1489 .clk_gates_count
= ARRAY_SIZE(gxbb_clk_gates
),
1490 .clk_mplls
= gxbb_clk_mplls
,
1491 .clk_mplls_count
= ARRAY_SIZE(gxbb_clk_mplls
),
1492 .clk_plls
= gxl_clk_plls
,
1493 .clk_plls_count
= ARRAY_SIZE(gxl_clk_plls
),
1494 .clk_muxes
= gxbb_clk_muxes
,
1495 .clk_muxes_count
= ARRAY_SIZE(gxbb_clk_muxes
),
1496 .clk_dividers
= gxbb_clk_dividers
,
1497 .clk_dividers_count
= ARRAY_SIZE(gxbb_clk_dividers
),
1498 .clk_audio_dividers
= gxbb_audio_dividers
,
1499 .clk_audio_dividers_count
= ARRAY_SIZE(gxbb_audio_dividers
),
1500 .hw_onecell_data
= &gxl_hw_onecell_data
,
1503 static const struct of_device_id clkc_match_table
[] = {
1504 { .compatible
= "amlogic,gxbb-clkc", .data
= &gxbb_clkc_data
},
1505 { .compatible
= "amlogic,gxl-clkc", .data
= &gxl_clkc_data
},
1509 static int gxbb_clkc_probe(struct platform_device
*pdev
)
1511 const struct clkc_data
*clkc_data
;
1512 void __iomem
*clk_base
;
1514 struct device
*dev
= &pdev
->dev
;
1516 clkc_data
= of_device_get_match_data(&pdev
->dev
);
1520 /* Generic clocks and PLLs */
1521 clk_base
= of_iomap(dev
->of_node
, 0);
1523 pr_err("%s: Unable to map clk base\n", __func__
);
1527 /* Populate base address for PLLs */
1528 for (i
= 0; i
< clkc_data
->clk_plls_count
; i
++)
1529 clkc_data
->clk_plls
[i
]->base
= clk_base
;
1531 /* Populate base address for MPLLs */
1532 for (i
= 0; i
< clkc_data
->clk_mplls_count
; i
++)
1533 clkc_data
->clk_mplls
[i
]->base
= clk_base
;
1535 /* Populate base address for gates */
1536 for (i
= 0; i
< clkc_data
->clk_gates_count
; i
++)
1537 clkc_data
->clk_gates
[i
]->reg
= clk_base
+
1538 (u64
)clkc_data
->clk_gates
[i
]->reg
;
1540 /* Populate base address for muxes */
1541 for (i
= 0; i
< clkc_data
->clk_muxes_count
; i
++)
1542 clkc_data
->clk_muxes
[i
]->reg
= clk_base
+
1543 (u64
)clkc_data
->clk_muxes
[i
]->reg
;
1545 /* Populate base address for dividers */
1546 for (i
= 0; i
< clkc_data
->clk_dividers_count
; i
++)
1547 clkc_data
->clk_dividers
[i
]->reg
= clk_base
+
1548 (u64
)clkc_data
->clk_dividers
[i
]->reg
;
1550 /* Populate base address for the audio dividers */
1551 for (i
= 0; i
< clkc_data
->clk_audio_dividers_count
; i
++)
1552 clkc_data
->clk_audio_dividers
[i
]->base
= clk_base
;
1557 for (clkid
= 0; clkid
< clkc_data
->hw_onecell_data
->num
; clkid
++) {
1558 /* array might be sparse */
1559 if (!clkc_data
->hw_onecell_data
->hws
[clkid
])
1562 ret
= devm_clk_hw_register(dev
,
1563 clkc_data
->hw_onecell_data
->hws
[clkid
]);
1568 return of_clk_add_hw_provider(dev
->of_node
, of_clk_hw_onecell_get
,
1569 clkc_data
->hw_onecell_data
);
1576 static struct platform_driver gxbb_driver
= {
1577 .probe
= gxbb_clkc_probe
,
1579 .name
= "gxbb-clkc",
1580 .of_match_table
= clkc_match_table
,
1584 builtin_platform_driver(gxbb_driver
);