2 * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
5 * Copyright (c) 2015 Endless Mobile, Inc.
6 * Author: Carlo Caione <carlo@endlessm.com>
8 * Copyright (c) 2016 BayLibre, Inc.
9 * Michael Turquette <mturquette@baylibre.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms and conditions of the GNU General Public License,
13 * version 2, as published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
21 * this program. If not, see <http://www.gnu.org/licenses/>.
24 #include <linux/clk.h>
25 #include <linux/clk-provider.h>
26 #include <linux/of_address.h>
27 #include <linux/platform_device.h>
28 #include <linux/init.h>
33 static DEFINE_SPINLOCK(clk_lock
);
35 static const struct pll_rate_table sys_pll_rate_table
[] = {
36 PLL_RATE(312000000, 52, 1, 2),
37 PLL_RATE(336000000, 56, 1, 2),
38 PLL_RATE(360000000, 60, 1, 2),
39 PLL_RATE(384000000, 64, 1, 2),
40 PLL_RATE(408000000, 68, 1, 2),
41 PLL_RATE(432000000, 72, 1, 2),
42 PLL_RATE(456000000, 76, 1, 2),
43 PLL_RATE(480000000, 80, 1, 2),
44 PLL_RATE(504000000, 84, 1, 2),
45 PLL_RATE(528000000, 88, 1, 2),
46 PLL_RATE(552000000, 92, 1, 2),
47 PLL_RATE(576000000, 96, 1, 2),
48 PLL_RATE(600000000, 50, 1, 1),
49 PLL_RATE(624000000, 52, 1, 1),
50 PLL_RATE(648000000, 54, 1, 1),
51 PLL_RATE(672000000, 56, 1, 1),
52 PLL_RATE(696000000, 58, 1, 1),
53 PLL_RATE(720000000, 60, 1, 1),
54 PLL_RATE(744000000, 62, 1, 1),
55 PLL_RATE(768000000, 64, 1, 1),
56 PLL_RATE(792000000, 66, 1, 1),
57 PLL_RATE(816000000, 68, 1, 1),
58 PLL_RATE(840000000, 70, 1, 1),
59 PLL_RATE(864000000, 72, 1, 1),
60 PLL_RATE(888000000, 74, 1, 1),
61 PLL_RATE(912000000, 76, 1, 1),
62 PLL_RATE(936000000, 78, 1, 1),
63 PLL_RATE(960000000, 80, 1, 1),
64 PLL_RATE(984000000, 82, 1, 1),
65 PLL_RATE(1008000000, 84, 1, 1),
66 PLL_RATE(1032000000, 86, 1, 1),
67 PLL_RATE(1056000000, 88, 1, 1),
68 PLL_RATE(1080000000, 90, 1, 1),
69 PLL_RATE(1104000000, 92, 1, 1),
70 PLL_RATE(1128000000, 94, 1, 1),
71 PLL_RATE(1152000000, 96, 1, 1),
72 PLL_RATE(1176000000, 98, 1, 1),
73 PLL_RATE(1200000000, 50, 1, 0),
74 PLL_RATE(1224000000, 51, 1, 0),
75 PLL_RATE(1248000000, 52, 1, 0),
76 PLL_RATE(1272000000, 53, 1, 0),
77 PLL_RATE(1296000000, 54, 1, 0),
78 PLL_RATE(1320000000, 55, 1, 0),
79 PLL_RATE(1344000000, 56, 1, 0),
80 PLL_RATE(1368000000, 57, 1, 0),
81 PLL_RATE(1392000000, 58, 1, 0),
82 PLL_RATE(1416000000, 59, 1, 0),
83 PLL_RATE(1440000000, 60, 1, 0),
84 PLL_RATE(1464000000, 61, 1, 0),
85 PLL_RATE(1488000000, 62, 1, 0),
86 PLL_RATE(1512000000, 63, 1, 0),
87 PLL_RATE(1536000000, 64, 1, 0),
91 static const struct clk_div_table cpu_div_table
[] = {
92 { .val
= 1, .div
= 1 },
93 { .val
= 2, .div
= 2 },
94 { .val
= 3, .div
= 3 },
95 { .val
= 2, .div
= 4 },
96 { .val
= 3, .div
= 6 },
97 { .val
= 4, .div
= 8 },
98 { .val
= 5, .div
= 10 },
99 { .val
= 6, .div
= 12 },
100 { .val
= 7, .div
= 14 },
101 { .val
= 8, .div
= 16 },
105 static struct clk_fixed_rate meson8b_xtal
= {
106 .fixed_rate
= 24000000,
107 .hw
.init
= &(struct clk_init_data
){
110 .ops
= &clk_fixed_rate_ops
,
114 static struct meson_clk_pll meson8b_fixed_pll
= {
116 .reg_off
= HHI_MPLL_CNTL
,
121 .reg_off
= HHI_MPLL_CNTL
,
126 .reg_off
= HHI_MPLL_CNTL
,
131 .hw
.init
= &(struct clk_init_data
){
133 .ops
= &meson_clk_pll_ro_ops
,
134 .parent_names
= (const char *[]){ "xtal" },
136 .flags
= CLK_GET_RATE_NOCACHE
,
140 static struct meson_clk_pll meson8b_vid_pll
= {
142 .reg_off
= HHI_VID_PLL_CNTL
,
147 .reg_off
= HHI_VID_PLL_CNTL
,
152 .reg_off
= HHI_VID_PLL_CNTL
,
157 .hw
.init
= &(struct clk_init_data
){
159 .ops
= &meson_clk_pll_ro_ops
,
160 .parent_names
= (const char *[]){ "xtal" },
162 .flags
= CLK_GET_RATE_NOCACHE
,
166 static struct meson_clk_pll meson8b_sys_pll
= {
168 .reg_off
= HHI_SYS_PLL_CNTL
,
173 .reg_off
= HHI_SYS_PLL_CNTL
,
178 .reg_off
= HHI_SYS_PLL_CNTL
,
182 .rate_table
= sys_pll_rate_table
,
183 .rate_count
= ARRAY_SIZE(sys_pll_rate_table
),
185 .hw
.init
= &(struct clk_init_data
){
187 .ops
= &meson_clk_pll_ops
,
188 .parent_names
= (const char *[]){ "xtal" },
190 .flags
= CLK_GET_RATE_NOCACHE
,
194 static struct clk_fixed_factor meson8b_fclk_div2
= {
197 .hw
.init
= &(struct clk_init_data
){
199 .ops
= &clk_fixed_factor_ops
,
200 .parent_names
= (const char *[]){ "fixed_pll" },
205 static struct clk_fixed_factor meson8b_fclk_div3
= {
208 .hw
.init
= &(struct clk_init_data
){
210 .ops
= &clk_fixed_factor_ops
,
211 .parent_names
= (const char *[]){ "fixed_pll" },
216 static struct clk_fixed_factor meson8b_fclk_div4
= {
219 .hw
.init
= &(struct clk_init_data
){
221 .ops
= &clk_fixed_factor_ops
,
222 .parent_names
= (const char *[]){ "fixed_pll" },
227 static struct clk_fixed_factor meson8b_fclk_div5
= {
230 .hw
.init
= &(struct clk_init_data
){
232 .ops
= &clk_fixed_factor_ops
,
233 .parent_names
= (const char *[]){ "fixed_pll" },
238 static struct clk_fixed_factor meson8b_fclk_div7
= {
241 .hw
.init
= &(struct clk_init_data
){
243 .ops
= &clk_fixed_factor_ops
,
244 .parent_names
= (const char *[]){ "fixed_pll" },
249 static struct meson_clk_mpll meson8b_mpll0
= {
251 .reg_off
= HHI_MPLL_CNTL7
,
256 .reg_off
= HHI_MPLL_CNTL7
,
261 .reg_off
= HHI_MPLL_CNTL7
,
266 .reg_off
= HHI_MPLL_CNTL7
,
271 .reg_off
= HHI_MPLL_CNTL
,
276 .hw
.init
= &(struct clk_init_data
){
278 .ops
= &meson_clk_mpll_ops
,
279 .parent_names
= (const char *[]){ "fixed_pll" },
284 static struct meson_clk_mpll meson8b_mpll1
= {
286 .reg_off
= HHI_MPLL_CNTL8
,
291 .reg_off
= HHI_MPLL_CNTL8
,
296 .reg_off
= HHI_MPLL_CNTL8
,
301 .reg_off
= HHI_MPLL_CNTL8
,
306 .hw
.init
= &(struct clk_init_data
){
308 .ops
= &meson_clk_mpll_ops
,
309 .parent_names
= (const char *[]){ "fixed_pll" },
314 static struct meson_clk_mpll meson8b_mpll2
= {
316 .reg_off
= HHI_MPLL_CNTL9
,
321 .reg_off
= HHI_MPLL_CNTL9
,
326 .reg_off
= HHI_MPLL_CNTL9
,
331 .reg_off
= HHI_MPLL_CNTL9
,
336 .hw
.init
= &(struct clk_init_data
){
338 .ops
= &meson_clk_mpll_ops
,
339 .parent_names
= (const char *[]){ "fixed_pll" },
345 * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
346 * post-dividers and should be modeled with their respective PLLs via the
347 * forthcoming coordinated clock rates feature
349 static struct meson_clk_cpu meson8b_cpu_clk
= {
350 .reg_off
= HHI_SYS_CPU_CLK_CNTL1
,
351 .div_table
= cpu_div_table
,
352 .clk_nb
.notifier_call
= meson_clk_cpu_notifier_cb
,
353 .hw
.init
= &(struct clk_init_data
){
355 .ops
= &meson_clk_cpu_ops
,
356 .parent_names
= (const char *[]){ "sys_pll" },
361 static u32 mux_table_clk81
[] = { 6, 5, 7 };
363 struct clk_mux meson8b_mpeg_clk_sel
= {
364 .reg
= (void *)HHI_MPEG_CLK_CNTL
,
367 .flags
= CLK_MUX_READ_ONLY
,
368 .table
= mux_table_clk81
,
370 .hw
.init
= &(struct clk_init_data
){
371 .name
= "mpeg_clk_sel",
372 .ops
= &clk_mux_ro_ops
,
374 * FIXME bits 14:12 selects from 8 possible parents:
375 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
376 * fclk_div4, fclk_div3, fclk_div5
378 .parent_names
= (const char *[]){ "fclk_div3", "fclk_div4",
381 .flags
= (CLK_SET_RATE_NO_REPARENT
| CLK_IGNORE_UNUSED
),
385 struct clk_divider meson8b_mpeg_clk_div
= {
386 .reg
= (void *)HHI_MPEG_CLK_CNTL
,
390 .hw
.init
= &(struct clk_init_data
){
391 .name
= "mpeg_clk_div",
392 .ops
= &clk_divider_ops
,
393 .parent_names
= (const char *[]){ "mpeg_clk_sel" },
395 .flags
= (CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
),
399 struct clk_gate meson8b_clk81
= {
400 .reg
= (void *)HHI_MPEG_CLK_CNTL
,
403 .hw
.init
= &(struct clk_init_data
){
405 .ops
= &clk_gate_ops
,
406 .parent_names
= (const char *[]){ "mpeg_clk_div" },
408 .flags
= (CLK_SET_RATE_PARENT
| CLK_IS_CRITICAL
),
412 /* Everything Else (EE) domain gates */
414 static MESON_GATE(meson8b_ddr
, HHI_GCLK_MPEG0
, 0);
415 static MESON_GATE(meson8b_dos
, HHI_GCLK_MPEG0
, 1);
416 static MESON_GATE(meson8b_isa
, HHI_GCLK_MPEG0
, 5);
417 static MESON_GATE(meson8b_pl301
, HHI_GCLK_MPEG0
, 6);
418 static MESON_GATE(meson8b_periphs
, HHI_GCLK_MPEG0
, 7);
419 static MESON_GATE(meson8b_spicc
, HHI_GCLK_MPEG0
, 8);
420 static MESON_GATE(meson8b_i2c
, HHI_GCLK_MPEG0
, 9);
421 static MESON_GATE(meson8b_sar_adc
, HHI_GCLK_MPEG0
, 10);
422 static MESON_GATE(meson8b_smart_card
, HHI_GCLK_MPEG0
, 11);
423 static MESON_GATE(meson8b_rng0
, HHI_GCLK_MPEG0
, 12);
424 static MESON_GATE(meson8b_uart0
, HHI_GCLK_MPEG0
, 13);
425 static MESON_GATE(meson8b_sdhc
, HHI_GCLK_MPEG0
, 14);
426 static MESON_GATE(meson8b_stream
, HHI_GCLK_MPEG0
, 15);
427 static MESON_GATE(meson8b_async_fifo
, HHI_GCLK_MPEG0
, 16);
428 static MESON_GATE(meson8b_sdio
, HHI_GCLK_MPEG0
, 17);
429 static MESON_GATE(meson8b_abuf
, HHI_GCLK_MPEG0
, 18);
430 static MESON_GATE(meson8b_hiu_iface
, HHI_GCLK_MPEG0
, 19);
431 static MESON_GATE(meson8b_assist_misc
, HHI_GCLK_MPEG0
, 23);
432 static MESON_GATE(meson8b_spi
, HHI_GCLK_MPEG0
, 30);
434 static MESON_GATE(meson8b_i2s_spdif
, HHI_GCLK_MPEG1
, 2);
435 static MESON_GATE(meson8b_eth
, HHI_GCLK_MPEG1
, 3);
436 static MESON_GATE(meson8b_demux
, HHI_GCLK_MPEG1
, 4);
437 static MESON_GATE(meson8b_aiu_glue
, HHI_GCLK_MPEG1
, 6);
438 static MESON_GATE(meson8b_iec958
, HHI_GCLK_MPEG1
, 7);
439 static MESON_GATE(meson8b_i2s_out
, HHI_GCLK_MPEG1
, 8);
440 static MESON_GATE(meson8b_amclk
, HHI_GCLK_MPEG1
, 9);
441 static MESON_GATE(meson8b_aififo2
, HHI_GCLK_MPEG1
, 10);
442 static MESON_GATE(meson8b_mixer
, HHI_GCLK_MPEG1
, 11);
443 static MESON_GATE(meson8b_mixer_iface
, HHI_GCLK_MPEG1
, 12);
444 static MESON_GATE(meson8b_adc
, HHI_GCLK_MPEG1
, 13);
445 static MESON_GATE(meson8b_blkmv
, HHI_GCLK_MPEG1
, 14);
446 static MESON_GATE(meson8b_aiu
, HHI_GCLK_MPEG1
, 15);
447 static MESON_GATE(meson8b_uart1
, HHI_GCLK_MPEG1
, 16);
448 static MESON_GATE(meson8b_g2d
, HHI_GCLK_MPEG1
, 20);
449 static MESON_GATE(meson8b_usb0
, HHI_GCLK_MPEG1
, 21);
450 static MESON_GATE(meson8b_usb1
, HHI_GCLK_MPEG1
, 22);
451 static MESON_GATE(meson8b_reset
, HHI_GCLK_MPEG1
, 23);
452 static MESON_GATE(meson8b_nand
, HHI_GCLK_MPEG1
, 24);
453 static MESON_GATE(meson8b_dos_parser
, HHI_GCLK_MPEG1
, 25);
454 static MESON_GATE(meson8b_usb
, HHI_GCLK_MPEG1
, 26);
455 static MESON_GATE(meson8b_vdin1
, HHI_GCLK_MPEG1
, 28);
456 static MESON_GATE(meson8b_ahb_arb0
, HHI_GCLK_MPEG1
, 29);
457 static MESON_GATE(meson8b_efuse
, HHI_GCLK_MPEG1
, 30);
458 static MESON_GATE(meson8b_boot_rom
, HHI_GCLK_MPEG1
, 31);
460 static MESON_GATE(meson8b_ahb_data_bus
, HHI_GCLK_MPEG2
, 1);
461 static MESON_GATE(meson8b_ahb_ctrl_bus
, HHI_GCLK_MPEG2
, 2);
462 static MESON_GATE(meson8b_hdmi_intr_sync
, HHI_GCLK_MPEG2
, 3);
463 static MESON_GATE(meson8b_hdmi_pclk
, HHI_GCLK_MPEG2
, 4);
464 static MESON_GATE(meson8b_usb1_ddr_bridge
, HHI_GCLK_MPEG2
, 8);
465 static MESON_GATE(meson8b_usb0_ddr_bridge
, HHI_GCLK_MPEG2
, 9);
466 static MESON_GATE(meson8b_mmc_pclk
, HHI_GCLK_MPEG2
, 11);
467 static MESON_GATE(meson8b_dvin
, HHI_GCLK_MPEG2
, 12);
468 static MESON_GATE(meson8b_uart2
, HHI_GCLK_MPEG2
, 15);
469 static MESON_GATE(meson8b_sana
, HHI_GCLK_MPEG2
, 22);
470 static MESON_GATE(meson8b_vpu_intr
, HHI_GCLK_MPEG2
, 25);
471 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge
, HHI_GCLK_MPEG2
, 26);
472 static MESON_GATE(meson8b_clk81_a9
, HHI_GCLK_MPEG2
, 29);
474 static MESON_GATE(meson8b_vclk2_venci0
, HHI_GCLK_OTHER
, 1);
475 static MESON_GATE(meson8b_vclk2_venci1
, HHI_GCLK_OTHER
, 2);
476 static MESON_GATE(meson8b_vclk2_vencp0
, HHI_GCLK_OTHER
, 3);
477 static MESON_GATE(meson8b_vclk2_vencp1
, HHI_GCLK_OTHER
, 4);
478 static MESON_GATE(meson8b_gclk_venci_int
, HHI_GCLK_OTHER
, 8);
479 static MESON_GATE(meson8b_gclk_vencp_int
, HHI_GCLK_OTHER
, 9);
480 static MESON_GATE(meson8b_dac_clk
, HHI_GCLK_OTHER
, 10);
481 static MESON_GATE(meson8b_aoclk_gate
, HHI_GCLK_OTHER
, 14);
482 static MESON_GATE(meson8b_iec958_gate
, HHI_GCLK_OTHER
, 16);
483 static MESON_GATE(meson8b_enc480p
, HHI_GCLK_OTHER
, 20);
484 static MESON_GATE(meson8b_rng1
, HHI_GCLK_OTHER
, 21);
485 static MESON_GATE(meson8b_gclk_vencl_int
, HHI_GCLK_OTHER
, 22);
486 static MESON_GATE(meson8b_vclk2_venclmcc
, HHI_GCLK_OTHER
, 24);
487 static MESON_GATE(meson8b_vclk2_vencl
, HHI_GCLK_OTHER
, 25);
488 static MESON_GATE(meson8b_vclk2_other
, HHI_GCLK_OTHER
, 26);
489 static MESON_GATE(meson8b_edp
, HHI_GCLK_OTHER
, 31);
491 /* Always On (AO) domain gates */
493 static MESON_GATE(meson8b_ao_media_cpu
, HHI_GCLK_AO
, 0);
494 static MESON_GATE(meson8b_ao_ahb_sram
, HHI_GCLK_AO
, 1);
495 static MESON_GATE(meson8b_ao_ahb_bus
, HHI_GCLK_AO
, 2);
496 static MESON_GATE(meson8b_ao_iface
, HHI_GCLK_AO
, 3);
498 static struct clk_hw_onecell_data meson8b_hw_onecell_data
= {
500 [CLKID_XTAL
] = &meson8b_xtal
.hw
,
501 [CLKID_PLL_FIXED
] = &meson8b_fixed_pll
.hw
,
502 [CLKID_PLL_VID
] = &meson8b_vid_pll
.hw
,
503 [CLKID_PLL_SYS
] = &meson8b_sys_pll
.hw
,
504 [CLKID_FCLK_DIV2
] = &meson8b_fclk_div2
.hw
,
505 [CLKID_FCLK_DIV3
] = &meson8b_fclk_div3
.hw
,
506 [CLKID_FCLK_DIV4
] = &meson8b_fclk_div4
.hw
,
507 [CLKID_FCLK_DIV5
] = &meson8b_fclk_div5
.hw
,
508 [CLKID_FCLK_DIV7
] = &meson8b_fclk_div7
.hw
,
509 [CLKID_CPUCLK
] = &meson8b_cpu_clk
.hw
,
510 [CLKID_MPEG_SEL
] = &meson8b_mpeg_clk_sel
.hw
,
511 [CLKID_MPEG_DIV
] = &meson8b_mpeg_clk_div
.hw
,
512 [CLKID_CLK81
] = &meson8b_clk81
.hw
,
513 [CLKID_DDR
] = &meson8b_ddr
.hw
,
514 [CLKID_DOS
] = &meson8b_dos
.hw
,
515 [CLKID_ISA
] = &meson8b_isa
.hw
,
516 [CLKID_PL301
] = &meson8b_pl301
.hw
,
517 [CLKID_PERIPHS
] = &meson8b_periphs
.hw
,
518 [CLKID_SPICC
] = &meson8b_spicc
.hw
,
519 [CLKID_I2C
] = &meson8b_i2c
.hw
,
520 [CLKID_SAR_ADC
] = &meson8b_sar_adc
.hw
,
521 [CLKID_SMART_CARD
] = &meson8b_smart_card
.hw
,
522 [CLKID_RNG0
] = &meson8b_rng0
.hw
,
523 [CLKID_UART0
] = &meson8b_uart0
.hw
,
524 [CLKID_SDHC
] = &meson8b_sdhc
.hw
,
525 [CLKID_STREAM
] = &meson8b_stream
.hw
,
526 [CLKID_ASYNC_FIFO
] = &meson8b_async_fifo
.hw
,
527 [CLKID_SDIO
] = &meson8b_sdio
.hw
,
528 [CLKID_ABUF
] = &meson8b_abuf
.hw
,
529 [CLKID_HIU_IFACE
] = &meson8b_hiu_iface
.hw
,
530 [CLKID_ASSIST_MISC
] = &meson8b_assist_misc
.hw
,
531 [CLKID_SPI
] = &meson8b_spi
.hw
,
532 [CLKID_I2S_SPDIF
] = &meson8b_i2s_spdif
.hw
,
533 [CLKID_ETH
] = &meson8b_eth
.hw
,
534 [CLKID_DEMUX
] = &meson8b_demux
.hw
,
535 [CLKID_AIU_GLUE
] = &meson8b_aiu_glue
.hw
,
536 [CLKID_IEC958
] = &meson8b_iec958
.hw
,
537 [CLKID_I2S_OUT
] = &meson8b_i2s_out
.hw
,
538 [CLKID_AMCLK
] = &meson8b_amclk
.hw
,
539 [CLKID_AIFIFO2
] = &meson8b_aififo2
.hw
,
540 [CLKID_MIXER
] = &meson8b_mixer
.hw
,
541 [CLKID_MIXER_IFACE
] = &meson8b_mixer_iface
.hw
,
542 [CLKID_ADC
] = &meson8b_adc
.hw
,
543 [CLKID_BLKMV
] = &meson8b_blkmv
.hw
,
544 [CLKID_AIU
] = &meson8b_aiu
.hw
,
545 [CLKID_UART1
] = &meson8b_uart1
.hw
,
546 [CLKID_G2D
] = &meson8b_g2d
.hw
,
547 [CLKID_USB0
] = &meson8b_usb0
.hw
,
548 [CLKID_USB1
] = &meson8b_usb1
.hw
,
549 [CLKID_RESET
] = &meson8b_reset
.hw
,
550 [CLKID_NAND
] = &meson8b_nand
.hw
,
551 [CLKID_DOS_PARSER
] = &meson8b_dos_parser
.hw
,
552 [CLKID_USB
] = &meson8b_usb
.hw
,
553 [CLKID_VDIN1
] = &meson8b_vdin1
.hw
,
554 [CLKID_AHB_ARB0
] = &meson8b_ahb_arb0
.hw
,
555 [CLKID_EFUSE
] = &meson8b_efuse
.hw
,
556 [CLKID_BOOT_ROM
] = &meson8b_boot_rom
.hw
,
557 [CLKID_AHB_DATA_BUS
] = &meson8b_ahb_data_bus
.hw
,
558 [CLKID_AHB_CTRL_BUS
] = &meson8b_ahb_ctrl_bus
.hw
,
559 [CLKID_HDMI_INTR_SYNC
] = &meson8b_hdmi_intr_sync
.hw
,
560 [CLKID_HDMI_PCLK
] = &meson8b_hdmi_pclk
.hw
,
561 [CLKID_USB1_DDR_BRIDGE
] = &meson8b_usb1_ddr_bridge
.hw
,
562 [CLKID_USB0_DDR_BRIDGE
] = &meson8b_usb0_ddr_bridge
.hw
,
563 [CLKID_MMC_PCLK
] = &meson8b_mmc_pclk
.hw
,
564 [CLKID_DVIN
] = &meson8b_dvin
.hw
,
565 [CLKID_UART2
] = &meson8b_uart2
.hw
,
566 [CLKID_SANA
] = &meson8b_sana
.hw
,
567 [CLKID_VPU_INTR
] = &meson8b_vpu_intr
.hw
,
568 [CLKID_SEC_AHB_AHB3_BRIDGE
] = &meson8b_sec_ahb_ahb3_bridge
.hw
,
569 [CLKID_CLK81_A9
] = &meson8b_clk81_a9
.hw
,
570 [CLKID_VCLK2_VENCI0
] = &meson8b_vclk2_venci0
.hw
,
571 [CLKID_VCLK2_VENCI1
] = &meson8b_vclk2_venci1
.hw
,
572 [CLKID_VCLK2_VENCP0
] = &meson8b_vclk2_vencp0
.hw
,
573 [CLKID_VCLK2_VENCP1
] = &meson8b_vclk2_vencp1
.hw
,
574 [CLKID_GCLK_VENCI_INT
] = &meson8b_gclk_venci_int
.hw
,
575 [CLKID_GCLK_VENCP_INT
] = &meson8b_gclk_vencp_int
.hw
,
576 [CLKID_DAC_CLK
] = &meson8b_dac_clk
.hw
,
577 [CLKID_AOCLK_GATE
] = &meson8b_aoclk_gate
.hw
,
578 [CLKID_IEC958_GATE
] = &meson8b_iec958_gate
.hw
,
579 [CLKID_ENC480P
] = &meson8b_enc480p
.hw
,
580 [CLKID_RNG1
] = &meson8b_rng1
.hw
,
581 [CLKID_GCLK_VENCL_INT
] = &meson8b_gclk_vencl_int
.hw
,
582 [CLKID_VCLK2_VENCLMCC
] = &meson8b_vclk2_venclmcc
.hw
,
583 [CLKID_VCLK2_VENCL
] = &meson8b_vclk2_vencl
.hw
,
584 [CLKID_VCLK2_OTHER
] = &meson8b_vclk2_other
.hw
,
585 [CLKID_EDP
] = &meson8b_edp
.hw
,
586 [CLKID_AO_MEDIA_CPU
] = &meson8b_ao_media_cpu
.hw
,
587 [CLKID_AO_AHB_SRAM
] = &meson8b_ao_ahb_sram
.hw
,
588 [CLKID_AO_AHB_BUS
] = &meson8b_ao_ahb_bus
.hw
,
589 [CLKID_AO_IFACE
] = &meson8b_ao_iface
.hw
,
590 [CLKID_MPLL0
] = &meson8b_mpll0
.hw
,
591 [CLKID_MPLL1
] = &meson8b_mpll1
.hw
,
592 [CLKID_MPLL2
] = &meson8b_mpll2
.hw
,
597 static struct meson_clk_pll
*const meson8b_clk_plls
[] = {
603 static struct meson_clk_mpll
*const meson8b_clk_mplls
[] = {
609 static struct clk_gate
*const meson8b_clk_gates
[] = {
628 &meson8b_assist_misc
,
639 &meson8b_mixer_iface
,
655 &meson8b_ahb_data_bus
,
656 &meson8b_ahb_ctrl_bus
,
657 &meson8b_hdmi_intr_sync
,
659 &meson8b_usb1_ddr_bridge
,
660 &meson8b_usb0_ddr_bridge
,
666 &meson8b_sec_ahb_ahb3_bridge
,
668 &meson8b_vclk2_venci0
,
669 &meson8b_vclk2_venci1
,
670 &meson8b_vclk2_vencp0
,
671 &meson8b_vclk2_vencp1
,
672 &meson8b_gclk_venci_int
,
673 &meson8b_gclk_vencp_int
,
676 &meson8b_iec958_gate
,
679 &meson8b_gclk_vencl_int
,
680 &meson8b_vclk2_venclmcc
,
681 &meson8b_vclk2_vencl
,
682 &meson8b_vclk2_other
,
684 &meson8b_ao_media_cpu
,
685 &meson8b_ao_ahb_sram
,
690 static struct clk_mux
*const meson8b_clk_muxes
[] = {
691 &meson8b_mpeg_clk_sel
,
694 static struct clk_divider
*const meson8b_clk_dividers
[] = {
695 &meson8b_mpeg_clk_div
,
698 static int meson8b_clkc_probe(struct platform_device
*pdev
)
700 void __iomem
*clk_base
;
702 struct clk_hw
*parent_hw
;
703 struct clk
*parent_clk
;
704 struct device
*dev
= &pdev
->dev
;
706 /* Generic clocks and PLLs */
707 clk_base
= of_iomap(dev
->of_node
, 1);
709 pr_err("%s: Unable to map clk base\n", __func__
);
713 /* Populate base address for PLLs */
714 for (i
= 0; i
< ARRAY_SIZE(meson8b_clk_plls
); i
++)
715 meson8b_clk_plls
[i
]->base
= clk_base
;
717 /* Populate base address for MPLLs */
718 for (i
= 0; i
< ARRAY_SIZE(meson8b_clk_mplls
); i
++)
719 meson8b_clk_mplls
[i
]->base
= clk_base
;
721 /* Populate the base address for CPU clk */
722 meson8b_cpu_clk
.base
= clk_base
;
724 /* Populate base address for gates */
725 for (i
= 0; i
< ARRAY_SIZE(meson8b_clk_gates
); i
++)
726 meson8b_clk_gates
[i
]->reg
= clk_base
+
727 (u32
)meson8b_clk_gates
[i
]->reg
;
729 /* Populate base address for muxes */
730 for (i
= 0; i
< ARRAY_SIZE(meson8b_clk_muxes
); i
++)
731 meson8b_clk_muxes
[i
]->reg
= clk_base
+
732 (u32
)meson8b_clk_muxes
[i
]->reg
;
734 /* Populate base address for dividers */
735 for (i
= 0; i
< ARRAY_SIZE(meson8b_clk_dividers
); i
++)
736 meson8b_clk_dividers
[i
]->reg
= clk_base
+
737 (u32
)meson8b_clk_dividers
[i
]->reg
;
741 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
743 for (clkid
= CLKID_XTAL
; clkid
< CLK_NR_CLKS
; clkid
++) {
744 /* array might be sparse */
745 if (!meson8b_hw_onecell_data
.hws
[clkid
])
748 /* FIXME convert to devm_clk_register */
749 ret
= devm_clk_hw_register(dev
, meson8b_hw_onecell_data
.hws
[clkid
]);
755 * Register CPU clk notifier
757 * FIXME this is wrong for a lot of reasons. First, the muxes should be
758 * struct clk_hw objects. Second, we shouldn't program the muxes in
759 * notifier handlers. The tricky programming sequence will be handled
760 * by the forthcoming coordinated clock rates mechanism once that
761 * feature is released.
763 * Furthermore, looking up the parent this way is terrible. At some
764 * point we will stop allocating a default struct clk when registering
765 * a new clk_hw, and this hack will no longer work. Releasing the ccr
766 * feature before that time solves the problem :-)
768 parent_hw
= clk_hw_get_parent(&meson8b_cpu_clk
.hw
);
769 parent_clk
= parent_hw
->clk
;
770 ret
= clk_notifier_register(parent_clk
, &meson8b_cpu_clk
.clk_nb
);
772 pr_err("%s: failed to register clock notifier for cpu_clk\n",
777 return of_clk_add_hw_provider(dev
->of_node
, of_clk_hw_onecell_get
,
778 &meson8b_hw_onecell_data
);
785 static const struct of_device_id meson8b_clkc_match_table
[] = {
786 { .compatible
= "amlogic,meson8-clkc" },
787 { .compatible
= "amlogic,meson8b-clkc" },
788 { .compatible
= "amlogic,meson8m2-clkc" },
792 static struct platform_driver meson8b_driver
= {
793 .probe
= meson8b_clkc_probe
,
795 .name
= "meson8b-clkc",
796 .of_match_table
= meson8b_clkc_match_table
,
800 builtin_platform_driver(meson8b_driver
);