drivers/clk/meson/meson8b.c

   1 /*
   2  * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
   3  * Driver
   4  *
   5  * Copyright (c) 2015 Endless Mobile, Inc.
   6  * Author: Carlo Caione <carlo@endlessm.com>
   7  *
   8  * Copyright (c) 2016 BayLibre, Inc.
   9  * Michael Turquette <mturquette@baylibre.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms and conditions of the GNU General Public License,
  13  * version 2, as published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program.  If not, see <http://www.gnu.org/licenses/>.
  22  */
  23
  24 #include <linux/clk.h>
  25 #include <linux/clk-provider.h>
  26 #include <linux/of_address.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/init.h>
  29
  30 #include "clkc.h"
  31 #include "meson8b.h"
  32
  33 static DEFINE_SPINLOCK(clk_lock);
  34
  35 static const struct pll_rate_table sys_pll_rate_table[] = {
  36         PLL_RATE(312000000, 52, 1, 2),
  37         PLL_RATE(336000000, 56, 1, 2),
  38         PLL_RATE(360000000, 60, 1, 2),
  39         PLL_RATE(384000000, 64, 1, 2),
  40         PLL_RATE(408000000, 68, 1, 2),
  41         PLL_RATE(432000000, 72, 1, 2),
  42         PLL_RATE(456000000, 76, 1, 2),
  43         PLL_RATE(480000000, 80, 1, 2),
  44         PLL_RATE(504000000, 84, 1, 2),
  45         PLL_RATE(528000000, 88, 1, 2),
  46         PLL_RATE(552000000, 92, 1, 2),
  47         PLL_RATE(576000000, 96, 1, 2),
  48         PLL_RATE(600000000, 50, 1, 1),
  49         PLL_RATE(624000000, 52, 1, 1),
  50         PLL_RATE(648000000, 54, 1, 1),
  51         PLL_RATE(672000000, 56, 1, 1),
  52         PLL_RATE(696000000, 58, 1, 1),
  53         PLL_RATE(720000000, 60, 1, 1),
  54         PLL_RATE(744000000, 62, 1, 1),
  55         PLL_RATE(768000000, 64, 1, 1),
  56         PLL_RATE(792000000, 66, 1, 1),
  57         PLL_RATE(816000000, 68, 1, 1),
  58         PLL_RATE(840000000, 70, 1, 1),
  59         PLL_RATE(864000000, 72, 1, 1),
  60         PLL_RATE(888000000, 74, 1, 1),
  61         PLL_RATE(912000000, 76, 1, 1),
  62         PLL_RATE(936000000, 78, 1, 1),
  63         PLL_RATE(960000000, 80, 1, 1),
  64         PLL_RATE(984000000, 82, 1, 1),
  65         PLL_RATE(1008000000, 84, 1, 1),
  66         PLL_RATE(1032000000, 86, 1, 1),
  67         PLL_RATE(1056000000, 88, 1, 1),
  68         PLL_RATE(1080000000, 90, 1, 1),
  69         PLL_RATE(1104000000, 92, 1, 1),
  70         PLL_RATE(1128000000, 94, 1, 1),
  71         PLL_RATE(1152000000, 96, 1, 1),
  72         PLL_RATE(1176000000, 98, 1, 1),
  73         PLL_RATE(1200000000, 50, 1, 0),
  74         PLL_RATE(1224000000, 51, 1, 0),
  75         PLL_RATE(1248000000, 52, 1, 0),
  76         PLL_RATE(1272000000, 53, 1, 0),
  77         PLL_RATE(1296000000, 54, 1, 0),
  78         PLL_RATE(1320000000, 55, 1, 0),
  79         PLL_RATE(1344000000, 56, 1, 0),
  80         PLL_RATE(1368000000, 57, 1, 0),
  81         PLL_RATE(1392000000, 58, 1, 0),
  82         PLL_RATE(1416000000, 59, 1, 0),
  83         PLL_RATE(1440000000, 60, 1, 0),
  84         PLL_RATE(1464000000, 61, 1, 0),
  85         PLL_RATE(1488000000, 62, 1, 0),
  86         PLL_RATE(1512000000, 63, 1, 0),
  87         PLL_RATE(1536000000, 64, 1, 0),
  88         { /* sentinel */ },
  89 };
  90
  91 static const struct clk_div_table cpu_div_table[] = {
  92         { .val = 1, .div = 1 },
  93         { .val = 2, .div = 2 },
  94         { .val = 3, .div = 3 },
  95         { .val = 2, .div = 4 },
  96         { .val = 3, .div = 6 },
  97         { .val = 4, .div = 8 },
  98         { .val = 5, .div = 10 },
  99         { .val = 6, .div = 12 },
 100         { .val = 7, .div = 14 },
 101         { .val = 8, .div = 16 },
 102         { /* sentinel */ },
 103 };
 104
 105 static struct clk_fixed_rate meson8b_xtal = {
 106         .fixed_rate = 24000000,
 107         .hw.init = &(struct clk_init_data){
 108                 .name = "xtal",
 109                 .num_parents = 0,
 110                 .ops = &clk_fixed_rate_ops,
 111         },
 112 };
 113
 114 static struct meson_clk_pll meson8b_fixed_pll = {
 115         .m = {
 116                 .reg_off = HHI_MPLL_CNTL,
 117                 .shift   = 0,
 118                 .width   = 9,
 119         },
 120         .n = {
 121                 .reg_off = HHI_MPLL_CNTL,
 122                 .shift   = 9,
 123                 .width   = 5,
 124         },
 125         .od = {
 126                 .reg_off = HHI_MPLL_CNTL,
 127                 .shift   = 16,
 128                 .width   = 2,
 129         },
 130         .lock = &clk_lock,
 131         .hw.init = &(struct clk_init_data){
 132                 .name = "fixed_pll",
 133                 .ops = &meson_clk_pll_ro_ops,
 134                 .parent_names = (const char *[]){ "xtal" },
 135                 .num_parents = 1,
 136                 .flags = CLK_GET_RATE_NOCACHE,
 137         },
 138 };
 139
 140 static struct meson_clk_pll meson8b_vid_pll = {
 141         .m = {
 142                 .reg_off = HHI_VID_PLL_CNTL,
 143                 .shift   = 0,
 144                 .width   = 9,
 145         },
 146         .n = {
 147                 .reg_off = HHI_VID_PLL_CNTL,
 148                 .shift   = 9,
 149                 .width   = 5,
 150         },
 151         .od = {
 152                 .reg_off = HHI_VID_PLL_CNTL,
 153                 .shift   = 16,
 154                 .width   = 2,
 155         },
 156         .lock = &clk_lock,
 157         .hw.init = &(struct clk_init_data){
 158                 .name = "vid_pll",
 159                 .ops = &meson_clk_pll_ro_ops,
 160                 .parent_names = (const char *[]){ "xtal" },
 161                 .num_parents = 1,
 162                 .flags = CLK_GET_RATE_NOCACHE,
 163         },
 164 };
 165
 166 static struct meson_clk_pll meson8b_sys_pll = {
 167         .m = {
 168                 .reg_off = HHI_SYS_PLL_CNTL,
 169                 .shift   = 0,
 170                 .width   = 9,
 171         },
 172         .n = {
 173                 .reg_off = HHI_SYS_PLL_CNTL,
 174                 .shift   = 9,
 175                 .width   = 5,
 176         },
 177         .od = {
 178                 .reg_off = HHI_SYS_PLL_CNTL,
 179                 .shift   = 16,
 180                 .width   = 2,
 181         },
 182         .rate_table = sys_pll_rate_table,
 183         .rate_count = ARRAY_SIZE(sys_pll_rate_table),
 184         .lock = &clk_lock,
 185         .hw.init = &(struct clk_init_data){
 186                 .name = "sys_pll",
 187                 .ops = &meson_clk_pll_ops,
 188                 .parent_names = (const char *[]){ "xtal" },
 189                 .num_parents = 1,
 190                 .flags = CLK_GET_RATE_NOCACHE,
 191         },
 192 };
 193
 194 static struct clk_fixed_factor meson8b_fclk_div2 = {
 195         .mult = 1,
 196         .div = 2,
 197         .hw.init = &(struct clk_init_data){
 198                 .name = "fclk_div2",
 199                 .ops = &clk_fixed_factor_ops,
 200                 .parent_names = (const char *[]){ "fixed_pll" },
 201                 .num_parents = 1,
 202         },
 203 };
 204
 205 static struct clk_fixed_factor meson8b_fclk_div3 = {
 206         .mult = 1,
 207         .div = 3,
 208         .hw.init = &(struct clk_init_data){
 209                 .name = "fclk_div3",
 210                 .ops = &clk_fixed_factor_ops,
 211                 .parent_names = (const char *[]){ "fixed_pll" },
 212                 .num_parents = 1,
 213         },
 214 };
 215
 216 static struct clk_fixed_factor meson8b_fclk_div4 = {
 217         .mult = 1,
 218         .div = 4,
 219         .hw.init = &(struct clk_init_data){
 220                 .name = "fclk_div4",
 221                 .ops = &clk_fixed_factor_ops,
 222                 .parent_names = (const char *[]){ "fixed_pll" },
 223                 .num_parents = 1,
 224         },
 225 };
 226
 227 static struct clk_fixed_factor meson8b_fclk_div5 = {
 228         .mult = 1,
 229         .div = 5,
 230         .hw.init = &(struct clk_init_data){
 231                 .name = "fclk_div5",
 232                 .ops = &clk_fixed_factor_ops,
 233                 .parent_names = (const char *[]){ "fixed_pll" },
 234                 .num_parents = 1,
 235         },
 236 };
 237
 238 static struct clk_fixed_factor meson8b_fclk_div7 = {
 239         .mult = 1,
 240         .div = 7,
 241         .hw.init = &(struct clk_init_data){
 242                 .name = "fclk_div7",
 243                 .ops = &clk_fixed_factor_ops,
 244                 .parent_names = (const char *[]){ "fixed_pll" },
 245                 .num_parents = 1,
 246         },
 247 };
 248
 249 static struct meson_clk_mpll meson8b_mpll0 = {
 250         .sdm = {
 251                 .reg_off = HHI_MPLL_CNTL7,
 252                 .shift   = 0,
 253                 .width   = 14,
 254         },
 255         .sdm_en = {
 256                 .reg_off = HHI_MPLL_CNTL7,
 257                 .shift   = 15,
 258                 .width   = 1,
 259         },
 260         .n2 = {
 261                 .reg_off = HHI_MPLL_CNTL7,
 262                 .shift   = 16,
 263                 .width   = 9,
 264         },
 265         .en = {
 266                 .reg_off = HHI_MPLL_CNTL7,
 267                 .shift   = 14,
 268                 .width   = 1,
 269         },
 270         .lock = &clk_lock,
 271         .hw.init = &(struct clk_init_data){
 272                 .name = "mpll0",
 273                 .ops = &meson_clk_mpll_ops,
 274                 .parent_names = (const char *[]){ "fixed_pll" },
 275                 .num_parents = 1,
 276         },
 277 };
 278
 279 static struct meson_clk_mpll meson8b_mpll1 = {
 280         .sdm = {
 281                 .reg_off = HHI_MPLL_CNTL8,
 282                 .shift   = 0,
 283                 .width   = 14,
 284         },
 285         .sdm_en = {
 286                 .reg_off = HHI_MPLL_CNTL8,
 287                 .shift   = 15,
 288                 .width   = 1,
 289         },
 290         .n2 = {
 291                 .reg_off = HHI_MPLL_CNTL8,
 292                 .shift   = 16,
 293                 .width   = 9,
 294         },
 295         .en = {
 296                 .reg_off = HHI_MPLL_CNTL8,
 297                 .shift   = 14,
 298                 .width   = 1,
 299         },
 300         .lock = &clk_lock,
 301         .hw.init = &(struct clk_init_data){
 302                 .name = "mpll1",
 303                 .ops = &meson_clk_mpll_ops,
 304                 .parent_names = (const char *[]){ "fixed_pll" },
 305                 .num_parents = 1,
 306         },
 307 };
 308
 309 static struct meson_clk_mpll meson8b_mpll2 = {
 310         .sdm = {
 311                 .reg_off = HHI_MPLL_CNTL9,
 312                 .shift   = 0,
 313                 .width   = 14,
 314         },
 315         .sdm_en = {
 316                 .reg_off = HHI_MPLL_CNTL9,
 317                 .shift   = 15,
 318                 .width   = 1,
 319         },
 320         .n2 = {
 321                 .reg_off = HHI_MPLL_CNTL9,
 322                 .shift   = 16,
 323                 .width   = 9,
 324         },
 325         .en = {
 326                 .reg_off = HHI_MPLL_CNTL9,
 327                 .shift   = 14,
 328                 .width   = 1,
 329         },
 330         .lock = &clk_lock,
 331         .hw.init = &(struct clk_init_data){
 332                 .name = "mpll2",
 333                 .ops = &meson_clk_mpll_ops,
 334                 .parent_names = (const char *[]){ "fixed_pll" },
 335                 .num_parents = 1,
 336         },
 337 };
 338
 339 /*
 340  * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
 341  * post-dividers and should be modeled with their respective PLLs via the
 342  * forthcoming coordinated clock rates feature
 343  */
 344 static struct meson_clk_cpu meson8b_cpu_clk = {
 345         .reg_off = HHI_SYS_CPU_CLK_CNTL1,
 346         .div_table = cpu_div_table,
 347         .clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
 348         .hw.init = &(struct clk_init_data){
 349                 .name = "cpu_clk",
 350                 .ops = &meson_clk_cpu_ops,
 351                 .parent_names = (const char *[]){ "sys_pll" },
 352                 .num_parents = 1,
 353         },
 354 };
 355
 356 static u32 mux_table_clk81[]    = { 6, 5, 7 };
 357
 358 struct clk_mux meson8b_mpeg_clk_sel = {
 359         .reg = (void *)HHI_MPEG_CLK_CNTL,
 360         .mask = 0x7,
 361         .shift = 12,
 362         .flags = CLK_MUX_READ_ONLY,
 363         .table = mux_table_clk81,
 364         .lock = &clk_lock,
 365         .hw.init = &(struct clk_init_data){
 366                 .name = "mpeg_clk_sel",
 367                 .ops = &clk_mux_ro_ops,
 368                 /*
 369                  * FIXME bits 14:12 selects from 8 possible parents:
 370                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 371                  * fclk_div4, fclk_div3, fclk_div5
 372                  */
 373                 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
 374                         "fclk_div5" },
 375                 .num_parents = 3,
 376                 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
 377         },
 378 };
 379
 380 struct clk_divider meson8b_mpeg_clk_div = {
 381         .reg = (void *)HHI_MPEG_CLK_CNTL,
 382         .shift = 0,
 383         .width = 7,
 384         .lock = &clk_lock,
 385         .hw.init = &(struct clk_init_data){
 386                 .name = "mpeg_clk_div",
 387                 .ops = &clk_divider_ops,
 388                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
 389                 .num_parents = 1,
 390                 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
 391         },
 392 };
 393
 394 struct clk_gate meson8b_clk81 = {
 395         .reg = (void *)HHI_MPEG_CLK_CNTL,
 396         .bit_idx = 7,
 397         .lock = &clk_lock,
 398         .hw.init = &(struct clk_init_data){
 399                 .name = "clk81",
 400                 .ops = &clk_gate_ops,
 401                 .parent_names = (const char *[]){ "mpeg_clk_div" },
 402                 .num_parents = 1,
 403                 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
 404         },
 405 };
 406
 407 /* Everything Else (EE) domain gates */
 408
 409 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
 410 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
 411 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
 412 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
 413 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
 414 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
 415 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
 416 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
 417 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
 418 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
 419 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
 420 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
 421 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
 422 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
 423 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
 424 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
 425 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
 426 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
 427 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
 428
 429 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
 430 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
 431 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
 432 static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
 433 static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
 434 static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
 435 static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
 436 static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
 437 static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
 438 static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
 439 static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
 440 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
 441 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
 442 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
 443 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
 444 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
 445 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
 446 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
 447 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
 448 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
 449 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
 450 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
 451 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
 452 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
 453 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
 454
 455 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
 456 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
 457 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
 458 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
 459 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
 460 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
 461 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
 462 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
 463 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
 464 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
 465 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
 466 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
 467 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
 468
 469 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
 470 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
 471 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
 472 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
 473 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
 474 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
 475 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
 476 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
 477 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
 478 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
 479 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
 480 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
 481 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
 482 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
 483 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
 484 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
 485
 486 /* Always On (AO) domain gates */
 487
 488 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
 489 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
 490 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
 491 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
 492
 493 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
 494         .hws = {
 495                 [CLKID_XTAL] = &meson8b_xtal.hw,
 496                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
 497                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
 498                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
 499                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
 500                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
 501                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
 502                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
 503                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
 504                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
 505                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
 506                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
 507                 [CLKID_CLK81] = &meson8b_clk81.hw,
 508                 [CLKID_DDR]                 = &meson8b_ddr.hw,
 509                 [CLKID_DOS]                 = &meson8b_dos.hw,
 510                 [CLKID_ISA]                 = &meson8b_isa.hw,
 511                 [CLKID_PL301]               = &meson8b_pl301.hw,
 512                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
 513                 [CLKID_SPICC]               = &meson8b_spicc.hw,
 514                 [CLKID_I2C]                 = &meson8b_i2c.hw,
 515                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
 516                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
 517                 [CLKID_RNG0]                = &meson8b_rng0.hw,
 518                 [CLKID_UART0]               = &meson8b_uart0.hw,
 519                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
 520                 [CLKID_STREAM]              = &meson8b_stream.hw,
 521                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
 522                 [CLKID_SDIO]                = &meson8b_sdio.hw,
 523                 [CLKID_ABUF]                = &meson8b_abuf.hw,
 524                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
 525                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
 526                 [CLKID_SPI]                 = &meson8b_spi.hw,
 527                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
 528                 [CLKID_ETH]                 = &meson8b_eth.hw,
 529                 [CLKID_DEMUX]               = &meson8b_demux.hw,
 530                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
 531                 [CLKID_IEC958]              = &meson8b_iec958.hw,
 532                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
 533                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
 534                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
 535                 [CLKID_MIXER]               = &meson8b_mixer.hw,
 536                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
 537                 [CLKID_ADC]                 = &meson8b_adc.hw,
 538                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
 539                 [CLKID_AIU]                 = &meson8b_aiu.hw,
 540                 [CLKID_UART1]               = &meson8b_uart1.hw,
 541                 [CLKID_G2D]                 = &meson8b_g2d.hw,
 542                 [CLKID_USB0]                = &meson8b_usb0.hw,
 543                 [CLKID_USB1]                = &meson8b_usb1.hw,
 544                 [CLKID_RESET]               = &meson8b_reset.hw,
 545                 [CLKID_NAND]                = &meson8b_nand.hw,
 546                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
 547                 [CLKID_USB]                 = &meson8b_usb.hw,
 548                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
 549                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
 550                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
 551                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
 552                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
 553                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
 554                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
 555                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
 556                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
 557                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
 558                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
 559                 [CLKID_DVIN]                = &meson8b_dvin.hw,
 560                 [CLKID_UART2]               = &meson8b_uart2.hw,
 561                 [CLKID_SANA]                = &meson8b_sana.hw,
 562                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
 563                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
 564                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
 565                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
 566                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
 567                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
 568                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
 569                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
 570                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
 571                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
 572                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
 573                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
 574                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
 575                 [CLKID_RNG1]                = &meson8b_rng1.hw,
 576                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
 577                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
 578                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
 579                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
 580                 [CLKID_EDP]                 = &meson8b_edp.hw,
 581                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
 582                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
 583                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
 584                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
 585                 [CLKID_MPLL0]               = &meson8b_mpll0.hw,
 586                 [CLKID_MPLL1]               = &meson8b_mpll1.hw,
 587                 [CLKID_MPLL2]               = &meson8b_mpll2.hw,
 588         },
 589         .num = CLK_NR_CLKS,
 590 };
 591
 592 static struct meson_clk_pll *const meson8b_clk_plls[] = {
 593         &meson8b_fixed_pll,
 594         &meson8b_vid_pll,
 595         &meson8b_sys_pll,
 596 };
 597
 598 static struct meson_clk_mpll *const meson8b_clk_mplls[] = {
 599         &meson8b_mpll0,
 600         &meson8b_mpll1,
 601         &meson8b_mpll2,
 602 };
 603
 604 static struct clk_gate *const meson8b_clk_gates[] = {
 605         &meson8b_clk81,
 606         &meson8b_ddr,
 607         &meson8b_dos,
 608         &meson8b_isa,
 609         &meson8b_pl301,
 610         &meson8b_periphs,
 611         &meson8b_spicc,
 612         &meson8b_i2c,
 613         &meson8b_sar_adc,
 614         &meson8b_smart_card,
 615         &meson8b_rng0,
 616         &meson8b_uart0,
 617         &meson8b_sdhc,
 618         &meson8b_stream,
 619         &meson8b_async_fifo,
 620         &meson8b_sdio,
 621         &meson8b_abuf,
 622         &meson8b_hiu_iface,
 623         &meson8b_assist_misc,
 624         &meson8b_spi,
 625         &meson8b_i2s_spdif,
 626         &meson8b_eth,
 627         &meson8b_demux,
 628         &meson8b_aiu_glue,
 629         &meson8b_iec958,
 630         &meson8b_i2s_out,
 631         &meson8b_amclk,
 632         &meson8b_aififo2,
 633         &meson8b_mixer,
 634         &meson8b_mixer_iface,
 635         &meson8b_adc,
 636         &meson8b_blkmv,
 637         &meson8b_aiu,
 638         &meson8b_uart1,
 639         &meson8b_g2d,
 640         &meson8b_usb0,
 641         &meson8b_usb1,
 642         &meson8b_reset,
 643         &meson8b_nand,
 644         &meson8b_dos_parser,
 645         &meson8b_usb,
 646         &meson8b_vdin1,
 647         &meson8b_ahb_arb0,
 648         &meson8b_efuse,
 649         &meson8b_boot_rom,
 650         &meson8b_ahb_data_bus,
 651         &meson8b_ahb_ctrl_bus,
 652         &meson8b_hdmi_intr_sync,
 653         &meson8b_hdmi_pclk,
 654         &meson8b_usb1_ddr_bridge,
 655         &meson8b_usb0_ddr_bridge,
 656         &meson8b_mmc_pclk,
 657         &meson8b_dvin,
 658         &meson8b_uart2,
 659         &meson8b_sana,
 660         &meson8b_vpu_intr,
 661         &meson8b_sec_ahb_ahb3_bridge,
 662         &meson8b_clk81_a9,
 663         &meson8b_vclk2_venci0,
 664         &meson8b_vclk2_venci1,
 665         &meson8b_vclk2_vencp0,
 666         &meson8b_vclk2_vencp1,
 667         &meson8b_gclk_venci_int,
 668         &meson8b_gclk_vencp_int,
 669         &meson8b_dac_clk,
 670         &meson8b_aoclk_gate,
 671         &meson8b_iec958_gate,
 672         &meson8b_enc480p,
 673         &meson8b_rng1,
 674         &meson8b_gclk_vencl_int,
 675         &meson8b_vclk2_venclmcc,
 676         &meson8b_vclk2_vencl,
 677         &meson8b_vclk2_other,
 678         &meson8b_edp,
 679         &meson8b_ao_media_cpu,
 680         &meson8b_ao_ahb_sram,
 681         &meson8b_ao_ahb_bus,
 682         &meson8b_ao_iface,
 683 };
 684
 685 static struct clk_mux *const meson8b_clk_muxes[] = {
 686         &meson8b_mpeg_clk_sel,
 687 };
 688
 689 static struct clk_divider *const meson8b_clk_dividers[] = {
 690         &meson8b_mpeg_clk_div,
 691 };
 692
 693 static int meson8b_clkc_probe(struct platform_device *pdev)
 694 {
 695         void __iomem *clk_base;
 696         int ret, clkid, i;
 697         struct clk_hw *parent_hw;
 698         struct clk *parent_clk;
 699         struct device *dev = &pdev->dev;
 700
 701         /*  Generic clocks and PLLs */
 702         clk_base = of_iomap(dev->of_node, 1);
 703         if (!clk_base) {
 704                 pr_err("%s: Unable to map clk base\n", __func__);
 705                 return -ENXIO;
 706         }
 707
 708         /* Populate base address for PLLs */
 709         for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
 710                 meson8b_clk_plls[i]->base = clk_base;
 711
 712         /* Populate base address for MPLLs */
 713         for (i = 0; i < ARRAY_SIZE(meson8b_clk_mplls); i++)
 714                 meson8b_clk_mplls[i]->base = clk_base;
 715
 716         /* Populate the base address for CPU clk */
 717         meson8b_cpu_clk.base = clk_base;
 718
 719         /* Populate base address for gates */
 720         for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
 721                 meson8b_clk_gates[i]->reg = clk_base +
 722                         (u32)meson8b_clk_gates[i]->reg;
 723
 724         /* Populate base address for muxes */
 725         for (i = 0; i < ARRAY_SIZE(meson8b_clk_muxes); i++)
 726                 meson8b_clk_muxes[i]->reg = clk_base +
 727                         (u32)meson8b_clk_muxes[i]->reg;
 728
 729         /* Populate base address for dividers */
 730         for (i = 0; i < ARRAY_SIZE(meson8b_clk_dividers); i++)
 731                 meson8b_clk_dividers[i]->reg = clk_base +
 732                         (u32)meson8b_clk_dividers[i]->reg;
 733
 734         /*
 735          * register all clks
 736          * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
 737          */
 738         for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) {
 739                 /* array might be sparse */
 740                 if (!meson8b_hw_onecell_data.hws[clkid])
 741                         continue;
 742
 743                 /* FIXME convert to devm_clk_register */
 744                 ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]);
 745                 if (ret)
 746                         goto iounmap;
 747         }
 748
 749         /*
 750          * Register CPU clk notifier
 751          *
 752          * FIXME this is wrong for a lot of reasons. First, the muxes should be
 753          * struct clk_hw objects. Second, we shouldn't program the muxes in
 754          * notifier handlers. The tricky programming sequence will be handled
 755          * by the forthcoming coordinated clock rates mechanism once that
 756          * feature is released.
 757          *
 758          * Furthermore, looking up the parent this way is terrible. At some
 759          * point we will stop allocating a default struct clk when registering
 760          * a new clk_hw, and this hack will no longer work. Releasing the ccr
 761          * feature before that time solves the problem :-)
 762          */
 763         parent_hw = clk_hw_get_parent(&meson8b_cpu_clk.hw);
 764         parent_clk = parent_hw->clk;
 765         ret = clk_notifier_register(parent_clk, &meson8b_cpu_clk.clk_nb);
 766         if (ret) {
 767                 pr_err("%s: failed to register clock notifier for cpu_clk\n",
 768                                 __func__);
 769                 goto iounmap;
 770         }
 771
 772         return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
 773                         &meson8b_hw_onecell_data);
 774
 775 iounmap:
 776         iounmap(clk_base);
 777         return ret;
 778 }
 779
 780 static const struct of_device_id meson8b_clkc_match_table[] = {
 781         { .compatible = "amlogic,meson8-clkc" },
 782         { .compatible = "amlogic,meson8b-clkc" },
 783         { .compatible = "amlogic,meson8m2-clkc" },
 784         { }
 785 };
 786
 787 static struct platform_driver meson8b_driver = {
 788         .probe          = meson8b_clkc_probe,
 789         .driver         = {
 790                 .name   = "meson8b-clkc",
 791                 .of_match_table = meson8b_clkc_match_table,
 792         },
 793 };
 794
 795 builtin_platform_driver(meson8b_driver);