drivers/clk/mvebu/common.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Marvell EBU SoC common clock handling
   4  *
   5  * Copyright (C) 2012 Marvell
   6  *
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   9  * Andrew Lunn <andrew@lunn.ch>
  10  *
  11  */
  12
  13 #ifndef __CLK_MVEBU_COMMON_H_
  14 #define __CLK_MVEBU_COMMON_H_
  15
  16 #include <linux/kernel.h>
  17
  18 extern spinlock_t ctrl_gating_lock;
  19
  20 struct device_node;
  21
  22 struct coreclk_ratio {
  23         int id;
  24         const char *name;
  25 };
  26
  27 struct coreclk_soc_desc {
  28         u32 (*get_tclk_freq)(void __iomem *sar);
  29         u32 (*get_cpu_freq)(void __iomem *sar);
  30         void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
  31         u32 (*get_refclk_freq)(void __iomem *sar);
  32         bool (*is_sscg_enabled)(void __iomem *sar);
  33         u32 (*fix_sscg_deviation)(u32 system_clk);
  34         const struct coreclk_ratio *ratios;
  35         int num_ratios;
  36 };
  37
  38 struct clk_gating_soc_desc {
  39         const char *name;
  40         const char *parent;
  41         int bit_idx;
  42         unsigned long flags;
  43 };
  44
  45 void __init mvebu_coreclk_setup(struct device_node *np,
  46                                 const struct coreclk_soc_desc *desc);
  47
  48 void __init mvebu_clk_gating_setup(struct device_node *np,
  49                                    const struct clk_gating_soc_desc *desc);
  50
  51 /*
  52  * This function is shared among the Kirkwood, Armada 370, Armada XP
  53  * and Armada 375 SoC
  54  */
  55 u32 kirkwood_fix_sscg_deviation(u32 system_clk);
  56 #endif