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git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blob - drivers/clk/mxs/clk-ref.c
2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/err.h>
16 #include <linux/slab.h>
20 * struct clk_ref - mxs reference clock
21 * @hw: clk_hw for the reference clock
22 * @reg: register address
23 * @idx: the index of the reference clock within the same register
25 * The mxs reference clock sources from pll. Every 4 reference clocks share
26 * one register space, and @idx is used to identify them. Each reference
27 * clock has a gate control and a fractional * divider. The rate is calculated
28 * as pll rate * (18 / FRAC), where FRAC = 18 ~ 35.
36 #define to_clk_ref(_hw) container_of(_hw, struct clk_ref, hw)
38 static int clk_ref_enable(struct clk_hw
*hw
)
40 struct clk_ref
*ref
= to_clk_ref(hw
);
42 writel_relaxed(1 << ((ref
->idx
+ 1) * 8 - 1), ref
->reg
+ CLR
);
47 static void clk_ref_disable(struct clk_hw
*hw
)
49 struct clk_ref
*ref
= to_clk_ref(hw
);
51 writel_relaxed(1 << ((ref
->idx
+ 1) * 8 - 1), ref
->reg
+ SET
);
54 static unsigned long clk_ref_recalc_rate(struct clk_hw
*hw
,
55 unsigned long parent_rate
)
57 struct clk_ref
*ref
= to_clk_ref(hw
);
58 u64 tmp
= parent_rate
;
59 u8 frac
= (readl_relaxed(ref
->reg
) >> (ref
->idx
* 8)) & 0x3f;
67 static long clk_ref_round_rate(struct clk_hw
*hw
, unsigned long rate
,
70 unsigned long parent_rate
= *prate
;
71 u64 tmp
= parent_rate
;
74 tmp
= tmp
* 18 + rate
/ 2;
90 static int clk_ref_set_rate(struct clk_hw
*hw
, unsigned long rate
,
91 unsigned long parent_rate
)
93 struct clk_ref
*ref
= to_clk_ref(hw
);
95 u64 tmp
= parent_rate
;
97 u8 frac
, shift
= ref
->idx
* 8;
99 tmp
= tmp
* 18 + rate
/ 2;
108 spin_lock_irqsave(&mxs_lock
, flags
);
110 val
= readl_relaxed(ref
->reg
);
111 val
&= ~(0x3f << shift
);
112 val
|= frac
<< shift
;
113 writel_relaxed(val
, ref
->reg
);
115 spin_unlock_irqrestore(&mxs_lock
, flags
);
120 static const struct clk_ops clk_ref_ops
= {
121 .enable
= clk_ref_enable
,
122 .disable
= clk_ref_disable
,
123 .recalc_rate
= clk_ref_recalc_rate
,
124 .round_rate
= clk_ref_round_rate
,
125 .set_rate
= clk_ref_set_rate
,
128 struct clk
*mxs_clk_ref(const char *name
, const char *parent_name
,
129 void __iomem
*reg
, u8 idx
)
133 struct clk_init_data init
;
135 ref
= kzalloc(sizeof(*ref
), GFP_KERNEL
);
137 return ERR_PTR(-ENOMEM
);
140 init
.ops
= &clk_ref_ops
;
142 init
.parent_names
= (parent_name
? &parent_name
: NULL
);
143 init
.num_parents
= (parent_name
? 1 : 0);
147 ref
->hw
.init
= &init
;
149 clk
= clk_register(NULL
, &ref
->hw
);