drivers/clk/qcom/clk-alpha-pll.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */
   3
   4 #ifndef __QCOM_CLK_ALPHA_PLL_H__
   5 #define __QCOM_CLK_ALPHA_PLL_H__
   6
   7 #include <linux/clk-provider.h>
   8 #include "clk-regmap.h"
   9
  10 /* Alpha PLL types */
  11 enum {
  12         CLK_ALPHA_PLL_TYPE_DEFAULT,
  13         CLK_ALPHA_PLL_TYPE_HUAYRA,
  14         CLK_ALPHA_PLL_TYPE_BRAMMO,
  15         CLK_ALPHA_PLL_TYPE_FABIA,
  16         CLK_ALPHA_PLL_TYPE_TRION,
  17         CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
  18         CLK_ALPHA_PLL_TYPE_MAX,
  19 };
  20
  21 enum {
  22         PLL_OFF_L_VAL,
  23         PLL_OFF_CAL_L_VAL,
  24         PLL_OFF_ALPHA_VAL,
  25         PLL_OFF_ALPHA_VAL_U,
  26         PLL_OFF_USER_CTL,
  27         PLL_OFF_USER_CTL_U,
  28         PLL_OFF_USER_CTL_U1,
  29         PLL_OFF_CONFIG_CTL,
  30         PLL_OFF_CONFIG_CTL_U,
  31         PLL_OFF_CONFIG_CTL_U1,
  32         PLL_OFF_TEST_CTL,
  33         PLL_OFF_TEST_CTL_U,
  34         PLL_OFF_TEST_CTL_U1,
  35         PLL_OFF_STATUS,
  36         PLL_OFF_OPMODE,
  37         PLL_OFF_FRAC,
  38         PLL_OFF_CAL_VAL,
  39         PLL_OFF_MAX_REGS
  40 };
  41
  42 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
  43
  44 struct pll_vco {
  45         unsigned long min_freq;
  46         unsigned long max_freq;
  47         u32 val;
  48 };
  49
  50 #define VCO(a, b, c) { \
  51         .val = a,\
  52         .min_freq = b,\
  53         .max_freq = c,\
  54 }
  55
  56 /**
  57  * struct clk_alpha_pll - phase locked loop (PLL)
  58  * @offset: base address of registers
  59  * @vco_table: array of VCO settings
  60  * @regs: alpha pll register map (see @clk_alpha_pll_regs)
  61  * @clkr: regmap clock handle
  62  */
  63 struct clk_alpha_pll {
  64         u32 offset;
  65         const u8 *regs;
  66
  67         const struct pll_vco *vco_table;
  68         size_t num_vco;
  69 #define SUPPORTS_OFFLINE_REQ    BIT(0)
  70 #define SUPPORTS_FSM_MODE       BIT(2)
  71 #define SUPPORTS_DYNAMIC_UPDATE BIT(3)
  72         u8 flags;
  73
  74         struct clk_regmap clkr;
  75 };
  76
  77 /**
  78  * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
  79  * @offset: base address of registers
  80  * @regs: alpha pll register map (see @clk_alpha_pll_regs)
  81  * @width: width of post-divider
  82  * @post_div_shift: shift to differentiate between odd & even post-divider
  83  * @post_div_table: table with PLL odd and even post-divider settings
  84  * @num_post_div: Number of PLL post-divider settings
  85  *
  86  * @clkr: regmap clock handle
  87  */
  88 struct clk_alpha_pll_postdiv {
  89         u32 offset;
  90         u8 width;
  91         const u8 *regs;
  92
  93         struct clk_regmap clkr;
  94         int post_div_shift;
  95         const struct clk_div_table *post_div_table;
  96         size_t num_post_div;
  97 };
  98
  99 struct alpha_pll_config {
 100         u32 l;
 101         u32 alpha;
 102         u32 alpha_hi;
 103         u32 config_ctl_val;
 104         u32 config_ctl_hi_val;
 105         u32 config_ctl_hi1_val;
 106         u32 user_ctl_val;
 107         u32 user_ctl_hi_val;
 108         u32 user_ctl_hi1_val;
 109         u32 test_ctl_val;
 110         u32 test_ctl_hi_val;
 111         u32 test_ctl_hi1_val;
 112         u32 main_output_mask;
 113         u32 aux_output_mask;
 114         u32 aux2_output_mask;
 115         u32 early_output_mask;
 116         u32 alpha_en_mask;
 117         u32 alpha_mode_mask;
 118         u32 pre_div_val;
 119         u32 pre_div_mask;
 120         u32 post_div_val;
 121         u32 post_div_mask;
 122         u32 vco_val;
 123         u32 vco_mask;
 124 };
 125
 126 extern const struct clk_ops clk_alpha_pll_ops;
 127 extern const struct clk_ops clk_alpha_pll_fixed_ops;
 128 extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
 129 extern const struct clk_ops clk_alpha_pll_postdiv_ops;
 130 extern const struct clk_ops clk_alpha_pll_huayra_ops;
 131 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
 132
 133 extern const struct clk_ops clk_alpha_pll_fabia_ops;
 134 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
 135 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
 136
 137 extern const struct clk_ops clk_alpha_pll_trion_ops;
 138 extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
 139 extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
 140
 141 extern const struct clk_ops clk_alpha_pll_lucid_ops;
 142 #define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
 143 extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
 144
 145 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 146                              const struct alpha_pll_config *config);
 147 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 148                                 const struct alpha_pll_config *config);
 149 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 150                              const struct alpha_pll_config *config);
 151 #define clk_lucid_pll_configure(pll, regmap, config) \
 152         clk_trion_pll_configure(pll, regmap, config)
 153
 154
 155
 156 #endif