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clk: qcom: Allow constant ratio freq tables for rcg
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1 /*
2 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/export.h>
15 #include <linux/module.h>
16 #include <linux/regmap.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk-provider.h>
19 #include <linux/reset-controller.h>
20 #include <linux/of.h>
21
22 #include "common.h"
23 #include "clk-rcg.h"
24 #include "clk-regmap.h"
25 #include "reset.h"
26 #include "gdsc.h"
27
28 struct qcom_cc {
29 struct qcom_reset_controller reset;
30 struct clk_regmap **rclks;
31 size_t num_rclks;
32 };
33
34 const
35 struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
36 {
37 if (!f)
38 return NULL;
39
40 if (!f->freq)
41 return f;
42
43 for (; f->freq; f++)
44 if (rate <= f->freq)
45 return f;
46
47 /* Default to our fastest rate */
48 return f - 1;
49 }
50 EXPORT_SYMBOL_GPL(qcom_find_freq);
51
52 const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
53 unsigned long rate)
54 {
55 const struct freq_tbl *best = NULL;
56
57 for ( ; f->freq; f++) {
58 if (rate >= f->freq)
59 best = f;
60 else
61 break;
62 }
63
64 return best;
65 }
66 EXPORT_SYMBOL_GPL(qcom_find_freq_floor);
67
68 int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
69 {
70 int i, num_parents = clk_hw_get_num_parents(hw);
71
72 for (i = 0; i < num_parents; i++)
73 if (src == map[i].src)
74 return i;
75
76 return -ENOENT;
77 }
78 EXPORT_SYMBOL_GPL(qcom_find_src_index);
79
80 struct regmap *
81 qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
82 {
83 void __iomem *base;
84 struct resource *res;
85 struct device *dev = &pdev->dev;
86
87 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
88 base = devm_ioremap_resource(dev, res);
89 if (IS_ERR(base))
90 return ERR_CAST(base);
91
92 return devm_regmap_init_mmio(dev, base, desc->config);
93 }
94 EXPORT_SYMBOL_GPL(qcom_cc_map);
95
96 void
97 qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
98 {
99 u32 val;
100 u32 mask;
101
102 /* De-assert reset to FSM */
103 regmap_update_bits(map, reg, PLL_VOTE_FSM_RESET, 0);
104
105 /* Program bias count and lock count */
106 val = bias_count << PLL_BIAS_COUNT_SHIFT |
107 lock_count << PLL_LOCK_COUNT_SHIFT;
108 mask = PLL_BIAS_COUNT_MASK << PLL_BIAS_COUNT_SHIFT;
109 mask |= PLL_LOCK_COUNT_MASK << PLL_LOCK_COUNT_SHIFT;
110 regmap_update_bits(map, reg, mask, val);
111
112 /* Enable PLL FSM voting */
113 regmap_update_bits(map, reg, PLL_VOTE_FSM_ENA, PLL_VOTE_FSM_ENA);
114 }
115 EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);
116
117 static void qcom_cc_gdsc_unregister(void *data)
118 {
119 gdsc_unregister(data);
120 }
121
122 /*
123 * Backwards compatibility with old DTs. Register a pass-through factor 1/1
124 * clock to translate 'path' clk into 'name' clk and register the 'path'
125 * clk as a fixed rate clock if it isn't present.
126 */
127 static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
128 const char *name, unsigned long rate,
129 bool add_factor)
130 {
131 struct device_node *node = NULL;
132 struct device_node *clocks_node;
133 struct clk_fixed_factor *factor;
134 struct clk_fixed_rate *fixed;
135 struct clk_init_data init_data = { };
136 int ret;
137
138 clocks_node = of_find_node_by_path("/clocks");
139 if (clocks_node) {
140 node = of_get_child_by_name(clocks_node, path);
141 of_node_put(clocks_node);
142 }
143
144 if (!node) {
145 fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
146 if (!fixed)
147 return -EINVAL;
148
149 fixed->fixed_rate = rate;
150 fixed->hw.init = &init_data;
151
152 init_data.name = path;
153 init_data.ops = &clk_fixed_rate_ops;
154
155 ret = devm_clk_hw_register(dev, &fixed->hw);
156 if (ret)
157 return ret;
158 }
159 of_node_put(node);
160
161 if (add_factor) {
162 factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
163 if (!factor)
164 return -EINVAL;
165
166 factor->mult = factor->div = 1;
167 factor->hw.init = &init_data;
168
169 init_data.name = name;
170 init_data.parent_names = &path;
171 init_data.num_parents = 1;
172 init_data.flags = 0;
173 init_data.ops = &clk_fixed_factor_ops;
174
175 ret = devm_clk_hw_register(dev, &factor->hw);
176 if (ret)
177 return ret;
178 }
179
180 return 0;
181 }
182
183 int qcom_cc_register_board_clk(struct device *dev, const char *path,
184 const char *name, unsigned long rate)
185 {
186 bool add_factor = true;
187
188 /*
189 * TODO: The RPM clock driver currently does not support the xo clock.
190 * When xo is added to the RPM clock driver, we should change this
191 * function to skip registration of xo factor clocks.
192 */
193
194 return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
195 }
196 EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);
197
198 int qcom_cc_register_sleep_clk(struct device *dev)
199 {
200 return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
201 32768, true);
202 }
203 EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
204
205 static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
206 void *data)
207 {
208 struct qcom_cc *cc = data;
209 unsigned int idx = clkspec->args[0];
210
211 if (idx >= cc->num_rclks) {
212 pr_err("%s: invalid index %u\n", __func__, idx);
213 return ERR_PTR(-EINVAL);
214 }
215
216 return cc->rclks[idx] ? &cc->rclks[idx]->hw : ERR_PTR(-ENOENT);
217 }
218
219 int qcom_cc_really_probe(struct platform_device *pdev,
220 const struct qcom_cc_desc *desc, struct regmap *regmap)
221 {
222 int i, ret;
223 struct device *dev = &pdev->dev;
224 struct qcom_reset_controller *reset;
225 struct qcom_cc *cc;
226 struct gdsc_desc *scd;
227 size_t num_clks = desc->num_clks;
228 struct clk_regmap **rclks = desc->clks;
229
230 cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
231 if (!cc)
232 return -ENOMEM;
233
234 cc->rclks = rclks;
235 cc->num_rclks = num_clks;
236
237 for (i = 0; i < num_clks; i++) {
238 if (!rclks[i])
239 continue;
240
241 ret = devm_clk_register_regmap(dev, rclks[i]);
242 if (ret)
243 return ret;
244 }
245
246 ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
247 if (ret)
248 return ret;
249
250 reset = &cc->reset;
251 reset->rcdev.of_node = dev->of_node;
252 reset->rcdev.ops = &qcom_reset_ops;
253 reset->rcdev.owner = dev->driver->owner;
254 reset->rcdev.nr_resets = desc->num_resets;
255 reset->regmap = regmap;
256 reset->reset_map = desc->resets;
257
258 ret = devm_reset_controller_register(dev, &reset->rcdev);
259 if (ret)
260 return ret;
261
262 if (desc->gdscs && desc->num_gdscs) {
263 scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
264 if (!scd)
265 return -ENOMEM;
266 scd->dev = dev;
267 scd->scs = desc->gdscs;
268 scd->num = desc->num_gdscs;
269 ret = gdsc_register(scd, &reset->rcdev, regmap);
270 if (ret)
271 return ret;
272 ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
273 scd);
274 if (ret)
275 return ret;
276 }
277
278 return 0;
279 }
280 EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
281
282 int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
283 {
284 struct regmap *regmap;
285
286 regmap = qcom_cc_map(pdev, desc);
287 if (IS_ERR(regmap))
288 return PTR_ERR(regmap);
289
290 return qcom_cc_really_probe(pdev, desc, regmap);
291 }
292 EXPORT_SYMBOL_GPL(qcom_cc_probe);
293
294 MODULE_LICENSE("GPL v2");