2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
26 #include <dt-bindings/reset/qcom,gcc-apq8084.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
47 static const struct parent_map gcc_xo_gpll0_map
[] = {
52 static const char * const gcc_xo_gpll0
[] = {
57 static const struct parent_map gcc_xo_gpll0_gpll4_map
[] = {
63 static const char * const gcc_xo_gpll0_gpll4
[] = {
69 static const struct parent_map gcc_xo_sata_asic0_map
[] = {
71 { P_SATA_ASIC0_CLK
, 2 }
74 static const char * const gcc_xo_sata_asic0
[] = {
79 static const struct parent_map gcc_xo_sata_rx_map
[] = {
84 static const char * const gcc_xo_sata_rx
[] = {
89 static const struct parent_map gcc_xo_pcie_map
[] = {
91 { P_PCIE_0_1_PIPE_CLK
, 2 }
94 static const char * const gcc_xo_pcie
[] = {
99 static const struct parent_map gcc_xo_pcie_sleep_map
[] = {
104 static const char * const gcc_xo_pcie_sleep
[] = {
109 static struct clk_pll gpll0
= {
113 .config_reg
= 0x0014,
115 .status_reg
= 0x001c,
117 .clkr
.hw
.init
= &(struct clk_init_data
){
119 .parent_names
= (const char *[]){ "xo" },
125 static struct clk_regmap gpll0_vote
= {
126 .enable_reg
= 0x1480,
127 .enable_mask
= BIT(0),
128 .hw
.init
= &(struct clk_init_data
){
129 .name
= "gpll0_vote",
130 .parent_names
= (const char *[]){ "gpll0" },
132 .ops
= &clk_pll_vote_ops
,
136 static struct clk_rcg2 config_noc_clk_src
= {
139 .parent_map
= gcc_xo_gpll0_map
,
140 .clkr
.hw
.init
= &(struct clk_init_data
){
141 .name
= "config_noc_clk_src",
142 .parent_names
= gcc_xo_gpll0
,
144 .ops
= &clk_rcg2_ops
,
148 static struct clk_rcg2 periph_noc_clk_src
= {
151 .parent_map
= gcc_xo_gpll0_map
,
152 .clkr
.hw
.init
= &(struct clk_init_data
){
153 .name
= "periph_noc_clk_src",
154 .parent_names
= gcc_xo_gpll0
,
156 .ops
= &clk_rcg2_ops
,
160 static struct clk_rcg2 system_noc_clk_src
= {
163 .parent_map
= gcc_xo_gpll0_map
,
164 .clkr
.hw
.init
= &(struct clk_init_data
){
165 .name
= "system_noc_clk_src",
166 .parent_names
= gcc_xo_gpll0
,
168 .ops
= &clk_rcg2_ops
,
172 static struct clk_pll gpll1
= {
176 .config_reg
= 0x0054,
178 .status_reg
= 0x005c,
180 .clkr
.hw
.init
= &(struct clk_init_data
){
182 .parent_names
= (const char *[]){ "xo" },
188 static struct clk_regmap gpll1_vote
= {
189 .enable_reg
= 0x1480,
190 .enable_mask
= BIT(1),
191 .hw
.init
= &(struct clk_init_data
){
192 .name
= "gpll1_vote",
193 .parent_names
= (const char *[]){ "gpll1" },
195 .ops
= &clk_pll_vote_ops
,
199 static struct clk_pll gpll4
= {
203 .config_reg
= 0x1dd4,
205 .status_reg
= 0x1ddc,
207 .clkr
.hw
.init
= &(struct clk_init_data
){
209 .parent_names
= (const char *[]){ "xo" },
215 static struct clk_regmap gpll4_vote
= {
216 .enable_reg
= 0x1480,
217 .enable_mask
= BIT(4),
218 .hw
.init
= &(struct clk_init_data
){
219 .name
= "gpll4_vote",
220 .parent_names
= (const char *[]){ "gpll4" },
222 .ops
= &clk_pll_vote_ops
,
226 static const struct freq_tbl ftbl_gcc_ufs_axi_clk
[] = {
227 F(100000000, P_GPLL0
, 6, 0, 0),
228 F(200000000, P_GPLL0
, 3, 0, 0),
229 F(240000000, P_GPLL0
, 2.5, 0, 0),
233 static struct clk_rcg2 ufs_axi_clk_src
= {
237 .parent_map
= gcc_xo_gpll0_map
,
238 .freq_tbl
= ftbl_gcc_ufs_axi_clk
,
239 .clkr
.hw
.init
= &(struct clk_init_data
){
240 .name
= "ufs_axi_clk_src",
241 .parent_names
= gcc_xo_gpll0
,
243 .ops
= &clk_rcg2_ops
,
247 static const struct freq_tbl ftbl_gcc_usb30_master_clk
[] = {
248 F(125000000, P_GPLL0
, 1, 5, 24),
252 static struct clk_rcg2 usb30_master_clk_src
= {
256 .parent_map
= gcc_xo_gpll0_map
,
257 .freq_tbl
= ftbl_gcc_usb30_master_clk
,
258 .clkr
.hw
.init
= &(struct clk_init_data
){
259 .name
= "usb30_master_clk_src",
260 .parent_names
= gcc_xo_gpll0
,
262 .ops
= &clk_rcg2_ops
,
266 static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk
[] = {
267 F(125000000, P_GPLL0
, 1, 5, 24),
271 static struct clk_rcg2 usb30_sec_master_clk_src
= {
275 .parent_map
= gcc_xo_gpll0_map
,
276 .freq_tbl
= ftbl_gcc_usb30_sec_master_clk
,
277 .clkr
.hw
.init
= &(struct clk_init_data
){
278 .name
= "usb30_sec_master_clk_src",
279 .parent_names
= gcc_xo_gpll0
,
281 .ops
= &clk_rcg2_ops
,
285 static struct clk_branch gcc_usb30_sec_mock_utmi_clk
= {
288 .enable_reg
= 0x1bd0,
289 .enable_mask
= BIT(0),
290 .hw
.init
= &(struct clk_init_data
){
291 .name
= "gcc_usb30_sec_mock_utmi_clk",
292 .parent_names
= (const char *[]){
293 "usb30_sec_mock_utmi_clk_src",
296 .flags
= CLK_SET_RATE_PARENT
,
297 .ops
= &clk_branch2_ops
,
302 static struct clk_branch gcc_usb30_sec_sleep_clk
= {
305 .enable_reg
= 0x1bcc,
306 .enable_mask
= BIT(0),
307 .hw
.init
= &(struct clk_init_data
){
308 .name
= "gcc_usb30_sec_sleep_clk",
309 .parent_names
= (const char *[]){
313 .flags
= CLK_SET_RATE_PARENT
,
314 .ops
= &clk_branch2_ops
,
319 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
[] = {
320 F(19200000, P_XO
, 1, 0, 0),
321 F(50000000, P_GPLL0
, 12, 0, 0),
325 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src
= {
328 .parent_map
= gcc_xo_gpll0_map
,
329 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
330 .clkr
.hw
.init
= &(struct clk_init_data
){
331 .name
= "blsp1_qup1_i2c_apps_clk_src",
332 .parent_names
= gcc_xo_gpll0
,
334 .ops
= &clk_rcg2_ops
,
338 static const struct freq_tbl ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
[] = {
339 F(960000, P_XO
, 10, 1, 2),
340 F(4800000, P_XO
, 4, 0, 0),
341 F(9600000, P_XO
, 2, 0, 0),
342 F(15000000, P_GPLL0
, 10, 1, 4),
343 F(19200000, P_XO
, 1, 0, 0),
344 F(25000000, P_GPLL0
, 12, 1, 2),
345 F(50000000, P_GPLL0
, 12, 0, 0),
349 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src
= {
353 .parent_map
= gcc_xo_gpll0_map
,
354 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
355 .clkr
.hw
.init
= &(struct clk_init_data
){
356 .name
= "blsp1_qup1_spi_apps_clk_src",
357 .parent_names
= gcc_xo_gpll0
,
359 .ops
= &clk_rcg2_ops
,
363 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src
= {
366 .parent_map
= gcc_xo_gpll0_map
,
367 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
368 .clkr
.hw
.init
= &(struct clk_init_data
){
369 .name
= "blsp1_qup2_i2c_apps_clk_src",
370 .parent_names
= gcc_xo_gpll0
,
372 .ops
= &clk_rcg2_ops
,
376 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src
= {
380 .parent_map
= gcc_xo_gpll0_map
,
381 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
382 .clkr
.hw
.init
= &(struct clk_init_data
){
383 .name
= "blsp1_qup2_spi_apps_clk_src",
384 .parent_names
= gcc_xo_gpll0
,
386 .ops
= &clk_rcg2_ops
,
390 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src
= {
393 .parent_map
= gcc_xo_gpll0_map
,
394 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
395 .clkr
.hw
.init
= &(struct clk_init_data
){
396 .name
= "blsp1_qup3_i2c_apps_clk_src",
397 .parent_names
= gcc_xo_gpll0
,
399 .ops
= &clk_rcg2_ops
,
403 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src
= {
407 .parent_map
= gcc_xo_gpll0_map
,
408 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
409 .clkr
.hw
.init
= &(struct clk_init_data
){
410 .name
= "blsp1_qup3_spi_apps_clk_src",
411 .parent_names
= gcc_xo_gpll0
,
413 .ops
= &clk_rcg2_ops
,
417 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src
= {
420 .parent_map
= gcc_xo_gpll0_map
,
421 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
422 .clkr
.hw
.init
= &(struct clk_init_data
){
423 .name
= "blsp1_qup4_i2c_apps_clk_src",
424 .parent_names
= gcc_xo_gpll0
,
426 .ops
= &clk_rcg2_ops
,
430 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src
= {
434 .parent_map
= gcc_xo_gpll0_map
,
435 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
436 .clkr
.hw
.init
= &(struct clk_init_data
){
437 .name
= "blsp1_qup4_spi_apps_clk_src",
438 .parent_names
= gcc_xo_gpll0
,
440 .ops
= &clk_rcg2_ops
,
444 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src
= {
447 .parent_map
= gcc_xo_gpll0_map
,
448 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
449 .clkr
.hw
.init
= &(struct clk_init_data
){
450 .name
= "blsp1_qup5_i2c_apps_clk_src",
451 .parent_names
= gcc_xo_gpll0
,
453 .ops
= &clk_rcg2_ops
,
457 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src
= {
461 .parent_map
= gcc_xo_gpll0_map
,
462 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
463 .clkr
.hw
.init
= &(struct clk_init_data
){
464 .name
= "blsp1_qup5_spi_apps_clk_src",
465 .parent_names
= gcc_xo_gpll0
,
467 .ops
= &clk_rcg2_ops
,
471 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src
= {
474 .parent_map
= gcc_xo_gpll0_map
,
475 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
476 .clkr
.hw
.init
= &(struct clk_init_data
){
477 .name
= "blsp1_qup6_i2c_apps_clk_src",
478 .parent_names
= gcc_xo_gpll0
,
480 .ops
= &clk_rcg2_ops
,
484 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src
= {
488 .parent_map
= gcc_xo_gpll0_map
,
489 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
490 .clkr
.hw
.init
= &(struct clk_init_data
){
491 .name
= "blsp1_qup6_spi_apps_clk_src",
492 .parent_names
= gcc_xo_gpll0
,
494 .ops
= &clk_rcg2_ops
,
498 static const struct freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk
[] = {
499 F(3686400, P_GPLL0
, 1, 96, 15625),
500 F(7372800, P_GPLL0
, 1, 192, 15625),
501 F(14745600, P_GPLL0
, 1, 384, 15625),
502 F(16000000, P_GPLL0
, 5, 2, 15),
503 F(19200000, P_XO
, 1, 0, 0),
504 F(24000000, P_GPLL0
, 5, 1, 5),
505 F(32000000, P_GPLL0
, 1, 4, 75),
506 F(40000000, P_GPLL0
, 15, 0, 0),
507 F(46400000, P_GPLL0
, 1, 29, 375),
508 F(48000000, P_GPLL0
, 12.5, 0, 0),
509 F(51200000, P_GPLL0
, 1, 32, 375),
510 F(56000000, P_GPLL0
, 1, 7, 75),
511 F(58982400, P_GPLL0
, 1, 1536, 15625),
512 F(60000000, P_GPLL0
, 10, 0, 0),
513 F(63160000, P_GPLL0
, 9.5, 0, 0),
517 static struct clk_rcg2 blsp1_uart1_apps_clk_src
= {
521 .parent_map
= gcc_xo_gpll0_map
,
522 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
523 .clkr
.hw
.init
= &(struct clk_init_data
){
524 .name
= "blsp1_uart1_apps_clk_src",
525 .parent_names
= gcc_xo_gpll0
,
527 .ops
= &clk_rcg2_ops
,
531 static struct clk_rcg2 blsp1_uart2_apps_clk_src
= {
535 .parent_map
= gcc_xo_gpll0_map
,
536 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
537 .clkr
.hw
.init
= &(struct clk_init_data
){
538 .name
= "blsp1_uart2_apps_clk_src",
539 .parent_names
= gcc_xo_gpll0
,
541 .ops
= &clk_rcg2_ops
,
545 static struct clk_rcg2 blsp1_uart3_apps_clk_src
= {
549 .parent_map
= gcc_xo_gpll0_map
,
550 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
551 .clkr
.hw
.init
= &(struct clk_init_data
){
552 .name
= "blsp1_uart3_apps_clk_src",
553 .parent_names
= gcc_xo_gpll0
,
555 .ops
= &clk_rcg2_ops
,
559 static struct clk_rcg2 blsp1_uart4_apps_clk_src
= {
563 .parent_map
= gcc_xo_gpll0_map
,
564 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
565 .clkr
.hw
.init
= &(struct clk_init_data
){
566 .name
= "blsp1_uart4_apps_clk_src",
567 .parent_names
= gcc_xo_gpll0
,
569 .ops
= &clk_rcg2_ops
,
573 static struct clk_rcg2 blsp1_uart5_apps_clk_src
= {
577 .parent_map
= gcc_xo_gpll0_map
,
578 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
579 .clkr
.hw
.init
= &(struct clk_init_data
){
580 .name
= "blsp1_uart5_apps_clk_src",
581 .parent_names
= gcc_xo_gpll0
,
583 .ops
= &clk_rcg2_ops
,
587 static struct clk_rcg2 blsp1_uart6_apps_clk_src
= {
591 .parent_map
= gcc_xo_gpll0_map
,
592 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
593 .clkr
.hw
.init
= &(struct clk_init_data
){
594 .name
= "blsp1_uart6_apps_clk_src",
595 .parent_names
= gcc_xo_gpll0
,
597 .ops
= &clk_rcg2_ops
,
601 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src
= {
604 .parent_map
= gcc_xo_gpll0_map
,
605 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
606 .clkr
.hw
.init
= &(struct clk_init_data
){
607 .name
= "blsp2_qup1_i2c_apps_clk_src",
608 .parent_names
= gcc_xo_gpll0
,
610 .ops
= &clk_rcg2_ops
,
614 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src
= {
618 .parent_map
= gcc_xo_gpll0_map
,
619 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
620 .clkr
.hw
.init
= &(struct clk_init_data
){
621 .name
= "blsp2_qup1_spi_apps_clk_src",
622 .parent_names
= gcc_xo_gpll0
,
624 .ops
= &clk_rcg2_ops
,
628 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src
= {
631 .parent_map
= gcc_xo_gpll0_map
,
632 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
633 .clkr
.hw
.init
= &(struct clk_init_data
){
634 .name
= "blsp2_qup2_i2c_apps_clk_src",
635 .parent_names
= gcc_xo_gpll0
,
637 .ops
= &clk_rcg2_ops
,
641 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src
= {
645 .parent_map
= gcc_xo_gpll0_map
,
646 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
647 .clkr
.hw
.init
= &(struct clk_init_data
){
648 .name
= "blsp2_qup2_spi_apps_clk_src",
649 .parent_names
= gcc_xo_gpll0
,
651 .ops
= &clk_rcg2_ops
,
655 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src
= {
658 .parent_map
= gcc_xo_gpll0_map
,
659 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
660 .clkr
.hw
.init
= &(struct clk_init_data
){
661 .name
= "blsp2_qup3_i2c_apps_clk_src",
662 .parent_names
= gcc_xo_gpll0
,
664 .ops
= &clk_rcg2_ops
,
668 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src
= {
672 .parent_map
= gcc_xo_gpll0_map
,
673 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
674 .clkr
.hw
.init
= &(struct clk_init_data
){
675 .name
= "blsp2_qup3_spi_apps_clk_src",
676 .parent_names
= gcc_xo_gpll0
,
678 .ops
= &clk_rcg2_ops
,
682 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src
= {
685 .parent_map
= gcc_xo_gpll0_map
,
686 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
687 .clkr
.hw
.init
= &(struct clk_init_data
){
688 .name
= "blsp2_qup4_i2c_apps_clk_src",
689 .parent_names
= gcc_xo_gpll0
,
691 .ops
= &clk_rcg2_ops
,
695 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src
= {
699 .parent_map
= gcc_xo_gpll0_map
,
700 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
701 .clkr
.hw
.init
= &(struct clk_init_data
){
702 .name
= "blsp2_qup4_spi_apps_clk_src",
703 .parent_names
= gcc_xo_gpll0
,
705 .ops
= &clk_rcg2_ops
,
709 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src
= {
712 .parent_map
= gcc_xo_gpll0_map
,
713 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
714 .clkr
.hw
.init
= &(struct clk_init_data
){
715 .name
= "blsp2_qup5_i2c_apps_clk_src",
716 .parent_names
= gcc_xo_gpll0
,
718 .ops
= &clk_rcg2_ops
,
722 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src
= {
726 .parent_map
= gcc_xo_gpll0_map
,
727 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
728 .clkr
.hw
.init
= &(struct clk_init_data
){
729 .name
= "blsp2_qup5_spi_apps_clk_src",
730 .parent_names
= gcc_xo_gpll0
,
732 .ops
= &clk_rcg2_ops
,
736 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src
= {
739 .parent_map
= gcc_xo_gpll0_map
,
740 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_i2c_apps_clk
,
741 .clkr
.hw
.init
= &(struct clk_init_data
){
742 .name
= "blsp2_qup6_i2c_apps_clk_src",
743 .parent_names
= gcc_xo_gpll0
,
745 .ops
= &clk_rcg2_ops
,
749 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src
= {
753 .parent_map
= gcc_xo_gpll0_map
,
754 .freq_tbl
= ftbl_gcc_blsp1_2_qup1_6_spi_apps_clk
,
755 .clkr
.hw
.init
= &(struct clk_init_data
){
756 .name
= "blsp2_qup6_spi_apps_clk_src",
757 .parent_names
= gcc_xo_gpll0
,
759 .ops
= &clk_rcg2_ops
,
763 static struct clk_rcg2 blsp2_uart1_apps_clk_src
= {
767 .parent_map
= gcc_xo_gpll0_map
,
768 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
769 .clkr
.hw
.init
= &(struct clk_init_data
){
770 .name
= "blsp2_uart1_apps_clk_src",
771 .parent_names
= gcc_xo_gpll0
,
773 .ops
= &clk_rcg2_ops
,
777 static struct clk_rcg2 blsp2_uart2_apps_clk_src
= {
781 .parent_map
= gcc_xo_gpll0_map
,
782 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
783 .clkr
.hw
.init
= &(struct clk_init_data
){
784 .name
= "blsp2_uart2_apps_clk_src",
785 .parent_names
= gcc_xo_gpll0
,
787 .ops
= &clk_rcg2_ops
,
791 static struct clk_rcg2 blsp2_uart3_apps_clk_src
= {
795 .parent_map
= gcc_xo_gpll0_map
,
796 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
797 .clkr
.hw
.init
= &(struct clk_init_data
){
798 .name
= "blsp2_uart3_apps_clk_src",
799 .parent_names
= gcc_xo_gpll0
,
801 .ops
= &clk_rcg2_ops
,
805 static struct clk_rcg2 blsp2_uart4_apps_clk_src
= {
809 .parent_map
= gcc_xo_gpll0_map
,
810 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
811 .clkr
.hw
.init
= &(struct clk_init_data
){
812 .name
= "blsp2_uart4_apps_clk_src",
813 .parent_names
= gcc_xo_gpll0
,
815 .ops
= &clk_rcg2_ops
,
819 static struct clk_rcg2 blsp2_uart5_apps_clk_src
= {
823 .parent_map
= gcc_xo_gpll0_map
,
824 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
825 .clkr
.hw
.init
= &(struct clk_init_data
){
826 .name
= "blsp2_uart5_apps_clk_src",
827 .parent_names
= gcc_xo_gpll0
,
829 .ops
= &clk_rcg2_ops
,
833 static struct clk_rcg2 blsp2_uart6_apps_clk_src
= {
837 .parent_map
= gcc_xo_gpll0_map
,
838 .freq_tbl
= ftbl_gcc_blsp1_2_uart1_6_apps_clk
,
839 .clkr
.hw
.init
= &(struct clk_init_data
){
840 .name
= "blsp2_uart6_apps_clk_src",
841 .parent_names
= gcc_xo_gpll0
,
843 .ops
= &clk_rcg2_ops
,
847 static const struct freq_tbl ftbl_gcc_ce1_clk
[] = {
848 F(50000000, P_GPLL0
, 12, 0, 0),
849 F(85710000, P_GPLL0
, 7, 0, 0),
850 F(100000000, P_GPLL0
, 6, 0, 0),
851 F(171430000, P_GPLL0
, 3.5, 0, 0),
855 static struct clk_rcg2 ce1_clk_src
= {
858 .parent_map
= gcc_xo_gpll0_map
,
859 .freq_tbl
= ftbl_gcc_ce1_clk
,
860 .clkr
.hw
.init
= &(struct clk_init_data
){
861 .name
= "ce1_clk_src",
862 .parent_names
= gcc_xo_gpll0
,
864 .ops
= &clk_rcg2_ops
,
868 static const struct freq_tbl ftbl_gcc_ce2_clk
[] = {
869 F(50000000, P_GPLL0
, 12, 0, 0),
870 F(85710000, P_GPLL0
, 7, 0, 0),
871 F(100000000, P_GPLL0
, 6, 0, 0),
872 F(171430000, P_GPLL0
, 3.5, 0, 0),
876 static struct clk_rcg2 ce2_clk_src
= {
879 .parent_map
= gcc_xo_gpll0_map
,
880 .freq_tbl
= ftbl_gcc_ce2_clk
,
881 .clkr
.hw
.init
= &(struct clk_init_data
){
882 .name
= "ce2_clk_src",
883 .parent_names
= gcc_xo_gpll0
,
885 .ops
= &clk_rcg2_ops
,
889 static const struct freq_tbl ftbl_gcc_ce3_clk
[] = {
890 F(50000000, P_GPLL0
, 12, 0, 0),
891 F(85710000, P_GPLL0
, 7, 0, 0),
892 F(100000000, P_GPLL0
, 6, 0, 0),
893 F(171430000, P_GPLL0
, 3.5, 0, 0),
897 static struct clk_rcg2 ce3_clk_src
= {
900 .parent_map
= gcc_xo_gpll0_map
,
901 .freq_tbl
= ftbl_gcc_ce3_clk
,
902 .clkr
.hw
.init
= &(struct clk_init_data
){
903 .name
= "ce3_clk_src",
904 .parent_names
= gcc_xo_gpll0
,
906 .ops
= &clk_rcg2_ops
,
910 static const struct freq_tbl ftbl_gcc_gp_clk
[] = {
911 F(19200000, P_XO
, 1, 0, 0),
912 F(100000000, P_GPLL0
, 6, 0, 0),
913 F(200000000, P_GPLL0
, 3, 0, 0),
917 static struct clk_rcg2 gp1_clk_src
= {
921 .parent_map
= gcc_xo_gpll0_map
,
922 .freq_tbl
= ftbl_gcc_gp_clk
,
923 .clkr
.hw
.init
= &(struct clk_init_data
){
924 .name
= "gp1_clk_src",
925 .parent_names
= gcc_xo_gpll0
,
927 .ops
= &clk_rcg2_ops
,
931 static struct clk_rcg2 gp2_clk_src
= {
935 .parent_map
= gcc_xo_gpll0_map
,
936 .freq_tbl
= ftbl_gcc_gp_clk
,
937 .clkr
.hw
.init
= &(struct clk_init_data
){
938 .name
= "gp2_clk_src",
939 .parent_names
= gcc_xo_gpll0
,
941 .ops
= &clk_rcg2_ops
,
945 static struct clk_rcg2 gp3_clk_src
= {
949 .parent_map
= gcc_xo_gpll0_map
,
950 .freq_tbl
= ftbl_gcc_gp_clk
,
951 .clkr
.hw
.init
= &(struct clk_init_data
){
952 .name
= "gp3_clk_src",
953 .parent_names
= gcc_xo_gpll0
,
955 .ops
= &clk_rcg2_ops
,
959 static const struct freq_tbl ftbl_gcc_pcie_0_1_aux_clk
[] = {
960 F(1010000, P_XO
, 1, 1, 19),
964 static struct clk_rcg2 pcie_0_aux_clk_src
= {
968 .parent_map
= gcc_xo_pcie_sleep_map
,
969 .freq_tbl
= ftbl_gcc_pcie_0_1_aux_clk
,
970 .clkr
.hw
.init
= &(struct clk_init_data
){
971 .name
= "pcie_0_aux_clk_src",
972 .parent_names
= gcc_xo_pcie_sleep
,
974 .ops
= &clk_rcg2_ops
,
978 static struct clk_rcg2 pcie_1_aux_clk_src
= {
982 .parent_map
= gcc_xo_pcie_sleep_map
,
983 .freq_tbl
= ftbl_gcc_pcie_0_1_aux_clk
,
984 .clkr
.hw
.init
= &(struct clk_init_data
){
985 .name
= "pcie_1_aux_clk_src",
986 .parent_names
= gcc_xo_pcie_sleep
,
988 .ops
= &clk_rcg2_ops
,
992 static const struct freq_tbl ftbl_gcc_pcie_0_1_pipe_clk
[] = {
993 F(125000000, P_PCIE_0_1_PIPE_CLK
, 1, 0, 0),
994 F(250000000, P_PCIE_0_1_PIPE_CLK
, 1, 0, 0),
998 static struct clk_rcg2 pcie_0_pipe_clk_src
= {
1001 .parent_map
= gcc_xo_pcie_map
,
1002 .freq_tbl
= ftbl_gcc_pcie_0_1_pipe_clk
,
1003 .clkr
.hw
.init
= &(struct clk_init_data
){
1004 .name
= "pcie_0_pipe_clk_src",
1005 .parent_names
= gcc_xo_pcie
,
1007 .ops
= &clk_rcg2_ops
,
1011 static struct clk_rcg2 pcie_1_pipe_clk_src
= {
1014 .parent_map
= gcc_xo_pcie_map
,
1015 .freq_tbl
= ftbl_gcc_pcie_0_1_pipe_clk
,
1016 .clkr
.hw
.init
= &(struct clk_init_data
){
1017 .name
= "pcie_1_pipe_clk_src",
1018 .parent_names
= gcc_xo_pcie
,
1020 .ops
= &clk_rcg2_ops
,
1024 static const struct freq_tbl ftbl_gcc_pdm2_clk
[] = {
1025 F(60000000, P_GPLL0
, 10, 0, 0),
1029 static struct clk_rcg2 pdm2_clk_src
= {
1032 .parent_map
= gcc_xo_gpll0_map
,
1033 .freq_tbl
= ftbl_gcc_pdm2_clk
,
1034 .clkr
.hw
.init
= &(struct clk_init_data
){
1035 .name
= "pdm2_clk_src",
1036 .parent_names
= gcc_xo_gpll0
,
1038 .ops
= &clk_rcg2_ops
,
1042 static const struct freq_tbl ftbl_gcc_sata_asic0_clk
[] = {
1043 F(75000000, P_SATA_ASIC0_CLK
, 1, 0, 0),
1044 F(150000000, P_SATA_ASIC0_CLK
, 1, 0, 0),
1045 F(300000000, P_SATA_ASIC0_CLK
, 1, 0, 0),
1049 static struct clk_rcg2 sata_asic0_clk_src
= {
1052 .parent_map
= gcc_xo_sata_asic0_map
,
1053 .freq_tbl
= ftbl_gcc_sata_asic0_clk
,
1054 .clkr
.hw
.init
= &(struct clk_init_data
){
1055 .name
= "sata_asic0_clk_src",
1056 .parent_names
= gcc_xo_sata_asic0
,
1058 .ops
= &clk_rcg2_ops
,
1062 static const struct freq_tbl ftbl_gcc_sata_pmalive_clk
[] = {
1063 F(19200000, P_XO
, 1, 0, 0),
1064 F(50000000, P_GPLL0
, 12, 0, 0),
1065 F(100000000, P_GPLL0
, 6, 0, 0),
1069 static struct clk_rcg2 sata_pmalive_clk_src
= {
1072 .parent_map
= gcc_xo_gpll0_map
,
1073 .freq_tbl
= ftbl_gcc_sata_pmalive_clk
,
1074 .clkr
.hw
.init
= &(struct clk_init_data
){
1075 .name
= "sata_pmalive_clk_src",
1076 .parent_names
= gcc_xo_gpll0
,
1078 .ops
= &clk_rcg2_ops
,
1082 static const struct freq_tbl ftbl_gcc_sata_rx_clk
[] = {
1083 F(75000000, P_SATA_RX_CLK
, 1, 0, 0),
1084 F(150000000, P_SATA_RX_CLK
, 1, 0, 0),
1085 F(300000000, P_SATA_RX_CLK
, 1, 0, 0),
1089 static struct clk_rcg2 sata_rx_clk_src
= {
1092 .parent_map
= gcc_xo_sata_rx_map
,
1093 .freq_tbl
= ftbl_gcc_sata_rx_clk
,
1094 .clkr
.hw
.init
= &(struct clk_init_data
){
1095 .name
= "sata_rx_clk_src",
1096 .parent_names
= gcc_xo_sata_rx
,
1098 .ops
= &clk_rcg2_ops
,
1102 static const struct freq_tbl ftbl_gcc_sata_rx_oob_clk
[] = {
1103 F(100000000, P_GPLL0
, 6, 0, 0),
1107 static struct clk_rcg2 sata_rx_oob_clk_src
= {
1110 .parent_map
= gcc_xo_gpll0_map
,
1111 .freq_tbl
= ftbl_gcc_sata_rx_oob_clk
,
1112 .clkr
.hw
.init
= &(struct clk_init_data
){
1113 .name
= "sata_rx_oob_clk_src",
1114 .parent_names
= gcc_xo_gpll0
,
1116 .ops
= &clk_rcg2_ops
,
1120 static const struct freq_tbl ftbl_gcc_sdcc1_4_apps_clk
[] = {
1121 F(144000, P_XO
, 16, 3, 25),
1122 F(400000, P_XO
, 12, 1, 4),
1123 F(20000000, P_GPLL0
, 15, 1, 2),
1124 F(25000000, P_GPLL0
, 12, 1, 2),
1125 F(50000000, P_GPLL0
, 12, 0, 0),
1126 F(100000000, P_GPLL0
, 6, 0, 0),
1127 F(192000000, P_GPLL4
, 4, 0, 0),
1128 F(200000000, P_GPLL0
, 3, 0, 0),
1129 F(384000000, P_GPLL4
, 2, 0, 0),
1133 static struct clk_rcg2 sdcc1_apps_clk_src
= {
1137 .parent_map
= gcc_xo_gpll0_gpll4_map
,
1138 .freq_tbl
= ftbl_gcc_sdcc1_4_apps_clk
,
1139 .clkr
.hw
.init
= &(struct clk_init_data
){
1140 .name
= "sdcc1_apps_clk_src",
1141 .parent_names
= gcc_xo_gpll0_gpll4
,
1143 .ops
= &clk_rcg2_floor_ops
,
1147 static struct clk_rcg2 sdcc2_apps_clk_src
= {
1151 .parent_map
= gcc_xo_gpll0_map
,
1152 .freq_tbl
= ftbl_gcc_sdcc1_4_apps_clk
,
1153 .clkr
.hw
.init
= &(struct clk_init_data
){
1154 .name
= "sdcc2_apps_clk_src",
1155 .parent_names
= gcc_xo_gpll0
,
1157 .ops
= &clk_rcg2_floor_ops
,
1161 static struct clk_rcg2 sdcc3_apps_clk_src
= {
1165 .parent_map
= gcc_xo_gpll0_map
,
1166 .freq_tbl
= ftbl_gcc_sdcc1_4_apps_clk
,
1167 .clkr
.hw
.init
= &(struct clk_init_data
){
1168 .name
= "sdcc3_apps_clk_src",
1169 .parent_names
= gcc_xo_gpll0
,
1171 .ops
= &clk_rcg2_floor_ops
,
1175 static struct clk_rcg2 sdcc4_apps_clk_src
= {
1179 .parent_map
= gcc_xo_gpll0_map
,
1180 .freq_tbl
= ftbl_gcc_sdcc1_4_apps_clk
,
1181 .clkr
.hw
.init
= &(struct clk_init_data
){
1182 .name
= "sdcc4_apps_clk_src",
1183 .parent_names
= gcc_xo_gpll0
,
1185 .ops
= &clk_rcg2_floor_ops
,
1189 static const struct freq_tbl ftbl_gcc_tsif_ref_clk
[] = {
1190 F(105000, P_XO
, 2, 1, 91),
1194 static struct clk_rcg2 tsif_ref_clk_src
= {
1198 .parent_map
= gcc_xo_gpll0_map
,
1199 .freq_tbl
= ftbl_gcc_tsif_ref_clk
,
1200 .clkr
.hw
.init
= &(struct clk_init_data
){
1201 .name
= "tsif_ref_clk_src",
1202 .parent_names
= gcc_xo_gpll0
,
1204 .ops
= &clk_rcg2_ops
,
1208 static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk
[] = {
1209 F(60000000, P_GPLL0
, 10, 0, 0),
1213 static struct clk_rcg2 usb30_mock_utmi_clk_src
= {
1216 .parent_map
= gcc_xo_gpll0_map
,
1217 .freq_tbl
= ftbl_gcc_usb30_mock_utmi_clk
,
1218 .clkr
.hw
.init
= &(struct clk_init_data
){
1219 .name
= "usb30_mock_utmi_clk_src",
1220 .parent_names
= gcc_xo_gpll0
,
1222 .ops
= &clk_rcg2_ops
,
1226 static const struct freq_tbl ftbl_gcc_usb30_sec_mock_utmi_clk
[] = {
1227 F(125000000, P_GPLL0
, 1, 5, 24),
1231 static struct clk_rcg2 usb30_sec_mock_utmi_clk_src
= {
1234 .parent_map
= gcc_xo_gpll0_map
,
1235 .freq_tbl
= ftbl_gcc_usb30_sec_mock_utmi_clk
,
1236 .clkr
.hw
.init
= &(struct clk_init_data
){
1237 .name
= "usb30_sec_mock_utmi_clk_src",
1238 .parent_names
= gcc_xo_gpll0
,
1240 .ops
= &clk_rcg2_ops
,
1244 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk
[] = {
1245 F(75000000, P_GPLL0
, 8, 0, 0),
1249 static struct clk_rcg2 usb_hs_system_clk_src
= {
1252 .parent_map
= gcc_xo_gpll0_map
,
1253 .freq_tbl
= ftbl_gcc_usb_hs_system_clk
,
1254 .clkr
.hw
.init
= &(struct clk_init_data
){
1255 .name
= "usb_hs_system_clk_src",
1256 .parent_names
= gcc_xo_gpll0
,
1258 .ops
= &clk_rcg2_ops
,
1262 static const struct freq_tbl ftbl_gcc_usb_hsic_clk
[] = {
1263 F(480000000, P_GPLL1
, 1, 0, 0),
1267 static const struct parent_map usb_hsic_clk_src_map
[] = {
1272 static struct clk_rcg2 usb_hsic_clk_src
= {
1275 .parent_map
= usb_hsic_clk_src_map
,
1276 .freq_tbl
= ftbl_gcc_usb_hsic_clk
,
1277 .clkr
.hw
.init
= &(struct clk_init_data
){
1278 .name
= "usb_hsic_clk_src",
1279 .parent_names
= (const char *[]){
1284 .ops
= &clk_rcg2_ops
,
1288 static const struct freq_tbl ftbl_gcc_usb_hsic_ahb_clk_src
[] = {
1289 F(60000000, P_GPLL1
, 8, 0, 0),
1293 static struct clk_rcg2 usb_hsic_ahb_clk_src
= {
1297 .parent_map
= usb_hsic_clk_src_map
,
1298 .freq_tbl
= ftbl_gcc_usb_hsic_ahb_clk_src
,
1299 .clkr
.hw
.init
= &(struct clk_init_data
){
1300 .name
= "usb_hsic_ahb_clk_src",
1301 .parent_names
= (const char *[]){
1306 .ops
= &clk_rcg2_ops
,
1310 static const struct freq_tbl ftbl_gcc_usb_hsic_io_cal_clk
[] = {
1311 F(9600000, P_XO
, 2, 0, 0),
1315 static struct clk_rcg2 usb_hsic_io_cal_clk_src
= {
1318 .parent_map
= gcc_xo_gpll0_map
,
1319 .freq_tbl
= ftbl_gcc_usb_hsic_io_cal_clk
,
1320 .clkr
.hw
.init
= &(struct clk_init_data
){
1321 .name
= "usb_hsic_io_cal_clk_src",
1322 .parent_names
= gcc_xo_gpll0
,
1324 .ops
= &clk_rcg2_ops
,
1328 static struct clk_branch gcc_usb_hsic_mock_utmi_clk
= {
1331 .enable_reg
= 0x1f14,
1332 .enable_mask
= BIT(0),
1333 .hw
.init
= &(struct clk_init_data
){
1334 .name
= "gcc_usb_hsic_mock_utmi_clk",
1335 .parent_names
= (const char *[]){
1336 "usb_hsic_mock_utmi_clk_src",
1339 .flags
= CLK_SET_RATE_PARENT
,
1340 .ops
= &clk_branch2_ops
,
1345 static const struct freq_tbl ftbl_gcc_usb_hsic_mock_utmi_clk
[] = {
1346 F(60000000, P_GPLL0
, 10, 0, 0),
1350 static struct clk_rcg2 usb_hsic_mock_utmi_clk_src
= {
1353 .parent_map
= gcc_xo_gpll0_map
,
1354 .freq_tbl
= ftbl_gcc_usb_hsic_mock_utmi_clk
,
1355 .clkr
.hw
.init
= &(struct clk_init_data
){
1356 .name
= "usb_hsic_mock_utmi_clk_src",
1357 .parent_names
= gcc_xo_gpll0
,
1359 .ops
= &clk_rcg2_ops
,
1363 static const struct freq_tbl ftbl_gcc_usb_hsic_system_clk
[] = {
1364 F(75000000, P_GPLL0
, 8, 0, 0),
1368 static struct clk_rcg2 usb_hsic_system_clk_src
= {
1371 .parent_map
= gcc_xo_gpll0_map
,
1372 .freq_tbl
= ftbl_gcc_usb_hsic_system_clk
,
1373 .clkr
.hw
.init
= &(struct clk_init_data
){
1374 .name
= "usb_hsic_system_clk_src",
1375 .parent_names
= gcc_xo_gpll0
,
1377 .ops
= &clk_rcg2_ops
,
1381 static struct clk_branch gcc_bam_dma_ahb_clk
= {
1383 .halt_check
= BRANCH_HALT_VOTED
,
1385 .enable_reg
= 0x1484,
1386 .enable_mask
= BIT(12),
1387 .hw
.init
= &(struct clk_init_data
){
1388 .name
= "gcc_bam_dma_ahb_clk",
1389 .parent_names
= (const char *[]){
1390 "periph_noc_clk_src",
1393 .ops
= &clk_branch2_ops
,
1398 static struct clk_branch gcc_blsp1_ahb_clk
= {
1400 .halt_check
= BRANCH_HALT_VOTED
,
1402 .enable_reg
= 0x1484,
1403 .enable_mask
= BIT(17),
1404 .hw
.init
= &(struct clk_init_data
){
1405 .name
= "gcc_blsp1_ahb_clk",
1406 .parent_names
= (const char *[]){
1407 "periph_noc_clk_src",
1410 .ops
= &clk_branch2_ops
,
1415 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk
= {
1418 .enable_reg
= 0x0648,
1419 .enable_mask
= BIT(0),
1420 .hw
.init
= &(struct clk_init_data
){
1421 .name
= "gcc_blsp1_qup1_i2c_apps_clk",
1422 .parent_names
= (const char *[]){
1423 "blsp1_qup1_i2c_apps_clk_src",
1426 .flags
= CLK_SET_RATE_PARENT
,
1427 .ops
= &clk_branch2_ops
,
1432 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk
= {
1435 .enable_reg
= 0x0644,
1436 .enable_mask
= BIT(0),
1437 .hw
.init
= &(struct clk_init_data
){
1438 .name
= "gcc_blsp1_qup1_spi_apps_clk",
1439 .parent_names
= (const char *[]){
1440 "blsp1_qup1_spi_apps_clk_src",
1443 .flags
= CLK_SET_RATE_PARENT
,
1444 .ops
= &clk_branch2_ops
,
1449 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk
= {
1452 .enable_reg
= 0x06c8,
1453 .enable_mask
= BIT(0),
1454 .hw
.init
= &(struct clk_init_data
){
1455 .name
= "gcc_blsp1_qup2_i2c_apps_clk",
1456 .parent_names
= (const char *[]){
1457 "blsp1_qup2_i2c_apps_clk_src",
1460 .flags
= CLK_SET_RATE_PARENT
,
1461 .ops
= &clk_branch2_ops
,
1466 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk
= {
1469 .enable_reg
= 0x06c4,
1470 .enable_mask
= BIT(0),
1471 .hw
.init
= &(struct clk_init_data
){
1472 .name
= "gcc_blsp1_qup2_spi_apps_clk",
1473 .parent_names
= (const char *[]){
1474 "blsp1_qup2_spi_apps_clk_src",
1477 .flags
= CLK_SET_RATE_PARENT
,
1478 .ops
= &clk_branch2_ops
,
1483 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk
= {
1486 .enable_reg
= 0x0748,
1487 .enable_mask
= BIT(0),
1488 .hw
.init
= &(struct clk_init_data
){
1489 .name
= "gcc_blsp1_qup3_i2c_apps_clk",
1490 .parent_names
= (const char *[]){
1491 "blsp1_qup3_i2c_apps_clk_src",
1494 .flags
= CLK_SET_RATE_PARENT
,
1495 .ops
= &clk_branch2_ops
,
1500 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk
= {
1503 .enable_reg
= 0x0744,
1504 .enable_mask
= BIT(0),
1505 .hw
.init
= &(struct clk_init_data
){
1506 .name
= "gcc_blsp1_qup3_spi_apps_clk",
1507 .parent_names
= (const char *[]){
1508 "blsp1_qup3_spi_apps_clk_src",
1511 .flags
= CLK_SET_RATE_PARENT
,
1512 .ops
= &clk_branch2_ops
,
1517 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk
= {
1520 .enable_reg
= 0x07c8,
1521 .enable_mask
= BIT(0),
1522 .hw
.init
= &(struct clk_init_data
){
1523 .name
= "gcc_blsp1_qup4_i2c_apps_clk",
1524 .parent_names
= (const char *[]){
1525 "blsp1_qup4_i2c_apps_clk_src",
1528 .flags
= CLK_SET_RATE_PARENT
,
1529 .ops
= &clk_branch2_ops
,
1534 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk
= {
1537 .enable_reg
= 0x07c4,
1538 .enable_mask
= BIT(0),
1539 .hw
.init
= &(struct clk_init_data
){
1540 .name
= "gcc_blsp1_qup4_spi_apps_clk",
1541 .parent_names
= (const char *[]){
1542 "blsp1_qup4_spi_apps_clk_src",
1545 .flags
= CLK_SET_RATE_PARENT
,
1546 .ops
= &clk_branch2_ops
,
1551 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk
= {
1554 .enable_reg
= 0x0848,
1555 .enable_mask
= BIT(0),
1556 .hw
.init
= &(struct clk_init_data
){
1557 .name
= "gcc_blsp1_qup5_i2c_apps_clk",
1558 .parent_names
= (const char *[]){
1559 "blsp1_qup5_i2c_apps_clk_src",
1562 .flags
= CLK_SET_RATE_PARENT
,
1563 .ops
= &clk_branch2_ops
,
1568 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk
= {
1571 .enable_reg
= 0x0844,
1572 .enable_mask
= BIT(0),
1573 .hw
.init
= &(struct clk_init_data
){
1574 .name
= "gcc_blsp1_qup5_spi_apps_clk",
1575 .parent_names
= (const char *[]){
1576 "blsp1_qup5_spi_apps_clk_src",
1579 .flags
= CLK_SET_RATE_PARENT
,
1580 .ops
= &clk_branch2_ops
,
1585 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk
= {
1588 .enable_reg
= 0x08c8,
1589 .enable_mask
= BIT(0),
1590 .hw
.init
= &(struct clk_init_data
){
1591 .name
= "gcc_blsp1_qup6_i2c_apps_clk",
1592 .parent_names
= (const char *[]){
1593 "blsp1_qup6_i2c_apps_clk_src",
1596 .flags
= CLK_SET_RATE_PARENT
,
1597 .ops
= &clk_branch2_ops
,
1602 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk
= {
1605 .enable_reg
= 0x08c4,
1606 .enable_mask
= BIT(0),
1607 .hw
.init
= &(struct clk_init_data
){
1608 .name
= "gcc_blsp1_qup6_spi_apps_clk",
1609 .parent_names
= (const char *[]){
1610 "blsp1_qup6_spi_apps_clk_src",
1613 .flags
= CLK_SET_RATE_PARENT
,
1614 .ops
= &clk_branch2_ops
,
1619 static struct clk_branch gcc_blsp1_uart1_apps_clk
= {
1622 .enable_reg
= 0x0684,
1623 .enable_mask
= BIT(0),
1624 .hw
.init
= &(struct clk_init_data
){
1625 .name
= "gcc_blsp1_uart1_apps_clk",
1626 .parent_names
= (const char *[]){
1627 "blsp1_uart1_apps_clk_src",
1630 .flags
= CLK_SET_RATE_PARENT
,
1631 .ops
= &clk_branch2_ops
,
1636 static struct clk_branch gcc_blsp1_uart2_apps_clk
= {
1639 .enable_reg
= 0x0704,
1640 .enable_mask
= BIT(0),
1641 .hw
.init
= &(struct clk_init_data
){
1642 .name
= "gcc_blsp1_uart2_apps_clk",
1643 .parent_names
= (const char *[]){
1644 "blsp1_uart2_apps_clk_src",
1647 .flags
= CLK_SET_RATE_PARENT
,
1648 .ops
= &clk_branch2_ops
,
1653 static struct clk_branch gcc_blsp1_uart3_apps_clk
= {
1656 .enable_reg
= 0x0784,
1657 .enable_mask
= BIT(0),
1658 .hw
.init
= &(struct clk_init_data
){
1659 .name
= "gcc_blsp1_uart3_apps_clk",
1660 .parent_names
= (const char *[]){
1661 "blsp1_uart3_apps_clk_src",
1664 .flags
= CLK_SET_RATE_PARENT
,
1665 .ops
= &clk_branch2_ops
,
1670 static struct clk_branch gcc_blsp1_uart4_apps_clk
= {
1673 .enable_reg
= 0x0804,
1674 .enable_mask
= BIT(0),
1675 .hw
.init
= &(struct clk_init_data
){
1676 .name
= "gcc_blsp1_uart4_apps_clk",
1677 .parent_names
= (const char *[]){
1678 "blsp1_uart4_apps_clk_src",
1681 .flags
= CLK_SET_RATE_PARENT
,
1682 .ops
= &clk_branch2_ops
,
1687 static struct clk_branch gcc_blsp1_uart5_apps_clk
= {
1690 .enable_reg
= 0x0884,
1691 .enable_mask
= BIT(0),
1692 .hw
.init
= &(struct clk_init_data
){
1693 .name
= "gcc_blsp1_uart5_apps_clk",
1694 .parent_names
= (const char *[]){
1695 "blsp1_uart5_apps_clk_src",
1698 .flags
= CLK_SET_RATE_PARENT
,
1699 .ops
= &clk_branch2_ops
,
1704 static struct clk_branch gcc_blsp1_uart6_apps_clk
= {
1707 .enable_reg
= 0x0904,
1708 .enable_mask
= BIT(0),
1709 .hw
.init
= &(struct clk_init_data
){
1710 .name
= "gcc_blsp1_uart6_apps_clk",
1711 .parent_names
= (const char *[]){
1712 "blsp1_uart6_apps_clk_src",
1715 .flags
= CLK_SET_RATE_PARENT
,
1716 .ops
= &clk_branch2_ops
,
1721 static struct clk_branch gcc_blsp2_ahb_clk
= {
1723 .halt_check
= BRANCH_HALT_VOTED
,
1725 .enable_reg
= 0x1484,
1726 .enable_mask
= BIT(15),
1727 .hw
.init
= &(struct clk_init_data
){
1728 .name
= "gcc_blsp2_ahb_clk",
1729 .parent_names
= (const char *[]){
1730 "periph_noc_clk_src",
1733 .ops
= &clk_branch2_ops
,
1738 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk
= {
1741 .enable_reg
= 0x0988,
1742 .enable_mask
= BIT(0),
1743 .hw
.init
= &(struct clk_init_data
){
1744 .name
= "gcc_blsp2_qup1_i2c_apps_clk",
1745 .parent_names
= (const char *[]){
1746 "blsp2_qup1_i2c_apps_clk_src",
1749 .flags
= CLK_SET_RATE_PARENT
,
1750 .ops
= &clk_branch2_ops
,
1755 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk
= {
1758 .enable_reg
= 0x0984,
1759 .enable_mask
= BIT(0),
1760 .hw
.init
= &(struct clk_init_data
){
1761 .name
= "gcc_blsp2_qup1_spi_apps_clk",
1762 .parent_names
= (const char *[]){
1763 "blsp2_qup1_spi_apps_clk_src",
1766 .flags
= CLK_SET_RATE_PARENT
,
1767 .ops
= &clk_branch2_ops
,
1772 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk
= {
1775 .enable_reg
= 0x0a08,
1776 .enable_mask
= BIT(0),
1777 .hw
.init
= &(struct clk_init_data
){
1778 .name
= "gcc_blsp2_qup2_i2c_apps_clk",
1779 .parent_names
= (const char *[]){
1780 "blsp2_qup2_i2c_apps_clk_src",
1783 .flags
= CLK_SET_RATE_PARENT
,
1784 .ops
= &clk_branch2_ops
,
1789 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk
= {
1792 .enable_reg
= 0x0a04,
1793 .enable_mask
= BIT(0),
1794 .hw
.init
= &(struct clk_init_data
){
1795 .name
= "gcc_blsp2_qup2_spi_apps_clk",
1796 .parent_names
= (const char *[]){
1797 "blsp2_qup2_spi_apps_clk_src",
1800 .flags
= CLK_SET_RATE_PARENT
,
1801 .ops
= &clk_branch2_ops
,
1806 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk
= {
1809 .enable_reg
= 0x0a88,
1810 .enable_mask
= BIT(0),
1811 .hw
.init
= &(struct clk_init_data
){
1812 .name
= "gcc_blsp2_qup3_i2c_apps_clk",
1813 .parent_names
= (const char *[]){
1814 "blsp2_qup3_i2c_apps_clk_src",
1817 .flags
= CLK_SET_RATE_PARENT
,
1818 .ops
= &clk_branch2_ops
,
1823 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk
= {
1826 .enable_reg
= 0x0a84,
1827 .enable_mask
= BIT(0),
1828 .hw
.init
= &(struct clk_init_data
){
1829 .name
= "gcc_blsp2_qup3_spi_apps_clk",
1830 .parent_names
= (const char *[]){
1831 "blsp2_qup3_spi_apps_clk_src",
1834 .flags
= CLK_SET_RATE_PARENT
,
1835 .ops
= &clk_branch2_ops
,
1840 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk
= {
1843 .enable_reg
= 0x0b08,
1844 .enable_mask
= BIT(0),
1845 .hw
.init
= &(struct clk_init_data
){
1846 .name
= "gcc_blsp2_qup4_i2c_apps_clk",
1847 .parent_names
= (const char *[]){
1848 "blsp2_qup4_i2c_apps_clk_src",
1851 .flags
= CLK_SET_RATE_PARENT
,
1852 .ops
= &clk_branch2_ops
,
1857 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk
= {
1860 .enable_reg
= 0x0b04,
1861 .enable_mask
= BIT(0),
1862 .hw
.init
= &(struct clk_init_data
){
1863 .name
= "gcc_blsp2_qup4_spi_apps_clk",
1864 .parent_names
= (const char *[]){
1865 "blsp2_qup4_spi_apps_clk_src",
1868 .flags
= CLK_SET_RATE_PARENT
,
1869 .ops
= &clk_branch2_ops
,
1874 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk
= {
1877 .enable_reg
= 0x0b88,
1878 .enable_mask
= BIT(0),
1879 .hw
.init
= &(struct clk_init_data
){
1880 .name
= "gcc_blsp2_qup5_i2c_apps_clk",
1881 .parent_names
= (const char *[]){
1882 "blsp2_qup5_i2c_apps_clk_src",
1885 .flags
= CLK_SET_RATE_PARENT
,
1886 .ops
= &clk_branch2_ops
,
1891 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk
= {
1894 .enable_reg
= 0x0b84,
1895 .enable_mask
= BIT(0),
1896 .hw
.init
= &(struct clk_init_data
){
1897 .name
= "gcc_blsp2_qup5_spi_apps_clk",
1898 .parent_names
= (const char *[]){
1899 "blsp2_qup5_spi_apps_clk_src",
1902 .flags
= CLK_SET_RATE_PARENT
,
1903 .ops
= &clk_branch2_ops
,
1908 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk
= {
1911 .enable_reg
= 0x0c08,
1912 .enable_mask
= BIT(0),
1913 .hw
.init
= &(struct clk_init_data
){
1914 .name
= "gcc_blsp2_qup6_i2c_apps_clk",
1915 .parent_names
= (const char *[]){
1916 "blsp2_qup6_i2c_apps_clk_src",
1919 .flags
= CLK_SET_RATE_PARENT
,
1920 .ops
= &clk_branch2_ops
,
1925 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk
= {
1928 .enable_reg
= 0x0c04,
1929 .enable_mask
= BIT(0),
1930 .hw
.init
= &(struct clk_init_data
){
1931 .name
= "gcc_blsp2_qup6_spi_apps_clk",
1932 .parent_names
= (const char *[]){
1933 "blsp2_qup6_spi_apps_clk_src",
1936 .flags
= CLK_SET_RATE_PARENT
,
1937 .ops
= &clk_branch2_ops
,
1942 static struct clk_branch gcc_blsp2_uart1_apps_clk
= {
1945 .enable_reg
= 0x09c4,
1946 .enable_mask
= BIT(0),
1947 .hw
.init
= &(struct clk_init_data
){
1948 .name
= "gcc_blsp2_uart1_apps_clk",
1949 .parent_names
= (const char *[]){
1950 "blsp2_uart1_apps_clk_src",
1953 .flags
= CLK_SET_RATE_PARENT
,
1954 .ops
= &clk_branch2_ops
,
1959 static struct clk_branch gcc_blsp2_uart2_apps_clk
= {
1962 .enable_reg
= 0x0a44,
1963 .enable_mask
= BIT(0),
1964 .hw
.init
= &(struct clk_init_data
){
1965 .name
= "gcc_blsp2_uart2_apps_clk",
1966 .parent_names
= (const char *[]){
1967 "blsp2_uart2_apps_clk_src",
1970 .flags
= CLK_SET_RATE_PARENT
,
1971 .ops
= &clk_branch2_ops
,
1976 static struct clk_branch gcc_blsp2_uart3_apps_clk
= {
1979 .enable_reg
= 0x0ac4,
1980 .enable_mask
= BIT(0),
1981 .hw
.init
= &(struct clk_init_data
){
1982 .name
= "gcc_blsp2_uart3_apps_clk",
1983 .parent_names
= (const char *[]){
1984 "blsp2_uart3_apps_clk_src",
1987 .flags
= CLK_SET_RATE_PARENT
,
1988 .ops
= &clk_branch2_ops
,
1993 static struct clk_branch gcc_blsp2_uart4_apps_clk
= {
1996 .enable_reg
= 0x0b44,
1997 .enable_mask
= BIT(0),
1998 .hw
.init
= &(struct clk_init_data
){
1999 .name
= "gcc_blsp2_uart4_apps_clk",
2000 .parent_names
= (const char *[]){
2001 "blsp2_uart4_apps_clk_src",
2004 .flags
= CLK_SET_RATE_PARENT
,
2005 .ops
= &clk_branch2_ops
,
2010 static struct clk_branch gcc_blsp2_uart5_apps_clk
= {
2013 .enable_reg
= 0x0bc4,
2014 .enable_mask
= BIT(0),
2015 .hw
.init
= &(struct clk_init_data
){
2016 .name
= "gcc_blsp2_uart5_apps_clk",
2017 .parent_names
= (const char *[]){
2018 "blsp2_uart5_apps_clk_src",
2021 .flags
= CLK_SET_RATE_PARENT
,
2022 .ops
= &clk_branch2_ops
,
2027 static struct clk_branch gcc_blsp2_uart6_apps_clk
= {
2030 .enable_reg
= 0x0c44,
2031 .enable_mask
= BIT(0),
2032 .hw
.init
= &(struct clk_init_data
){
2033 .name
= "gcc_blsp2_uart6_apps_clk",
2034 .parent_names
= (const char *[]){
2035 "blsp2_uart6_apps_clk_src",
2038 .flags
= CLK_SET_RATE_PARENT
,
2039 .ops
= &clk_branch2_ops
,
2044 static struct clk_branch gcc_boot_rom_ahb_clk
= {
2046 .halt_check
= BRANCH_HALT_VOTED
,
2048 .enable_reg
= 0x1484,
2049 .enable_mask
= BIT(10),
2050 .hw
.init
= &(struct clk_init_data
){
2051 .name
= "gcc_boot_rom_ahb_clk",
2052 .parent_names
= (const char *[]){
2053 "config_noc_clk_src",
2056 .ops
= &clk_branch2_ops
,
2061 static struct clk_branch gcc_ce1_ahb_clk
= {
2063 .halt_check
= BRANCH_HALT_VOTED
,
2065 .enable_reg
= 0x1484,
2066 .enable_mask
= BIT(3),
2067 .hw
.init
= &(struct clk_init_data
){
2068 .name
= "gcc_ce1_ahb_clk",
2069 .parent_names
= (const char *[]){
2070 "config_noc_clk_src",
2073 .ops
= &clk_branch2_ops
,
2078 static struct clk_branch gcc_ce1_axi_clk
= {
2080 .halt_check
= BRANCH_HALT_VOTED
,
2082 .enable_reg
= 0x1484,
2083 .enable_mask
= BIT(4),
2084 .hw
.init
= &(struct clk_init_data
){
2085 .name
= "gcc_ce1_axi_clk",
2086 .parent_names
= (const char *[]){
2087 "system_noc_clk_src",
2090 .ops
= &clk_branch2_ops
,
2095 static struct clk_branch gcc_ce1_clk
= {
2097 .halt_check
= BRANCH_HALT_VOTED
,
2099 .enable_reg
= 0x1484,
2100 .enable_mask
= BIT(5),
2101 .hw
.init
= &(struct clk_init_data
){
2102 .name
= "gcc_ce1_clk",
2103 .parent_names
= (const char *[]){
2107 .flags
= CLK_SET_RATE_PARENT
,
2108 .ops
= &clk_branch2_ops
,
2113 static struct clk_branch gcc_ce2_ahb_clk
= {
2115 .halt_check
= BRANCH_HALT_VOTED
,
2117 .enable_reg
= 0x1484,
2118 .enable_mask
= BIT(0),
2119 .hw
.init
= &(struct clk_init_data
){
2120 .name
= "gcc_ce2_ahb_clk",
2121 .parent_names
= (const char *[]){
2122 "config_noc_clk_src",
2125 .ops
= &clk_branch2_ops
,
2130 static struct clk_branch gcc_ce2_axi_clk
= {
2132 .halt_check
= BRANCH_HALT_VOTED
,
2134 .enable_reg
= 0x1484,
2135 .enable_mask
= BIT(1),
2136 .hw
.init
= &(struct clk_init_data
){
2137 .name
= "gcc_ce2_axi_clk",
2138 .parent_names
= (const char *[]){
2139 "system_noc_clk_src",
2142 .ops
= &clk_branch2_ops
,
2147 static struct clk_branch gcc_ce2_clk
= {
2149 .halt_check
= BRANCH_HALT_VOTED
,
2151 .enable_reg
= 0x1484,
2152 .enable_mask
= BIT(2),
2153 .hw
.init
= &(struct clk_init_data
){
2154 .name
= "gcc_ce2_clk",
2155 .parent_names
= (const char *[]){
2159 .flags
= CLK_SET_RATE_PARENT
,
2160 .ops
= &clk_branch2_ops
,
2165 static struct clk_branch gcc_ce3_ahb_clk
= {
2167 .halt_check
= BRANCH_HALT_VOTED
,
2169 .enable_reg
= 0x1d0c,
2170 .enable_mask
= BIT(0),
2171 .hw
.init
= &(struct clk_init_data
){
2172 .name
= "gcc_ce3_ahb_clk",
2173 .parent_names
= (const char *[]){
2174 "config_noc_clk_src",
2177 .ops
= &clk_branch2_ops
,
2182 static struct clk_branch gcc_ce3_axi_clk
= {
2184 .halt_check
= BRANCH_HALT_VOTED
,
2186 .enable_reg
= 0x1d08,
2187 .enable_mask
= BIT(0),
2188 .hw
.init
= &(struct clk_init_data
){
2189 .name
= "gcc_ce3_axi_clk",
2190 .parent_names
= (const char *[]){
2191 "system_noc_clk_src",
2194 .ops
= &clk_branch2_ops
,
2199 static struct clk_branch gcc_ce3_clk
= {
2201 .halt_check
= BRANCH_HALT_VOTED
,
2203 .enable_reg
= 0x1d04,
2204 .enable_mask
= BIT(0),
2205 .hw
.init
= &(struct clk_init_data
){
2206 .name
= "gcc_ce3_clk",
2207 .parent_names
= (const char *[]){
2211 .flags
= CLK_SET_RATE_PARENT
,
2212 .ops
= &clk_branch2_ops
,
2217 static struct clk_branch gcc_gp1_clk
= {
2220 .enable_reg
= 0x1900,
2221 .enable_mask
= BIT(0),
2222 .hw
.init
= &(struct clk_init_data
){
2223 .name
= "gcc_gp1_clk",
2224 .parent_names
= (const char *[]){
2228 .flags
= CLK_SET_RATE_PARENT
,
2229 .ops
= &clk_branch2_ops
,
2234 static struct clk_branch gcc_gp2_clk
= {
2237 .enable_reg
= 0x1940,
2238 .enable_mask
= BIT(0),
2239 .hw
.init
= &(struct clk_init_data
){
2240 .name
= "gcc_gp2_clk",
2241 .parent_names
= (const char *[]){
2245 .flags
= CLK_SET_RATE_PARENT
,
2246 .ops
= &clk_branch2_ops
,
2251 static struct clk_branch gcc_gp3_clk
= {
2254 .enable_reg
= 0x1980,
2255 .enable_mask
= BIT(0),
2256 .hw
.init
= &(struct clk_init_data
){
2257 .name
= "gcc_gp3_clk",
2258 .parent_names
= (const char *[]){
2262 .flags
= CLK_SET_RATE_PARENT
,
2263 .ops
= &clk_branch2_ops
,
2268 static struct clk_branch gcc_ocmem_noc_cfg_ahb_clk
= {
2271 .enable_reg
= 0x0248,
2272 .enable_mask
= BIT(0),
2273 .hw
.init
= &(struct clk_init_data
){
2274 .name
= "gcc_ocmem_noc_cfg_ahb_clk",
2275 .parent_names
= (const char *[]){
2276 "config_noc_clk_src",
2279 .ops
= &clk_branch2_ops
,
2284 static struct clk_branch gcc_pcie_0_aux_clk
= {
2287 .enable_reg
= 0x1b10,
2288 .enable_mask
= BIT(0),
2289 .hw
.init
= &(struct clk_init_data
){
2290 .name
= "gcc_pcie_0_aux_clk",
2291 .parent_names
= (const char *[]){
2292 "pcie_0_aux_clk_src",
2295 .flags
= CLK_SET_RATE_PARENT
,
2296 .ops
= &clk_branch2_ops
,
2301 static struct clk_branch gcc_pcie_0_cfg_ahb_clk
= {
2304 .enable_reg
= 0x1b0c,
2305 .enable_mask
= BIT(0),
2306 .hw
.init
= &(struct clk_init_data
){
2307 .name
= "gcc_pcie_0_cfg_ahb_clk",
2308 .parent_names
= (const char *[]){
2309 "config_noc_clk_src",
2312 .flags
= CLK_SET_RATE_PARENT
,
2313 .ops
= &clk_branch2_ops
,
2318 static struct clk_branch gcc_pcie_0_mstr_axi_clk
= {
2321 .enable_reg
= 0x1b08,
2322 .enable_mask
= BIT(0),
2323 .hw
.init
= &(struct clk_init_data
){
2324 .name
= "gcc_pcie_0_mstr_axi_clk",
2325 .parent_names
= (const char *[]){
2326 "config_noc_clk_src",
2329 .flags
= CLK_SET_RATE_PARENT
,
2330 .ops
= &clk_branch2_ops
,
2335 static struct clk_branch gcc_pcie_0_pipe_clk
= {
2338 .enable_reg
= 0x1b14,
2339 .enable_mask
= BIT(0),
2340 .hw
.init
= &(struct clk_init_data
){
2341 .name
= "gcc_pcie_0_pipe_clk",
2342 .parent_names
= (const char *[]){
2343 "pcie_0_pipe_clk_src",
2346 .flags
= CLK_SET_RATE_PARENT
,
2347 .ops
= &clk_branch2_ops
,
2352 static struct clk_branch gcc_pcie_0_slv_axi_clk
= {
2355 .enable_reg
= 0x1b04,
2356 .enable_mask
= BIT(0),
2357 .hw
.init
= &(struct clk_init_data
){
2358 .name
= "gcc_pcie_0_slv_axi_clk",
2359 .parent_names
= (const char *[]){
2360 "config_noc_clk_src",
2363 .flags
= CLK_SET_RATE_PARENT
,
2364 .ops
= &clk_branch2_ops
,
2369 static struct clk_branch gcc_pcie_1_aux_clk
= {
2372 .enable_reg
= 0x1b90,
2373 .enable_mask
= BIT(0),
2374 .hw
.init
= &(struct clk_init_data
){
2375 .name
= "gcc_pcie_1_aux_clk",
2376 .parent_names
= (const char *[]){
2377 "pcie_1_aux_clk_src",
2380 .flags
= CLK_SET_RATE_PARENT
,
2381 .ops
= &clk_branch2_ops
,
2386 static struct clk_branch gcc_pcie_1_cfg_ahb_clk
= {
2389 .enable_reg
= 0x1b8c,
2390 .enable_mask
= BIT(0),
2391 .hw
.init
= &(struct clk_init_data
){
2392 .name
= "gcc_pcie_1_cfg_ahb_clk",
2393 .parent_names
= (const char *[]){
2394 "config_noc_clk_src",
2397 .flags
= CLK_SET_RATE_PARENT
,
2398 .ops
= &clk_branch2_ops
,
2403 static struct clk_branch gcc_pcie_1_mstr_axi_clk
= {
2406 .enable_reg
= 0x1b88,
2407 .enable_mask
= BIT(0),
2408 .hw
.init
= &(struct clk_init_data
){
2409 .name
= "gcc_pcie_1_mstr_axi_clk",
2410 .parent_names
= (const char *[]){
2411 "config_noc_clk_src",
2414 .flags
= CLK_SET_RATE_PARENT
,
2415 .ops
= &clk_branch2_ops
,
2420 static struct clk_branch gcc_pcie_1_pipe_clk
= {
2423 .enable_reg
= 0x1b94,
2424 .enable_mask
= BIT(0),
2425 .hw
.init
= &(struct clk_init_data
){
2426 .name
= "gcc_pcie_1_pipe_clk",
2427 .parent_names
= (const char *[]){
2428 "pcie_1_pipe_clk_src",
2431 .flags
= CLK_SET_RATE_PARENT
,
2432 .ops
= &clk_branch2_ops
,
2437 static struct clk_branch gcc_pcie_1_slv_axi_clk
= {
2440 .enable_reg
= 0x1b84,
2441 .enable_mask
= BIT(0),
2442 .hw
.init
= &(struct clk_init_data
){
2443 .name
= "gcc_pcie_1_slv_axi_clk",
2444 .parent_names
= (const char *[]){
2445 "config_noc_clk_src",
2448 .flags
= CLK_SET_RATE_PARENT
,
2449 .ops
= &clk_branch2_ops
,
2454 static struct clk_branch gcc_pdm2_clk
= {
2457 .enable_reg
= 0x0ccc,
2458 .enable_mask
= BIT(0),
2459 .hw
.init
= &(struct clk_init_data
){
2460 .name
= "gcc_pdm2_clk",
2461 .parent_names
= (const char *[]){
2465 .flags
= CLK_SET_RATE_PARENT
,
2466 .ops
= &clk_branch2_ops
,
2471 static struct clk_branch gcc_pdm_ahb_clk
= {
2474 .enable_reg
= 0x0cc4,
2475 .enable_mask
= BIT(0),
2476 .hw
.init
= &(struct clk_init_data
){
2477 .name
= "gcc_pdm_ahb_clk",
2478 .parent_names
= (const char *[]){
2479 "periph_noc_clk_src",
2482 .ops
= &clk_branch2_ops
,
2487 static struct clk_branch gcc_periph_noc_usb_hsic_ahb_clk
= {
2490 .enable_reg
= 0x01a4,
2491 .enable_mask
= BIT(0),
2492 .hw
.init
= &(struct clk_init_data
){
2493 .name
= "gcc_periph_noc_usb_hsic_ahb_clk",
2494 .parent_names
= (const char *[]){
2495 "usb_hsic_ahb_clk_src",
2498 .flags
= CLK_SET_RATE_PARENT
,
2499 .ops
= &clk_branch2_ops
,
2504 static struct clk_branch gcc_prng_ahb_clk
= {
2506 .halt_check
= BRANCH_HALT_VOTED
,
2508 .enable_reg
= 0x1484,
2509 .enable_mask
= BIT(13),
2510 .hw
.init
= &(struct clk_init_data
){
2511 .name
= "gcc_prng_ahb_clk",
2512 .parent_names
= (const char *[]){
2513 "periph_noc_clk_src",
2516 .ops
= &clk_branch2_ops
,
2521 static struct clk_branch gcc_sata_asic0_clk
= {
2524 .enable_reg
= 0x1c54,
2525 .enable_mask
= BIT(0),
2526 .hw
.init
= &(struct clk_init_data
){
2527 .name
= "gcc_sata_asic0_clk",
2528 .parent_names
= (const char *[]){
2529 "sata_asic0_clk_src",
2532 .flags
= CLK_SET_RATE_PARENT
,
2533 .ops
= &clk_branch2_ops
,
2538 static struct clk_branch gcc_sata_axi_clk
= {
2541 .enable_reg
= 0x1c44,
2542 .enable_mask
= BIT(0),
2543 .hw
.init
= &(struct clk_init_data
){
2544 .name
= "gcc_sata_axi_clk",
2545 .parent_names
= (const char *[]){
2546 "config_noc_clk_src",
2549 .flags
= CLK_SET_RATE_PARENT
,
2550 .ops
= &clk_branch2_ops
,
2555 static struct clk_branch gcc_sata_cfg_ahb_clk
= {
2558 .enable_reg
= 0x1c48,
2559 .enable_mask
= BIT(0),
2560 .hw
.init
= &(struct clk_init_data
){
2561 .name
= "gcc_sata_cfg_ahb_clk",
2562 .parent_names
= (const char *[]){
2563 "config_noc_clk_src",
2566 .flags
= CLK_SET_RATE_PARENT
,
2567 .ops
= &clk_branch2_ops
,
2572 static struct clk_branch gcc_sata_pmalive_clk
= {
2575 .enable_reg
= 0x1c50,
2576 .enable_mask
= BIT(0),
2577 .hw
.init
= &(struct clk_init_data
){
2578 .name
= "gcc_sata_pmalive_clk",
2579 .parent_names
= (const char *[]){
2580 "sata_pmalive_clk_src",
2583 .flags
= CLK_SET_RATE_PARENT
,
2584 .ops
= &clk_branch2_ops
,
2589 static struct clk_branch gcc_sata_rx_clk
= {
2592 .enable_reg
= 0x1c58,
2593 .enable_mask
= BIT(0),
2594 .hw
.init
= &(struct clk_init_data
){
2595 .name
= "gcc_sata_rx_clk",
2596 .parent_names
= (const char *[]){
2600 .flags
= CLK_SET_RATE_PARENT
,
2601 .ops
= &clk_branch2_ops
,
2606 static struct clk_branch gcc_sata_rx_oob_clk
= {
2609 .enable_reg
= 0x1c4c,
2610 .enable_mask
= BIT(0),
2611 .hw
.init
= &(struct clk_init_data
){
2612 .name
= "gcc_sata_rx_oob_clk",
2613 .parent_names
= (const char *[]){
2614 "sata_rx_oob_clk_src",
2617 .flags
= CLK_SET_RATE_PARENT
,
2618 .ops
= &clk_branch2_ops
,
2623 static struct clk_branch gcc_sdcc1_ahb_clk
= {
2626 .enable_reg
= 0x04c8,
2627 .enable_mask
= BIT(0),
2628 .hw
.init
= &(struct clk_init_data
){
2629 .name
= "gcc_sdcc1_ahb_clk",
2630 .parent_names
= (const char *[]){
2631 "periph_noc_clk_src",
2634 .ops
= &clk_branch2_ops
,
2639 static struct clk_branch gcc_sdcc1_apps_clk
= {
2642 .enable_reg
= 0x04c4,
2643 .enable_mask
= BIT(0),
2644 .hw
.init
= &(struct clk_init_data
){
2645 .name
= "gcc_sdcc1_apps_clk",
2646 .parent_names
= (const char *[]){
2647 "sdcc1_apps_clk_src",
2650 .flags
= CLK_SET_RATE_PARENT
,
2651 .ops
= &clk_branch2_ops
,
2656 static struct clk_branch gcc_sdcc1_cdccal_ff_clk
= {
2659 .enable_reg
= 0x04e8,
2660 .enable_mask
= BIT(0),
2661 .hw
.init
= &(struct clk_init_data
){
2662 .name
= "gcc_sdcc1_cdccal_ff_clk",
2663 .parent_names
= (const char *[]){
2667 .ops
= &clk_branch2_ops
,
2672 static struct clk_branch gcc_sdcc1_cdccal_sleep_clk
= {
2675 .enable_reg
= 0x04e4,
2676 .enable_mask
= BIT(0),
2677 .hw
.init
= &(struct clk_init_data
){
2678 .name
= "gcc_sdcc1_cdccal_sleep_clk",
2679 .parent_names
= (const char *[]){
2683 .ops
= &clk_branch2_ops
,
2688 static struct clk_branch gcc_sdcc2_ahb_clk
= {
2691 .enable_reg
= 0x0508,
2692 .enable_mask
= BIT(0),
2693 .hw
.init
= &(struct clk_init_data
){
2694 .name
= "gcc_sdcc2_ahb_clk",
2695 .parent_names
= (const char *[]){
2696 "periph_noc_clk_src",
2699 .ops
= &clk_branch2_ops
,
2704 static struct clk_branch gcc_sdcc2_apps_clk
= {
2707 .enable_reg
= 0x0504,
2708 .enable_mask
= BIT(0),
2709 .hw
.init
= &(struct clk_init_data
){
2710 .name
= "gcc_sdcc2_apps_clk",
2711 .parent_names
= (const char *[]){
2712 "sdcc2_apps_clk_src",
2715 .flags
= CLK_SET_RATE_PARENT
,
2716 .ops
= &clk_branch2_ops
,
2721 static struct clk_branch gcc_sdcc3_ahb_clk
= {
2724 .enable_reg
= 0x0548,
2725 .enable_mask
= BIT(0),
2726 .hw
.init
= &(struct clk_init_data
){
2727 .name
= "gcc_sdcc3_ahb_clk",
2728 .parent_names
= (const char *[]){
2729 "periph_noc_clk_src",
2732 .ops
= &clk_branch2_ops
,
2737 static struct clk_branch gcc_sdcc3_apps_clk
= {
2740 .enable_reg
= 0x0544,
2741 .enable_mask
= BIT(0),
2742 .hw
.init
= &(struct clk_init_data
){
2743 .name
= "gcc_sdcc3_apps_clk",
2744 .parent_names
= (const char *[]){
2745 "sdcc3_apps_clk_src",
2748 .flags
= CLK_SET_RATE_PARENT
,
2749 .ops
= &clk_branch2_ops
,
2754 static struct clk_branch gcc_sdcc4_ahb_clk
= {
2757 .enable_reg
= 0x0588,
2758 .enable_mask
= BIT(0),
2759 .hw
.init
= &(struct clk_init_data
){
2760 .name
= "gcc_sdcc4_ahb_clk",
2761 .parent_names
= (const char *[]){
2762 "periph_noc_clk_src",
2765 .ops
= &clk_branch2_ops
,
2770 static struct clk_branch gcc_sdcc4_apps_clk
= {
2773 .enable_reg
= 0x0584,
2774 .enable_mask
= BIT(0),
2775 .hw
.init
= &(struct clk_init_data
){
2776 .name
= "gcc_sdcc4_apps_clk",
2777 .parent_names
= (const char *[]){
2778 "sdcc4_apps_clk_src",
2781 .flags
= CLK_SET_RATE_PARENT
,
2782 .ops
= &clk_branch2_ops
,
2787 static struct clk_branch gcc_sys_noc_ufs_axi_clk
= {
2790 .enable_reg
= 0x013c,
2791 .enable_mask
= BIT(0),
2792 .hw
.init
= &(struct clk_init_data
){
2793 .name
= "gcc_sys_noc_ufs_axi_clk",
2794 .parent_names
= (const char *[]){
2798 .flags
= CLK_SET_RATE_PARENT
,
2799 .ops
= &clk_branch2_ops
,
2804 static struct clk_branch gcc_sys_noc_usb3_axi_clk
= {
2807 .enable_reg
= 0x0108,
2808 .enable_mask
= BIT(0),
2809 .hw
.init
= &(struct clk_init_data
){
2810 .name
= "gcc_sys_noc_usb3_axi_clk",
2811 .parent_names
= (const char *[]){
2812 "usb30_master_clk_src",
2815 .flags
= CLK_SET_RATE_PARENT
,
2816 .ops
= &clk_branch2_ops
,
2821 static struct clk_branch gcc_sys_noc_usb3_sec_axi_clk
= {
2824 .enable_reg
= 0x0138,
2825 .enable_mask
= BIT(0),
2826 .hw
.init
= &(struct clk_init_data
){
2827 .name
= "gcc_sys_noc_usb3_sec_axi_clk",
2828 .parent_names
= (const char *[]){
2829 "usb30_sec_master_clk_src",
2832 .flags
= CLK_SET_RATE_PARENT
,
2833 .ops
= &clk_branch2_ops
,
2838 static struct clk_branch gcc_tsif_ahb_clk
= {
2841 .enable_reg
= 0x0d84,
2842 .enable_mask
= BIT(0),
2843 .hw
.init
= &(struct clk_init_data
){
2844 .name
= "gcc_tsif_ahb_clk",
2845 .parent_names
= (const char *[]){
2846 "periph_noc_clk_src",
2849 .ops
= &clk_branch2_ops
,
2854 static struct clk_branch gcc_tsif_inactivity_timers_clk
= {
2857 .enable_reg
= 0x0d8c,
2858 .enable_mask
= BIT(0),
2859 .hw
.init
= &(struct clk_init_data
){
2860 .name
= "gcc_tsif_inactivity_timers_clk",
2861 .parent_names
= (const char *[]){
2865 .flags
= CLK_SET_RATE_PARENT
,
2866 .ops
= &clk_branch2_ops
,
2871 static struct clk_branch gcc_tsif_ref_clk
= {
2874 .enable_reg
= 0x0d88,
2875 .enable_mask
= BIT(0),
2876 .hw
.init
= &(struct clk_init_data
){
2877 .name
= "gcc_tsif_ref_clk",
2878 .parent_names
= (const char *[]){
2882 .flags
= CLK_SET_RATE_PARENT
,
2883 .ops
= &clk_branch2_ops
,
2888 static struct clk_branch gcc_ufs_ahb_clk
= {
2891 .enable_reg
= 0x1d48,
2892 .enable_mask
= BIT(0),
2893 .hw
.init
= &(struct clk_init_data
){
2894 .name
= "gcc_ufs_ahb_clk",
2895 .parent_names
= (const char *[]){
2896 "config_noc_clk_src",
2899 .flags
= CLK_SET_RATE_PARENT
,
2900 .ops
= &clk_branch2_ops
,
2905 static struct clk_branch gcc_ufs_axi_clk
= {
2908 .enable_reg
= 0x1d44,
2909 .enable_mask
= BIT(0),
2910 .hw
.init
= &(struct clk_init_data
){
2911 .name
= "gcc_ufs_axi_clk",
2912 .parent_names
= (const char *[]){
2916 .flags
= CLK_SET_RATE_PARENT
,
2917 .ops
= &clk_branch2_ops
,
2922 static struct clk_branch gcc_ufs_rx_cfg_clk
= {
2925 .enable_reg
= 0x1d50,
2926 .enable_mask
= BIT(0),
2927 .hw
.init
= &(struct clk_init_data
){
2928 .name
= "gcc_ufs_rx_cfg_clk",
2929 .parent_names
= (const char *[]){
2933 .flags
= CLK_SET_RATE_PARENT
,
2934 .ops
= &clk_branch2_ops
,
2939 static struct clk_branch gcc_ufs_rx_symbol_0_clk
= {
2942 .enable_reg
= 0x1d5c,
2943 .enable_mask
= BIT(0),
2944 .hw
.init
= &(struct clk_init_data
){
2945 .name
= "gcc_ufs_rx_symbol_0_clk",
2946 .parent_names
= (const char *[]){
2947 "ufs_rx_symbol_0_clk_src",
2950 .flags
= CLK_SET_RATE_PARENT
,
2951 .ops
= &clk_branch2_ops
,
2956 static struct clk_branch gcc_ufs_rx_symbol_1_clk
= {
2959 .enable_reg
= 0x1d60,
2960 .enable_mask
= BIT(0),
2961 .hw
.init
= &(struct clk_init_data
){
2962 .name
= "gcc_ufs_rx_symbol_1_clk",
2963 .parent_names
= (const char *[]){
2964 "ufs_rx_symbol_1_clk_src",
2967 .flags
= CLK_SET_RATE_PARENT
,
2968 .ops
= &clk_branch2_ops
,
2973 static struct clk_branch gcc_ufs_tx_cfg_clk
= {
2976 .enable_reg
= 0x1d4c,
2977 .enable_mask
= BIT(0),
2978 .hw
.init
= &(struct clk_init_data
){
2979 .name
= "gcc_ufs_tx_cfg_clk",
2980 .parent_names
= (const char *[]){
2984 .flags
= CLK_SET_RATE_PARENT
,
2985 .ops
= &clk_branch2_ops
,
2990 static struct clk_branch gcc_ufs_tx_symbol_0_clk
= {
2993 .enable_reg
= 0x1d54,
2994 .enable_mask
= BIT(0),
2995 .hw
.init
= &(struct clk_init_data
){
2996 .name
= "gcc_ufs_tx_symbol_0_clk",
2997 .parent_names
= (const char *[]){
2998 "ufs_tx_symbol_0_clk_src",
3001 .flags
= CLK_SET_RATE_PARENT
,
3002 .ops
= &clk_branch2_ops
,
3007 static struct clk_branch gcc_ufs_tx_symbol_1_clk
= {
3010 .enable_reg
= 0x1d58,
3011 .enable_mask
= BIT(0),
3012 .hw
.init
= &(struct clk_init_data
){
3013 .name
= "gcc_ufs_tx_symbol_1_clk",
3014 .parent_names
= (const char *[]){
3015 "ufs_tx_symbol_1_clk_src",
3018 .flags
= CLK_SET_RATE_PARENT
,
3019 .ops
= &clk_branch2_ops
,
3024 static struct clk_branch gcc_usb2a_phy_sleep_clk
= {
3027 .enable_reg
= 0x04ac,
3028 .enable_mask
= BIT(0),
3029 .hw
.init
= &(struct clk_init_data
){
3030 .name
= "gcc_usb2a_phy_sleep_clk",
3031 .parent_names
= (const char *[]){
3035 .ops
= &clk_branch2_ops
,
3040 static struct clk_branch gcc_usb2b_phy_sleep_clk
= {
3043 .enable_reg
= 0x04b4,
3044 .enable_mask
= BIT(0),
3045 .hw
.init
= &(struct clk_init_data
){
3046 .name
= "gcc_usb2b_phy_sleep_clk",
3047 .parent_names
= (const char *[]){
3051 .ops
= &clk_branch2_ops
,
3056 static struct clk_branch gcc_usb30_master_clk
= {
3059 .enable_reg
= 0x03c8,
3060 .enable_mask
= BIT(0),
3061 .hw
.init
= &(struct clk_init_data
){
3062 .name
= "gcc_usb30_master_clk",
3063 .parent_names
= (const char *[]){
3064 "usb30_master_clk_src",
3067 .flags
= CLK_SET_RATE_PARENT
,
3068 .ops
= &clk_branch2_ops
,
3073 static struct clk_branch gcc_usb30_sec_master_clk
= {
3076 .enable_reg
= 0x1bc8,
3077 .enable_mask
= BIT(0),
3078 .hw
.init
= &(struct clk_init_data
){
3079 .name
= "gcc_usb30_sec_master_clk",
3080 .parent_names
= (const char *[]){
3081 "usb30_sec_master_clk_src",
3084 .flags
= CLK_SET_RATE_PARENT
,
3085 .ops
= &clk_branch2_ops
,
3090 static struct clk_branch gcc_usb30_mock_utmi_clk
= {
3093 .enable_reg
= 0x03d0,
3094 .enable_mask
= BIT(0),
3095 .hw
.init
= &(struct clk_init_data
){
3096 .name
= "gcc_usb30_mock_utmi_clk",
3097 .parent_names
= (const char *[]){
3098 "usb30_mock_utmi_clk_src",
3101 .flags
= CLK_SET_RATE_PARENT
,
3102 .ops
= &clk_branch2_ops
,
3107 static struct clk_branch gcc_usb30_sleep_clk
= {
3110 .enable_reg
= 0x03cc,
3111 .enable_mask
= BIT(0),
3112 .hw
.init
= &(struct clk_init_data
){
3113 .name
= "gcc_usb30_sleep_clk",
3114 .parent_names
= (const char *[]){
3118 .ops
= &clk_branch2_ops
,
3123 static struct clk_branch gcc_usb_hs_ahb_clk
= {
3126 .enable_reg
= 0x0488,
3127 .enable_mask
= BIT(0),
3128 .hw
.init
= &(struct clk_init_data
){
3129 .name
= "gcc_usb_hs_ahb_clk",
3130 .parent_names
= (const char *[]){
3131 "periph_noc_clk_src",
3134 .ops
= &clk_branch2_ops
,
3139 static struct clk_branch gcc_usb_hs_inactivity_timers_clk
= {
3142 .enable_reg
= 0x048c,
3143 .enable_mask
= BIT(0),
3144 .hw
.init
= &(struct clk_init_data
){
3145 .name
= "gcc_usb_hs_inactivity_timers_clk",
3146 .parent_names
= (const char *[]){
3150 .flags
= CLK_SET_RATE_PARENT
,
3151 .ops
= &clk_branch2_ops
,
3156 static struct clk_branch gcc_usb_hs_system_clk
= {
3159 .enable_reg
= 0x0484,
3160 .enable_mask
= BIT(0),
3161 .hw
.init
= &(struct clk_init_data
){
3162 .name
= "gcc_usb_hs_system_clk",
3163 .parent_names
= (const char *[]){
3164 "usb_hs_system_clk_src",
3167 .flags
= CLK_SET_RATE_PARENT
,
3168 .ops
= &clk_branch2_ops
,
3173 static struct clk_branch gcc_usb_hsic_ahb_clk
= {
3176 .enable_reg
= 0x0408,
3177 .enable_mask
= BIT(0),
3178 .hw
.init
= &(struct clk_init_data
){
3179 .name
= "gcc_usb_hsic_ahb_clk",
3180 .parent_names
= (const char *[]){
3181 "periph_noc_clk_src",
3184 .ops
= &clk_branch2_ops
,
3189 static struct clk_branch gcc_usb_hsic_clk
= {
3192 .enable_reg
= 0x0410,
3193 .enable_mask
= BIT(0),
3194 .hw
.init
= &(struct clk_init_data
){
3195 .name
= "gcc_usb_hsic_clk",
3196 .parent_names
= (const char *[]){
3200 .flags
= CLK_SET_RATE_PARENT
,
3201 .ops
= &clk_branch2_ops
,
3206 static struct clk_branch gcc_usb_hsic_io_cal_clk
= {
3209 .enable_reg
= 0x0414,
3210 .enable_mask
= BIT(0),
3211 .hw
.init
= &(struct clk_init_data
){
3212 .name
= "gcc_usb_hsic_io_cal_clk",
3213 .parent_names
= (const char *[]){
3214 "usb_hsic_io_cal_clk_src",
3217 .flags
= CLK_SET_RATE_PARENT
,
3218 .ops
= &clk_branch2_ops
,
3223 static struct clk_branch gcc_usb_hsic_io_cal_sleep_clk
= {
3226 .enable_reg
= 0x0418,
3227 .enable_mask
= BIT(0),
3228 .hw
.init
= &(struct clk_init_data
){
3229 .name
= "gcc_usb_hsic_io_cal_sleep_clk",
3230 .parent_names
= (const char *[]){
3234 .ops
= &clk_branch2_ops
,
3239 static struct clk_branch gcc_usb_hsic_system_clk
= {
3242 .enable_reg
= 0x040c,
3243 .enable_mask
= BIT(0),
3244 .hw
.init
= &(struct clk_init_data
){
3245 .name
= "gcc_usb_hsic_system_clk",
3246 .parent_names
= (const char *[]){
3247 "usb_hsic_system_clk_src",
3250 .flags
= CLK_SET_RATE_PARENT
,
3251 .ops
= &clk_branch2_ops
,
3256 static struct gdsc usb_hs_hsic_gdsc
= {
3259 .name
= "usb_hs_hsic",
3261 .pwrsts
= PWRSTS_OFF_ON
,
3264 static struct gdsc pcie0_gdsc
= {
3269 .pwrsts
= PWRSTS_OFF_ON
,
3272 static struct gdsc pcie1_gdsc
= {
3277 .pwrsts
= PWRSTS_OFF_ON
,
3280 static struct gdsc usb30_gdsc
= {
3285 .pwrsts
= PWRSTS_OFF_ON
,
3288 static struct clk_regmap
*gcc_apq8084_clocks
[] = {
3289 [GPLL0
] = &gpll0
.clkr
,
3290 [GPLL0_VOTE
] = &gpll0_vote
,
3291 [GPLL1
] = &gpll1
.clkr
,
3292 [GPLL1_VOTE
] = &gpll1_vote
,
3293 [GPLL4
] = &gpll4
.clkr
,
3294 [GPLL4_VOTE
] = &gpll4_vote
,
3295 [CONFIG_NOC_CLK_SRC
] = &config_noc_clk_src
.clkr
,
3296 [PERIPH_NOC_CLK_SRC
] = &periph_noc_clk_src
.clkr
,
3297 [SYSTEM_NOC_CLK_SRC
] = &system_noc_clk_src
.clkr
,
3298 [UFS_AXI_CLK_SRC
] = &ufs_axi_clk_src
.clkr
,
3299 [USB30_MASTER_CLK_SRC
] = &usb30_master_clk_src
.clkr
,
3300 [USB30_SEC_MASTER_CLK_SRC
] = &usb30_sec_master_clk_src
.clkr
,
3301 [USB_HSIC_AHB_CLK_SRC
] = &usb_hsic_ahb_clk_src
.clkr
,
3302 [BLSP1_QUP1_I2C_APPS_CLK_SRC
] = &blsp1_qup1_i2c_apps_clk_src
.clkr
,
3303 [BLSP1_QUP1_SPI_APPS_CLK_SRC
] = &blsp1_qup1_spi_apps_clk_src
.clkr
,
3304 [BLSP1_QUP2_I2C_APPS_CLK_SRC
] = &blsp1_qup2_i2c_apps_clk_src
.clkr
,
3305 [BLSP1_QUP2_SPI_APPS_CLK_SRC
] = &blsp1_qup2_spi_apps_clk_src
.clkr
,
3306 [BLSP1_QUP3_I2C_APPS_CLK_SRC
] = &blsp1_qup3_i2c_apps_clk_src
.clkr
,
3307 [BLSP1_QUP3_SPI_APPS_CLK_SRC
] = &blsp1_qup3_spi_apps_clk_src
.clkr
,
3308 [BLSP1_QUP4_I2C_APPS_CLK_SRC
] = &blsp1_qup4_i2c_apps_clk_src
.clkr
,
3309 [BLSP1_QUP4_SPI_APPS_CLK_SRC
] = &blsp1_qup4_spi_apps_clk_src
.clkr
,
3310 [BLSP1_QUP5_I2C_APPS_CLK_SRC
] = &blsp1_qup5_i2c_apps_clk_src
.clkr
,
3311 [BLSP1_QUP5_SPI_APPS_CLK_SRC
] = &blsp1_qup5_spi_apps_clk_src
.clkr
,
3312 [BLSP1_QUP6_I2C_APPS_CLK_SRC
] = &blsp1_qup6_i2c_apps_clk_src
.clkr
,
3313 [BLSP1_QUP6_SPI_APPS_CLK_SRC
] = &blsp1_qup6_spi_apps_clk_src
.clkr
,
3314 [BLSP1_UART1_APPS_CLK_SRC
] = &blsp1_uart1_apps_clk_src
.clkr
,
3315 [BLSP1_UART2_APPS_CLK_SRC
] = &blsp1_uart2_apps_clk_src
.clkr
,
3316 [BLSP1_UART3_APPS_CLK_SRC
] = &blsp1_uart3_apps_clk_src
.clkr
,
3317 [BLSP1_UART4_APPS_CLK_SRC
] = &blsp1_uart4_apps_clk_src
.clkr
,
3318 [BLSP1_UART5_APPS_CLK_SRC
] = &blsp1_uart5_apps_clk_src
.clkr
,
3319 [BLSP1_UART6_APPS_CLK_SRC
] = &blsp1_uart6_apps_clk_src
.clkr
,
3320 [BLSP2_QUP1_I2C_APPS_CLK_SRC
] = &blsp2_qup1_i2c_apps_clk_src
.clkr
,
3321 [BLSP2_QUP1_SPI_APPS_CLK_SRC
] = &blsp2_qup1_spi_apps_clk_src
.clkr
,
3322 [BLSP2_QUP2_I2C_APPS_CLK_SRC
] = &blsp2_qup2_i2c_apps_clk_src
.clkr
,
3323 [BLSP2_QUP2_SPI_APPS_CLK_SRC
] = &blsp2_qup2_spi_apps_clk_src
.clkr
,
3324 [BLSP2_QUP3_I2C_APPS_CLK_SRC
] = &blsp2_qup3_i2c_apps_clk_src
.clkr
,
3325 [BLSP2_QUP3_SPI_APPS_CLK_SRC
] = &blsp2_qup3_spi_apps_clk_src
.clkr
,
3326 [BLSP2_QUP4_I2C_APPS_CLK_SRC
] = &blsp2_qup4_i2c_apps_clk_src
.clkr
,
3327 [BLSP2_QUP4_SPI_APPS_CLK_SRC
] = &blsp2_qup4_spi_apps_clk_src
.clkr
,
3328 [BLSP2_QUP5_I2C_APPS_CLK_SRC
] = &blsp2_qup5_i2c_apps_clk_src
.clkr
,
3329 [BLSP2_QUP5_SPI_APPS_CLK_SRC
] = &blsp2_qup5_spi_apps_clk_src
.clkr
,
3330 [BLSP2_QUP6_I2C_APPS_CLK_SRC
] = &blsp2_qup6_i2c_apps_clk_src
.clkr
,
3331 [BLSP2_QUP6_SPI_APPS_CLK_SRC
] = &blsp2_qup6_spi_apps_clk_src
.clkr
,
3332 [BLSP2_UART1_APPS_CLK_SRC
] = &blsp2_uart1_apps_clk_src
.clkr
,
3333 [BLSP2_UART2_APPS_CLK_SRC
] = &blsp2_uart2_apps_clk_src
.clkr
,
3334 [BLSP2_UART3_APPS_CLK_SRC
] = &blsp2_uart3_apps_clk_src
.clkr
,
3335 [BLSP2_UART4_APPS_CLK_SRC
] = &blsp2_uart4_apps_clk_src
.clkr
,
3336 [BLSP2_UART5_APPS_CLK_SRC
] = &blsp2_uart5_apps_clk_src
.clkr
,
3337 [BLSP2_UART6_APPS_CLK_SRC
] = &blsp2_uart6_apps_clk_src
.clkr
,
3338 [CE1_CLK_SRC
] = &ce1_clk_src
.clkr
,
3339 [CE2_CLK_SRC
] = &ce2_clk_src
.clkr
,
3340 [CE3_CLK_SRC
] = &ce3_clk_src
.clkr
,
3341 [GP1_CLK_SRC
] = &gp1_clk_src
.clkr
,
3342 [GP2_CLK_SRC
] = &gp2_clk_src
.clkr
,
3343 [GP3_CLK_SRC
] = &gp3_clk_src
.clkr
,
3344 [PCIE_0_AUX_CLK_SRC
] = &pcie_0_aux_clk_src
.clkr
,
3345 [PCIE_0_PIPE_CLK_SRC
] = &pcie_0_pipe_clk_src
.clkr
,
3346 [PCIE_1_AUX_CLK_SRC
] = &pcie_1_aux_clk_src
.clkr
,
3347 [PCIE_1_PIPE_CLK_SRC
] = &pcie_1_pipe_clk_src
.clkr
,
3348 [PDM2_CLK_SRC
] = &pdm2_clk_src
.clkr
,
3349 [SATA_ASIC0_CLK_SRC
] = &sata_asic0_clk_src
.clkr
,
3350 [SATA_PMALIVE_CLK_SRC
] = &sata_pmalive_clk_src
.clkr
,
3351 [SATA_RX_CLK_SRC
] = &sata_rx_clk_src
.clkr
,
3352 [SATA_RX_OOB_CLK_SRC
] = &sata_rx_oob_clk_src
.clkr
,
3353 [SDCC1_APPS_CLK_SRC
] = &sdcc1_apps_clk_src
.clkr
,
3354 [SDCC2_APPS_CLK_SRC
] = &sdcc2_apps_clk_src
.clkr
,
3355 [SDCC3_APPS_CLK_SRC
] = &sdcc3_apps_clk_src
.clkr
,
3356 [SDCC4_APPS_CLK_SRC
] = &sdcc4_apps_clk_src
.clkr
,
3357 [TSIF_REF_CLK_SRC
] = &tsif_ref_clk_src
.clkr
,
3358 [USB30_MOCK_UTMI_CLK_SRC
] = &usb30_mock_utmi_clk_src
.clkr
,
3359 [USB30_SEC_MOCK_UTMI_CLK_SRC
] = &usb30_sec_mock_utmi_clk_src
.clkr
,
3360 [USB_HS_SYSTEM_CLK_SRC
] = &usb_hs_system_clk_src
.clkr
,
3361 [USB_HSIC_CLK_SRC
] = &usb_hsic_clk_src
.clkr
,
3362 [USB_HSIC_IO_CAL_CLK_SRC
] = &usb_hsic_io_cal_clk_src
.clkr
,
3363 [USB_HSIC_MOCK_UTMI_CLK_SRC
] = &usb_hsic_mock_utmi_clk_src
.clkr
,
3364 [USB_HSIC_SYSTEM_CLK_SRC
] = &usb_hsic_system_clk_src
.clkr
,
3365 [GCC_BAM_DMA_AHB_CLK
] = &gcc_bam_dma_ahb_clk
.clkr
,
3366 [GCC_BLSP1_AHB_CLK
] = &gcc_blsp1_ahb_clk
.clkr
,
3367 [GCC_BLSP1_QUP1_I2C_APPS_CLK
] = &gcc_blsp1_qup1_i2c_apps_clk
.clkr
,
3368 [GCC_BLSP1_QUP1_SPI_APPS_CLK
] = &gcc_blsp1_qup1_spi_apps_clk
.clkr
,
3369 [GCC_BLSP1_QUP2_I2C_APPS_CLK
] = &gcc_blsp1_qup2_i2c_apps_clk
.clkr
,
3370 [GCC_BLSP1_QUP2_SPI_APPS_CLK
] = &gcc_blsp1_qup2_spi_apps_clk
.clkr
,
3371 [GCC_BLSP1_QUP3_I2C_APPS_CLK
] = &gcc_blsp1_qup3_i2c_apps_clk
.clkr
,
3372 [GCC_BLSP1_QUP3_SPI_APPS_CLK
] = &gcc_blsp1_qup3_spi_apps_clk
.clkr
,
3373 [GCC_BLSP1_QUP4_I2C_APPS_CLK
] = &gcc_blsp1_qup4_i2c_apps_clk
.clkr
,
3374 [GCC_BLSP1_QUP4_SPI_APPS_CLK
] = &gcc_blsp1_qup4_spi_apps_clk
.clkr
,
3375 [GCC_BLSP1_QUP5_I2C_APPS_CLK
] = &gcc_blsp1_qup5_i2c_apps_clk
.clkr
,
3376 [GCC_BLSP1_QUP5_SPI_APPS_CLK
] = &gcc_blsp1_qup5_spi_apps_clk
.clkr
,
3377 [GCC_BLSP1_QUP6_I2C_APPS_CLK
] = &gcc_blsp1_qup6_i2c_apps_clk
.clkr
,
3378 [GCC_BLSP1_QUP6_SPI_APPS_CLK
] = &gcc_blsp1_qup6_spi_apps_clk
.clkr
,
3379 [GCC_BLSP1_UART1_APPS_CLK
] = &gcc_blsp1_uart1_apps_clk
.clkr
,
3380 [GCC_BLSP1_UART2_APPS_CLK
] = &gcc_blsp1_uart2_apps_clk
.clkr
,
3381 [GCC_BLSP1_UART3_APPS_CLK
] = &gcc_blsp1_uart3_apps_clk
.clkr
,
3382 [GCC_BLSP1_UART4_APPS_CLK
] = &gcc_blsp1_uart4_apps_clk
.clkr
,
3383 [GCC_BLSP1_UART5_APPS_CLK
] = &gcc_blsp1_uart5_apps_clk
.clkr
,
3384 [GCC_BLSP1_UART6_APPS_CLK
] = &gcc_blsp1_uart6_apps_clk
.clkr
,
3385 [GCC_BLSP2_AHB_CLK
] = &gcc_blsp2_ahb_clk
.clkr
,
3386 [GCC_BLSP2_QUP1_I2C_APPS_CLK
] = &gcc_blsp2_qup1_i2c_apps_clk
.clkr
,
3387 [GCC_BLSP2_QUP1_SPI_APPS_CLK
] = &gcc_blsp2_qup1_spi_apps_clk
.clkr
,
3388 [GCC_BLSP2_QUP2_I2C_APPS_CLK
] = &gcc_blsp2_qup2_i2c_apps_clk
.clkr
,
3389 [GCC_BLSP2_QUP2_SPI_APPS_CLK
] = &gcc_blsp2_qup2_spi_apps_clk
.clkr
,
3390 [GCC_BLSP2_QUP3_I2C_APPS_CLK
] = &gcc_blsp2_qup3_i2c_apps_clk
.clkr
,
3391 [GCC_BLSP2_QUP3_SPI_APPS_CLK
] = &gcc_blsp2_qup3_spi_apps_clk
.clkr
,
3392 [GCC_BLSP2_QUP4_I2C_APPS_CLK
] = &gcc_blsp2_qup4_i2c_apps_clk
.clkr
,
3393 [GCC_BLSP2_QUP4_SPI_APPS_CLK
] = &gcc_blsp2_qup4_spi_apps_clk
.clkr
,
3394 [GCC_BLSP2_QUP5_I2C_APPS_CLK
] = &gcc_blsp2_qup5_i2c_apps_clk
.clkr
,
3395 [GCC_BLSP2_QUP5_SPI_APPS_CLK
] = &gcc_blsp2_qup5_spi_apps_clk
.clkr
,
3396 [GCC_BLSP2_QUP6_I2C_APPS_CLK
] = &gcc_blsp2_qup6_i2c_apps_clk
.clkr
,
3397 [GCC_BLSP2_QUP6_SPI_APPS_CLK
] = &gcc_blsp2_qup6_spi_apps_clk
.clkr
,
3398 [GCC_BLSP2_UART1_APPS_CLK
] = &gcc_blsp2_uart1_apps_clk
.clkr
,
3399 [GCC_BLSP2_UART2_APPS_CLK
] = &gcc_blsp2_uart2_apps_clk
.clkr
,
3400 [GCC_BLSP2_UART3_APPS_CLK
] = &gcc_blsp2_uart3_apps_clk
.clkr
,
3401 [GCC_BLSP2_UART4_APPS_CLK
] = &gcc_blsp2_uart4_apps_clk
.clkr
,
3402 [GCC_BLSP2_UART5_APPS_CLK
] = &gcc_blsp2_uart5_apps_clk
.clkr
,
3403 [GCC_BLSP2_UART6_APPS_CLK
] = &gcc_blsp2_uart6_apps_clk
.clkr
,
3404 [GCC_BOOT_ROM_AHB_CLK
] = &gcc_boot_rom_ahb_clk
.clkr
,
3405 [GCC_CE1_AHB_CLK
] = &gcc_ce1_ahb_clk
.clkr
,
3406 [GCC_CE1_AXI_CLK
] = &gcc_ce1_axi_clk
.clkr
,
3407 [GCC_CE1_CLK
] = &gcc_ce1_clk
.clkr
,
3408 [GCC_CE2_AHB_CLK
] = &gcc_ce2_ahb_clk
.clkr
,
3409 [GCC_CE2_AXI_CLK
] = &gcc_ce2_axi_clk
.clkr
,
3410 [GCC_CE2_CLK
] = &gcc_ce2_clk
.clkr
,
3411 [GCC_CE3_AHB_CLK
] = &gcc_ce3_ahb_clk
.clkr
,
3412 [GCC_CE3_AXI_CLK
] = &gcc_ce3_axi_clk
.clkr
,
3413 [GCC_CE3_CLK
] = &gcc_ce3_clk
.clkr
,
3414 [GCC_GP1_CLK
] = &gcc_gp1_clk
.clkr
,
3415 [GCC_GP2_CLK
] = &gcc_gp2_clk
.clkr
,
3416 [GCC_GP3_CLK
] = &gcc_gp3_clk
.clkr
,
3417 [GCC_OCMEM_NOC_CFG_AHB_CLK
] = &gcc_ocmem_noc_cfg_ahb_clk
.clkr
,
3418 [GCC_PCIE_0_AUX_CLK
] = &gcc_pcie_0_aux_clk
.clkr
,
3419 [GCC_PCIE_0_CFG_AHB_CLK
] = &gcc_pcie_0_cfg_ahb_clk
.clkr
,
3420 [GCC_PCIE_0_MSTR_AXI_CLK
] = &gcc_pcie_0_mstr_axi_clk
.clkr
,
3421 [GCC_PCIE_0_PIPE_CLK
] = &gcc_pcie_0_pipe_clk
.clkr
,
3422 [GCC_PCIE_0_SLV_AXI_CLK
] = &gcc_pcie_0_slv_axi_clk
.clkr
,
3423 [GCC_PCIE_1_AUX_CLK
] = &gcc_pcie_1_aux_clk
.clkr
,
3424 [GCC_PCIE_1_CFG_AHB_CLK
] = &gcc_pcie_1_cfg_ahb_clk
.clkr
,
3425 [GCC_PCIE_1_MSTR_AXI_CLK
] = &gcc_pcie_1_mstr_axi_clk
.clkr
,
3426 [GCC_PCIE_1_PIPE_CLK
] = &gcc_pcie_1_pipe_clk
.clkr
,
3427 [GCC_PCIE_1_SLV_AXI_CLK
] = &gcc_pcie_1_slv_axi_clk
.clkr
,
3428 [GCC_PDM2_CLK
] = &gcc_pdm2_clk
.clkr
,
3429 [GCC_PDM_AHB_CLK
] = &gcc_pdm_ahb_clk
.clkr
,
3430 [GCC_PERIPH_NOC_USB_HSIC_AHB_CLK
] = &gcc_periph_noc_usb_hsic_ahb_clk
.clkr
,
3431 [GCC_PRNG_AHB_CLK
] = &gcc_prng_ahb_clk
.clkr
,
3432 [GCC_SATA_ASIC0_CLK
] = &gcc_sata_asic0_clk
.clkr
,
3433 [GCC_SATA_AXI_CLK
] = &gcc_sata_axi_clk
.clkr
,
3434 [GCC_SATA_CFG_AHB_CLK
] = &gcc_sata_cfg_ahb_clk
.clkr
,
3435 [GCC_SATA_PMALIVE_CLK
] = &gcc_sata_pmalive_clk
.clkr
,
3436 [GCC_SATA_RX_CLK
] = &gcc_sata_rx_clk
.clkr
,
3437 [GCC_SATA_RX_OOB_CLK
] = &gcc_sata_rx_oob_clk
.clkr
,
3438 [GCC_SDCC1_AHB_CLK
] = &gcc_sdcc1_ahb_clk
.clkr
,
3439 [GCC_SDCC1_APPS_CLK
] = &gcc_sdcc1_apps_clk
.clkr
,
3440 [GCC_SDCC1_CDCCAL_FF_CLK
] = &gcc_sdcc1_cdccal_ff_clk
.clkr
,
3441 [GCC_SDCC1_CDCCAL_SLEEP_CLK
] = &gcc_sdcc1_cdccal_sleep_clk
.clkr
,
3442 [GCC_SDCC2_AHB_CLK
] = &gcc_sdcc2_ahb_clk
.clkr
,
3443 [GCC_SDCC2_APPS_CLK
] = &gcc_sdcc2_apps_clk
.clkr
,
3444 [GCC_SDCC3_AHB_CLK
] = &gcc_sdcc3_ahb_clk
.clkr
,
3445 [GCC_SDCC3_APPS_CLK
] = &gcc_sdcc3_apps_clk
.clkr
,
3446 [GCC_SDCC4_AHB_CLK
] = &gcc_sdcc4_ahb_clk
.clkr
,
3447 [GCC_SDCC4_APPS_CLK
] = &gcc_sdcc4_apps_clk
.clkr
,
3448 [GCC_SYS_NOC_UFS_AXI_CLK
] = &gcc_sys_noc_ufs_axi_clk
.clkr
,
3449 [GCC_SYS_NOC_USB3_AXI_CLK
] = &gcc_sys_noc_usb3_axi_clk
.clkr
,
3450 [GCC_SYS_NOC_USB3_SEC_AXI_CLK
] = &gcc_sys_noc_usb3_sec_axi_clk
.clkr
,
3451 [GCC_TSIF_AHB_CLK
] = &gcc_tsif_ahb_clk
.clkr
,
3452 [GCC_TSIF_INACTIVITY_TIMERS_CLK
] = &gcc_tsif_inactivity_timers_clk
.clkr
,
3453 [GCC_TSIF_REF_CLK
] = &gcc_tsif_ref_clk
.clkr
,
3454 [GCC_UFS_AHB_CLK
] = &gcc_ufs_ahb_clk
.clkr
,
3455 [GCC_UFS_AXI_CLK
] = &gcc_ufs_axi_clk
.clkr
,
3456 [GCC_UFS_RX_CFG_CLK
] = &gcc_ufs_rx_cfg_clk
.clkr
,
3457 [GCC_UFS_RX_SYMBOL_0_CLK
] = &gcc_ufs_rx_symbol_0_clk
.clkr
,
3458 [GCC_UFS_RX_SYMBOL_1_CLK
] = &gcc_ufs_rx_symbol_1_clk
.clkr
,
3459 [GCC_UFS_TX_CFG_CLK
] = &gcc_ufs_tx_cfg_clk
.clkr
,
3460 [GCC_UFS_TX_SYMBOL_0_CLK
] = &gcc_ufs_tx_symbol_0_clk
.clkr
,
3461 [GCC_UFS_TX_SYMBOL_1_CLK
] = &gcc_ufs_tx_symbol_1_clk
.clkr
,
3462 [GCC_USB2A_PHY_SLEEP_CLK
] = &gcc_usb2a_phy_sleep_clk
.clkr
,
3463 [GCC_USB2B_PHY_SLEEP_CLK
] = &gcc_usb2b_phy_sleep_clk
.clkr
,
3464 [GCC_USB30_MASTER_CLK
] = &gcc_usb30_master_clk
.clkr
,
3465 [GCC_USB30_MOCK_UTMI_CLK
] = &gcc_usb30_mock_utmi_clk
.clkr
,
3466 [GCC_USB30_SLEEP_CLK
] = &gcc_usb30_sleep_clk
.clkr
,
3467 [GCC_USB30_SEC_MASTER_CLK
] = &gcc_usb30_sec_master_clk
.clkr
,
3468 [GCC_USB30_SEC_MOCK_UTMI_CLK
] = &gcc_usb30_sec_mock_utmi_clk
.clkr
,
3469 [GCC_USB30_SEC_SLEEP_CLK
] = &gcc_usb30_sec_sleep_clk
.clkr
,
3470 [GCC_USB_HS_AHB_CLK
] = &gcc_usb_hs_ahb_clk
.clkr
,
3471 [GCC_USB_HS_INACTIVITY_TIMERS_CLK
] = &gcc_usb_hs_inactivity_timers_clk
.clkr
,
3472 [GCC_USB_HS_SYSTEM_CLK
] = &gcc_usb_hs_system_clk
.clkr
,
3473 [GCC_USB_HSIC_AHB_CLK
] = &gcc_usb_hsic_ahb_clk
.clkr
,
3474 [GCC_USB_HSIC_CLK
] = &gcc_usb_hsic_clk
.clkr
,
3475 [GCC_USB_HSIC_IO_CAL_CLK
] = &gcc_usb_hsic_io_cal_clk
.clkr
,
3476 [GCC_USB_HSIC_IO_CAL_SLEEP_CLK
] = &gcc_usb_hsic_io_cal_sleep_clk
.clkr
,
3477 [GCC_USB_HSIC_MOCK_UTMI_CLK
] = &gcc_usb_hsic_mock_utmi_clk
.clkr
,
3478 [GCC_USB_HSIC_SYSTEM_CLK
] = &gcc_usb_hsic_system_clk
.clkr
,
3481 static struct gdsc
*gcc_apq8084_gdscs
[] = {
3482 [USB_HS_HSIC_GDSC
] = &usb_hs_hsic_gdsc
,
3483 [PCIE0_GDSC
] = &pcie0_gdsc
,
3484 [PCIE1_GDSC
] = &pcie1_gdsc
,
3485 [USB30_GDSC
] = &usb30_gdsc
,
3488 static const struct qcom_reset_map gcc_apq8084_resets
[] = {
3489 [GCC_SYSTEM_NOC_BCR
] = { 0x0100 },
3490 [GCC_CONFIG_NOC_BCR
] = { 0x0140 },
3491 [GCC_PERIPH_NOC_BCR
] = { 0x0180 },
3492 [GCC_IMEM_BCR
] = { 0x0200 },
3493 [GCC_MMSS_BCR
] = { 0x0240 },
3494 [GCC_QDSS_BCR
] = { 0x0300 },
3495 [GCC_USB_30_BCR
] = { 0x03c0 },
3496 [GCC_USB3_PHY_BCR
] = { 0x03fc },
3497 [GCC_USB_HS_HSIC_BCR
] = { 0x0400 },
3498 [GCC_USB_HS_BCR
] = { 0x0480 },
3499 [GCC_USB2A_PHY_BCR
] = { 0x04a8 },
3500 [GCC_USB2B_PHY_BCR
] = { 0x04b0 },
3501 [GCC_SDCC1_BCR
] = { 0x04c0 },
3502 [GCC_SDCC2_BCR
] = { 0x0500 },
3503 [GCC_SDCC3_BCR
] = { 0x0540 },
3504 [GCC_SDCC4_BCR
] = { 0x0580 },
3505 [GCC_BLSP1_BCR
] = { 0x05c0 },
3506 [GCC_BLSP1_QUP1_BCR
] = { 0x0640 },
3507 [GCC_BLSP1_UART1_BCR
] = { 0x0680 },
3508 [GCC_BLSP1_QUP2_BCR
] = { 0x06c0 },
3509 [GCC_BLSP1_UART2_BCR
] = { 0x0700 },
3510 [GCC_BLSP1_QUP3_BCR
] = { 0x0740 },
3511 [GCC_BLSP1_UART3_BCR
] = { 0x0780 },
3512 [GCC_BLSP1_QUP4_BCR
] = { 0x07c0 },
3513 [GCC_BLSP1_UART4_BCR
] = { 0x0800 },
3514 [GCC_BLSP1_QUP5_BCR
] = { 0x0840 },
3515 [GCC_BLSP1_UART5_BCR
] = { 0x0880 },
3516 [GCC_BLSP1_QUP6_BCR
] = { 0x08c0 },
3517 [GCC_BLSP1_UART6_BCR
] = { 0x0900 },
3518 [GCC_BLSP2_BCR
] = { 0x0940 },
3519 [GCC_BLSP2_QUP1_BCR
] = { 0x0980 },
3520 [GCC_BLSP2_UART1_BCR
] = { 0x09c0 },
3521 [GCC_BLSP2_QUP2_BCR
] = { 0x0a00 },
3522 [GCC_BLSP2_UART2_BCR
] = { 0x0a40 },
3523 [GCC_BLSP2_QUP3_BCR
] = { 0x0a80 },
3524 [GCC_BLSP2_UART3_BCR
] = { 0x0ac0 },
3525 [GCC_BLSP2_QUP4_BCR
] = { 0x0b00 },
3526 [GCC_BLSP2_UART4_BCR
] = { 0x0b40 },
3527 [GCC_BLSP2_QUP5_BCR
] = { 0x0b80 },
3528 [GCC_BLSP2_UART5_BCR
] = { 0x0bc0 },
3529 [GCC_BLSP2_QUP6_BCR
] = { 0x0c00 },
3530 [GCC_BLSP2_UART6_BCR
] = { 0x0c40 },
3531 [GCC_PDM_BCR
] = { 0x0cc0 },
3532 [GCC_PRNG_BCR
] = { 0x0d00 },
3533 [GCC_BAM_DMA_BCR
] = { 0x0d40 },
3534 [GCC_TSIF_BCR
] = { 0x0d80 },
3535 [GCC_TCSR_BCR
] = { 0x0dc0 },
3536 [GCC_BOOT_ROM_BCR
] = { 0x0e00 },
3537 [GCC_MSG_RAM_BCR
] = { 0x0e40 },
3538 [GCC_TLMM_BCR
] = { 0x0e80 },
3539 [GCC_MPM_BCR
] = { 0x0ec0 },
3540 [GCC_MPM_AHB_RESET
] = { 0x0ec4, 1 },
3541 [GCC_MPM_NON_AHB_RESET
] = { 0x0ec4, 2 },
3542 [GCC_SEC_CTRL_BCR
] = { 0x0f40 },
3543 [GCC_SPMI_BCR
] = { 0x0fc0 },
3544 [GCC_SPDM_BCR
] = { 0x1000 },
3545 [GCC_CE1_BCR
] = { 0x1040 },
3546 [GCC_CE2_BCR
] = { 0x1080 },
3547 [GCC_BIMC_BCR
] = { 0x1100 },
3548 [GCC_SNOC_BUS_TIMEOUT0_BCR
] = { 0x1240 },
3549 [GCC_SNOC_BUS_TIMEOUT2_BCR
] = { 0x1248 },
3550 [GCC_PNOC_BUS_TIMEOUT0_BCR
] = { 0x1280 },
3551 [GCC_PNOC_BUS_TIMEOUT1_BCR
] = { 0x1288 },
3552 [GCC_PNOC_BUS_TIMEOUT2_BCR
] = { 0x1290 },
3553 [GCC_PNOC_BUS_TIMEOUT3_BCR
] = { 0x1298 },
3554 [GCC_PNOC_BUS_TIMEOUT4_BCR
] = { 0x12a0 },
3555 [GCC_CNOC_BUS_TIMEOUT0_BCR
] = { 0x12c0 },
3556 [GCC_CNOC_BUS_TIMEOUT1_BCR
] = { 0x12c8 },
3557 [GCC_CNOC_BUS_TIMEOUT2_BCR
] = { 0x12d0 },
3558 [GCC_CNOC_BUS_TIMEOUT3_BCR
] = { 0x12d8 },
3559 [GCC_CNOC_BUS_TIMEOUT4_BCR
] = { 0x12e0 },
3560 [GCC_CNOC_BUS_TIMEOUT5_BCR
] = { 0x12e8 },
3561 [GCC_CNOC_BUS_TIMEOUT6_BCR
] = { 0x12f0 },
3562 [GCC_DEHR_BCR
] = { 0x1300 },
3563 [GCC_RBCPR_BCR
] = { 0x1380 },
3564 [GCC_MSS_RESTART
] = { 0x1680 },
3565 [GCC_LPASS_RESTART
] = { 0x16c0 },
3566 [GCC_WCSS_RESTART
] = { 0x1700 },
3567 [GCC_VENUS_RESTART
] = { 0x1740 },
3568 [GCC_COPSS_SMMU_BCR
] = { 0x1a40 },
3569 [GCC_SPSS_BCR
] = { 0x1a80 },
3570 [GCC_PCIE_0_BCR
] = { 0x1ac0 },
3571 [GCC_PCIE_0_PHY_BCR
] = { 0x1b00 },
3572 [GCC_PCIE_1_BCR
] = { 0x1b40 },
3573 [GCC_PCIE_1_PHY_BCR
] = { 0x1b80 },
3574 [GCC_USB_30_SEC_BCR
] = { 0x1bc0 },
3575 [GCC_USB3_SEC_PHY_BCR
] = { 0x1bfc },
3576 [GCC_SATA_BCR
] = { 0x1c40 },
3577 [GCC_CE3_BCR
] = { 0x1d00 },
3578 [GCC_UFS_BCR
] = { 0x1d40 },
3579 [GCC_USB30_PHY_COM_BCR
] = { 0x1e80 },
3582 static const struct regmap_config gcc_apq8084_regmap_config
= {
3586 .max_register
= 0x1fc0,
3590 static const struct qcom_cc_desc gcc_apq8084_desc
= {
3591 .config
= &gcc_apq8084_regmap_config
,
3592 .clks
= gcc_apq8084_clocks
,
3593 .num_clks
= ARRAY_SIZE(gcc_apq8084_clocks
),
3594 .resets
= gcc_apq8084_resets
,
3595 .num_resets
= ARRAY_SIZE(gcc_apq8084_resets
),
3596 .gdscs
= gcc_apq8084_gdscs
,
3597 .num_gdscs
= ARRAY_SIZE(gcc_apq8084_gdscs
),
3600 static const struct of_device_id gcc_apq8084_match_table
[] = {
3601 { .compatible
= "qcom,gcc-apq8084" },
3604 MODULE_DEVICE_TABLE(of
, gcc_apq8084_match_table
);
3606 static int gcc_apq8084_probe(struct platform_device
*pdev
)
3609 struct device
*dev
= &pdev
->dev
;
3611 ret
= qcom_cc_register_board_clk(dev
, "xo_board", "xo", 19200000);
3615 ret
= qcom_cc_register_sleep_clk(dev
);
3619 return qcom_cc_probe(pdev
, &gcc_apq8084_desc
);
3622 static struct platform_driver gcc_apq8084_driver
= {
3623 .probe
= gcc_apq8084_probe
,
3625 .name
= "gcc-apq8084",
3626 .of_match_table
= gcc_apq8084_match_table
,
3630 static int __init
gcc_apq8084_init(void)
3632 return platform_driver_register(&gcc_apq8084_driver
);
3634 core_initcall(gcc_apq8084_init
);
3636 static void __exit
gcc_apq8084_exit(void)
3638 platform_driver_unregister(&gcc_apq8084_driver
);
3640 module_exit(gcc_apq8084_exit
);
3642 MODULE_DESCRIPTION("QCOM GCC APQ8084 Driver");
3643 MODULE_LICENSE("GPL v2");
3644 MODULE_ALIAS("platform:gcc-apq8084");