2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
26 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
33 #include "clk-hfpll.h"
36 static struct clk_pll pll0
= {
44 .clkr
.hw
.init
= &(struct clk_init_data
){
46 .parent_names
= (const char *[]){ "pxo" },
52 static struct clk_regmap pll0_vote
= {
54 .enable_mask
= BIT(0),
55 .hw
.init
= &(struct clk_init_data
){
57 .parent_names
= (const char *[]){ "pll0" },
59 .ops
= &clk_pll_vote_ops
,
63 static struct clk_pll pll3
= {
71 .clkr
.hw
.init
= &(struct clk_init_data
){
73 .parent_names
= (const char *[]){ "pxo" },
79 static struct clk_regmap pll4_vote
= {
81 .enable_mask
= BIT(4),
82 .hw
.init
= &(struct clk_init_data
){
84 .parent_names
= (const char *[]){ "pll4" },
86 .ops
= &clk_pll_vote_ops
,
90 static struct clk_pll pll8
= {
98 .clkr
.hw
.init
= &(struct clk_init_data
){
100 .parent_names
= (const char *[]){ "pxo" },
106 static struct clk_regmap pll8_vote
= {
107 .enable_reg
= 0x34c0,
108 .enable_mask
= BIT(8),
109 .hw
.init
= &(struct clk_init_data
){
111 .parent_names
= (const char *[]){ "pll8" },
113 .ops
= &clk_pll_vote_ops
,
117 static struct hfpll_data hfpll0_data
= {
122 .config_reg
= 0x3204,
123 .status_reg
= 0x321c,
124 .config_val
= 0x7845c665,
126 .droop_val
= 0x0108c000,
127 .min_rate
= 600000000UL,
128 .max_rate
= 1800000000UL,
131 static struct clk_hfpll hfpll0
= {
133 .clkr
.hw
.init
= &(struct clk_init_data
){
134 .parent_names
= (const char *[]){ "pxo" },
137 .ops
= &clk_ops_hfpll
,
138 .flags
= CLK_IGNORE_UNUSED
,
140 .lock
= __SPIN_LOCK_UNLOCKED(hfpll0
.lock
),
143 static struct hfpll_data hfpll1_data
= {
148 .config_reg
= 0x3244,
149 .status_reg
= 0x325c,
150 .config_val
= 0x7845c665,
152 .droop_val
= 0x0108c000,
153 .min_rate
= 600000000UL,
154 .max_rate
= 1800000000UL,
157 static struct clk_hfpll hfpll1
= {
159 .clkr
.hw
.init
= &(struct clk_init_data
){
160 .parent_names
= (const char *[]){ "pxo" },
163 .ops
= &clk_ops_hfpll
,
164 .flags
= CLK_IGNORE_UNUSED
,
166 .lock
= __SPIN_LOCK_UNLOCKED(hfpll1
.lock
),
169 static struct hfpll_data hfpll_l2_data
= {
174 .config_reg
= 0x3304,
175 .status_reg
= 0x331c,
176 .config_val
= 0x7845c665,
178 .droop_val
= 0x0108c000,
179 .min_rate
= 600000000UL,
180 .max_rate
= 1800000000UL,
183 static struct clk_hfpll hfpll_l2
= {
185 .clkr
.hw
.init
= &(struct clk_init_data
){
186 .parent_names
= (const char *[]){ "pxo" },
189 .ops
= &clk_ops_hfpll
,
190 .flags
= CLK_IGNORE_UNUSED
,
192 .lock
= __SPIN_LOCK_UNLOCKED(hfpll_l2
.lock
),
195 static struct clk_pll pll14
= {
199 .config_reg
= 0x31d4,
201 .status_reg
= 0x31d8,
203 .clkr
.hw
.init
= &(struct clk_init_data
){
205 .parent_names
= (const char *[]){ "pxo" },
211 static struct clk_regmap pll14_vote
= {
212 .enable_reg
= 0x34c0,
213 .enable_mask
= BIT(14),
214 .hw
.init
= &(struct clk_init_data
){
215 .name
= "pll14_vote",
216 .parent_names
= (const char *[]){ "pll14" },
218 .ops
= &clk_pll_vote_ops
,
222 #define NSS_PLL_RATE(f, _l, _m, _n, i) \
231 static struct pll_freq_tbl pll18_freq_tbl
[] = {
232 NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
233 NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
236 static struct clk_pll pll18
= {
240 .config_reg
= 0x31b4,
242 .status_reg
= 0x31b8,
244 .post_div_shift
= 16,
246 .freq_tbl
= pll18_freq_tbl
,
247 .clkr
.hw
.init
= &(struct clk_init_data
){
249 .parent_names
= (const char *[]){ "pxo" },
265 static const struct parent_map gcc_pxo_pll8_map
[] = {
270 static const char * const gcc_pxo_pll8
[] = {
275 static const struct parent_map gcc_pxo_pll8_cxo_map
[] = {
281 static const char * const gcc_pxo_pll8_cxo
[] = {
287 static const struct parent_map gcc_pxo_pll3_map
[] = {
292 static const struct parent_map gcc_pxo_pll3_sata_map
[] = {
297 static const char * const gcc_pxo_pll3
[] = {
302 static const struct parent_map gcc_pxo_pll8_pll0
[] = {
308 static const char * const gcc_pxo_pll8_pll0_map
[] = {
314 static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map
[] = {
322 static const char * const gcc_pxo_pll8_pll14_pll18_pll0
[] = {
330 static struct freq_tbl clk_tbl_gsbi_uart
[] = {
331 { 1843200, P_PLL8
, 2, 6, 625 },
332 { 3686400, P_PLL8
, 2, 12, 625 },
333 { 7372800, P_PLL8
, 2, 24, 625 },
334 { 14745600, P_PLL8
, 2, 48, 625 },
335 { 16000000, P_PLL8
, 4, 1, 6 },
336 { 24000000, P_PLL8
, 4, 1, 4 },
337 { 32000000, P_PLL8
, 4, 1, 3 },
338 { 40000000, P_PLL8
, 1, 5, 48 },
339 { 46400000, P_PLL8
, 1, 29, 240 },
340 { 48000000, P_PLL8
, 4, 1, 2 },
341 { 51200000, P_PLL8
, 1, 2, 15 },
342 { 56000000, P_PLL8
, 1, 7, 48 },
343 { 58982400, P_PLL8
, 1, 96, 625 },
344 { 64000000, P_PLL8
, 2, 1, 3 },
348 static struct clk_rcg gsbi1_uart_src
= {
353 .mnctr_reset_bit
= 7,
354 .mnctr_mode_shift
= 5,
365 .parent_map
= gcc_pxo_pll8_map
,
367 .freq_tbl
= clk_tbl_gsbi_uart
,
369 .enable_reg
= 0x29d4,
370 .enable_mask
= BIT(11),
371 .hw
.init
= &(struct clk_init_data
){
372 .name
= "gsbi1_uart_src",
373 .parent_names
= gcc_pxo_pll8
,
376 .flags
= CLK_SET_PARENT_GATE
,
381 static struct clk_branch gsbi1_uart_clk
= {
385 .enable_reg
= 0x29d4,
386 .enable_mask
= BIT(9),
387 .hw
.init
= &(struct clk_init_data
){
388 .name
= "gsbi1_uart_clk",
389 .parent_names
= (const char *[]){
393 .ops
= &clk_branch_ops
,
394 .flags
= CLK_SET_RATE_PARENT
,
399 static struct clk_rcg gsbi2_uart_src
= {
404 .mnctr_reset_bit
= 7,
405 .mnctr_mode_shift
= 5,
416 .parent_map
= gcc_pxo_pll8_map
,
418 .freq_tbl
= clk_tbl_gsbi_uart
,
420 .enable_reg
= 0x29f4,
421 .enable_mask
= BIT(11),
422 .hw
.init
= &(struct clk_init_data
){
423 .name
= "gsbi2_uart_src",
424 .parent_names
= gcc_pxo_pll8
,
427 .flags
= CLK_SET_PARENT_GATE
,
432 static struct clk_branch gsbi2_uart_clk
= {
436 .enable_reg
= 0x29f4,
437 .enable_mask
= BIT(9),
438 .hw
.init
= &(struct clk_init_data
){
439 .name
= "gsbi2_uart_clk",
440 .parent_names
= (const char *[]){
444 .ops
= &clk_branch_ops
,
445 .flags
= CLK_SET_RATE_PARENT
,
450 static struct clk_rcg gsbi4_uart_src
= {
455 .mnctr_reset_bit
= 7,
456 .mnctr_mode_shift
= 5,
467 .parent_map
= gcc_pxo_pll8_map
,
469 .freq_tbl
= clk_tbl_gsbi_uart
,
471 .enable_reg
= 0x2a34,
472 .enable_mask
= BIT(11),
473 .hw
.init
= &(struct clk_init_data
){
474 .name
= "gsbi4_uart_src",
475 .parent_names
= gcc_pxo_pll8
,
478 .flags
= CLK_SET_PARENT_GATE
,
483 static struct clk_branch gsbi4_uart_clk
= {
487 .enable_reg
= 0x2a34,
488 .enable_mask
= BIT(9),
489 .hw
.init
= &(struct clk_init_data
){
490 .name
= "gsbi4_uart_clk",
491 .parent_names
= (const char *[]){
495 .ops
= &clk_branch_ops
,
496 .flags
= CLK_SET_RATE_PARENT
,
501 static struct clk_rcg gsbi5_uart_src
= {
506 .mnctr_reset_bit
= 7,
507 .mnctr_mode_shift
= 5,
518 .parent_map
= gcc_pxo_pll8_map
,
520 .freq_tbl
= clk_tbl_gsbi_uart
,
522 .enable_reg
= 0x2a54,
523 .enable_mask
= BIT(11),
524 .hw
.init
= &(struct clk_init_data
){
525 .name
= "gsbi5_uart_src",
526 .parent_names
= gcc_pxo_pll8
,
529 .flags
= CLK_SET_PARENT_GATE
,
534 static struct clk_branch gsbi5_uart_clk
= {
538 .enable_reg
= 0x2a54,
539 .enable_mask
= BIT(9),
540 .hw
.init
= &(struct clk_init_data
){
541 .name
= "gsbi5_uart_clk",
542 .parent_names
= (const char *[]){
546 .ops
= &clk_branch_ops
,
547 .flags
= CLK_SET_RATE_PARENT
,
552 static struct clk_rcg gsbi6_uart_src
= {
557 .mnctr_reset_bit
= 7,
558 .mnctr_mode_shift
= 5,
569 .parent_map
= gcc_pxo_pll8_map
,
571 .freq_tbl
= clk_tbl_gsbi_uart
,
573 .enable_reg
= 0x2a74,
574 .enable_mask
= BIT(11),
575 .hw
.init
= &(struct clk_init_data
){
576 .name
= "gsbi6_uart_src",
577 .parent_names
= gcc_pxo_pll8
,
580 .flags
= CLK_SET_PARENT_GATE
,
585 static struct clk_branch gsbi6_uart_clk
= {
589 .enable_reg
= 0x2a74,
590 .enable_mask
= BIT(9),
591 .hw
.init
= &(struct clk_init_data
){
592 .name
= "gsbi6_uart_clk",
593 .parent_names
= (const char *[]){
597 .ops
= &clk_branch_ops
,
598 .flags
= CLK_SET_RATE_PARENT
,
603 static struct clk_rcg gsbi7_uart_src
= {
608 .mnctr_reset_bit
= 7,
609 .mnctr_mode_shift
= 5,
620 .parent_map
= gcc_pxo_pll8_map
,
622 .freq_tbl
= clk_tbl_gsbi_uart
,
624 .enable_reg
= 0x2a94,
625 .enable_mask
= BIT(11),
626 .hw
.init
= &(struct clk_init_data
){
627 .name
= "gsbi7_uart_src",
628 .parent_names
= gcc_pxo_pll8
,
631 .flags
= CLK_SET_PARENT_GATE
,
636 static struct clk_branch gsbi7_uart_clk
= {
640 .enable_reg
= 0x2a94,
641 .enable_mask
= BIT(9),
642 .hw
.init
= &(struct clk_init_data
){
643 .name
= "gsbi7_uart_clk",
644 .parent_names
= (const char *[]){
648 .ops
= &clk_branch_ops
,
649 .flags
= CLK_SET_RATE_PARENT
,
654 static struct freq_tbl clk_tbl_gsbi_qup
[] = {
655 { 1100000, P_PXO
, 1, 2, 49 },
656 { 5400000, P_PXO
, 1, 1, 5 },
657 { 10800000, P_PXO
, 1, 2, 5 },
658 { 15060000, P_PLL8
, 1, 2, 51 },
659 { 24000000, P_PLL8
, 4, 1, 4 },
660 { 25000000, P_PXO
, 1, 0, 0 },
661 { 25600000, P_PLL8
, 1, 1, 15 },
662 { 48000000, P_PLL8
, 4, 1, 2 },
663 { 51200000, P_PLL8
, 1, 2, 15 },
667 static struct clk_rcg gsbi1_qup_src
= {
672 .mnctr_reset_bit
= 7,
673 .mnctr_mode_shift
= 5,
684 .parent_map
= gcc_pxo_pll8_map
,
686 .freq_tbl
= clk_tbl_gsbi_qup
,
688 .enable_reg
= 0x29cc,
689 .enable_mask
= BIT(11),
690 .hw
.init
= &(struct clk_init_data
){
691 .name
= "gsbi1_qup_src",
692 .parent_names
= gcc_pxo_pll8
,
695 .flags
= CLK_SET_PARENT_GATE
,
700 static struct clk_branch gsbi1_qup_clk
= {
704 .enable_reg
= 0x29cc,
705 .enable_mask
= BIT(9),
706 .hw
.init
= &(struct clk_init_data
){
707 .name
= "gsbi1_qup_clk",
708 .parent_names
= (const char *[]){ "gsbi1_qup_src" },
710 .ops
= &clk_branch_ops
,
711 .flags
= CLK_SET_RATE_PARENT
,
716 static struct clk_rcg gsbi2_qup_src
= {
721 .mnctr_reset_bit
= 7,
722 .mnctr_mode_shift
= 5,
733 .parent_map
= gcc_pxo_pll8_map
,
735 .freq_tbl
= clk_tbl_gsbi_qup
,
737 .enable_reg
= 0x29ec,
738 .enable_mask
= BIT(11),
739 .hw
.init
= &(struct clk_init_data
){
740 .name
= "gsbi2_qup_src",
741 .parent_names
= gcc_pxo_pll8
,
744 .flags
= CLK_SET_PARENT_GATE
,
749 static struct clk_branch gsbi2_qup_clk
= {
753 .enable_reg
= 0x29ec,
754 .enable_mask
= BIT(9),
755 .hw
.init
= &(struct clk_init_data
){
756 .name
= "gsbi2_qup_clk",
757 .parent_names
= (const char *[]){ "gsbi2_qup_src" },
759 .ops
= &clk_branch_ops
,
760 .flags
= CLK_SET_RATE_PARENT
,
765 static struct clk_rcg gsbi4_qup_src
= {
770 .mnctr_reset_bit
= 7,
771 .mnctr_mode_shift
= 5,
782 .parent_map
= gcc_pxo_pll8_map
,
784 .freq_tbl
= clk_tbl_gsbi_qup
,
786 .enable_reg
= 0x2a2c,
787 .enable_mask
= BIT(11),
788 .hw
.init
= &(struct clk_init_data
){
789 .name
= "gsbi4_qup_src",
790 .parent_names
= gcc_pxo_pll8
,
793 .flags
= CLK_SET_PARENT_GATE
,
798 static struct clk_branch gsbi4_qup_clk
= {
802 .enable_reg
= 0x2a2c,
803 .enable_mask
= BIT(9),
804 .hw
.init
= &(struct clk_init_data
){
805 .name
= "gsbi4_qup_clk",
806 .parent_names
= (const char *[]){ "gsbi4_qup_src" },
808 .ops
= &clk_branch_ops
,
809 .flags
= CLK_SET_RATE_PARENT
,
814 static struct clk_rcg gsbi5_qup_src
= {
819 .mnctr_reset_bit
= 7,
820 .mnctr_mode_shift
= 5,
831 .parent_map
= gcc_pxo_pll8_map
,
833 .freq_tbl
= clk_tbl_gsbi_qup
,
835 .enable_reg
= 0x2a4c,
836 .enable_mask
= BIT(11),
837 .hw
.init
= &(struct clk_init_data
){
838 .name
= "gsbi5_qup_src",
839 .parent_names
= gcc_pxo_pll8
,
842 .flags
= CLK_SET_PARENT_GATE
,
847 static struct clk_branch gsbi5_qup_clk
= {
851 .enable_reg
= 0x2a4c,
852 .enable_mask
= BIT(9),
853 .hw
.init
= &(struct clk_init_data
){
854 .name
= "gsbi5_qup_clk",
855 .parent_names
= (const char *[]){ "gsbi5_qup_src" },
857 .ops
= &clk_branch_ops
,
858 .flags
= CLK_SET_RATE_PARENT
,
863 static struct clk_rcg gsbi6_qup_src
= {
868 .mnctr_reset_bit
= 7,
869 .mnctr_mode_shift
= 5,
880 .parent_map
= gcc_pxo_pll8_map
,
882 .freq_tbl
= clk_tbl_gsbi_qup
,
884 .enable_reg
= 0x2a6c,
885 .enable_mask
= BIT(11),
886 .hw
.init
= &(struct clk_init_data
){
887 .name
= "gsbi6_qup_src",
888 .parent_names
= gcc_pxo_pll8
,
891 .flags
= CLK_SET_PARENT_GATE
,
896 static struct clk_branch gsbi6_qup_clk
= {
900 .enable_reg
= 0x2a6c,
901 .enable_mask
= BIT(9),
902 .hw
.init
= &(struct clk_init_data
){
903 .name
= "gsbi6_qup_clk",
904 .parent_names
= (const char *[]){ "gsbi6_qup_src" },
906 .ops
= &clk_branch_ops
,
907 .flags
= CLK_SET_RATE_PARENT
,
912 static struct clk_rcg gsbi7_qup_src
= {
917 .mnctr_reset_bit
= 7,
918 .mnctr_mode_shift
= 5,
929 .parent_map
= gcc_pxo_pll8_map
,
931 .freq_tbl
= clk_tbl_gsbi_qup
,
933 .enable_reg
= 0x2a8c,
934 .enable_mask
= BIT(11),
935 .hw
.init
= &(struct clk_init_data
){
936 .name
= "gsbi7_qup_src",
937 .parent_names
= gcc_pxo_pll8
,
940 .flags
= CLK_SET_PARENT_GATE
,
945 static struct clk_branch gsbi7_qup_clk
= {
949 .enable_reg
= 0x2a8c,
950 .enable_mask
= BIT(9),
951 .hw
.init
= &(struct clk_init_data
){
952 .name
= "gsbi7_qup_clk",
953 .parent_names
= (const char *[]){ "gsbi7_qup_src" },
955 .ops
= &clk_branch_ops
,
956 .flags
= CLK_SET_RATE_PARENT
,
961 static struct clk_branch gsbi1_h_clk
= {
967 .enable_reg
= 0x29c0,
968 .enable_mask
= BIT(4),
969 .hw
.init
= &(struct clk_init_data
){
970 .name
= "gsbi1_h_clk",
971 .ops
= &clk_branch_ops
,
976 static struct clk_branch gsbi2_h_clk
= {
982 .enable_reg
= 0x29e0,
983 .enable_mask
= BIT(4),
984 .hw
.init
= &(struct clk_init_data
){
985 .name
= "gsbi2_h_clk",
986 .ops
= &clk_branch_ops
,
991 static struct clk_branch gsbi4_h_clk
= {
997 .enable_reg
= 0x2a20,
998 .enable_mask
= BIT(4),
999 .hw
.init
= &(struct clk_init_data
){
1000 .name
= "gsbi4_h_clk",
1001 .ops
= &clk_branch_ops
,
1006 static struct clk_branch gsbi5_h_clk
= {
1012 .enable_reg
= 0x2a40,
1013 .enable_mask
= BIT(4),
1014 .hw
.init
= &(struct clk_init_data
){
1015 .name
= "gsbi5_h_clk",
1016 .ops
= &clk_branch_ops
,
1021 static struct clk_branch gsbi6_h_clk
= {
1027 .enable_reg
= 0x2a60,
1028 .enable_mask
= BIT(4),
1029 .hw
.init
= &(struct clk_init_data
){
1030 .name
= "gsbi6_h_clk",
1031 .ops
= &clk_branch_ops
,
1036 static struct clk_branch gsbi7_h_clk
= {
1042 .enable_reg
= 0x2a80,
1043 .enable_mask
= BIT(4),
1044 .hw
.init
= &(struct clk_init_data
){
1045 .name
= "gsbi7_h_clk",
1046 .ops
= &clk_branch_ops
,
1051 static const struct freq_tbl clk_tbl_gp
[] = {
1052 { 12500000, P_PXO
, 2, 0, 0 },
1053 { 25000000, P_PXO
, 1, 0, 0 },
1054 { 64000000, P_PLL8
, 2, 1, 3 },
1055 { 76800000, P_PLL8
, 1, 1, 5 },
1056 { 96000000, P_PLL8
, 4, 0, 0 },
1057 { 128000000, P_PLL8
, 3, 0, 0 },
1058 { 192000000, P_PLL8
, 2, 0, 0 },
1062 static struct clk_rcg gp0_src
= {
1067 .mnctr_reset_bit
= 7,
1068 .mnctr_mode_shift
= 5,
1079 .parent_map
= gcc_pxo_pll8_cxo_map
,
1081 .freq_tbl
= clk_tbl_gp
,
1083 .enable_reg
= 0x2d24,
1084 .enable_mask
= BIT(11),
1085 .hw
.init
= &(struct clk_init_data
){
1087 .parent_names
= gcc_pxo_pll8_cxo
,
1089 .ops
= &clk_rcg_ops
,
1090 .flags
= CLK_SET_PARENT_GATE
,
1095 static struct clk_branch gp0_clk
= {
1099 .enable_reg
= 0x2d24,
1100 .enable_mask
= BIT(9),
1101 .hw
.init
= &(struct clk_init_data
){
1103 .parent_names
= (const char *[]){ "gp0_src" },
1105 .ops
= &clk_branch_ops
,
1106 .flags
= CLK_SET_RATE_PARENT
,
1111 static struct clk_rcg gp1_src
= {
1116 .mnctr_reset_bit
= 7,
1117 .mnctr_mode_shift
= 5,
1128 .parent_map
= gcc_pxo_pll8_cxo_map
,
1130 .freq_tbl
= clk_tbl_gp
,
1132 .enable_reg
= 0x2d44,
1133 .enable_mask
= BIT(11),
1134 .hw
.init
= &(struct clk_init_data
){
1136 .parent_names
= gcc_pxo_pll8_cxo
,
1138 .ops
= &clk_rcg_ops
,
1139 .flags
= CLK_SET_RATE_GATE
,
1144 static struct clk_branch gp1_clk
= {
1148 .enable_reg
= 0x2d44,
1149 .enable_mask
= BIT(9),
1150 .hw
.init
= &(struct clk_init_data
){
1152 .parent_names
= (const char *[]){ "gp1_src" },
1154 .ops
= &clk_branch_ops
,
1155 .flags
= CLK_SET_RATE_PARENT
,
1160 static struct clk_rcg gp2_src
= {
1165 .mnctr_reset_bit
= 7,
1166 .mnctr_mode_shift
= 5,
1177 .parent_map
= gcc_pxo_pll8_cxo_map
,
1179 .freq_tbl
= clk_tbl_gp
,
1181 .enable_reg
= 0x2d64,
1182 .enable_mask
= BIT(11),
1183 .hw
.init
= &(struct clk_init_data
){
1185 .parent_names
= gcc_pxo_pll8_cxo
,
1187 .ops
= &clk_rcg_ops
,
1188 .flags
= CLK_SET_RATE_GATE
,
1193 static struct clk_branch gp2_clk
= {
1197 .enable_reg
= 0x2d64,
1198 .enable_mask
= BIT(9),
1199 .hw
.init
= &(struct clk_init_data
){
1201 .parent_names
= (const char *[]){ "gp2_src" },
1203 .ops
= &clk_branch_ops
,
1204 .flags
= CLK_SET_RATE_PARENT
,
1209 static struct clk_branch pmem_clk
= {
1215 .enable_reg
= 0x25a0,
1216 .enable_mask
= BIT(4),
1217 .hw
.init
= &(struct clk_init_data
){
1219 .ops
= &clk_branch_ops
,
1224 static struct clk_rcg prng_src
= {
1232 .parent_map
= gcc_pxo_pll8_map
,
1235 .hw
.init
= &(struct clk_init_data
){
1237 .parent_names
= gcc_pxo_pll8
,
1239 .ops
= &clk_rcg_ops
,
1244 static struct clk_branch prng_clk
= {
1246 .halt_check
= BRANCH_HALT_VOTED
,
1249 .enable_reg
= 0x3080,
1250 .enable_mask
= BIT(10),
1251 .hw
.init
= &(struct clk_init_data
){
1253 .parent_names
= (const char *[]){ "prng_src" },
1255 .ops
= &clk_branch_ops
,
1260 static const struct freq_tbl clk_tbl_sdc
[] = {
1261 { 200000, P_PXO
, 2, 2, 125 },
1262 { 400000, P_PLL8
, 4, 1, 240 },
1263 { 16000000, P_PLL8
, 4, 1, 6 },
1264 { 17070000, P_PLL8
, 1, 2, 45 },
1265 { 20210000, P_PLL8
, 1, 1, 19 },
1266 { 24000000, P_PLL8
, 4, 1, 4 },
1267 { 48000000, P_PLL8
, 4, 1, 2 },
1268 { 64000000, P_PLL8
, 3, 1, 2 },
1269 { 96000000, P_PLL8
, 4, 0, 0 },
1270 { 192000000, P_PLL8
, 2, 0, 0 },
1274 static struct clk_rcg sdc1_src
= {
1279 .mnctr_reset_bit
= 7,
1280 .mnctr_mode_shift
= 5,
1291 .parent_map
= gcc_pxo_pll8_map
,
1293 .freq_tbl
= clk_tbl_sdc
,
1295 .enable_reg
= 0x282c,
1296 .enable_mask
= BIT(11),
1297 .hw
.init
= &(struct clk_init_data
){
1299 .parent_names
= gcc_pxo_pll8
,
1301 .ops
= &clk_rcg_ops
,
1306 static struct clk_branch sdc1_clk
= {
1310 .enable_reg
= 0x282c,
1311 .enable_mask
= BIT(9),
1312 .hw
.init
= &(struct clk_init_data
){
1314 .parent_names
= (const char *[]){ "sdc1_src" },
1316 .ops
= &clk_branch_ops
,
1317 .flags
= CLK_SET_RATE_PARENT
,
1322 static struct clk_rcg sdc3_src
= {
1327 .mnctr_reset_bit
= 7,
1328 .mnctr_mode_shift
= 5,
1339 .parent_map
= gcc_pxo_pll8_map
,
1341 .freq_tbl
= clk_tbl_sdc
,
1343 .enable_reg
= 0x286c,
1344 .enable_mask
= BIT(11),
1345 .hw
.init
= &(struct clk_init_data
){
1347 .parent_names
= gcc_pxo_pll8
,
1349 .ops
= &clk_rcg_ops
,
1354 static struct clk_branch sdc3_clk
= {
1358 .enable_reg
= 0x286c,
1359 .enable_mask
= BIT(9),
1360 .hw
.init
= &(struct clk_init_data
){
1362 .parent_names
= (const char *[]){ "sdc3_src" },
1364 .ops
= &clk_branch_ops
,
1365 .flags
= CLK_SET_RATE_PARENT
,
1370 static struct clk_branch sdc1_h_clk
= {
1376 .enable_reg
= 0x2820,
1377 .enable_mask
= BIT(4),
1378 .hw
.init
= &(struct clk_init_data
){
1379 .name
= "sdc1_h_clk",
1380 .ops
= &clk_branch_ops
,
1385 static struct clk_branch sdc3_h_clk
= {
1391 .enable_reg
= 0x2860,
1392 .enable_mask
= BIT(4),
1393 .hw
.init
= &(struct clk_init_data
){
1394 .name
= "sdc3_h_clk",
1395 .ops
= &clk_branch_ops
,
1400 static const struct freq_tbl clk_tbl_tsif_ref
[] = {
1401 { 105000, P_PXO
, 1, 1, 256 },
1405 static struct clk_rcg tsif_ref_src
= {
1410 .mnctr_reset_bit
= 7,
1411 .mnctr_mode_shift
= 5,
1422 .parent_map
= gcc_pxo_pll8_map
,
1424 .freq_tbl
= clk_tbl_tsif_ref
,
1426 .enable_reg
= 0x2710,
1427 .enable_mask
= BIT(11),
1428 .hw
.init
= &(struct clk_init_data
){
1429 .name
= "tsif_ref_src",
1430 .parent_names
= gcc_pxo_pll8
,
1432 .ops
= &clk_rcg_ops
,
1437 static struct clk_branch tsif_ref_clk
= {
1441 .enable_reg
= 0x2710,
1442 .enable_mask
= BIT(9),
1443 .hw
.init
= &(struct clk_init_data
){
1444 .name
= "tsif_ref_clk",
1445 .parent_names
= (const char *[]){ "tsif_ref_src" },
1447 .ops
= &clk_branch_ops
,
1448 .flags
= CLK_SET_RATE_PARENT
,
1453 static struct clk_branch tsif_h_clk
= {
1459 .enable_reg
= 0x2700,
1460 .enable_mask
= BIT(4),
1461 .hw
.init
= &(struct clk_init_data
){
1462 .name
= "tsif_h_clk",
1463 .ops
= &clk_branch_ops
,
1468 static struct clk_branch dma_bam_h_clk
= {
1474 .enable_reg
= 0x25c0,
1475 .enable_mask
= BIT(4),
1476 .hw
.init
= &(struct clk_init_data
){
1477 .name
= "dma_bam_h_clk",
1478 .ops
= &clk_branch_ops
,
1483 static struct clk_branch adm0_clk
= {
1485 .halt_check
= BRANCH_HALT_VOTED
,
1488 .enable_reg
= 0x3080,
1489 .enable_mask
= BIT(2),
1490 .hw
.init
= &(struct clk_init_data
){
1492 .ops
= &clk_branch_ops
,
1497 static struct clk_branch adm0_pbus_clk
= {
1501 .halt_check
= BRANCH_HALT_VOTED
,
1504 .enable_reg
= 0x3080,
1505 .enable_mask
= BIT(3),
1506 .hw
.init
= &(struct clk_init_data
){
1507 .name
= "adm0_pbus_clk",
1508 .ops
= &clk_branch_ops
,
1513 static struct clk_branch pmic_arb0_h_clk
= {
1515 .halt_check
= BRANCH_HALT_VOTED
,
1518 .enable_reg
= 0x3080,
1519 .enable_mask
= BIT(8),
1520 .hw
.init
= &(struct clk_init_data
){
1521 .name
= "pmic_arb0_h_clk",
1522 .ops
= &clk_branch_ops
,
1527 static struct clk_branch pmic_arb1_h_clk
= {
1529 .halt_check
= BRANCH_HALT_VOTED
,
1532 .enable_reg
= 0x3080,
1533 .enable_mask
= BIT(9),
1534 .hw
.init
= &(struct clk_init_data
){
1535 .name
= "pmic_arb1_h_clk",
1536 .ops
= &clk_branch_ops
,
1541 static struct clk_branch pmic_ssbi2_clk
= {
1543 .halt_check
= BRANCH_HALT_VOTED
,
1546 .enable_reg
= 0x3080,
1547 .enable_mask
= BIT(7),
1548 .hw
.init
= &(struct clk_init_data
){
1549 .name
= "pmic_ssbi2_clk",
1550 .ops
= &clk_branch_ops
,
1555 static struct clk_branch rpm_msg_ram_h_clk
= {
1559 .halt_check
= BRANCH_HALT_VOTED
,
1562 .enable_reg
= 0x3080,
1563 .enable_mask
= BIT(6),
1564 .hw
.init
= &(struct clk_init_data
){
1565 .name
= "rpm_msg_ram_h_clk",
1566 .ops
= &clk_branch_ops
,
1571 static const struct freq_tbl clk_tbl_pcie_ref
[] = {
1572 { 100000000, P_PLL3
, 12, 0, 0 },
1576 static struct clk_rcg pcie_ref_src
= {
1584 .parent_map
= gcc_pxo_pll3_map
,
1586 .freq_tbl
= clk_tbl_pcie_ref
,
1588 .enable_reg
= 0x3860,
1589 .enable_mask
= BIT(11),
1590 .hw
.init
= &(struct clk_init_data
){
1591 .name
= "pcie_ref_src",
1592 .parent_names
= gcc_pxo_pll3
,
1594 .ops
= &clk_rcg_ops
,
1595 .flags
= CLK_SET_RATE_GATE
,
1600 static struct clk_branch pcie_ref_src_clk
= {
1604 .enable_reg
= 0x3860,
1605 .enable_mask
= BIT(9),
1606 .hw
.init
= &(struct clk_init_data
){
1607 .name
= "pcie_ref_src_clk",
1608 .parent_names
= (const char *[]){ "pcie_ref_src" },
1610 .ops
= &clk_branch_ops
,
1611 .flags
= CLK_SET_RATE_PARENT
,
1616 static struct clk_branch pcie_a_clk
= {
1620 .enable_reg
= 0x22c0,
1621 .enable_mask
= BIT(4),
1622 .hw
.init
= &(struct clk_init_data
){
1623 .name
= "pcie_a_clk",
1624 .ops
= &clk_branch_ops
,
1629 static struct clk_branch pcie_aux_clk
= {
1633 .enable_reg
= 0x22c8,
1634 .enable_mask
= BIT(4),
1635 .hw
.init
= &(struct clk_init_data
){
1636 .name
= "pcie_aux_clk",
1637 .ops
= &clk_branch_ops
,
1642 static struct clk_branch pcie_h_clk
= {
1646 .enable_reg
= 0x22cc,
1647 .enable_mask
= BIT(4),
1648 .hw
.init
= &(struct clk_init_data
){
1649 .name
= "pcie_h_clk",
1650 .ops
= &clk_branch_ops
,
1655 static struct clk_branch pcie_phy_clk
= {
1659 .enable_reg
= 0x22d0,
1660 .enable_mask
= BIT(4),
1661 .hw
.init
= &(struct clk_init_data
){
1662 .name
= "pcie_phy_clk",
1663 .ops
= &clk_branch_ops
,
1668 static struct clk_rcg pcie1_ref_src
= {
1676 .parent_map
= gcc_pxo_pll3_map
,
1678 .freq_tbl
= clk_tbl_pcie_ref
,
1680 .enable_reg
= 0x3aa0,
1681 .enable_mask
= BIT(11),
1682 .hw
.init
= &(struct clk_init_data
){
1683 .name
= "pcie1_ref_src",
1684 .parent_names
= gcc_pxo_pll3
,
1686 .ops
= &clk_rcg_ops
,
1687 .flags
= CLK_SET_RATE_GATE
,
1692 static struct clk_branch pcie1_ref_src_clk
= {
1696 .enable_reg
= 0x3aa0,
1697 .enable_mask
= BIT(9),
1698 .hw
.init
= &(struct clk_init_data
){
1699 .name
= "pcie1_ref_src_clk",
1700 .parent_names
= (const char *[]){ "pcie1_ref_src" },
1702 .ops
= &clk_branch_ops
,
1703 .flags
= CLK_SET_RATE_PARENT
,
1708 static struct clk_branch pcie1_a_clk
= {
1712 .enable_reg
= 0x3a80,
1713 .enable_mask
= BIT(4),
1714 .hw
.init
= &(struct clk_init_data
){
1715 .name
= "pcie1_a_clk",
1716 .ops
= &clk_branch_ops
,
1721 static struct clk_branch pcie1_aux_clk
= {
1725 .enable_reg
= 0x3a88,
1726 .enable_mask
= BIT(4),
1727 .hw
.init
= &(struct clk_init_data
){
1728 .name
= "pcie1_aux_clk",
1729 .ops
= &clk_branch_ops
,
1734 static struct clk_branch pcie1_h_clk
= {
1738 .enable_reg
= 0x3a8c,
1739 .enable_mask
= BIT(4),
1740 .hw
.init
= &(struct clk_init_data
){
1741 .name
= "pcie1_h_clk",
1742 .ops
= &clk_branch_ops
,
1747 static struct clk_branch pcie1_phy_clk
= {
1751 .enable_reg
= 0x3a90,
1752 .enable_mask
= BIT(4),
1753 .hw
.init
= &(struct clk_init_data
){
1754 .name
= "pcie1_phy_clk",
1755 .ops
= &clk_branch_ops
,
1760 static struct clk_rcg pcie2_ref_src
= {
1768 .parent_map
= gcc_pxo_pll3_map
,
1770 .freq_tbl
= clk_tbl_pcie_ref
,
1772 .enable_reg
= 0x3ae0,
1773 .enable_mask
= BIT(11),
1774 .hw
.init
= &(struct clk_init_data
){
1775 .name
= "pcie2_ref_src",
1776 .parent_names
= gcc_pxo_pll3
,
1778 .ops
= &clk_rcg_ops
,
1779 .flags
= CLK_SET_RATE_GATE
,
1784 static struct clk_branch pcie2_ref_src_clk
= {
1788 .enable_reg
= 0x3ae0,
1789 .enable_mask
= BIT(9),
1790 .hw
.init
= &(struct clk_init_data
){
1791 .name
= "pcie2_ref_src_clk",
1792 .parent_names
= (const char *[]){ "pcie2_ref_src" },
1794 .ops
= &clk_branch_ops
,
1795 .flags
= CLK_SET_RATE_PARENT
,
1800 static struct clk_branch pcie2_a_clk
= {
1804 .enable_reg
= 0x3ac0,
1805 .enable_mask
= BIT(4),
1806 .hw
.init
= &(struct clk_init_data
){
1807 .name
= "pcie2_a_clk",
1808 .ops
= &clk_branch_ops
,
1813 static struct clk_branch pcie2_aux_clk
= {
1817 .enable_reg
= 0x3ac8,
1818 .enable_mask
= BIT(4),
1819 .hw
.init
= &(struct clk_init_data
){
1820 .name
= "pcie2_aux_clk",
1821 .ops
= &clk_branch_ops
,
1826 static struct clk_branch pcie2_h_clk
= {
1830 .enable_reg
= 0x3acc,
1831 .enable_mask
= BIT(4),
1832 .hw
.init
= &(struct clk_init_data
){
1833 .name
= "pcie2_h_clk",
1834 .ops
= &clk_branch_ops
,
1839 static struct clk_branch pcie2_phy_clk
= {
1843 .enable_reg
= 0x3ad0,
1844 .enable_mask
= BIT(4),
1845 .hw
.init
= &(struct clk_init_data
){
1846 .name
= "pcie2_phy_clk",
1847 .ops
= &clk_branch_ops
,
1852 static const struct freq_tbl clk_tbl_sata_ref
[] = {
1853 { 100000000, P_PLL3
, 12, 0, 0 },
1857 static struct clk_rcg sata_ref_src
= {
1865 .parent_map
= gcc_pxo_pll3_sata_map
,
1867 .freq_tbl
= clk_tbl_sata_ref
,
1869 .enable_reg
= 0x2c08,
1870 .enable_mask
= BIT(7),
1871 .hw
.init
= &(struct clk_init_data
){
1872 .name
= "sata_ref_src",
1873 .parent_names
= gcc_pxo_pll3
,
1875 .ops
= &clk_rcg_ops
,
1876 .flags
= CLK_SET_RATE_GATE
,
1881 static struct clk_branch sata_rxoob_clk
= {
1885 .enable_reg
= 0x2c0c,
1886 .enable_mask
= BIT(4),
1887 .hw
.init
= &(struct clk_init_data
){
1888 .name
= "sata_rxoob_clk",
1889 .parent_names
= (const char *[]){ "sata_ref_src" },
1891 .ops
= &clk_branch_ops
,
1892 .flags
= CLK_SET_RATE_PARENT
,
1897 static struct clk_branch sata_pmalive_clk
= {
1901 .enable_reg
= 0x2c10,
1902 .enable_mask
= BIT(4),
1903 .hw
.init
= &(struct clk_init_data
){
1904 .name
= "sata_pmalive_clk",
1905 .parent_names
= (const char *[]){ "sata_ref_src" },
1907 .ops
= &clk_branch_ops
,
1908 .flags
= CLK_SET_RATE_PARENT
,
1913 static struct clk_branch sata_phy_ref_clk
= {
1917 .enable_reg
= 0x2c14,
1918 .enable_mask
= BIT(4),
1919 .hw
.init
= &(struct clk_init_data
){
1920 .name
= "sata_phy_ref_clk",
1921 .parent_names
= (const char *[]){ "pxo" },
1923 .ops
= &clk_branch_ops
,
1928 static struct clk_branch sata_a_clk
= {
1932 .enable_reg
= 0x2c20,
1933 .enable_mask
= BIT(4),
1934 .hw
.init
= &(struct clk_init_data
){
1935 .name
= "sata_a_clk",
1936 .ops
= &clk_branch_ops
,
1941 static struct clk_branch sata_h_clk
= {
1945 .enable_reg
= 0x2c00,
1946 .enable_mask
= BIT(4),
1947 .hw
.init
= &(struct clk_init_data
){
1948 .name
= "sata_h_clk",
1949 .ops
= &clk_branch_ops
,
1954 static struct clk_branch sfab_sata_s_h_clk
= {
1958 .enable_reg
= 0x2480,
1959 .enable_mask
= BIT(4),
1960 .hw
.init
= &(struct clk_init_data
){
1961 .name
= "sfab_sata_s_h_clk",
1962 .ops
= &clk_branch_ops
,
1967 static struct clk_branch sata_phy_cfg_clk
= {
1971 .enable_reg
= 0x2c40,
1972 .enable_mask
= BIT(4),
1973 .hw
.init
= &(struct clk_init_data
){
1974 .name
= "sata_phy_cfg_clk",
1975 .ops
= &clk_branch_ops
,
1980 static const struct freq_tbl clk_tbl_usb30_master
[] = {
1981 { 125000000, P_PLL0
, 1, 5, 32 },
1985 static struct clk_rcg usb30_master_clk_src
= {
1990 .mnctr_reset_bit
= 7,
1991 .mnctr_mode_shift
= 5,
2002 .parent_map
= gcc_pxo_pll8_pll0
,
2004 .freq_tbl
= clk_tbl_usb30_master
,
2006 .enable_reg
= 0x3b2c,
2007 .enable_mask
= BIT(11),
2008 .hw
.init
= &(struct clk_init_data
){
2009 .name
= "usb30_master_ref_src",
2010 .parent_names
= gcc_pxo_pll8_pll0_map
,
2012 .ops
= &clk_rcg_ops
,
2013 .flags
= CLK_SET_RATE_GATE
,
2018 static struct clk_branch usb30_0_branch_clk
= {
2022 .enable_reg
= 0x3b24,
2023 .enable_mask
= BIT(4),
2024 .hw
.init
= &(struct clk_init_data
){
2025 .name
= "usb30_0_branch_clk",
2026 .parent_names
= (const char *[]){ "usb30_master_ref_src", },
2028 .ops
= &clk_branch_ops
,
2029 .flags
= CLK_SET_RATE_PARENT
,
2034 static struct clk_branch usb30_1_branch_clk
= {
2038 .enable_reg
= 0x3b34,
2039 .enable_mask
= BIT(4),
2040 .hw
.init
= &(struct clk_init_data
){
2041 .name
= "usb30_1_branch_clk",
2042 .parent_names
= (const char *[]){ "usb30_master_ref_src", },
2044 .ops
= &clk_branch_ops
,
2045 .flags
= CLK_SET_RATE_PARENT
,
2050 static const struct freq_tbl clk_tbl_usb30_utmi
[] = {
2051 { 60000000, P_PLL8
, 1, 5, 32 },
2055 static struct clk_rcg usb30_utmi_clk
= {
2060 .mnctr_reset_bit
= 7,
2061 .mnctr_mode_shift
= 5,
2072 .parent_map
= gcc_pxo_pll8_pll0
,
2074 .freq_tbl
= clk_tbl_usb30_utmi
,
2076 .enable_reg
= 0x3b44,
2077 .enable_mask
= BIT(11),
2078 .hw
.init
= &(struct clk_init_data
){
2079 .name
= "usb30_utmi_clk",
2080 .parent_names
= gcc_pxo_pll8_pll0_map
,
2082 .ops
= &clk_rcg_ops
,
2083 .flags
= CLK_SET_RATE_GATE
,
2088 static struct clk_branch usb30_0_utmi_clk_ctl
= {
2092 .enable_reg
= 0x3b48,
2093 .enable_mask
= BIT(4),
2094 .hw
.init
= &(struct clk_init_data
){
2095 .name
= "usb30_0_utmi_clk_ctl",
2096 .parent_names
= (const char *[]){ "usb30_utmi_clk", },
2098 .ops
= &clk_branch_ops
,
2099 .flags
= CLK_SET_RATE_PARENT
,
2104 static struct clk_branch usb30_1_utmi_clk_ctl
= {
2108 .enable_reg
= 0x3b4c,
2109 .enable_mask
= BIT(4),
2110 .hw
.init
= &(struct clk_init_data
){
2111 .name
= "usb30_1_utmi_clk_ctl",
2112 .parent_names
= (const char *[]){ "usb30_utmi_clk", },
2114 .ops
= &clk_branch_ops
,
2115 .flags
= CLK_SET_RATE_PARENT
,
2120 static const struct freq_tbl clk_tbl_usb
[] = {
2121 { 60000000, P_PLL8
, 1, 5, 32 },
2125 static struct clk_rcg usb_hs1_xcvr_clk_src
= {
2130 .mnctr_reset_bit
= 7,
2131 .mnctr_mode_shift
= 5,
2142 .parent_map
= gcc_pxo_pll8_pll0
,
2144 .freq_tbl
= clk_tbl_usb
,
2146 .enable_reg
= 0x2968,
2147 .enable_mask
= BIT(11),
2148 .hw
.init
= &(struct clk_init_data
){
2149 .name
= "usb_hs1_xcvr_src",
2150 .parent_names
= gcc_pxo_pll8_pll0_map
,
2152 .ops
= &clk_rcg_ops
,
2153 .flags
= CLK_SET_RATE_GATE
,
2158 static struct clk_branch usb_hs1_xcvr_clk
= {
2162 .enable_reg
= 0x290c,
2163 .enable_mask
= BIT(9),
2164 .hw
.init
= &(struct clk_init_data
){
2165 .name
= "usb_hs1_xcvr_clk",
2166 .parent_names
= (const char *[]){ "usb_hs1_xcvr_src" },
2168 .ops
= &clk_branch_ops
,
2169 .flags
= CLK_SET_RATE_PARENT
,
2174 static struct clk_branch usb_hs1_h_clk
= {
2180 .enable_reg
= 0x2900,
2181 .enable_mask
= BIT(4),
2182 .hw
.init
= &(struct clk_init_data
){
2183 .name
= "usb_hs1_h_clk",
2184 .ops
= &clk_branch_ops
,
2189 static struct clk_rcg usb_fs1_xcvr_clk_src
= {
2194 .mnctr_reset_bit
= 7,
2195 .mnctr_mode_shift
= 5,
2206 .parent_map
= gcc_pxo_pll8_pll0
,
2208 .freq_tbl
= clk_tbl_usb
,
2210 .enable_reg
= 0x2968,
2211 .enable_mask
= BIT(11),
2212 .hw
.init
= &(struct clk_init_data
){
2213 .name
= "usb_fs1_xcvr_src",
2214 .parent_names
= gcc_pxo_pll8_pll0_map
,
2216 .ops
= &clk_rcg_ops
,
2217 .flags
= CLK_SET_RATE_GATE
,
2222 static struct clk_branch usb_fs1_xcvr_clk
= {
2226 .enable_reg
= 0x2968,
2227 .enable_mask
= BIT(9),
2228 .hw
.init
= &(struct clk_init_data
){
2229 .name
= "usb_fs1_xcvr_clk",
2230 .parent_names
= (const char *[]){ "usb_fs1_xcvr_src", },
2232 .ops
= &clk_branch_ops
,
2233 .flags
= CLK_SET_RATE_PARENT
,
2238 static struct clk_branch usb_fs1_sys_clk
= {
2242 .enable_reg
= 0x296c,
2243 .enable_mask
= BIT(4),
2244 .hw
.init
= &(struct clk_init_data
){
2245 .name
= "usb_fs1_sys_clk",
2246 .parent_names
= (const char *[]){ "usb_fs1_xcvr_src", },
2248 .ops
= &clk_branch_ops
,
2249 .flags
= CLK_SET_RATE_PARENT
,
2254 static struct clk_branch usb_fs1_h_clk
= {
2258 .enable_reg
= 0x2960,
2259 .enable_mask
= BIT(4),
2260 .hw
.init
= &(struct clk_init_data
){
2261 .name
= "usb_fs1_h_clk",
2262 .ops
= &clk_branch_ops
,
2267 static struct clk_branch ebi2_clk
= {
2273 .enable_reg
= 0x3b00,
2274 .enable_mask
= BIT(4),
2275 .hw
.init
= &(struct clk_init_data
){
2277 .ops
= &clk_branch_ops
,
2282 static struct clk_branch ebi2_aon_clk
= {
2286 .enable_reg
= 0x3b00,
2287 .enable_mask
= BIT(8),
2288 .hw
.init
= &(struct clk_init_data
){
2289 .name
= "ebi2_always_on_clk",
2290 .ops
= &clk_branch_ops
,
2295 static const struct freq_tbl clk_tbl_gmac
[] = {
2296 { 133000000, P_PLL0
, 1, 50, 301 },
2297 { 266000000, P_PLL0
, 1, 127, 382 },
2301 static struct clk_dyn_rcg gmac_core1_src
= {
2302 .ns_reg
[0] = 0x3cac,
2303 .ns_reg
[1] = 0x3cb0,
2304 .md_reg
[0] = 0x3ca4,
2305 .md_reg
[1] = 0x3ca8,
2309 .mnctr_reset_bit
= 7,
2310 .mnctr_mode_shift
= 5,
2317 .mnctr_reset_bit
= 7,
2318 .mnctr_mode_shift
= 5,
2325 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2329 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2340 .freq_tbl
= clk_tbl_gmac
,
2342 .enable_reg
= 0x3ca0,
2343 .enable_mask
= BIT(1),
2344 .hw
.init
= &(struct clk_init_data
){
2345 .name
= "gmac_core1_src",
2346 .parent_names
= gcc_pxo_pll8_pll14_pll18_pll0
,
2348 .ops
= &clk_dyn_rcg_ops
,
2353 static struct clk_branch gmac_core1_clk
= {
2359 .enable_reg
= 0x3cb4,
2360 .enable_mask
= BIT(4),
2361 .hw
.init
= &(struct clk_init_data
){
2362 .name
= "gmac_core1_clk",
2363 .parent_names
= (const char *[]){
2367 .ops
= &clk_branch_ops
,
2368 .flags
= CLK_SET_RATE_PARENT
,
2373 static struct clk_dyn_rcg gmac_core2_src
= {
2374 .ns_reg
[0] = 0x3ccc,
2375 .ns_reg
[1] = 0x3cd0,
2376 .md_reg
[0] = 0x3cc4,
2377 .md_reg
[1] = 0x3cc8,
2381 .mnctr_reset_bit
= 7,
2382 .mnctr_mode_shift
= 5,
2389 .mnctr_reset_bit
= 7,
2390 .mnctr_mode_shift
= 5,
2397 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2401 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2412 .freq_tbl
= clk_tbl_gmac
,
2414 .enable_reg
= 0x3cc0,
2415 .enable_mask
= BIT(1),
2416 .hw
.init
= &(struct clk_init_data
){
2417 .name
= "gmac_core2_src",
2418 .parent_names
= gcc_pxo_pll8_pll14_pll18_pll0
,
2420 .ops
= &clk_dyn_rcg_ops
,
2425 static struct clk_branch gmac_core2_clk
= {
2431 .enable_reg
= 0x3cd4,
2432 .enable_mask
= BIT(4),
2433 .hw
.init
= &(struct clk_init_data
){
2434 .name
= "gmac_core2_clk",
2435 .parent_names
= (const char *[]){
2439 .ops
= &clk_branch_ops
,
2440 .flags
= CLK_SET_RATE_PARENT
,
2445 static struct clk_dyn_rcg gmac_core3_src
= {
2446 .ns_reg
[0] = 0x3cec,
2447 .ns_reg
[1] = 0x3cf0,
2448 .md_reg
[0] = 0x3ce4,
2449 .md_reg
[1] = 0x3ce8,
2453 .mnctr_reset_bit
= 7,
2454 .mnctr_mode_shift
= 5,
2461 .mnctr_reset_bit
= 7,
2462 .mnctr_mode_shift
= 5,
2469 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2473 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2484 .freq_tbl
= clk_tbl_gmac
,
2486 .enable_reg
= 0x3ce0,
2487 .enable_mask
= BIT(1),
2488 .hw
.init
= &(struct clk_init_data
){
2489 .name
= "gmac_core3_src",
2490 .parent_names
= gcc_pxo_pll8_pll14_pll18_pll0
,
2492 .ops
= &clk_dyn_rcg_ops
,
2497 static struct clk_branch gmac_core3_clk
= {
2503 .enable_reg
= 0x3cf4,
2504 .enable_mask
= BIT(4),
2505 .hw
.init
= &(struct clk_init_data
){
2506 .name
= "gmac_core3_clk",
2507 .parent_names
= (const char *[]){
2511 .ops
= &clk_branch_ops
,
2512 .flags
= CLK_SET_RATE_PARENT
,
2517 static struct clk_dyn_rcg gmac_core4_src
= {
2518 .ns_reg
[0] = 0x3d0c,
2519 .ns_reg
[1] = 0x3d10,
2520 .md_reg
[0] = 0x3d04,
2521 .md_reg
[1] = 0x3d08,
2525 .mnctr_reset_bit
= 7,
2526 .mnctr_mode_shift
= 5,
2533 .mnctr_reset_bit
= 7,
2534 .mnctr_mode_shift
= 5,
2541 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2545 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2556 .freq_tbl
= clk_tbl_gmac
,
2558 .enable_reg
= 0x3d00,
2559 .enable_mask
= BIT(1),
2560 .hw
.init
= &(struct clk_init_data
){
2561 .name
= "gmac_core4_src",
2562 .parent_names
= gcc_pxo_pll8_pll14_pll18_pll0
,
2564 .ops
= &clk_dyn_rcg_ops
,
2569 static struct clk_branch gmac_core4_clk
= {
2575 .enable_reg
= 0x3d14,
2576 .enable_mask
= BIT(4),
2577 .hw
.init
= &(struct clk_init_data
){
2578 .name
= "gmac_core4_clk",
2579 .parent_names
= (const char *[]){
2583 .ops
= &clk_branch_ops
,
2584 .flags
= CLK_SET_RATE_PARENT
,
2589 static const struct freq_tbl clk_tbl_nss_tcm
[] = {
2590 { 266000000, P_PLL0
, 3, 0, 0 },
2591 { 400000000, P_PLL0
, 2, 0, 0 },
2595 static struct clk_dyn_rcg nss_tcm_src
= {
2596 .ns_reg
[0] = 0x3dc4,
2597 .ns_reg
[1] = 0x3dc8,
2601 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2605 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2616 .freq_tbl
= clk_tbl_nss_tcm
,
2618 .enable_reg
= 0x3dc0,
2619 .enable_mask
= BIT(1),
2620 .hw
.init
= &(struct clk_init_data
){
2621 .name
= "nss_tcm_src",
2622 .parent_names
= gcc_pxo_pll8_pll14_pll18_pll0
,
2624 .ops
= &clk_dyn_rcg_ops
,
2629 static struct clk_branch nss_tcm_clk
= {
2633 .enable_reg
= 0x3dd0,
2634 .enable_mask
= BIT(6) | BIT(4),
2635 .hw
.init
= &(struct clk_init_data
){
2636 .name
= "nss_tcm_clk",
2637 .parent_names
= (const char *[]){
2641 .ops
= &clk_branch_ops
,
2642 .flags
= CLK_SET_RATE_PARENT
,
2647 static const struct freq_tbl clk_tbl_nss
[] = {
2648 { 110000000, P_PLL18
, 1, 1, 5 },
2649 { 275000000, P_PLL18
, 2, 0, 0 },
2650 { 550000000, P_PLL18
, 1, 0, 0 },
2651 { 733000000, P_PLL18
, 1, 0, 0 },
2655 static struct clk_dyn_rcg ubi32_core1_src_clk
= {
2656 .ns_reg
[0] = 0x3d2c,
2657 .ns_reg
[1] = 0x3d30,
2658 .md_reg
[0] = 0x3d24,
2659 .md_reg
[1] = 0x3d28,
2663 .mnctr_reset_bit
= 7,
2664 .mnctr_mode_shift
= 5,
2671 .mnctr_reset_bit
= 7,
2672 .mnctr_mode_shift
= 5,
2679 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2683 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2694 .freq_tbl
= clk_tbl_nss
,
2696 .enable_reg
= 0x3d20,
2697 .enable_mask
= BIT(1),
2698 .hw
.init
= &(struct clk_init_data
){
2699 .name
= "ubi32_core1_src_clk",
2700 .parent_names
= gcc_pxo_pll8_pll14_pll18_pll0
,
2702 .ops
= &clk_dyn_rcg_ops
,
2703 .flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
,
2708 static struct clk_dyn_rcg ubi32_core2_src_clk
= {
2709 .ns_reg
[0] = 0x3d4c,
2710 .ns_reg
[1] = 0x3d50,
2711 .md_reg
[0] = 0x3d44,
2712 .md_reg
[1] = 0x3d48,
2716 .mnctr_reset_bit
= 7,
2717 .mnctr_mode_shift
= 5,
2724 .mnctr_reset_bit
= 7,
2725 .mnctr_mode_shift
= 5,
2732 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2736 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2747 .freq_tbl
= clk_tbl_nss
,
2749 .enable_reg
= 0x3d40,
2750 .enable_mask
= BIT(1),
2751 .hw
.init
= &(struct clk_init_data
){
2752 .name
= "ubi32_core2_src_clk",
2753 .parent_names
= gcc_pxo_pll8_pll14_pll18_pll0
,
2755 .ops
= &clk_dyn_rcg_ops
,
2756 .flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
,
2761 static struct clk_regmap
*gcc_ipq806x_clks
[] = {
2762 [PLL0
] = &pll0
.clkr
,
2763 [PLL0_VOTE
] = &pll0_vote
,
2764 [PLL3
] = &pll3
.clkr
,
2765 [PLL4_VOTE
] = &pll4_vote
,
2766 [PLL8
] = &pll8
.clkr
,
2767 [PLL8_VOTE
] = &pll8_vote
,
2768 [PLL14
] = &pll14
.clkr
,
2769 [PLL14_VOTE
] = &pll14_vote
,
2770 [PLL18
] = &pll18
.clkr
,
2771 [GSBI1_UART_SRC
] = &gsbi1_uart_src
.clkr
,
2772 [GSBI1_UART_CLK
] = &gsbi1_uart_clk
.clkr
,
2773 [GSBI2_UART_SRC
] = &gsbi2_uart_src
.clkr
,
2774 [GSBI2_UART_CLK
] = &gsbi2_uart_clk
.clkr
,
2775 [GSBI4_UART_SRC
] = &gsbi4_uart_src
.clkr
,
2776 [GSBI4_UART_CLK
] = &gsbi4_uart_clk
.clkr
,
2777 [GSBI5_UART_SRC
] = &gsbi5_uart_src
.clkr
,
2778 [GSBI5_UART_CLK
] = &gsbi5_uart_clk
.clkr
,
2779 [GSBI6_UART_SRC
] = &gsbi6_uart_src
.clkr
,
2780 [GSBI6_UART_CLK
] = &gsbi6_uart_clk
.clkr
,
2781 [GSBI7_UART_SRC
] = &gsbi7_uart_src
.clkr
,
2782 [GSBI7_UART_CLK
] = &gsbi7_uart_clk
.clkr
,
2783 [GSBI1_QUP_SRC
] = &gsbi1_qup_src
.clkr
,
2784 [GSBI1_QUP_CLK
] = &gsbi1_qup_clk
.clkr
,
2785 [GSBI2_QUP_SRC
] = &gsbi2_qup_src
.clkr
,
2786 [GSBI2_QUP_CLK
] = &gsbi2_qup_clk
.clkr
,
2787 [GSBI4_QUP_SRC
] = &gsbi4_qup_src
.clkr
,
2788 [GSBI4_QUP_CLK
] = &gsbi4_qup_clk
.clkr
,
2789 [GSBI5_QUP_SRC
] = &gsbi5_qup_src
.clkr
,
2790 [GSBI5_QUP_CLK
] = &gsbi5_qup_clk
.clkr
,
2791 [GSBI6_QUP_SRC
] = &gsbi6_qup_src
.clkr
,
2792 [GSBI6_QUP_CLK
] = &gsbi6_qup_clk
.clkr
,
2793 [GSBI7_QUP_SRC
] = &gsbi7_qup_src
.clkr
,
2794 [GSBI7_QUP_CLK
] = &gsbi7_qup_clk
.clkr
,
2795 [GP0_SRC
] = &gp0_src
.clkr
,
2796 [GP0_CLK
] = &gp0_clk
.clkr
,
2797 [GP1_SRC
] = &gp1_src
.clkr
,
2798 [GP1_CLK
] = &gp1_clk
.clkr
,
2799 [GP2_SRC
] = &gp2_src
.clkr
,
2800 [GP2_CLK
] = &gp2_clk
.clkr
,
2801 [PMEM_A_CLK
] = &pmem_clk
.clkr
,
2802 [PRNG_SRC
] = &prng_src
.clkr
,
2803 [PRNG_CLK
] = &prng_clk
.clkr
,
2804 [SDC1_SRC
] = &sdc1_src
.clkr
,
2805 [SDC1_CLK
] = &sdc1_clk
.clkr
,
2806 [SDC3_SRC
] = &sdc3_src
.clkr
,
2807 [SDC3_CLK
] = &sdc3_clk
.clkr
,
2808 [TSIF_REF_SRC
] = &tsif_ref_src
.clkr
,
2809 [TSIF_REF_CLK
] = &tsif_ref_clk
.clkr
,
2810 [DMA_BAM_H_CLK
] = &dma_bam_h_clk
.clkr
,
2811 [GSBI1_H_CLK
] = &gsbi1_h_clk
.clkr
,
2812 [GSBI2_H_CLK
] = &gsbi2_h_clk
.clkr
,
2813 [GSBI4_H_CLK
] = &gsbi4_h_clk
.clkr
,
2814 [GSBI5_H_CLK
] = &gsbi5_h_clk
.clkr
,
2815 [GSBI6_H_CLK
] = &gsbi6_h_clk
.clkr
,
2816 [GSBI7_H_CLK
] = &gsbi7_h_clk
.clkr
,
2817 [TSIF_H_CLK
] = &tsif_h_clk
.clkr
,
2818 [SDC1_H_CLK
] = &sdc1_h_clk
.clkr
,
2819 [SDC3_H_CLK
] = &sdc3_h_clk
.clkr
,
2820 [ADM0_CLK
] = &adm0_clk
.clkr
,
2821 [ADM0_PBUS_CLK
] = &adm0_pbus_clk
.clkr
,
2822 [PCIE_A_CLK
] = &pcie_a_clk
.clkr
,
2823 [PCIE_AUX_CLK
] = &pcie_aux_clk
.clkr
,
2824 [PCIE_H_CLK
] = &pcie_h_clk
.clkr
,
2825 [PCIE_PHY_CLK
] = &pcie_phy_clk
.clkr
,
2826 [SFAB_SATA_S_H_CLK
] = &sfab_sata_s_h_clk
.clkr
,
2827 [PMIC_ARB0_H_CLK
] = &pmic_arb0_h_clk
.clkr
,
2828 [PMIC_ARB1_H_CLK
] = &pmic_arb1_h_clk
.clkr
,
2829 [PMIC_SSBI2_CLK
] = &pmic_ssbi2_clk
.clkr
,
2830 [RPM_MSG_RAM_H_CLK
] = &rpm_msg_ram_h_clk
.clkr
,
2831 [SATA_H_CLK
] = &sata_h_clk
.clkr
,
2832 [SATA_CLK_SRC
] = &sata_ref_src
.clkr
,
2833 [SATA_RXOOB_CLK
] = &sata_rxoob_clk
.clkr
,
2834 [SATA_PMALIVE_CLK
] = &sata_pmalive_clk
.clkr
,
2835 [SATA_PHY_REF_CLK
] = &sata_phy_ref_clk
.clkr
,
2836 [SATA_A_CLK
] = &sata_a_clk
.clkr
,
2837 [SATA_PHY_CFG_CLK
] = &sata_phy_cfg_clk
.clkr
,
2838 [PCIE_ALT_REF_SRC
] = &pcie_ref_src
.clkr
,
2839 [PCIE_ALT_REF_CLK
] = &pcie_ref_src_clk
.clkr
,
2840 [PCIE_1_A_CLK
] = &pcie1_a_clk
.clkr
,
2841 [PCIE_1_AUX_CLK
] = &pcie1_aux_clk
.clkr
,
2842 [PCIE_1_H_CLK
] = &pcie1_h_clk
.clkr
,
2843 [PCIE_1_PHY_CLK
] = &pcie1_phy_clk
.clkr
,
2844 [PCIE_1_ALT_REF_SRC
] = &pcie1_ref_src
.clkr
,
2845 [PCIE_1_ALT_REF_CLK
] = &pcie1_ref_src_clk
.clkr
,
2846 [PCIE_2_A_CLK
] = &pcie2_a_clk
.clkr
,
2847 [PCIE_2_AUX_CLK
] = &pcie2_aux_clk
.clkr
,
2848 [PCIE_2_H_CLK
] = &pcie2_h_clk
.clkr
,
2849 [PCIE_2_PHY_CLK
] = &pcie2_phy_clk
.clkr
,
2850 [PCIE_2_ALT_REF_SRC
] = &pcie2_ref_src
.clkr
,
2851 [PCIE_2_ALT_REF_CLK
] = &pcie2_ref_src_clk
.clkr
,
2852 [USB30_MASTER_SRC
] = &usb30_master_clk_src
.clkr
,
2853 [USB30_0_MASTER_CLK
] = &usb30_0_branch_clk
.clkr
,
2854 [USB30_1_MASTER_CLK
] = &usb30_1_branch_clk
.clkr
,
2855 [USB30_UTMI_SRC
] = &usb30_utmi_clk
.clkr
,
2856 [USB30_0_UTMI_CLK
] = &usb30_0_utmi_clk_ctl
.clkr
,
2857 [USB30_1_UTMI_CLK
] = &usb30_1_utmi_clk_ctl
.clkr
,
2858 [USB_HS1_H_CLK
] = &usb_hs1_h_clk
.clkr
,
2859 [USB_HS1_XCVR_SRC
] = &usb_hs1_xcvr_clk_src
.clkr
,
2860 [USB_HS1_XCVR_CLK
] = &usb_hs1_xcvr_clk
.clkr
,
2861 [USB_FS1_H_CLK
] = &usb_fs1_h_clk
.clkr
,
2862 [USB_FS1_XCVR_SRC
] = &usb_fs1_xcvr_clk_src
.clkr
,
2863 [USB_FS1_XCVR_CLK
] = &usb_fs1_xcvr_clk
.clkr
,
2864 [USB_FS1_SYSTEM_CLK
] = &usb_fs1_sys_clk
.clkr
,
2865 [EBI2_CLK
] = &ebi2_clk
.clkr
,
2866 [EBI2_AON_CLK
] = &ebi2_aon_clk
.clkr
,
2867 [GMAC_CORE1_CLK_SRC
] = &gmac_core1_src
.clkr
,
2868 [GMAC_CORE1_CLK
] = &gmac_core1_clk
.clkr
,
2869 [GMAC_CORE2_CLK_SRC
] = &gmac_core2_src
.clkr
,
2870 [GMAC_CORE2_CLK
] = &gmac_core2_clk
.clkr
,
2871 [GMAC_CORE3_CLK_SRC
] = &gmac_core3_src
.clkr
,
2872 [GMAC_CORE3_CLK
] = &gmac_core3_clk
.clkr
,
2873 [GMAC_CORE4_CLK_SRC
] = &gmac_core4_src
.clkr
,
2874 [GMAC_CORE4_CLK
] = &gmac_core4_clk
.clkr
,
2875 [UBI32_CORE1_CLK_SRC
] = &ubi32_core1_src_clk
.clkr
,
2876 [UBI32_CORE2_CLK_SRC
] = &ubi32_core2_src_clk
.clkr
,
2877 [NSSTCM_CLK_SRC
] = &nss_tcm_src
.clkr
,
2878 [NSSTCM_CLK
] = &nss_tcm_clk
.clkr
,
2879 [PLL9
] = &hfpll0
.clkr
,
2880 [PLL10
] = &hfpll1
.clkr
,
2881 [PLL12
] = &hfpll_l2
.clkr
,
2884 static const struct qcom_reset_map gcc_ipq806x_resets
[] = {
2885 [QDSS_STM_RESET
] = { 0x2060, 6 },
2886 [AFAB_SMPSS_S_RESET
] = { 0x20b8, 2 },
2887 [AFAB_SMPSS_M1_RESET
] = { 0x20b8, 1 },
2888 [AFAB_SMPSS_M0_RESET
] = { 0x20b8, 0 },
2889 [AFAB_EBI1_CH0_RESET
] = { 0x20c0, 7 },
2890 [AFAB_EBI1_CH1_RESET
] = { 0x20c4, 7 },
2891 [SFAB_ADM0_M0_RESET
] = { 0x21e0, 7 },
2892 [SFAB_ADM0_M1_RESET
] = { 0x21e4, 7 },
2893 [SFAB_ADM0_M2_RESET
] = { 0x21e8, 7 },
2894 [ADM0_C2_RESET
] = { 0x220c, 4 },
2895 [ADM0_C1_RESET
] = { 0x220c, 3 },
2896 [ADM0_C0_RESET
] = { 0x220c, 2 },
2897 [ADM0_PBUS_RESET
] = { 0x220c, 1 },
2898 [ADM0_RESET
] = { 0x220c, 0 },
2899 [QDSS_CLKS_SW_RESET
] = { 0x2260, 5 },
2900 [QDSS_POR_RESET
] = { 0x2260, 4 },
2901 [QDSS_TSCTR_RESET
] = { 0x2260, 3 },
2902 [QDSS_HRESET_RESET
] = { 0x2260, 2 },
2903 [QDSS_AXI_RESET
] = { 0x2260, 1 },
2904 [QDSS_DBG_RESET
] = { 0x2260, 0 },
2905 [SFAB_PCIE_M_RESET
] = { 0x22d8, 1 },
2906 [SFAB_PCIE_S_RESET
] = { 0x22d8, 0 },
2907 [PCIE_EXT_RESET
] = { 0x22dc, 6 },
2908 [PCIE_PHY_RESET
] = { 0x22dc, 5 },
2909 [PCIE_PCI_RESET
] = { 0x22dc, 4 },
2910 [PCIE_POR_RESET
] = { 0x22dc, 3 },
2911 [PCIE_HCLK_RESET
] = { 0x22dc, 2 },
2912 [PCIE_ACLK_RESET
] = { 0x22dc, 0 },
2913 [SFAB_LPASS_RESET
] = { 0x23a0, 7 },
2914 [SFAB_AFAB_M_RESET
] = { 0x23e0, 7 },
2915 [AFAB_SFAB_M0_RESET
] = { 0x2420, 7 },
2916 [AFAB_SFAB_M1_RESET
] = { 0x2424, 7 },
2917 [SFAB_SATA_S_RESET
] = { 0x2480, 7 },
2918 [SFAB_DFAB_M_RESET
] = { 0x2500, 7 },
2919 [DFAB_SFAB_M_RESET
] = { 0x2520, 7 },
2920 [DFAB_SWAY0_RESET
] = { 0x2540, 7 },
2921 [DFAB_SWAY1_RESET
] = { 0x2544, 7 },
2922 [DFAB_ARB0_RESET
] = { 0x2560, 7 },
2923 [DFAB_ARB1_RESET
] = { 0x2564, 7 },
2924 [PPSS_PROC_RESET
] = { 0x2594, 1 },
2925 [PPSS_RESET
] = { 0x2594, 0 },
2926 [DMA_BAM_RESET
] = { 0x25c0, 7 },
2927 [SPS_TIC_H_RESET
] = { 0x2600, 7 },
2928 [SFAB_CFPB_M_RESET
] = { 0x2680, 7 },
2929 [SFAB_CFPB_S_RESET
] = { 0x26c0, 7 },
2930 [TSIF_H_RESET
] = { 0x2700, 7 },
2931 [CE1_H_RESET
] = { 0x2720, 7 },
2932 [CE1_CORE_RESET
] = { 0x2724, 7 },
2933 [CE1_SLEEP_RESET
] = { 0x2728, 7 },
2934 [CE2_H_RESET
] = { 0x2740, 7 },
2935 [CE2_CORE_RESET
] = { 0x2744, 7 },
2936 [SFAB_SFPB_M_RESET
] = { 0x2780, 7 },
2937 [SFAB_SFPB_S_RESET
] = { 0x27a0, 7 },
2938 [RPM_PROC_RESET
] = { 0x27c0, 7 },
2939 [PMIC_SSBI2_RESET
] = { 0x280c, 12 },
2940 [SDC1_RESET
] = { 0x2830, 0 },
2941 [SDC2_RESET
] = { 0x2850, 0 },
2942 [SDC3_RESET
] = { 0x2870, 0 },
2943 [SDC4_RESET
] = { 0x2890, 0 },
2944 [USB_HS1_RESET
] = { 0x2910, 0 },
2945 [USB_HSIC_RESET
] = { 0x2934, 0 },
2946 [USB_FS1_XCVR_RESET
] = { 0x2974, 1 },
2947 [USB_FS1_RESET
] = { 0x2974, 0 },
2948 [GSBI1_RESET
] = { 0x29dc, 0 },
2949 [GSBI2_RESET
] = { 0x29fc, 0 },
2950 [GSBI3_RESET
] = { 0x2a1c, 0 },
2951 [GSBI4_RESET
] = { 0x2a3c, 0 },
2952 [GSBI5_RESET
] = { 0x2a5c, 0 },
2953 [GSBI6_RESET
] = { 0x2a7c, 0 },
2954 [GSBI7_RESET
] = { 0x2a9c, 0 },
2955 [SPDM_RESET
] = { 0x2b6c, 0 },
2956 [SEC_CTRL_RESET
] = { 0x2b80, 7 },
2957 [TLMM_H_RESET
] = { 0x2ba0, 7 },
2958 [SFAB_SATA_M_RESET
] = { 0x2c18, 0 },
2959 [SATA_RESET
] = { 0x2c1c, 0 },
2960 [TSSC_RESET
] = { 0x2ca0, 7 },
2961 [PDM_RESET
] = { 0x2cc0, 12 },
2962 [MPM_H_RESET
] = { 0x2da0, 7 },
2963 [MPM_RESET
] = { 0x2da4, 0 },
2964 [SFAB_SMPSS_S_RESET
] = { 0x2e00, 7 },
2965 [PRNG_RESET
] = { 0x2e80, 12 },
2966 [SFAB_CE3_M_RESET
] = { 0x36c8, 1 },
2967 [SFAB_CE3_S_RESET
] = { 0x36c8, 0 },
2968 [CE3_SLEEP_RESET
] = { 0x36d0, 7 },
2969 [PCIE_1_M_RESET
] = { 0x3a98, 1 },
2970 [PCIE_1_S_RESET
] = { 0x3a98, 0 },
2971 [PCIE_1_EXT_RESET
] = { 0x3a9c, 6 },
2972 [PCIE_1_PHY_RESET
] = { 0x3a9c, 5 },
2973 [PCIE_1_PCI_RESET
] = { 0x3a9c, 4 },
2974 [PCIE_1_POR_RESET
] = { 0x3a9c, 3 },
2975 [PCIE_1_HCLK_RESET
] = { 0x3a9c, 2 },
2976 [PCIE_1_ACLK_RESET
] = { 0x3a9c, 0 },
2977 [PCIE_2_M_RESET
] = { 0x3ad8, 1 },
2978 [PCIE_2_S_RESET
] = { 0x3ad8, 0 },
2979 [PCIE_2_EXT_RESET
] = { 0x3adc, 6 },
2980 [PCIE_2_PHY_RESET
] = { 0x3adc, 5 },
2981 [PCIE_2_PCI_RESET
] = { 0x3adc, 4 },
2982 [PCIE_2_POR_RESET
] = { 0x3adc, 3 },
2983 [PCIE_2_HCLK_RESET
] = { 0x3adc, 2 },
2984 [PCIE_2_ACLK_RESET
] = { 0x3adc, 0 },
2985 [SFAB_USB30_S_RESET
] = { 0x3b54, 1 },
2986 [SFAB_USB30_M_RESET
] = { 0x3b54, 0 },
2987 [USB30_0_PORT2_HS_PHY_RESET
] = { 0x3b50, 5 },
2988 [USB30_0_MASTER_RESET
] = { 0x3b50, 4 },
2989 [USB30_0_SLEEP_RESET
] = { 0x3b50, 3 },
2990 [USB30_0_UTMI_PHY_RESET
] = { 0x3b50, 2 },
2991 [USB30_0_POWERON_RESET
] = { 0x3b50, 1 },
2992 [USB30_0_PHY_RESET
] = { 0x3b50, 0 },
2993 [USB30_1_MASTER_RESET
] = { 0x3b58, 4 },
2994 [USB30_1_SLEEP_RESET
] = { 0x3b58, 3 },
2995 [USB30_1_UTMI_PHY_RESET
] = { 0x3b58, 2 },
2996 [USB30_1_POWERON_RESET
] = { 0x3b58, 1 },
2997 [USB30_1_PHY_RESET
] = { 0x3b58, 0 },
2998 [NSSFB0_RESET
] = { 0x3b60, 6 },
2999 [NSSFB1_RESET
] = { 0x3b60, 7 },
3000 [UBI32_CORE1_CLKRST_CLAMP_RESET
] = { 0x3d3c, 3},
3001 [UBI32_CORE1_CLAMP_RESET
] = { 0x3d3c, 2 },
3002 [UBI32_CORE1_AHB_RESET
] = { 0x3d3c, 1 },
3003 [UBI32_CORE1_AXI_RESET
] = { 0x3d3c, 0 },
3004 [UBI32_CORE2_CLKRST_CLAMP_RESET
] = { 0x3d5c, 3 },
3005 [UBI32_CORE2_CLAMP_RESET
] = { 0x3d5c, 2 },
3006 [UBI32_CORE2_AHB_RESET
] = { 0x3d5c, 1 },
3007 [UBI32_CORE2_AXI_RESET
] = { 0x3d5c, 0 },
3008 [GMAC_CORE1_RESET
] = { 0x3cbc, 0 },
3009 [GMAC_CORE2_RESET
] = { 0x3cdc, 0 },
3010 [GMAC_CORE3_RESET
] = { 0x3cfc, 0 },
3011 [GMAC_CORE4_RESET
] = { 0x3d1c, 0 },
3012 [GMAC_AHB_RESET
] = { 0x3e24, 0 },
3013 [NSS_CH0_RST_RX_CLK_N_RESET
] = { 0x3b60, 0 },
3014 [NSS_CH0_RST_TX_CLK_N_RESET
] = { 0x3b60, 1 },
3015 [NSS_CH0_RST_RX_125M_N_RESET
] = { 0x3b60, 2 },
3016 [NSS_CH0_HW_RST_RX_125M_N_RESET
] = { 0x3b60, 3 },
3017 [NSS_CH0_RST_TX_125M_N_RESET
] = { 0x3b60, 4 },
3018 [NSS_CH1_RST_RX_CLK_N_RESET
] = { 0x3b60, 5 },
3019 [NSS_CH1_RST_TX_CLK_N_RESET
] = { 0x3b60, 6 },
3020 [NSS_CH1_RST_RX_125M_N_RESET
] = { 0x3b60, 7 },
3021 [NSS_CH1_HW_RST_RX_125M_N_RESET
] = { 0x3b60, 8 },
3022 [NSS_CH1_RST_TX_125M_N_RESET
] = { 0x3b60, 9 },
3023 [NSS_CH2_RST_RX_CLK_N_RESET
] = { 0x3b60, 10 },
3024 [NSS_CH2_RST_TX_CLK_N_RESET
] = { 0x3b60, 11 },
3025 [NSS_CH2_RST_RX_125M_N_RESET
] = { 0x3b60, 12 },
3026 [NSS_CH2_HW_RST_RX_125M_N_RESET
] = { 0x3b60, 13 },
3027 [NSS_CH2_RST_TX_125M_N_RESET
] = { 0x3b60, 14 },
3028 [NSS_CH3_RST_RX_CLK_N_RESET
] = { 0x3b60, 15 },
3029 [NSS_CH3_RST_TX_CLK_N_RESET
] = { 0x3b60, 16 },
3030 [NSS_CH3_RST_RX_125M_N_RESET
] = { 0x3b60, 17 },
3031 [NSS_CH3_HW_RST_RX_125M_N_RESET
] = { 0x3b60, 18 },
3032 [NSS_CH3_RST_TX_125M_N_RESET
] = { 0x3b60, 19 },
3033 [NSS_RST_RX_250M_125M_N_RESET
] = { 0x3b60, 20 },
3034 [NSS_RST_TX_250M_125M_N_RESET
] = { 0x3b60, 21 },
3035 [NSS_QSGMII_TXPI_RST_N_RESET
] = { 0x3b60, 22 },
3036 [NSS_QSGMII_CDR_RST_N_RESET
] = { 0x3b60, 23 },
3037 [NSS_SGMII2_CDR_RST_N_RESET
] = { 0x3b60, 24 },
3038 [NSS_SGMII3_CDR_RST_N_RESET
] = { 0x3b60, 25 },
3039 [NSS_CAL_PRBS_RST_N_RESET
] = { 0x3b60, 26 },
3040 [NSS_LCKDT_RST_N_RESET
] = { 0x3b60, 27 },
3041 [NSS_SRDS_N_RESET
] = { 0x3b60, 28 },
3044 static const struct regmap_config gcc_ipq806x_regmap_config
= {
3048 .max_register
= 0x3e40,
3052 static const struct qcom_cc_desc gcc_ipq806x_desc
= {
3053 .config
= &gcc_ipq806x_regmap_config
,
3054 .clks
= gcc_ipq806x_clks
,
3055 .num_clks
= ARRAY_SIZE(gcc_ipq806x_clks
),
3056 .resets
= gcc_ipq806x_resets
,
3057 .num_resets
= ARRAY_SIZE(gcc_ipq806x_resets
),
3060 static const struct of_device_id gcc_ipq806x_match_table
[] = {
3061 { .compatible
= "qcom,gcc-ipq8064" },
3064 MODULE_DEVICE_TABLE(of
, gcc_ipq806x_match_table
);
3066 static int gcc_ipq806x_probe(struct platform_device
*pdev
)
3068 struct device
*dev
= &pdev
->dev
;
3069 struct regmap
*regmap
;
3072 ret
= qcom_cc_register_board_clk(dev
, "cxo_board", "cxo", 25000000);
3076 ret
= qcom_cc_register_board_clk(dev
, "pxo_board", "pxo", 25000000);
3080 ret
= qcom_cc_probe(pdev
, &gcc_ipq806x_desc
);
3084 regmap
= dev_get_regmap(dev
, NULL
);
3088 /* Setup PLL18 static bits */
3089 regmap_update_bits(regmap
, 0x31a4, 0xffffffc0, 0x40000400);
3090 regmap_write(regmap
, 0x31b0, 0x3080);
3092 /* Set GMAC footswitch sleep/wakeup values */
3093 regmap_write(regmap
, 0x3cb8, 8);
3094 regmap_write(regmap
, 0x3cd8, 8);
3095 regmap_write(regmap
, 0x3cf8, 8);
3096 regmap_write(regmap
, 0x3d18, 8);
3101 static struct platform_driver gcc_ipq806x_driver
= {
3102 .probe
= gcc_ipq806x_probe
,
3104 .name
= "gcc-ipq806x",
3105 .of_match_table
= gcc_ipq806x_match_table
,
3109 static int __init
gcc_ipq806x_init(void)
3111 return platform_driver_register(&gcc_ipq806x_driver
);
3113 core_initcall(gcc_ipq806x_init
);
3115 static void __exit
gcc_ipq806x_exit(void)
3117 platform_driver_unregister(&gcc_ipq806x_driver
);
3119 module_exit(gcc_ipq806x_exit
);
3121 MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
3122 MODULE_LICENSE("GPL v2");
3123 MODULE_ALIAS("platform:gcc-ipq806x");