2 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
26 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
35 static struct clk_pll pll0
= {
43 .clkr
.hw
.init
= &(struct clk_init_data
){
45 .parent_names
= (const char *[]){ "pxo" },
51 static struct clk_regmap pll0_vote
= {
53 .enable_mask
= BIT(0),
54 .hw
.init
= &(struct clk_init_data
){
56 .parent_names
= (const char *[]){ "pll0" },
58 .ops
= &clk_pll_vote_ops
,
62 static struct clk_pll pll3
= {
70 .clkr
.hw
.init
= &(struct clk_init_data
){
72 .parent_names
= (const char *[]){ "pxo" },
78 static struct clk_regmap pll4_vote
= {
80 .enable_mask
= BIT(4),
81 .hw
.init
= &(struct clk_init_data
){
83 .parent_names
= (const char *[]){ "pll4" },
85 .ops
= &clk_pll_vote_ops
,
89 static struct clk_pll pll8
= {
97 .clkr
.hw
.init
= &(struct clk_init_data
){
99 .parent_names
= (const char *[]){ "pxo" },
105 static struct clk_regmap pll8_vote
= {
106 .enable_reg
= 0x34c0,
107 .enable_mask
= BIT(8),
108 .hw
.init
= &(struct clk_init_data
){
110 .parent_names
= (const char *[]){ "pll8" },
112 .ops
= &clk_pll_vote_ops
,
116 static struct clk_pll pll14
= {
120 .config_reg
= 0x31d4,
122 .status_reg
= 0x31d8,
124 .clkr
.hw
.init
= &(struct clk_init_data
){
126 .parent_names
= (const char *[]){ "pxo" },
132 static struct clk_regmap pll14_vote
= {
133 .enable_reg
= 0x34c0,
134 .enable_mask
= BIT(14),
135 .hw
.init
= &(struct clk_init_data
){
136 .name
= "pll14_vote",
137 .parent_names
= (const char *[]){ "pll14" },
139 .ops
= &clk_pll_vote_ops
,
143 #define NSS_PLL_RATE(f, _l, _m, _n, i) \
152 static struct pll_freq_tbl pll18_freq_tbl
[] = {
153 NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
154 NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
157 static struct clk_pll pll18
= {
161 .config_reg
= 0x31b4,
163 .status_reg
= 0x31b8,
165 .post_div_shift
= 16,
167 .freq_tbl
= pll18_freq_tbl
,
168 .clkr
.hw
.init
= &(struct clk_init_data
){
170 .parent_names
= (const char *[]){ "pxo" },
186 static const struct parent_map gcc_pxo_pll8_map
[] = {
191 static const char * const gcc_pxo_pll8
[] = {
196 static const struct parent_map gcc_pxo_pll8_cxo_map
[] = {
202 static const char * const gcc_pxo_pll8_cxo
[] = {
208 static const struct parent_map gcc_pxo_pll3_map
[] = {
213 static const struct parent_map gcc_pxo_pll3_sata_map
[] = {
218 static const char * const gcc_pxo_pll3
[] = {
223 static const struct parent_map gcc_pxo_pll8_pll0
[] = {
229 static const char * const gcc_pxo_pll8_pll0_map
[] = {
235 static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map
[] = {
243 static const char * const gcc_pxo_pll8_pll14_pll18_pll0
[] = {
251 static struct freq_tbl clk_tbl_gsbi_uart
[] = {
252 { 1843200, P_PLL8
, 2, 6, 625 },
253 { 3686400, P_PLL8
, 2, 12, 625 },
254 { 7372800, P_PLL8
, 2, 24, 625 },
255 { 14745600, P_PLL8
, 2, 48, 625 },
256 { 16000000, P_PLL8
, 4, 1, 6 },
257 { 24000000, P_PLL8
, 4, 1, 4 },
258 { 32000000, P_PLL8
, 4, 1, 3 },
259 { 40000000, P_PLL8
, 1, 5, 48 },
260 { 46400000, P_PLL8
, 1, 29, 240 },
261 { 48000000, P_PLL8
, 4, 1, 2 },
262 { 51200000, P_PLL8
, 1, 2, 15 },
263 { 56000000, P_PLL8
, 1, 7, 48 },
264 { 58982400, P_PLL8
, 1, 96, 625 },
265 { 64000000, P_PLL8
, 2, 1, 3 },
269 static struct clk_rcg gsbi1_uart_src
= {
274 .mnctr_reset_bit
= 7,
275 .mnctr_mode_shift
= 5,
286 .parent_map
= gcc_pxo_pll8_map
,
288 .freq_tbl
= clk_tbl_gsbi_uart
,
290 .enable_reg
= 0x29d4,
291 .enable_mask
= BIT(11),
292 .hw
.init
= &(struct clk_init_data
){
293 .name
= "gsbi1_uart_src",
294 .parent_names
= gcc_pxo_pll8
,
297 .flags
= CLK_SET_PARENT_GATE
,
302 static struct clk_branch gsbi1_uart_clk
= {
306 .enable_reg
= 0x29d4,
307 .enable_mask
= BIT(9),
308 .hw
.init
= &(struct clk_init_data
){
309 .name
= "gsbi1_uart_clk",
310 .parent_names
= (const char *[]){
314 .ops
= &clk_branch_ops
,
315 .flags
= CLK_SET_RATE_PARENT
,
320 static struct clk_rcg gsbi2_uart_src
= {
325 .mnctr_reset_bit
= 7,
326 .mnctr_mode_shift
= 5,
337 .parent_map
= gcc_pxo_pll8_map
,
339 .freq_tbl
= clk_tbl_gsbi_uart
,
341 .enable_reg
= 0x29f4,
342 .enable_mask
= BIT(11),
343 .hw
.init
= &(struct clk_init_data
){
344 .name
= "gsbi2_uart_src",
345 .parent_names
= gcc_pxo_pll8
,
348 .flags
= CLK_SET_PARENT_GATE
,
353 static struct clk_branch gsbi2_uart_clk
= {
357 .enable_reg
= 0x29f4,
358 .enable_mask
= BIT(9),
359 .hw
.init
= &(struct clk_init_data
){
360 .name
= "gsbi2_uart_clk",
361 .parent_names
= (const char *[]){
365 .ops
= &clk_branch_ops
,
366 .flags
= CLK_SET_RATE_PARENT
,
371 static struct clk_rcg gsbi4_uart_src
= {
376 .mnctr_reset_bit
= 7,
377 .mnctr_mode_shift
= 5,
388 .parent_map
= gcc_pxo_pll8_map
,
390 .freq_tbl
= clk_tbl_gsbi_uart
,
392 .enable_reg
= 0x2a34,
393 .enable_mask
= BIT(11),
394 .hw
.init
= &(struct clk_init_data
){
395 .name
= "gsbi4_uart_src",
396 .parent_names
= gcc_pxo_pll8
,
399 .flags
= CLK_SET_PARENT_GATE
,
404 static struct clk_branch gsbi4_uart_clk
= {
408 .enable_reg
= 0x2a34,
409 .enable_mask
= BIT(9),
410 .hw
.init
= &(struct clk_init_data
){
411 .name
= "gsbi4_uart_clk",
412 .parent_names
= (const char *[]){
416 .ops
= &clk_branch_ops
,
417 .flags
= CLK_SET_RATE_PARENT
,
422 static struct clk_rcg gsbi5_uart_src
= {
427 .mnctr_reset_bit
= 7,
428 .mnctr_mode_shift
= 5,
439 .parent_map
= gcc_pxo_pll8_map
,
441 .freq_tbl
= clk_tbl_gsbi_uart
,
443 .enable_reg
= 0x2a54,
444 .enable_mask
= BIT(11),
445 .hw
.init
= &(struct clk_init_data
){
446 .name
= "gsbi5_uart_src",
447 .parent_names
= gcc_pxo_pll8
,
450 .flags
= CLK_SET_PARENT_GATE
,
455 static struct clk_branch gsbi5_uart_clk
= {
459 .enable_reg
= 0x2a54,
460 .enable_mask
= BIT(9),
461 .hw
.init
= &(struct clk_init_data
){
462 .name
= "gsbi5_uart_clk",
463 .parent_names
= (const char *[]){
467 .ops
= &clk_branch_ops
,
468 .flags
= CLK_SET_RATE_PARENT
,
473 static struct clk_rcg gsbi6_uart_src
= {
478 .mnctr_reset_bit
= 7,
479 .mnctr_mode_shift
= 5,
490 .parent_map
= gcc_pxo_pll8_map
,
492 .freq_tbl
= clk_tbl_gsbi_uart
,
494 .enable_reg
= 0x2a74,
495 .enable_mask
= BIT(11),
496 .hw
.init
= &(struct clk_init_data
){
497 .name
= "gsbi6_uart_src",
498 .parent_names
= gcc_pxo_pll8
,
501 .flags
= CLK_SET_PARENT_GATE
,
506 static struct clk_branch gsbi6_uart_clk
= {
510 .enable_reg
= 0x2a74,
511 .enable_mask
= BIT(9),
512 .hw
.init
= &(struct clk_init_data
){
513 .name
= "gsbi6_uart_clk",
514 .parent_names
= (const char *[]){
518 .ops
= &clk_branch_ops
,
519 .flags
= CLK_SET_RATE_PARENT
,
524 static struct clk_rcg gsbi7_uart_src
= {
529 .mnctr_reset_bit
= 7,
530 .mnctr_mode_shift
= 5,
541 .parent_map
= gcc_pxo_pll8_map
,
543 .freq_tbl
= clk_tbl_gsbi_uart
,
545 .enable_reg
= 0x2a94,
546 .enable_mask
= BIT(11),
547 .hw
.init
= &(struct clk_init_data
){
548 .name
= "gsbi7_uart_src",
549 .parent_names
= gcc_pxo_pll8
,
552 .flags
= CLK_SET_PARENT_GATE
,
557 static struct clk_branch gsbi7_uart_clk
= {
561 .enable_reg
= 0x2a94,
562 .enable_mask
= BIT(9),
563 .hw
.init
= &(struct clk_init_data
){
564 .name
= "gsbi7_uart_clk",
565 .parent_names
= (const char *[]){
569 .ops
= &clk_branch_ops
,
570 .flags
= CLK_SET_RATE_PARENT
,
575 static struct freq_tbl clk_tbl_gsbi_qup
[] = {
576 { 1100000, P_PXO
, 1, 2, 49 },
577 { 5400000, P_PXO
, 1, 1, 5 },
578 { 10800000, P_PXO
, 1, 2, 5 },
579 { 15060000, P_PLL8
, 1, 2, 51 },
580 { 24000000, P_PLL8
, 4, 1, 4 },
581 { 25000000, P_PXO
, 1, 0, 0 },
582 { 25600000, P_PLL8
, 1, 1, 15 },
583 { 48000000, P_PLL8
, 4, 1, 2 },
584 { 51200000, P_PLL8
, 1, 2, 15 },
588 static struct clk_rcg gsbi1_qup_src
= {
593 .mnctr_reset_bit
= 7,
594 .mnctr_mode_shift
= 5,
605 .parent_map
= gcc_pxo_pll8_map
,
607 .freq_tbl
= clk_tbl_gsbi_qup
,
609 .enable_reg
= 0x29cc,
610 .enable_mask
= BIT(11),
611 .hw
.init
= &(struct clk_init_data
){
612 .name
= "gsbi1_qup_src",
613 .parent_names
= gcc_pxo_pll8
,
616 .flags
= CLK_SET_PARENT_GATE
,
621 static struct clk_branch gsbi1_qup_clk
= {
625 .enable_reg
= 0x29cc,
626 .enable_mask
= BIT(9),
627 .hw
.init
= &(struct clk_init_data
){
628 .name
= "gsbi1_qup_clk",
629 .parent_names
= (const char *[]){ "gsbi1_qup_src" },
631 .ops
= &clk_branch_ops
,
632 .flags
= CLK_SET_RATE_PARENT
,
637 static struct clk_rcg gsbi2_qup_src
= {
642 .mnctr_reset_bit
= 7,
643 .mnctr_mode_shift
= 5,
654 .parent_map
= gcc_pxo_pll8_map
,
656 .freq_tbl
= clk_tbl_gsbi_qup
,
658 .enable_reg
= 0x29ec,
659 .enable_mask
= BIT(11),
660 .hw
.init
= &(struct clk_init_data
){
661 .name
= "gsbi2_qup_src",
662 .parent_names
= gcc_pxo_pll8
,
665 .flags
= CLK_SET_PARENT_GATE
,
670 static struct clk_branch gsbi2_qup_clk
= {
674 .enable_reg
= 0x29ec,
675 .enable_mask
= BIT(9),
676 .hw
.init
= &(struct clk_init_data
){
677 .name
= "gsbi2_qup_clk",
678 .parent_names
= (const char *[]){ "gsbi2_qup_src" },
680 .ops
= &clk_branch_ops
,
681 .flags
= CLK_SET_RATE_PARENT
,
686 static struct clk_rcg gsbi4_qup_src
= {
691 .mnctr_reset_bit
= 7,
692 .mnctr_mode_shift
= 5,
703 .parent_map
= gcc_pxo_pll8_map
,
705 .freq_tbl
= clk_tbl_gsbi_qup
,
707 .enable_reg
= 0x2a2c,
708 .enable_mask
= BIT(11),
709 .hw
.init
= &(struct clk_init_data
){
710 .name
= "gsbi4_qup_src",
711 .parent_names
= gcc_pxo_pll8
,
714 .flags
= CLK_SET_PARENT_GATE
,
719 static struct clk_branch gsbi4_qup_clk
= {
723 .enable_reg
= 0x2a2c,
724 .enable_mask
= BIT(9),
725 .hw
.init
= &(struct clk_init_data
){
726 .name
= "gsbi4_qup_clk",
727 .parent_names
= (const char *[]){ "gsbi4_qup_src" },
729 .ops
= &clk_branch_ops
,
730 .flags
= CLK_SET_RATE_PARENT
,
735 static struct clk_rcg gsbi5_qup_src
= {
740 .mnctr_reset_bit
= 7,
741 .mnctr_mode_shift
= 5,
752 .parent_map
= gcc_pxo_pll8_map
,
754 .freq_tbl
= clk_tbl_gsbi_qup
,
756 .enable_reg
= 0x2a4c,
757 .enable_mask
= BIT(11),
758 .hw
.init
= &(struct clk_init_data
){
759 .name
= "gsbi5_qup_src",
760 .parent_names
= gcc_pxo_pll8
,
763 .flags
= CLK_SET_PARENT_GATE
,
768 static struct clk_branch gsbi5_qup_clk
= {
772 .enable_reg
= 0x2a4c,
773 .enable_mask
= BIT(9),
774 .hw
.init
= &(struct clk_init_data
){
775 .name
= "gsbi5_qup_clk",
776 .parent_names
= (const char *[]){ "gsbi5_qup_src" },
778 .ops
= &clk_branch_ops
,
779 .flags
= CLK_SET_RATE_PARENT
,
784 static struct clk_rcg gsbi6_qup_src
= {
789 .mnctr_reset_bit
= 7,
790 .mnctr_mode_shift
= 5,
801 .parent_map
= gcc_pxo_pll8_map
,
803 .freq_tbl
= clk_tbl_gsbi_qup
,
805 .enable_reg
= 0x2a6c,
806 .enable_mask
= BIT(11),
807 .hw
.init
= &(struct clk_init_data
){
808 .name
= "gsbi6_qup_src",
809 .parent_names
= gcc_pxo_pll8
,
812 .flags
= CLK_SET_PARENT_GATE
,
817 static struct clk_branch gsbi6_qup_clk
= {
821 .enable_reg
= 0x2a6c,
822 .enable_mask
= BIT(9),
823 .hw
.init
= &(struct clk_init_data
){
824 .name
= "gsbi6_qup_clk",
825 .parent_names
= (const char *[]){ "gsbi6_qup_src" },
827 .ops
= &clk_branch_ops
,
828 .flags
= CLK_SET_RATE_PARENT
,
833 static struct clk_rcg gsbi7_qup_src
= {
838 .mnctr_reset_bit
= 7,
839 .mnctr_mode_shift
= 5,
850 .parent_map
= gcc_pxo_pll8_map
,
852 .freq_tbl
= clk_tbl_gsbi_qup
,
854 .enable_reg
= 0x2a8c,
855 .enable_mask
= BIT(11),
856 .hw
.init
= &(struct clk_init_data
){
857 .name
= "gsbi7_qup_src",
858 .parent_names
= gcc_pxo_pll8
,
861 .flags
= CLK_SET_PARENT_GATE
,
866 static struct clk_branch gsbi7_qup_clk
= {
870 .enable_reg
= 0x2a8c,
871 .enable_mask
= BIT(9),
872 .hw
.init
= &(struct clk_init_data
){
873 .name
= "gsbi7_qup_clk",
874 .parent_names
= (const char *[]){ "gsbi7_qup_src" },
876 .ops
= &clk_branch_ops
,
877 .flags
= CLK_SET_RATE_PARENT
,
882 static struct clk_branch gsbi1_h_clk
= {
888 .enable_reg
= 0x29c0,
889 .enable_mask
= BIT(4),
890 .hw
.init
= &(struct clk_init_data
){
891 .name
= "gsbi1_h_clk",
892 .ops
= &clk_branch_ops
,
893 .flags
= CLK_IS_ROOT
,
898 static struct clk_branch gsbi2_h_clk
= {
904 .enable_reg
= 0x29e0,
905 .enable_mask
= BIT(4),
906 .hw
.init
= &(struct clk_init_data
){
907 .name
= "gsbi2_h_clk",
908 .ops
= &clk_branch_ops
,
909 .flags
= CLK_IS_ROOT
,
914 static struct clk_branch gsbi4_h_clk
= {
920 .enable_reg
= 0x2a20,
921 .enable_mask
= BIT(4),
922 .hw
.init
= &(struct clk_init_data
){
923 .name
= "gsbi4_h_clk",
924 .ops
= &clk_branch_ops
,
925 .flags
= CLK_IS_ROOT
,
930 static struct clk_branch gsbi5_h_clk
= {
936 .enable_reg
= 0x2a40,
937 .enable_mask
= BIT(4),
938 .hw
.init
= &(struct clk_init_data
){
939 .name
= "gsbi5_h_clk",
940 .ops
= &clk_branch_ops
,
941 .flags
= CLK_IS_ROOT
,
946 static struct clk_branch gsbi6_h_clk
= {
952 .enable_reg
= 0x2a60,
953 .enable_mask
= BIT(4),
954 .hw
.init
= &(struct clk_init_data
){
955 .name
= "gsbi6_h_clk",
956 .ops
= &clk_branch_ops
,
957 .flags
= CLK_IS_ROOT
,
962 static struct clk_branch gsbi7_h_clk
= {
968 .enable_reg
= 0x2a80,
969 .enable_mask
= BIT(4),
970 .hw
.init
= &(struct clk_init_data
){
971 .name
= "gsbi7_h_clk",
972 .ops
= &clk_branch_ops
,
973 .flags
= CLK_IS_ROOT
,
978 static const struct freq_tbl clk_tbl_gp
[] = {
979 { 12500000, P_PXO
, 2, 0, 0 },
980 { 25000000, P_PXO
, 1, 0, 0 },
981 { 64000000, P_PLL8
, 2, 1, 3 },
982 { 76800000, P_PLL8
, 1, 1, 5 },
983 { 96000000, P_PLL8
, 4, 0, 0 },
984 { 128000000, P_PLL8
, 3, 0, 0 },
985 { 192000000, P_PLL8
, 2, 0, 0 },
989 static struct clk_rcg gp0_src
= {
994 .mnctr_reset_bit
= 7,
995 .mnctr_mode_shift
= 5,
1006 .parent_map
= gcc_pxo_pll8_cxo_map
,
1008 .freq_tbl
= clk_tbl_gp
,
1010 .enable_reg
= 0x2d24,
1011 .enable_mask
= BIT(11),
1012 .hw
.init
= &(struct clk_init_data
){
1014 .parent_names
= gcc_pxo_pll8_cxo
,
1016 .ops
= &clk_rcg_ops
,
1017 .flags
= CLK_SET_PARENT_GATE
,
1022 static struct clk_branch gp0_clk
= {
1026 .enable_reg
= 0x2d24,
1027 .enable_mask
= BIT(9),
1028 .hw
.init
= &(struct clk_init_data
){
1030 .parent_names
= (const char *[]){ "gp0_src" },
1032 .ops
= &clk_branch_ops
,
1033 .flags
= CLK_SET_RATE_PARENT
,
1038 static struct clk_rcg gp1_src
= {
1043 .mnctr_reset_bit
= 7,
1044 .mnctr_mode_shift
= 5,
1055 .parent_map
= gcc_pxo_pll8_cxo_map
,
1057 .freq_tbl
= clk_tbl_gp
,
1059 .enable_reg
= 0x2d44,
1060 .enable_mask
= BIT(11),
1061 .hw
.init
= &(struct clk_init_data
){
1063 .parent_names
= gcc_pxo_pll8_cxo
,
1065 .ops
= &clk_rcg_ops
,
1066 .flags
= CLK_SET_RATE_GATE
,
1071 static struct clk_branch gp1_clk
= {
1075 .enable_reg
= 0x2d44,
1076 .enable_mask
= BIT(9),
1077 .hw
.init
= &(struct clk_init_data
){
1079 .parent_names
= (const char *[]){ "gp1_src" },
1081 .ops
= &clk_branch_ops
,
1082 .flags
= CLK_SET_RATE_PARENT
,
1087 static struct clk_rcg gp2_src
= {
1092 .mnctr_reset_bit
= 7,
1093 .mnctr_mode_shift
= 5,
1104 .parent_map
= gcc_pxo_pll8_cxo_map
,
1106 .freq_tbl
= clk_tbl_gp
,
1108 .enable_reg
= 0x2d64,
1109 .enable_mask
= BIT(11),
1110 .hw
.init
= &(struct clk_init_data
){
1112 .parent_names
= gcc_pxo_pll8_cxo
,
1114 .ops
= &clk_rcg_ops
,
1115 .flags
= CLK_SET_RATE_GATE
,
1120 static struct clk_branch gp2_clk
= {
1124 .enable_reg
= 0x2d64,
1125 .enable_mask
= BIT(9),
1126 .hw
.init
= &(struct clk_init_data
){
1128 .parent_names
= (const char *[]){ "gp2_src" },
1130 .ops
= &clk_branch_ops
,
1131 .flags
= CLK_SET_RATE_PARENT
,
1136 static struct clk_branch pmem_clk
= {
1142 .enable_reg
= 0x25a0,
1143 .enable_mask
= BIT(4),
1144 .hw
.init
= &(struct clk_init_data
){
1146 .ops
= &clk_branch_ops
,
1147 .flags
= CLK_IS_ROOT
,
1152 static struct clk_rcg prng_src
= {
1160 .parent_map
= gcc_pxo_pll8_map
,
1163 .hw
.init
= &(struct clk_init_data
){
1165 .parent_names
= gcc_pxo_pll8
,
1167 .ops
= &clk_rcg_ops
,
1172 static struct clk_branch prng_clk
= {
1174 .halt_check
= BRANCH_HALT_VOTED
,
1177 .enable_reg
= 0x3080,
1178 .enable_mask
= BIT(10),
1179 .hw
.init
= &(struct clk_init_data
){
1181 .parent_names
= (const char *[]){ "prng_src" },
1183 .ops
= &clk_branch_ops
,
1188 static const struct freq_tbl clk_tbl_sdc
[] = {
1189 { 200000, P_PXO
, 2, 2, 125 },
1190 { 400000, P_PLL8
, 4, 1, 240 },
1191 { 16000000, P_PLL8
, 4, 1, 6 },
1192 { 17070000, P_PLL8
, 1, 2, 45 },
1193 { 20210000, P_PLL8
, 1, 1, 19 },
1194 { 24000000, P_PLL8
, 4, 1, 4 },
1195 { 48000000, P_PLL8
, 4, 1, 2 },
1196 { 64000000, P_PLL8
, 3, 1, 2 },
1197 { 96000000, P_PLL8
, 4, 0, 0 },
1198 { 192000000, P_PLL8
, 2, 0, 0 },
1202 static struct clk_rcg sdc1_src
= {
1207 .mnctr_reset_bit
= 7,
1208 .mnctr_mode_shift
= 5,
1219 .parent_map
= gcc_pxo_pll8_map
,
1221 .freq_tbl
= clk_tbl_sdc
,
1223 .enable_reg
= 0x282c,
1224 .enable_mask
= BIT(11),
1225 .hw
.init
= &(struct clk_init_data
){
1227 .parent_names
= gcc_pxo_pll8
,
1229 .ops
= &clk_rcg_ops
,
1230 .flags
= CLK_SET_RATE_GATE
,
1235 static struct clk_branch sdc1_clk
= {
1239 .enable_reg
= 0x282c,
1240 .enable_mask
= BIT(9),
1241 .hw
.init
= &(struct clk_init_data
){
1243 .parent_names
= (const char *[]){ "sdc1_src" },
1245 .ops
= &clk_branch_ops
,
1246 .flags
= CLK_SET_RATE_PARENT
,
1251 static struct clk_rcg sdc3_src
= {
1256 .mnctr_reset_bit
= 7,
1257 .mnctr_mode_shift
= 5,
1268 .parent_map
= gcc_pxo_pll8_map
,
1270 .freq_tbl
= clk_tbl_sdc
,
1272 .enable_reg
= 0x286c,
1273 .enable_mask
= BIT(11),
1274 .hw
.init
= &(struct clk_init_data
){
1276 .parent_names
= gcc_pxo_pll8
,
1278 .ops
= &clk_rcg_ops
,
1279 .flags
= CLK_SET_RATE_GATE
,
1284 static struct clk_branch sdc3_clk
= {
1288 .enable_reg
= 0x286c,
1289 .enable_mask
= BIT(9),
1290 .hw
.init
= &(struct clk_init_data
){
1292 .parent_names
= (const char *[]){ "sdc3_src" },
1294 .ops
= &clk_branch_ops
,
1295 .flags
= CLK_SET_RATE_PARENT
,
1300 static struct clk_branch sdc1_h_clk
= {
1306 .enable_reg
= 0x2820,
1307 .enable_mask
= BIT(4),
1308 .hw
.init
= &(struct clk_init_data
){
1309 .name
= "sdc1_h_clk",
1310 .ops
= &clk_branch_ops
,
1311 .flags
= CLK_IS_ROOT
,
1316 static struct clk_branch sdc3_h_clk
= {
1322 .enable_reg
= 0x2860,
1323 .enable_mask
= BIT(4),
1324 .hw
.init
= &(struct clk_init_data
){
1325 .name
= "sdc3_h_clk",
1326 .ops
= &clk_branch_ops
,
1327 .flags
= CLK_IS_ROOT
,
1332 static const struct freq_tbl clk_tbl_tsif_ref
[] = {
1333 { 105000, P_PXO
, 1, 1, 256 },
1337 static struct clk_rcg tsif_ref_src
= {
1342 .mnctr_reset_bit
= 7,
1343 .mnctr_mode_shift
= 5,
1354 .parent_map
= gcc_pxo_pll8_map
,
1356 .freq_tbl
= clk_tbl_tsif_ref
,
1358 .enable_reg
= 0x2710,
1359 .enable_mask
= BIT(11),
1360 .hw
.init
= &(struct clk_init_data
){
1361 .name
= "tsif_ref_src",
1362 .parent_names
= gcc_pxo_pll8
,
1364 .ops
= &clk_rcg_ops
,
1365 .flags
= CLK_SET_RATE_GATE
,
1370 static struct clk_branch tsif_ref_clk
= {
1374 .enable_reg
= 0x2710,
1375 .enable_mask
= BIT(9),
1376 .hw
.init
= &(struct clk_init_data
){
1377 .name
= "tsif_ref_clk",
1378 .parent_names
= (const char *[]){ "tsif_ref_src" },
1380 .ops
= &clk_branch_ops
,
1381 .flags
= CLK_SET_RATE_PARENT
,
1386 static struct clk_branch tsif_h_clk
= {
1392 .enable_reg
= 0x2700,
1393 .enable_mask
= BIT(4),
1394 .hw
.init
= &(struct clk_init_data
){
1395 .name
= "tsif_h_clk",
1396 .ops
= &clk_branch_ops
,
1397 .flags
= CLK_IS_ROOT
,
1402 static struct clk_branch dma_bam_h_clk
= {
1408 .enable_reg
= 0x25c0,
1409 .enable_mask
= BIT(4),
1410 .hw
.init
= &(struct clk_init_data
){
1411 .name
= "dma_bam_h_clk",
1412 .ops
= &clk_branch_ops
,
1413 .flags
= CLK_IS_ROOT
,
1418 static struct clk_branch adm0_clk
= {
1420 .halt_check
= BRANCH_HALT_VOTED
,
1423 .enable_reg
= 0x3080,
1424 .enable_mask
= BIT(2),
1425 .hw
.init
= &(struct clk_init_data
){
1427 .ops
= &clk_branch_ops
,
1428 .flags
= CLK_IS_ROOT
,
1433 static struct clk_branch adm0_pbus_clk
= {
1437 .halt_check
= BRANCH_HALT_VOTED
,
1440 .enable_reg
= 0x3080,
1441 .enable_mask
= BIT(3),
1442 .hw
.init
= &(struct clk_init_data
){
1443 .name
= "adm0_pbus_clk",
1444 .ops
= &clk_branch_ops
,
1445 .flags
= CLK_IS_ROOT
,
1450 static struct clk_branch pmic_arb0_h_clk
= {
1452 .halt_check
= BRANCH_HALT_VOTED
,
1455 .enable_reg
= 0x3080,
1456 .enable_mask
= BIT(8),
1457 .hw
.init
= &(struct clk_init_data
){
1458 .name
= "pmic_arb0_h_clk",
1459 .ops
= &clk_branch_ops
,
1460 .flags
= CLK_IS_ROOT
,
1465 static struct clk_branch pmic_arb1_h_clk
= {
1467 .halt_check
= BRANCH_HALT_VOTED
,
1470 .enable_reg
= 0x3080,
1471 .enable_mask
= BIT(9),
1472 .hw
.init
= &(struct clk_init_data
){
1473 .name
= "pmic_arb1_h_clk",
1474 .ops
= &clk_branch_ops
,
1475 .flags
= CLK_IS_ROOT
,
1480 static struct clk_branch pmic_ssbi2_clk
= {
1482 .halt_check
= BRANCH_HALT_VOTED
,
1485 .enable_reg
= 0x3080,
1486 .enable_mask
= BIT(7),
1487 .hw
.init
= &(struct clk_init_data
){
1488 .name
= "pmic_ssbi2_clk",
1489 .ops
= &clk_branch_ops
,
1490 .flags
= CLK_IS_ROOT
,
1495 static struct clk_branch rpm_msg_ram_h_clk
= {
1499 .halt_check
= BRANCH_HALT_VOTED
,
1502 .enable_reg
= 0x3080,
1503 .enable_mask
= BIT(6),
1504 .hw
.init
= &(struct clk_init_data
){
1505 .name
= "rpm_msg_ram_h_clk",
1506 .ops
= &clk_branch_ops
,
1507 .flags
= CLK_IS_ROOT
,
1512 static const struct freq_tbl clk_tbl_pcie_ref
[] = {
1513 { 100000000, P_PLL3
, 12, 0, 0 },
1517 static struct clk_rcg pcie_ref_src
= {
1525 .parent_map
= gcc_pxo_pll3_map
,
1527 .freq_tbl
= clk_tbl_pcie_ref
,
1529 .enable_reg
= 0x3860,
1530 .enable_mask
= BIT(11),
1531 .hw
.init
= &(struct clk_init_data
){
1532 .name
= "pcie_ref_src",
1533 .parent_names
= gcc_pxo_pll3
,
1535 .ops
= &clk_rcg_ops
,
1536 .flags
= CLK_SET_RATE_GATE
,
1541 static struct clk_branch pcie_ref_src_clk
= {
1545 .enable_reg
= 0x3860,
1546 .enable_mask
= BIT(9),
1547 .hw
.init
= &(struct clk_init_data
){
1548 .name
= "pcie_ref_src_clk",
1549 .parent_names
= (const char *[]){ "pcie_ref_src" },
1551 .ops
= &clk_branch_ops
,
1552 .flags
= CLK_SET_RATE_PARENT
,
1557 static struct clk_branch pcie_a_clk
= {
1561 .enable_reg
= 0x22c0,
1562 .enable_mask
= BIT(4),
1563 .hw
.init
= &(struct clk_init_data
){
1564 .name
= "pcie_a_clk",
1565 .ops
= &clk_branch_ops
,
1566 .flags
= CLK_IS_ROOT
,
1571 static struct clk_branch pcie_aux_clk
= {
1575 .enable_reg
= 0x22c8,
1576 .enable_mask
= BIT(4),
1577 .hw
.init
= &(struct clk_init_data
){
1578 .name
= "pcie_aux_clk",
1579 .ops
= &clk_branch_ops
,
1580 .flags
= CLK_IS_ROOT
,
1585 static struct clk_branch pcie_h_clk
= {
1589 .enable_reg
= 0x22cc,
1590 .enable_mask
= BIT(4),
1591 .hw
.init
= &(struct clk_init_data
){
1592 .name
= "pcie_h_clk",
1593 .ops
= &clk_branch_ops
,
1594 .flags
= CLK_IS_ROOT
,
1599 static struct clk_branch pcie_phy_clk
= {
1603 .enable_reg
= 0x22d0,
1604 .enable_mask
= BIT(4),
1605 .hw
.init
= &(struct clk_init_data
){
1606 .name
= "pcie_phy_clk",
1607 .ops
= &clk_branch_ops
,
1608 .flags
= CLK_IS_ROOT
,
1613 static struct clk_rcg pcie1_ref_src
= {
1621 .parent_map
= gcc_pxo_pll3_map
,
1623 .freq_tbl
= clk_tbl_pcie_ref
,
1625 .enable_reg
= 0x3aa0,
1626 .enable_mask
= BIT(11),
1627 .hw
.init
= &(struct clk_init_data
){
1628 .name
= "pcie1_ref_src",
1629 .parent_names
= gcc_pxo_pll3
,
1631 .ops
= &clk_rcg_ops
,
1632 .flags
= CLK_SET_RATE_GATE
,
1637 static struct clk_branch pcie1_ref_src_clk
= {
1641 .enable_reg
= 0x3aa0,
1642 .enable_mask
= BIT(9),
1643 .hw
.init
= &(struct clk_init_data
){
1644 .name
= "pcie1_ref_src_clk",
1645 .parent_names
= (const char *[]){ "pcie1_ref_src" },
1647 .ops
= &clk_branch_ops
,
1648 .flags
= CLK_SET_RATE_PARENT
,
1653 static struct clk_branch pcie1_a_clk
= {
1657 .enable_reg
= 0x3a80,
1658 .enable_mask
= BIT(4),
1659 .hw
.init
= &(struct clk_init_data
){
1660 .name
= "pcie1_a_clk",
1661 .ops
= &clk_branch_ops
,
1662 .flags
= CLK_IS_ROOT
,
1667 static struct clk_branch pcie1_aux_clk
= {
1671 .enable_reg
= 0x3a88,
1672 .enable_mask
= BIT(4),
1673 .hw
.init
= &(struct clk_init_data
){
1674 .name
= "pcie1_aux_clk",
1675 .ops
= &clk_branch_ops
,
1676 .flags
= CLK_IS_ROOT
,
1681 static struct clk_branch pcie1_h_clk
= {
1685 .enable_reg
= 0x3a8c,
1686 .enable_mask
= BIT(4),
1687 .hw
.init
= &(struct clk_init_data
){
1688 .name
= "pcie1_h_clk",
1689 .ops
= &clk_branch_ops
,
1690 .flags
= CLK_IS_ROOT
,
1695 static struct clk_branch pcie1_phy_clk
= {
1699 .enable_reg
= 0x3a90,
1700 .enable_mask
= BIT(4),
1701 .hw
.init
= &(struct clk_init_data
){
1702 .name
= "pcie1_phy_clk",
1703 .ops
= &clk_branch_ops
,
1704 .flags
= CLK_IS_ROOT
,
1709 static struct clk_rcg pcie2_ref_src
= {
1717 .parent_map
= gcc_pxo_pll3_map
,
1719 .freq_tbl
= clk_tbl_pcie_ref
,
1721 .enable_reg
= 0x3ae0,
1722 .enable_mask
= BIT(11),
1723 .hw
.init
= &(struct clk_init_data
){
1724 .name
= "pcie2_ref_src",
1725 .parent_names
= gcc_pxo_pll3
,
1727 .ops
= &clk_rcg_ops
,
1728 .flags
= CLK_SET_RATE_GATE
,
1733 static struct clk_branch pcie2_ref_src_clk
= {
1737 .enable_reg
= 0x3ae0,
1738 .enable_mask
= BIT(9),
1739 .hw
.init
= &(struct clk_init_data
){
1740 .name
= "pcie2_ref_src_clk",
1741 .parent_names
= (const char *[]){ "pcie2_ref_src" },
1743 .ops
= &clk_branch_ops
,
1744 .flags
= CLK_SET_RATE_PARENT
,
1749 static struct clk_branch pcie2_a_clk
= {
1753 .enable_reg
= 0x3ac0,
1754 .enable_mask
= BIT(4),
1755 .hw
.init
= &(struct clk_init_data
){
1756 .name
= "pcie2_a_clk",
1757 .ops
= &clk_branch_ops
,
1758 .flags
= CLK_IS_ROOT
,
1763 static struct clk_branch pcie2_aux_clk
= {
1767 .enable_reg
= 0x3ac8,
1768 .enable_mask
= BIT(4),
1769 .hw
.init
= &(struct clk_init_data
){
1770 .name
= "pcie2_aux_clk",
1771 .ops
= &clk_branch_ops
,
1772 .flags
= CLK_IS_ROOT
,
1777 static struct clk_branch pcie2_h_clk
= {
1781 .enable_reg
= 0x3acc,
1782 .enable_mask
= BIT(4),
1783 .hw
.init
= &(struct clk_init_data
){
1784 .name
= "pcie2_h_clk",
1785 .ops
= &clk_branch_ops
,
1786 .flags
= CLK_IS_ROOT
,
1791 static struct clk_branch pcie2_phy_clk
= {
1795 .enable_reg
= 0x3ad0,
1796 .enable_mask
= BIT(4),
1797 .hw
.init
= &(struct clk_init_data
){
1798 .name
= "pcie2_phy_clk",
1799 .ops
= &clk_branch_ops
,
1800 .flags
= CLK_IS_ROOT
,
1805 static const struct freq_tbl clk_tbl_sata_ref
[] = {
1806 { 100000000, P_PLL3
, 12, 0, 0 },
1810 static struct clk_rcg sata_ref_src
= {
1818 .parent_map
= gcc_pxo_pll3_sata_map
,
1820 .freq_tbl
= clk_tbl_sata_ref
,
1822 .enable_reg
= 0x2c08,
1823 .enable_mask
= BIT(7),
1824 .hw
.init
= &(struct clk_init_data
){
1825 .name
= "sata_ref_src",
1826 .parent_names
= gcc_pxo_pll3
,
1828 .ops
= &clk_rcg_ops
,
1829 .flags
= CLK_SET_RATE_GATE
,
1834 static struct clk_branch sata_rxoob_clk
= {
1838 .enable_reg
= 0x2c0c,
1839 .enable_mask
= BIT(4),
1840 .hw
.init
= &(struct clk_init_data
){
1841 .name
= "sata_rxoob_clk",
1842 .parent_names
= (const char *[]){ "sata_ref_src" },
1844 .ops
= &clk_branch_ops
,
1845 .flags
= CLK_SET_RATE_PARENT
,
1850 static struct clk_branch sata_pmalive_clk
= {
1854 .enable_reg
= 0x2c10,
1855 .enable_mask
= BIT(4),
1856 .hw
.init
= &(struct clk_init_data
){
1857 .name
= "sata_pmalive_clk",
1858 .parent_names
= (const char *[]){ "sata_ref_src" },
1860 .ops
= &clk_branch_ops
,
1861 .flags
= CLK_SET_RATE_PARENT
,
1866 static struct clk_branch sata_phy_ref_clk
= {
1870 .enable_reg
= 0x2c14,
1871 .enable_mask
= BIT(4),
1872 .hw
.init
= &(struct clk_init_data
){
1873 .name
= "sata_phy_ref_clk",
1874 .parent_names
= (const char *[]){ "pxo" },
1876 .ops
= &clk_branch_ops
,
1881 static struct clk_branch sata_a_clk
= {
1885 .enable_reg
= 0x2c20,
1886 .enable_mask
= BIT(4),
1887 .hw
.init
= &(struct clk_init_data
){
1888 .name
= "sata_a_clk",
1889 .ops
= &clk_branch_ops
,
1890 .flags
= CLK_IS_ROOT
,
1895 static struct clk_branch sata_h_clk
= {
1899 .enable_reg
= 0x2c00,
1900 .enable_mask
= BIT(4),
1901 .hw
.init
= &(struct clk_init_data
){
1902 .name
= "sata_h_clk",
1903 .ops
= &clk_branch_ops
,
1904 .flags
= CLK_IS_ROOT
,
1909 static struct clk_branch sfab_sata_s_h_clk
= {
1913 .enable_reg
= 0x2480,
1914 .enable_mask
= BIT(4),
1915 .hw
.init
= &(struct clk_init_data
){
1916 .name
= "sfab_sata_s_h_clk",
1917 .ops
= &clk_branch_ops
,
1918 .flags
= CLK_IS_ROOT
,
1923 static struct clk_branch sata_phy_cfg_clk
= {
1927 .enable_reg
= 0x2c40,
1928 .enable_mask
= BIT(4),
1929 .hw
.init
= &(struct clk_init_data
){
1930 .name
= "sata_phy_cfg_clk",
1931 .ops
= &clk_branch_ops
,
1932 .flags
= CLK_IS_ROOT
,
1937 static const struct freq_tbl clk_tbl_usb30_master
[] = {
1938 { 125000000, P_PLL0
, 1, 5, 32 },
1942 static struct clk_rcg usb30_master_clk_src
= {
1947 .mnctr_reset_bit
= 7,
1948 .mnctr_mode_shift
= 5,
1959 .parent_map
= gcc_pxo_pll8_pll0
,
1961 .freq_tbl
= clk_tbl_usb30_master
,
1963 .enable_reg
= 0x3b2c,
1964 .enable_mask
= BIT(11),
1965 .hw
.init
= &(struct clk_init_data
){
1966 .name
= "usb30_master_ref_src",
1967 .parent_names
= gcc_pxo_pll8_pll0_map
,
1969 .ops
= &clk_rcg_ops
,
1970 .flags
= CLK_SET_RATE_GATE
,
1975 static struct clk_branch usb30_0_branch_clk
= {
1979 .enable_reg
= 0x3b24,
1980 .enable_mask
= BIT(4),
1981 .hw
.init
= &(struct clk_init_data
){
1982 .name
= "usb30_0_branch_clk",
1983 .parent_names
= (const char *[]){ "usb30_master_ref_src", },
1985 .ops
= &clk_branch_ops
,
1986 .flags
= CLK_SET_RATE_PARENT
,
1991 static struct clk_branch usb30_1_branch_clk
= {
1995 .enable_reg
= 0x3b34,
1996 .enable_mask
= BIT(4),
1997 .hw
.init
= &(struct clk_init_data
){
1998 .name
= "usb30_1_branch_clk",
1999 .parent_names
= (const char *[]){ "usb30_master_ref_src", },
2001 .ops
= &clk_branch_ops
,
2002 .flags
= CLK_SET_RATE_PARENT
,
2007 static const struct freq_tbl clk_tbl_usb30_utmi
[] = {
2008 { 60000000, P_PLL8
, 1, 5, 32 },
2012 static struct clk_rcg usb30_utmi_clk
= {
2017 .mnctr_reset_bit
= 7,
2018 .mnctr_mode_shift
= 5,
2029 .parent_map
= gcc_pxo_pll8_pll0
,
2031 .freq_tbl
= clk_tbl_usb30_utmi
,
2033 .enable_reg
= 0x3b44,
2034 .enable_mask
= BIT(11),
2035 .hw
.init
= &(struct clk_init_data
){
2036 .name
= "usb30_utmi_clk",
2037 .parent_names
= gcc_pxo_pll8_pll0_map
,
2039 .ops
= &clk_rcg_ops
,
2040 .flags
= CLK_SET_RATE_GATE
,
2045 static struct clk_branch usb30_0_utmi_clk_ctl
= {
2049 .enable_reg
= 0x3b48,
2050 .enable_mask
= BIT(4),
2051 .hw
.init
= &(struct clk_init_data
){
2052 .name
= "usb30_0_utmi_clk_ctl",
2053 .parent_names
= (const char *[]){ "usb30_utmi_clk", },
2055 .ops
= &clk_branch_ops
,
2056 .flags
= CLK_SET_RATE_PARENT
,
2061 static struct clk_branch usb30_1_utmi_clk_ctl
= {
2065 .enable_reg
= 0x3b4c,
2066 .enable_mask
= BIT(4),
2067 .hw
.init
= &(struct clk_init_data
){
2068 .name
= "usb30_1_utmi_clk_ctl",
2069 .parent_names
= (const char *[]){ "usb30_utmi_clk", },
2071 .ops
= &clk_branch_ops
,
2072 .flags
= CLK_SET_RATE_PARENT
,
2077 static const struct freq_tbl clk_tbl_usb
[] = {
2078 { 60000000, P_PLL8
, 1, 5, 32 },
2082 static struct clk_rcg usb_hs1_xcvr_clk_src
= {
2087 .mnctr_reset_bit
= 7,
2088 .mnctr_mode_shift
= 5,
2099 .parent_map
= gcc_pxo_pll8_pll0
,
2101 .freq_tbl
= clk_tbl_usb
,
2103 .enable_reg
= 0x2968,
2104 .enable_mask
= BIT(11),
2105 .hw
.init
= &(struct clk_init_data
){
2106 .name
= "usb_hs1_xcvr_src",
2107 .parent_names
= gcc_pxo_pll8_pll0_map
,
2109 .ops
= &clk_rcg_ops
,
2110 .flags
= CLK_SET_RATE_GATE
,
2115 static struct clk_branch usb_hs1_xcvr_clk
= {
2119 .enable_reg
= 0x290c,
2120 .enable_mask
= BIT(9),
2121 .hw
.init
= &(struct clk_init_data
){
2122 .name
= "usb_hs1_xcvr_clk",
2123 .parent_names
= (const char *[]){ "usb_hs1_xcvr_src" },
2125 .ops
= &clk_branch_ops
,
2126 .flags
= CLK_SET_RATE_PARENT
,
2131 static struct clk_branch usb_hs1_h_clk
= {
2137 .enable_reg
= 0x2900,
2138 .enable_mask
= BIT(4),
2139 .hw
.init
= &(struct clk_init_data
){
2140 .name
= "usb_hs1_h_clk",
2141 .ops
= &clk_branch_ops
,
2142 .flags
= CLK_IS_ROOT
,
2147 static struct clk_rcg usb_fs1_xcvr_clk_src
= {
2152 .mnctr_reset_bit
= 7,
2153 .mnctr_mode_shift
= 5,
2164 .parent_map
= gcc_pxo_pll8_pll0
,
2166 .freq_tbl
= clk_tbl_usb
,
2168 .enable_reg
= 0x2968,
2169 .enable_mask
= BIT(11),
2170 .hw
.init
= &(struct clk_init_data
){
2171 .name
= "usb_fs1_xcvr_src",
2172 .parent_names
= gcc_pxo_pll8_pll0_map
,
2174 .ops
= &clk_rcg_ops
,
2175 .flags
= CLK_SET_RATE_GATE
,
2180 static struct clk_branch usb_fs1_xcvr_clk
= {
2184 .enable_reg
= 0x2968,
2185 .enable_mask
= BIT(9),
2186 .hw
.init
= &(struct clk_init_data
){
2187 .name
= "usb_fs1_xcvr_clk",
2188 .parent_names
= (const char *[]){ "usb_fs1_xcvr_src", },
2190 .ops
= &clk_branch_ops
,
2191 .flags
= CLK_SET_RATE_PARENT
,
2196 static struct clk_branch usb_fs1_sys_clk
= {
2200 .enable_reg
= 0x296c,
2201 .enable_mask
= BIT(4),
2202 .hw
.init
= &(struct clk_init_data
){
2203 .name
= "usb_fs1_sys_clk",
2204 .parent_names
= (const char *[]){ "usb_fs1_xcvr_src", },
2206 .ops
= &clk_branch_ops
,
2207 .flags
= CLK_SET_RATE_PARENT
,
2212 static struct clk_branch usb_fs1_h_clk
= {
2216 .enable_reg
= 0x2960,
2217 .enable_mask
= BIT(4),
2218 .hw
.init
= &(struct clk_init_data
){
2219 .name
= "usb_fs1_h_clk",
2220 .ops
= &clk_branch_ops
,
2221 .flags
= CLK_IS_ROOT
,
2226 static struct clk_branch ebi2_clk
= {
2232 .enable_reg
= 0x3b00,
2233 .enable_mask
= BIT(4),
2234 .hw
.init
= &(struct clk_init_data
){
2236 .ops
= &clk_branch_ops
,
2237 .flags
= CLK_IS_ROOT
,
2242 static struct clk_branch ebi2_aon_clk
= {
2246 .enable_reg
= 0x3b00,
2247 .enable_mask
= BIT(8),
2248 .hw
.init
= &(struct clk_init_data
){
2249 .name
= "ebi2_always_on_clk",
2250 .ops
= &clk_branch_ops
,
2251 .flags
= CLK_IS_ROOT
,
2256 static const struct freq_tbl clk_tbl_gmac
[] = {
2257 { 133000000, P_PLL0
, 1, 50, 301 },
2258 { 266000000, P_PLL0
, 1, 127, 382 },
2262 static struct clk_dyn_rcg gmac_core1_src
= {
2263 .ns_reg
[0] = 0x3cac,
2264 .ns_reg
[1] = 0x3cb0,
2265 .md_reg
[0] = 0x3ca4,
2266 .md_reg
[1] = 0x3ca8,
2270 .mnctr_reset_bit
= 7,
2271 .mnctr_mode_shift
= 5,
2278 .mnctr_reset_bit
= 7,
2279 .mnctr_mode_shift
= 5,
2286 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2290 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2301 .freq_tbl
= clk_tbl_gmac
,
2303 .enable_reg
= 0x3ca0,
2304 .enable_mask
= BIT(1),
2305 .hw
.init
= &(struct clk_init_data
){
2306 .name
= "gmac_core1_src",
2307 .parent_names
= gcc_pxo_pll8_pll14_pll18_pll0
,
2309 .ops
= &clk_dyn_rcg_ops
,
2314 static struct clk_branch gmac_core1_clk
= {
2320 .enable_reg
= 0x3cb4,
2321 .enable_mask
= BIT(4),
2322 .hw
.init
= &(struct clk_init_data
){
2323 .name
= "gmac_core1_clk",
2324 .parent_names
= (const char *[]){
2328 .ops
= &clk_branch_ops
,
2329 .flags
= CLK_SET_RATE_PARENT
,
2334 static struct clk_dyn_rcg gmac_core2_src
= {
2335 .ns_reg
[0] = 0x3ccc,
2336 .ns_reg
[1] = 0x3cd0,
2337 .md_reg
[0] = 0x3cc4,
2338 .md_reg
[1] = 0x3cc8,
2342 .mnctr_reset_bit
= 7,
2343 .mnctr_mode_shift
= 5,
2350 .mnctr_reset_bit
= 7,
2351 .mnctr_mode_shift
= 5,
2358 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2362 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2373 .freq_tbl
= clk_tbl_gmac
,
2375 .enable_reg
= 0x3cc0,
2376 .enable_mask
= BIT(1),
2377 .hw
.init
= &(struct clk_init_data
){
2378 .name
= "gmac_core2_src",
2379 .parent_names
= gcc_pxo_pll8_pll14_pll18_pll0
,
2381 .ops
= &clk_dyn_rcg_ops
,
2386 static struct clk_branch gmac_core2_clk
= {
2392 .enable_reg
= 0x3cd4,
2393 .enable_mask
= BIT(4),
2394 .hw
.init
= &(struct clk_init_data
){
2395 .name
= "gmac_core2_clk",
2396 .parent_names
= (const char *[]){
2400 .ops
= &clk_branch_ops
,
2401 .flags
= CLK_SET_RATE_PARENT
,
2406 static struct clk_dyn_rcg gmac_core3_src
= {
2407 .ns_reg
[0] = 0x3cec,
2408 .ns_reg
[1] = 0x3cf0,
2409 .md_reg
[0] = 0x3ce4,
2410 .md_reg
[1] = 0x3ce8,
2414 .mnctr_reset_bit
= 7,
2415 .mnctr_mode_shift
= 5,
2422 .mnctr_reset_bit
= 7,
2423 .mnctr_mode_shift
= 5,
2430 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2434 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2445 .freq_tbl
= clk_tbl_gmac
,
2447 .enable_reg
= 0x3ce0,
2448 .enable_mask
= BIT(1),
2449 .hw
.init
= &(struct clk_init_data
){
2450 .name
= "gmac_core3_src",
2451 .parent_names
= gcc_pxo_pll8_pll14_pll18_pll0
,
2453 .ops
= &clk_dyn_rcg_ops
,
2458 static struct clk_branch gmac_core3_clk
= {
2464 .enable_reg
= 0x3cf4,
2465 .enable_mask
= BIT(4),
2466 .hw
.init
= &(struct clk_init_data
){
2467 .name
= "gmac_core3_clk",
2468 .parent_names
= (const char *[]){
2472 .ops
= &clk_branch_ops
,
2473 .flags
= CLK_SET_RATE_PARENT
,
2478 static struct clk_dyn_rcg gmac_core4_src
= {
2479 .ns_reg
[0] = 0x3d0c,
2480 .ns_reg
[1] = 0x3d10,
2481 .md_reg
[0] = 0x3d04,
2482 .md_reg
[1] = 0x3d08,
2486 .mnctr_reset_bit
= 7,
2487 .mnctr_mode_shift
= 5,
2494 .mnctr_reset_bit
= 7,
2495 .mnctr_mode_shift
= 5,
2502 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2506 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2517 .freq_tbl
= clk_tbl_gmac
,
2519 .enable_reg
= 0x3d00,
2520 .enable_mask
= BIT(1),
2521 .hw
.init
= &(struct clk_init_data
){
2522 .name
= "gmac_core4_src",
2523 .parent_names
= gcc_pxo_pll8_pll14_pll18_pll0
,
2525 .ops
= &clk_dyn_rcg_ops
,
2530 static struct clk_branch gmac_core4_clk
= {
2536 .enable_reg
= 0x3d14,
2537 .enable_mask
= BIT(4),
2538 .hw
.init
= &(struct clk_init_data
){
2539 .name
= "gmac_core4_clk",
2540 .parent_names
= (const char *[]){
2544 .ops
= &clk_branch_ops
,
2545 .flags
= CLK_SET_RATE_PARENT
,
2550 static const struct freq_tbl clk_tbl_nss_tcm
[] = {
2551 { 266000000, P_PLL0
, 3, 0, 0 },
2552 { 400000000, P_PLL0
, 2, 0, 0 },
2556 static struct clk_dyn_rcg nss_tcm_src
= {
2557 .ns_reg
[0] = 0x3dc4,
2558 .ns_reg
[1] = 0x3dc8,
2562 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2566 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2577 .freq_tbl
= clk_tbl_nss_tcm
,
2579 .enable_reg
= 0x3dc0,
2580 .enable_mask
= BIT(1),
2581 .hw
.init
= &(struct clk_init_data
){
2582 .name
= "nss_tcm_src",
2583 .parent_names
= gcc_pxo_pll8_pll14_pll18_pll0
,
2585 .ops
= &clk_dyn_rcg_ops
,
2590 static struct clk_branch nss_tcm_clk
= {
2594 .enable_reg
= 0x3dd0,
2595 .enable_mask
= BIT(6) | BIT(4),
2596 .hw
.init
= &(struct clk_init_data
){
2597 .name
= "nss_tcm_clk",
2598 .parent_names
= (const char *[]){
2602 .ops
= &clk_branch_ops
,
2603 .flags
= CLK_SET_RATE_PARENT
,
2608 static const struct freq_tbl clk_tbl_nss
[] = {
2609 { 110000000, P_PLL18
, 1, 1, 5 },
2610 { 275000000, P_PLL18
, 2, 0, 0 },
2611 { 550000000, P_PLL18
, 1, 0, 0 },
2612 { 733000000, P_PLL18
, 1, 0, 0 },
2616 static struct clk_dyn_rcg ubi32_core1_src_clk
= {
2617 .ns_reg
[0] = 0x3d2c,
2618 .ns_reg
[1] = 0x3d30,
2619 .md_reg
[0] = 0x3d24,
2620 .md_reg
[1] = 0x3d28,
2624 .mnctr_reset_bit
= 7,
2625 .mnctr_mode_shift
= 5,
2632 .mnctr_reset_bit
= 7,
2633 .mnctr_mode_shift
= 5,
2640 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2644 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2655 .freq_tbl
= clk_tbl_nss
,
2657 .enable_reg
= 0x3d20,
2658 .enable_mask
= BIT(1),
2659 .hw
.init
= &(struct clk_init_data
){
2660 .name
= "ubi32_core1_src_clk",
2661 .parent_names
= gcc_pxo_pll8_pll14_pll18_pll0
,
2663 .ops
= &clk_dyn_rcg_ops
,
2664 .flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
,
2669 static struct clk_dyn_rcg ubi32_core2_src_clk
= {
2670 .ns_reg
[0] = 0x3d4c,
2671 .ns_reg
[1] = 0x3d50,
2672 .md_reg
[0] = 0x3d44,
2673 .md_reg
[1] = 0x3d48,
2677 .mnctr_reset_bit
= 7,
2678 .mnctr_mode_shift
= 5,
2685 .mnctr_reset_bit
= 7,
2686 .mnctr_mode_shift
= 5,
2693 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2697 .parent_map
= gcc_pxo_pll8_pll14_pll18_pll0_map
,
2708 .freq_tbl
= clk_tbl_nss
,
2710 .enable_reg
= 0x3d40,
2711 .enable_mask
= BIT(1),
2712 .hw
.init
= &(struct clk_init_data
){
2713 .name
= "ubi32_core2_src_clk",
2714 .parent_names
= gcc_pxo_pll8_pll14_pll18_pll0
,
2716 .ops
= &clk_dyn_rcg_ops
,
2717 .flags
= CLK_SET_RATE_PARENT
| CLK_GET_RATE_NOCACHE
,
2722 static struct clk_regmap
*gcc_ipq806x_clks
[] = {
2723 [PLL0
] = &pll0
.clkr
,
2724 [PLL0_VOTE
] = &pll0_vote
,
2725 [PLL3
] = &pll3
.clkr
,
2726 [PLL4_VOTE
] = &pll4_vote
,
2727 [PLL8
] = &pll8
.clkr
,
2728 [PLL8_VOTE
] = &pll8_vote
,
2729 [PLL14
] = &pll14
.clkr
,
2730 [PLL14_VOTE
] = &pll14_vote
,
2731 [PLL18
] = &pll18
.clkr
,
2732 [GSBI1_UART_SRC
] = &gsbi1_uart_src
.clkr
,
2733 [GSBI1_UART_CLK
] = &gsbi1_uart_clk
.clkr
,
2734 [GSBI2_UART_SRC
] = &gsbi2_uart_src
.clkr
,
2735 [GSBI2_UART_CLK
] = &gsbi2_uart_clk
.clkr
,
2736 [GSBI4_UART_SRC
] = &gsbi4_uart_src
.clkr
,
2737 [GSBI4_UART_CLK
] = &gsbi4_uart_clk
.clkr
,
2738 [GSBI5_UART_SRC
] = &gsbi5_uart_src
.clkr
,
2739 [GSBI5_UART_CLK
] = &gsbi5_uart_clk
.clkr
,
2740 [GSBI6_UART_SRC
] = &gsbi6_uart_src
.clkr
,
2741 [GSBI6_UART_CLK
] = &gsbi6_uart_clk
.clkr
,
2742 [GSBI7_UART_SRC
] = &gsbi7_uart_src
.clkr
,
2743 [GSBI7_UART_CLK
] = &gsbi7_uart_clk
.clkr
,
2744 [GSBI1_QUP_SRC
] = &gsbi1_qup_src
.clkr
,
2745 [GSBI1_QUP_CLK
] = &gsbi1_qup_clk
.clkr
,
2746 [GSBI2_QUP_SRC
] = &gsbi2_qup_src
.clkr
,
2747 [GSBI2_QUP_CLK
] = &gsbi2_qup_clk
.clkr
,
2748 [GSBI4_QUP_SRC
] = &gsbi4_qup_src
.clkr
,
2749 [GSBI4_QUP_CLK
] = &gsbi4_qup_clk
.clkr
,
2750 [GSBI5_QUP_SRC
] = &gsbi5_qup_src
.clkr
,
2751 [GSBI5_QUP_CLK
] = &gsbi5_qup_clk
.clkr
,
2752 [GSBI6_QUP_SRC
] = &gsbi6_qup_src
.clkr
,
2753 [GSBI6_QUP_CLK
] = &gsbi6_qup_clk
.clkr
,
2754 [GSBI7_QUP_SRC
] = &gsbi7_qup_src
.clkr
,
2755 [GSBI7_QUP_CLK
] = &gsbi7_qup_clk
.clkr
,
2756 [GP0_SRC
] = &gp0_src
.clkr
,
2757 [GP0_CLK
] = &gp0_clk
.clkr
,
2758 [GP1_SRC
] = &gp1_src
.clkr
,
2759 [GP1_CLK
] = &gp1_clk
.clkr
,
2760 [GP2_SRC
] = &gp2_src
.clkr
,
2761 [GP2_CLK
] = &gp2_clk
.clkr
,
2762 [PMEM_A_CLK
] = &pmem_clk
.clkr
,
2763 [PRNG_SRC
] = &prng_src
.clkr
,
2764 [PRNG_CLK
] = &prng_clk
.clkr
,
2765 [SDC1_SRC
] = &sdc1_src
.clkr
,
2766 [SDC1_CLK
] = &sdc1_clk
.clkr
,
2767 [SDC3_SRC
] = &sdc3_src
.clkr
,
2768 [SDC3_CLK
] = &sdc3_clk
.clkr
,
2769 [TSIF_REF_SRC
] = &tsif_ref_src
.clkr
,
2770 [TSIF_REF_CLK
] = &tsif_ref_clk
.clkr
,
2771 [DMA_BAM_H_CLK
] = &dma_bam_h_clk
.clkr
,
2772 [GSBI1_H_CLK
] = &gsbi1_h_clk
.clkr
,
2773 [GSBI2_H_CLK
] = &gsbi2_h_clk
.clkr
,
2774 [GSBI4_H_CLK
] = &gsbi4_h_clk
.clkr
,
2775 [GSBI5_H_CLK
] = &gsbi5_h_clk
.clkr
,
2776 [GSBI6_H_CLK
] = &gsbi6_h_clk
.clkr
,
2777 [GSBI7_H_CLK
] = &gsbi7_h_clk
.clkr
,
2778 [TSIF_H_CLK
] = &tsif_h_clk
.clkr
,
2779 [SDC1_H_CLK
] = &sdc1_h_clk
.clkr
,
2780 [SDC3_H_CLK
] = &sdc3_h_clk
.clkr
,
2781 [ADM0_CLK
] = &adm0_clk
.clkr
,
2782 [ADM0_PBUS_CLK
] = &adm0_pbus_clk
.clkr
,
2783 [PCIE_A_CLK
] = &pcie_a_clk
.clkr
,
2784 [PCIE_AUX_CLK
] = &pcie_aux_clk
.clkr
,
2785 [PCIE_H_CLK
] = &pcie_h_clk
.clkr
,
2786 [PCIE_PHY_CLK
] = &pcie_phy_clk
.clkr
,
2787 [SFAB_SATA_S_H_CLK
] = &sfab_sata_s_h_clk
.clkr
,
2788 [PMIC_ARB0_H_CLK
] = &pmic_arb0_h_clk
.clkr
,
2789 [PMIC_ARB1_H_CLK
] = &pmic_arb1_h_clk
.clkr
,
2790 [PMIC_SSBI2_CLK
] = &pmic_ssbi2_clk
.clkr
,
2791 [RPM_MSG_RAM_H_CLK
] = &rpm_msg_ram_h_clk
.clkr
,
2792 [SATA_H_CLK
] = &sata_h_clk
.clkr
,
2793 [SATA_CLK_SRC
] = &sata_ref_src
.clkr
,
2794 [SATA_RXOOB_CLK
] = &sata_rxoob_clk
.clkr
,
2795 [SATA_PMALIVE_CLK
] = &sata_pmalive_clk
.clkr
,
2796 [SATA_PHY_REF_CLK
] = &sata_phy_ref_clk
.clkr
,
2797 [SATA_A_CLK
] = &sata_a_clk
.clkr
,
2798 [SATA_PHY_CFG_CLK
] = &sata_phy_cfg_clk
.clkr
,
2799 [PCIE_ALT_REF_SRC
] = &pcie_ref_src
.clkr
,
2800 [PCIE_ALT_REF_CLK
] = &pcie_ref_src_clk
.clkr
,
2801 [PCIE_1_A_CLK
] = &pcie1_a_clk
.clkr
,
2802 [PCIE_1_AUX_CLK
] = &pcie1_aux_clk
.clkr
,
2803 [PCIE_1_H_CLK
] = &pcie1_h_clk
.clkr
,
2804 [PCIE_1_PHY_CLK
] = &pcie1_phy_clk
.clkr
,
2805 [PCIE_1_ALT_REF_SRC
] = &pcie1_ref_src
.clkr
,
2806 [PCIE_1_ALT_REF_CLK
] = &pcie1_ref_src_clk
.clkr
,
2807 [PCIE_2_A_CLK
] = &pcie2_a_clk
.clkr
,
2808 [PCIE_2_AUX_CLK
] = &pcie2_aux_clk
.clkr
,
2809 [PCIE_2_H_CLK
] = &pcie2_h_clk
.clkr
,
2810 [PCIE_2_PHY_CLK
] = &pcie2_phy_clk
.clkr
,
2811 [PCIE_2_ALT_REF_SRC
] = &pcie2_ref_src
.clkr
,
2812 [PCIE_2_ALT_REF_CLK
] = &pcie2_ref_src_clk
.clkr
,
2813 [USB30_MASTER_SRC
] = &usb30_master_clk_src
.clkr
,
2814 [USB30_0_MASTER_CLK
] = &usb30_0_branch_clk
.clkr
,
2815 [USB30_1_MASTER_CLK
] = &usb30_1_branch_clk
.clkr
,
2816 [USB30_UTMI_SRC
] = &usb30_utmi_clk
.clkr
,
2817 [USB30_0_UTMI_CLK
] = &usb30_0_utmi_clk_ctl
.clkr
,
2818 [USB30_1_UTMI_CLK
] = &usb30_1_utmi_clk_ctl
.clkr
,
2819 [USB_HS1_H_CLK
] = &usb_hs1_h_clk
.clkr
,
2820 [USB_HS1_XCVR_SRC
] = &usb_hs1_xcvr_clk_src
.clkr
,
2821 [USB_HS1_XCVR_CLK
] = &usb_hs1_xcvr_clk
.clkr
,
2822 [USB_FS1_H_CLK
] = &usb_fs1_h_clk
.clkr
,
2823 [USB_FS1_XCVR_SRC
] = &usb_fs1_xcvr_clk_src
.clkr
,
2824 [USB_FS1_XCVR_CLK
] = &usb_fs1_xcvr_clk
.clkr
,
2825 [USB_FS1_SYSTEM_CLK
] = &usb_fs1_sys_clk
.clkr
,
2826 [EBI2_CLK
] = &ebi2_clk
.clkr
,
2827 [EBI2_AON_CLK
] = &ebi2_aon_clk
.clkr
,
2828 [GMAC_CORE1_CLK_SRC
] = &gmac_core1_src
.clkr
,
2829 [GMAC_CORE1_CLK
] = &gmac_core1_clk
.clkr
,
2830 [GMAC_CORE2_CLK_SRC
] = &gmac_core2_src
.clkr
,
2831 [GMAC_CORE2_CLK
] = &gmac_core2_clk
.clkr
,
2832 [GMAC_CORE3_CLK_SRC
] = &gmac_core3_src
.clkr
,
2833 [GMAC_CORE3_CLK
] = &gmac_core3_clk
.clkr
,
2834 [GMAC_CORE4_CLK_SRC
] = &gmac_core4_src
.clkr
,
2835 [GMAC_CORE4_CLK
] = &gmac_core4_clk
.clkr
,
2836 [UBI32_CORE1_CLK_SRC
] = &ubi32_core1_src_clk
.clkr
,
2837 [UBI32_CORE2_CLK_SRC
] = &ubi32_core2_src_clk
.clkr
,
2838 [NSSTCM_CLK_SRC
] = &nss_tcm_src
.clkr
,
2839 [NSSTCM_CLK
] = &nss_tcm_clk
.clkr
,
2842 static const struct qcom_reset_map gcc_ipq806x_resets
[] = {
2843 [QDSS_STM_RESET
] = { 0x2060, 6 },
2844 [AFAB_SMPSS_S_RESET
] = { 0x20b8, 2 },
2845 [AFAB_SMPSS_M1_RESET
] = { 0x20b8, 1 },
2846 [AFAB_SMPSS_M0_RESET
] = { 0x20b8, 0 },
2847 [AFAB_EBI1_CH0_RESET
] = { 0x20c0, 7 },
2848 [AFAB_EBI1_CH1_RESET
] = { 0x20c4, 7 },
2849 [SFAB_ADM0_M0_RESET
] = { 0x21e0, 7 },
2850 [SFAB_ADM0_M1_RESET
] = { 0x21e4, 7 },
2851 [SFAB_ADM0_M2_RESET
] = { 0x21e8, 7 },
2852 [ADM0_C2_RESET
] = { 0x220c, 4 },
2853 [ADM0_C1_RESET
] = { 0x220c, 3 },
2854 [ADM0_C0_RESET
] = { 0x220c, 2 },
2855 [ADM0_PBUS_RESET
] = { 0x220c, 1 },
2856 [ADM0_RESET
] = { 0x220c, 0 },
2857 [QDSS_CLKS_SW_RESET
] = { 0x2260, 5 },
2858 [QDSS_POR_RESET
] = { 0x2260, 4 },
2859 [QDSS_TSCTR_RESET
] = { 0x2260, 3 },
2860 [QDSS_HRESET_RESET
] = { 0x2260, 2 },
2861 [QDSS_AXI_RESET
] = { 0x2260, 1 },
2862 [QDSS_DBG_RESET
] = { 0x2260, 0 },
2863 [SFAB_PCIE_M_RESET
] = { 0x22d8, 1 },
2864 [SFAB_PCIE_S_RESET
] = { 0x22d8, 0 },
2865 [PCIE_EXT_RESET
] = { 0x22dc, 6 },
2866 [PCIE_PHY_RESET
] = { 0x22dc, 5 },
2867 [PCIE_PCI_RESET
] = { 0x22dc, 4 },
2868 [PCIE_POR_RESET
] = { 0x22dc, 3 },
2869 [PCIE_HCLK_RESET
] = { 0x22dc, 2 },
2870 [PCIE_ACLK_RESET
] = { 0x22dc, 0 },
2871 [SFAB_LPASS_RESET
] = { 0x23a0, 7 },
2872 [SFAB_AFAB_M_RESET
] = { 0x23e0, 7 },
2873 [AFAB_SFAB_M0_RESET
] = { 0x2420, 7 },
2874 [AFAB_SFAB_M1_RESET
] = { 0x2424, 7 },
2875 [SFAB_SATA_S_RESET
] = { 0x2480, 7 },
2876 [SFAB_DFAB_M_RESET
] = { 0x2500, 7 },
2877 [DFAB_SFAB_M_RESET
] = { 0x2520, 7 },
2878 [DFAB_SWAY0_RESET
] = { 0x2540, 7 },
2879 [DFAB_SWAY1_RESET
] = { 0x2544, 7 },
2880 [DFAB_ARB0_RESET
] = { 0x2560, 7 },
2881 [DFAB_ARB1_RESET
] = { 0x2564, 7 },
2882 [PPSS_PROC_RESET
] = { 0x2594, 1 },
2883 [PPSS_RESET
] = { 0x2594, 0 },
2884 [DMA_BAM_RESET
] = { 0x25c0, 7 },
2885 [SPS_TIC_H_RESET
] = { 0x2600, 7 },
2886 [SFAB_CFPB_M_RESET
] = { 0x2680, 7 },
2887 [SFAB_CFPB_S_RESET
] = { 0x26c0, 7 },
2888 [TSIF_H_RESET
] = { 0x2700, 7 },
2889 [CE1_H_RESET
] = { 0x2720, 7 },
2890 [CE1_CORE_RESET
] = { 0x2724, 7 },
2891 [CE1_SLEEP_RESET
] = { 0x2728, 7 },
2892 [CE2_H_RESET
] = { 0x2740, 7 },
2893 [CE2_CORE_RESET
] = { 0x2744, 7 },
2894 [SFAB_SFPB_M_RESET
] = { 0x2780, 7 },
2895 [SFAB_SFPB_S_RESET
] = { 0x27a0, 7 },
2896 [RPM_PROC_RESET
] = { 0x27c0, 7 },
2897 [PMIC_SSBI2_RESET
] = { 0x280c, 12 },
2898 [SDC1_RESET
] = { 0x2830, 0 },
2899 [SDC2_RESET
] = { 0x2850, 0 },
2900 [SDC3_RESET
] = { 0x2870, 0 },
2901 [SDC4_RESET
] = { 0x2890, 0 },
2902 [USB_HS1_RESET
] = { 0x2910, 0 },
2903 [USB_HSIC_RESET
] = { 0x2934, 0 },
2904 [USB_FS1_XCVR_RESET
] = { 0x2974, 1 },
2905 [USB_FS1_RESET
] = { 0x2974, 0 },
2906 [GSBI1_RESET
] = { 0x29dc, 0 },
2907 [GSBI2_RESET
] = { 0x29fc, 0 },
2908 [GSBI3_RESET
] = { 0x2a1c, 0 },
2909 [GSBI4_RESET
] = { 0x2a3c, 0 },
2910 [GSBI5_RESET
] = { 0x2a5c, 0 },
2911 [GSBI6_RESET
] = { 0x2a7c, 0 },
2912 [GSBI7_RESET
] = { 0x2a9c, 0 },
2913 [SPDM_RESET
] = { 0x2b6c, 0 },
2914 [SEC_CTRL_RESET
] = { 0x2b80, 7 },
2915 [TLMM_H_RESET
] = { 0x2ba0, 7 },
2916 [SFAB_SATA_M_RESET
] = { 0x2c18, 0 },
2917 [SATA_RESET
] = { 0x2c1c, 0 },
2918 [TSSC_RESET
] = { 0x2ca0, 7 },
2919 [PDM_RESET
] = { 0x2cc0, 12 },
2920 [MPM_H_RESET
] = { 0x2da0, 7 },
2921 [MPM_RESET
] = { 0x2da4, 0 },
2922 [SFAB_SMPSS_S_RESET
] = { 0x2e00, 7 },
2923 [PRNG_RESET
] = { 0x2e80, 12 },
2924 [SFAB_CE3_M_RESET
] = { 0x36c8, 1 },
2925 [SFAB_CE3_S_RESET
] = { 0x36c8, 0 },
2926 [CE3_SLEEP_RESET
] = { 0x36d0, 7 },
2927 [PCIE_1_M_RESET
] = { 0x3a98, 1 },
2928 [PCIE_1_S_RESET
] = { 0x3a98, 0 },
2929 [PCIE_1_EXT_RESET
] = { 0x3a9c, 6 },
2930 [PCIE_1_PHY_RESET
] = { 0x3a9c, 5 },
2931 [PCIE_1_PCI_RESET
] = { 0x3a9c, 4 },
2932 [PCIE_1_POR_RESET
] = { 0x3a9c, 3 },
2933 [PCIE_1_HCLK_RESET
] = { 0x3a9c, 2 },
2934 [PCIE_1_ACLK_RESET
] = { 0x3a9c, 0 },
2935 [PCIE_2_M_RESET
] = { 0x3ad8, 1 },
2936 [PCIE_2_S_RESET
] = { 0x3ad8, 0 },
2937 [PCIE_2_EXT_RESET
] = { 0x3adc, 6 },
2938 [PCIE_2_PHY_RESET
] = { 0x3adc, 5 },
2939 [PCIE_2_PCI_RESET
] = { 0x3adc, 4 },
2940 [PCIE_2_POR_RESET
] = { 0x3adc, 3 },
2941 [PCIE_2_HCLK_RESET
] = { 0x3adc, 2 },
2942 [PCIE_2_ACLK_RESET
] = { 0x3adc, 0 },
2943 [SFAB_USB30_S_RESET
] = { 0x3b54, 1 },
2944 [SFAB_USB30_M_RESET
] = { 0x3b54, 0 },
2945 [USB30_0_PORT2_HS_PHY_RESET
] = { 0x3b50, 5 },
2946 [USB30_0_MASTER_RESET
] = { 0x3b50, 4 },
2947 [USB30_0_SLEEP_RESET
] = { 0x3b50, 3 },
2948 [USB30_0_UTMI_PHY_RESET
] = { 0x3b50, 2 },
2949 [USB30_0_POWERON_RESET
] = { 0x3b50, 1 },
2950 [USB30_0_PHY_RESET
] = { 0x3b50, 0 },
2951 [USB30_1_MASTER_RESET
] = { 0x3b58, 4 },
2952 [USB30_1_SLEEP_RESET
] = { 0x3b58, 3 },
2953 [USB30_1_UTMI_PHY_RESET
] = { 0x3b58, 2 },
2954 [USB30_1_POWERON_RESET
] = { 0x3b58, 1 },
2955 [USB30_1_PHY_RESET
] = { 0x3b58, 0 },
2956 [NSSFB0_RESET
] = { 0x3b60, 6 },
2957 [NSSFB1_RESET
] = { 0x3b60, 7 },
2958 [UBI32_CORE1_CLKRST_CLAMP_RESET
] = { 0x3d3c, 3},
2959 [UBI32_CORE1_CLAMP_RESET
] = { 0x3d3c, 2 },
2960 [UBI32_CORE1_AHB_RESET
] = { 0x3d3c, 1 },
2961 [UBI32_CORE1_AXI_RESET
] = { 0x3d3c, 0 },
2962 [UBI32_CORE2_CLKRST_CLAMP_RESET
] = { 0x3d5c, 3 },
2963 [UBI32_CORE2_CLAMP_RESET
] = { 0x3d5c, 2 },
2964 [UBI32_CORE2_AHB_RESET
] = { 0x3d5c, 1 },
2965 [UBI32_CORE2_AXI_RESET
] = { 0x3d5c, 0 },
2966 [GMAC_CORE1_RESET
] = { 0x3cbc, 0 },
2967 [GMAC_CORE2_RESET
] = { 0x3cdc, 0 },
2968 [GMAC_CORE3_RESET
] = { 0x3cfc, 0 },
2969 [GMAC_CORE4_RESET
] = { 0x3d1c, 0 },
2970 [GMAC_AHB_RESET
] = { 0x3e24, 0 },
2971 [NSS_CH0_RST_RX_CLK_N_RESET
] = { 0x3b60, 0 },
2972 [NSS_CH0_RST_TX_CLK_N_RESET
] = { 0x3b60, 1 },
2973 [NSS_CH0_RST_RX_125M_N_RESET
] = { 0x3b60, 2 },
2974 [NSS_CH0_HW_RST_RX_125M_N_RESET
] = { 0x3b60, 3 },
2975 [NSS_CH0_RST_TX_125M_N_RESET
] = { 0x3b60, 4 },
2976 [NSS_CH1_RST_RX_CLK_N_RESET
] = { 0x3b60, 5 },
2977 [NSS_CH1_RST_TX_CLK_N_RESET
] = { 0x3b60, 6 },
2978 [NSS_CH1_RST_RX_125M_N_RESET
] = { 0x3b60, 7 },
2979 [NSS_CH1_HW_RST_RX_125M_N_RESET
] = { 0x3b60, 8 },
2980 [NSS_CH1_RST_TX_125M_N_RESET
] = { 0x3b60, 9 },
2981 [NSS_CH2_RST_RX_CLK_N_RESET
] = { 0x3b60, 10 },
2982 [NSS_CH2_RST_TX_CLK_N_RESET
] = { 0x3b60, 11 },
2983 [NSS_CH2_RST_RX_125M_N_RESET
] = { 0x3b60, 12 },
2984 [NSS_CH2_HW_RST_RX_125M_N_RESET
] = { 0x3b60, 13 },
2985 [NSS_CH2_RST_TX_125M_N_RESET
] = { 0x3b60, 14 },
2986 [NSS_CH3_RST_RX_CLK_N_RESET
] = { 0x3b60, 15 },
2987 [NSS_CH3_RST_TX_CLK_N_RESET
] = { 0x3b60, 16 },
2988 [NSS_CH3_RST_RX_125M_N_RESET
] = { 0x3b60, 17 },
2989 [NSS_CH3_HW_RST_RX_125M_N_RESET
] = { 0x3b60, 18 },
2990 [NSS_CH3_RST_TX_125M_N_RESET
] = { 0x3b60, 19 },
2991 [NSS_RST_RX_250M_125M_N_RESET
] = { 0x3b60, 20 },
2992 [NSS_RST_TX_250M_125M_N_RESET
] = { 0x3b60, 21 },
2993 [NSS_QSGMII_TXPI_RST_N_RESET
] = { 0x3b60, 22 },
2994 [NSS_QSGMII_CDR_RST_N_RESET
] = { 0x3b60, 23 },
2995 [NSS_SGMII2_CDR_RST_N_RESET
] = { 0x3b60, 24 },
2996 [NSS_SGMII3_CDR_RST_N_RESET
] = { 0x3b60, 25 },
2997 [NSS_CAL_PRBS_RST_N_RESET
] = { 0x3b60, 26 },
2998 [NSS_LCKDT_RST_N_RESET
] = { 0x3b60, 27 },
2999 [NSS_SRDS_N_RESET
] = { 0x3b60, 28 },
3002 static const struct regmap_config gcc_ipq806x_regmap_config
= {
3006 .max_register
= 0x3e40,
3010 static const struct qcom_cc_desc gcc_ipq806x_desc
= {
3011 .config
= &gcc_ipq806x_regmap_config
,
3012 .clks
= gcc_ipq806x_clks
,
3013 .num_clks
= ARRAY_SIZE(gcc_ipq806x_clks
),
3014 .resets
= gcc_ipq806x_resets
,
3015 .num_resets
= ARRAY_SIZE(gcc_ipq806x_resets
),
3018 static const struct of_device_id gcc_ipq806x_match_table
[] = {
3019 { .compatible
= "qcom,gcc-ipq8064" },
3022 MODULE_DEVICE_TABLE(of
, gcc_ipq806x_match_table
);
3024 static int gcc_ipq806x_probe(struct platform_device
*pdev
)
3027 struct device
*dev
= &pdev
->dev
;
3028 struct regmap
*regmap
;
3031 /* Temporary until RPM clocks supported */
3032 clk
= clk_register_fixed_rate(dev
, "cxo", NULL
, CLK_IS_ROOT
, 25000000);
3034 return PTR_ERR(clk
);
3036 clk
= clk_register_fixed_rate(dev
, "pxo", NULL
, CLK_IS_ROOT
, 25000000);
3038 return PTR_ERR(clk
);
3040 ret
= qcom_cc_probe(pdev
, &gcc_ipq806x_desc
);
3044 regmap
= dev_get_regmap(dev
, NULL
);
3048 /* Setup PLL18 static bits */
3049 regmap_update_bits(regmap
, 0x31a4, 0xffffffc0, 0x40000400);
3050 regmap_write(regmap
, 0x31b0, 0x3080);
3052 /* Set GMAC footswitch sleep/wakeup values */
3053 regmap_write(regmap
, 0x3cb8, 8);
3054 regmap_write(regmap
, 0x3cd8, 8);
3055 regmap_write(regmap
, 0x3cf8, 8);
3056 regmap_write(regmap
, 0x3d18, 8);
3061 static int gcc_ipq806x_remove(struct platform_device
*pdev
)
3063 qcom_cc_remove(pdev
);
3067 static struct platform_driver gcc_ipq806x_driver
= {
3068 .probe
= gcc_ipq806x_probe
,
3069 .remove
= gcc_ipq806x_remove
,
3071 .name
= "gcc-ipq806x",
3072 .of_match_table
= gcc_ipq806x_match_table
,
3076 static int __init
gcc_ipq806x_init(void)
3078 return platform_driver_register(&gcc_ipq806x_driver
);
3080 core_initcall(gcc_ipq806x_init
);
3082 static void __exit
gcc_ipq806x_exit(void)
3084 platform_driver_unregister(&gcc_ipq806x_driver
);
3086 module_exit(gcc_ipq806x_exit
);
3088 MODULE_DESCRIPTION("QCOM GCC IPQ806x Driver");
3089 MODULE_LICENSE("GPL v2");
3090 MODULE_ALIAS("platform:gcc-ipq806x");