2 * Copyright 2015 Linaro Limited
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/kernel.h>
15 #include <linux/bitops.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/clk-provider.h>
22 #include <linux/regmap.h>
23 #include <linux/reset-controller.h>
25 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
26 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
29 #include "clk-regmap.h"
32 #include "clk-branch.h"
53 static const struct parent_map gcc_xo_gpll0_map
[] = {
58 static const char * const gcc_xo_gpll0
[] = {
63 static const struct parent_map gcc_xo_gpll0_bimc_map
[] = {
69 static const char * const gcc_xo_gpll0_bimc
[] = {
75 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2a_map
[] = {
82 static const char * const gcc_xo_gpll0a_gpll1_gpll2a
[] = {
89 static const struct parent_map gcc_xo_gpll0_gpll2_map
[] = {
95 static const char * const gcc_xo_gpll0_gpll2
[] = {
101 static const struct parent_map gcc_xo_gpll0a_map
[] = {
106 static const char * const gcc_xo_gpll0a
[] = {
111 static const struct parent_map gcc_xo_gpll0_gpll1a_sleep_map
[] = {
118 static const char * const gcc_xo_gpll0_gpll1a_sleep
[] = {
125 static const struct parent_map gcc_xo_gpll0_gpll1a_map
[] = {
131 static const char * const gcc_xo_gpll0_gpll1a
[] = {
137 static const struct parent_map gcc_xo_dsibyte_map
[] = {
139 { P_DSI0_PHYPLL_BYTE
, 2 },
142 static const char * const gcc_xo_dsibyte
[] = {
147 static const struct parent_map gcc_xo_gpll0a_dsibyte_map
[] = {
150 { P_DSI0_PHYPLL_BYTE
, 1 },
153 static const char * const gcc_xo_gpll0a_dsibyte
[] = {
159 static const struct parent_map gcc_xo_gpll0_dsiphy_map
[] = {
162 { P_DSI0_PHYPLL_DSI
, 2 },
165 static const char * const gcc_xo_gpll0_dsiphy
[] = {
171 static const struct parent_map gcc_xo_gpll0a_dsiphy_map
[] = {
174 { P_DSI0_PHYPLL_DSI
, 1 },
177 static const char * const gcc_xo_gpll0a_dsiphy
[] = {
183 static const struct parent_map gcc_xo_gpll0a_gpll1_gpll2_map
[] = {
190 static const char * const gcc_xo_gpll0a_gpll1_gpll2
[] = {
197 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map
[] = {
204 static const char * const gcc_xo_gpll0_gpll1_sleep
[] = {
211 static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map
[] = {
214 { P_EXT_PRI_I2S
, 2 },
219 static const char * const gcc_xo_gpll1_epi2s_emclk_sleep
[] = {
227 static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map
[] = {
230 { P_EXT_SEC_I2S
, 2 },
235 static const char * const gcc_xo_gpll1_esi2s_emclk_sleep
[] = {
243 static const struct parent_map gcc_xo_sleep_map
[] = {
248 static const char * const gcc_xo_sleep
[] = {
253 static const struct parent_map gcc_xo_gpll1_emclk_sleep_map
[] = {
260 static const char * const gcc_xo_gpll1_emclk_sleep
[] = {
267 static struct clk_pll gpll0
= {
271 .config_reg
= 0x21014,
273 .status_reg
= 0x2101c,
275 .clkr
.hw
.init
= &(struct clk_init_data
){
277 .parent_names
= (const char *[]){ "xo" },
283 static struct clk_regmap gpll0_vote
= {
284 .enable_reg
= 0x45000,
285 .enable_mask
= BIT(0),
286 .hw
.init
= &(struct clk_init_data
){
287 .name
= "gpll0_vote",
288 .parent_names
= (const char *[]){ "gpll0" },
290 .ops
= &clk_pll_vote_ops
,
294 static struct clk_pll gpll1
= {
298 .config_reg
= 0x20014,
300 .status_reg
= 0x2001c,
302 .clkr
.hw
.init
= &(struct clk_init_data
){
304 .parent_names
= (const char *[]){ "xo" },
310 static struct clk_regmap gpll1_vote
= {
311 .enable_reg
= 0x45000,
312 .enable_mask
= BIT(1),
313 .hw
.init
= &(struct clk_init_data
){
314 .name
= "gpll1_vote",
315 .parent_names
= (const char *[]){ "gpll1" },
317 .ops
= &clk_pll_vote_ops
,
321 static struct clk_pll gpll2
= {
325 .config_reg
= 0x4a014,
327 .status_reg
= 0x4a01c,
329 .clkr
.hw
.init
= &(struct clk_init_data
){
331 .parent_names
= (const char *[]){ "xo" },
337 static struct clk_regmap gpll2_vote
= {
338 .enable_reg
= 0x45000,
339 .enable_mask
= BIT(2),
340 .hw
.init
= &(struct clk_init_data
){
341 .name
= "gpll2_vote",
342 .parent_names
= (const char *[]){ "gpll2" },
344 .ops
= &clk_pll_vote_ops
,
348 static struct clk_pll bimc_pll
= {
352 .config_reg
= 0x23014,
354 .status_reg
= 0x2301c,
356 .clkr
.hw
.init
= &(struct clk_init_data
){
358 .parent_names
= (const char *[]){ "xo" },
364 static struct clk_regmap bimc_pll_vote
= {
365 .enable_reg
= 0x45000,
366 .enable_mask
= BIT(3),
367 .hw
.init
= &(struct clk_init_data
){
368 .name
= "bimc_pll_vote",
369 .parent_names
= (const char *[]){ "bimc_pll" },
371 .ops
= &clk_pll_vote_ops
,
375 static struct clk_rcg2 pcnoc_bfdcd_clk_src
= {
378 .parent_map
= gcc_xo_gpll0_bimc_map
,
379 .clkr
.hw
.init
= &(struct clk_init_data
){
380 .name
= "pcnoc_bfdcd_clk_src",
381 .parent_names
= gcc_xo_gpll0_bimc
,
383 .ops
= &clk_rcg2_ops
,
387 static struct clk_rcg2 system_noc_bfdcd_clk_src
= {
390 .parent_map
= gcc_xo_gpll0_bimc_map
,
391 .clkr
.hw
.init
= &(struct clk_init_data
){
392 .name
= "system_noc_bfdcd_clk_src",
393 .parent_names
= gcc_xo_gpll0_bimc
,
395 .ops
= &clk_rcg2_ops
,
399 static const struct freq_tbl ftbl_gcc_camss_ahb_clk
[] = {
400 F(40000000, P_GPLL0
, 10, 1, 2),
401 F(80000000, P_GPLL0
, 10, 0, 0),
405 static struct clk_rcg2 camss_ahb_clk_src
= {
409 .parent_map
= gcc_xo_gpll0_map
,
410 .freq_tbl
= ftbl_gcc_camss_ahb_clk
,
411 .clkr
.hw
.init
= &(struct clk_init_data
){
412 .name
= "camss_ahb_clk_src",
413 .parent_names
= gcc_xo_gpll0
,
415 .ops
= &clk_rcg2_ops
,
419 static const struct freq_tbl ftbl_apss_ahb_clk
[] = {
420 F(19200000, P_XO
, 1, 0, 0),
421 F(50000000, P_GPLL0
, 16, 0, 0),
422 F(100000000, P_GPLL0
, 8, 0, 0),
423 F(133330000, P_GPLL0
, 6, 0, 0),
427 static struct clk_rcg2 apss_ahb_clk_src
= {
430 .parent_map
= gcc_xo_gpll0_map
,
431 .freq_tbl
= ftbl_apss_ahb_clk
,
432 .clkr
.hw
.init
= &(struct clk_init_data
){
433 .name
= "apss_ahb_clk_src",
434 .parent_names
= gcc_xo_gpll0
,
436 .ops
= &clk_rcg2_ops
,
440 static const struct freq_tbl ftbl_gcc_camss_csi0_1_clk
[] = {
441 F(100000000, P_GPLL0
, 8, 0, 0),
442 F(200000000, P_GPLL0
, 4, 0, 0),
446 static struct clk_rcg2 csi0_clk_src
= {
449 .parent_map
= gcc_xo_gpll0_map
,
450 .freq_tbl
= ftbl_gcc_camss_csi0_1_clk
,
451 .clkr
.hw
.init
= &(struct clk_init_data
){
452 .name
= "csi0_clk_src",
453 .parent_names
= gcc_xo_gpll0
,
455 .ops
= &clk_rcg2_ops
,
459 static struct clk_rcg2 csi1_clk_src
= {
462 .parent_map
= gcc_xo_gpll0_map
,
463 .freq_tbl
= ftbl_gcc_camss_csi0_1_clk
,
464 .clkr
.hw
.init
= &(struct clk_init_data
){
465 .name
= "csi1_clk_src",
466 .parent_names
= gcc_xo_gpll0
,
468 .ops
= &clk_rcg2_ops
,
472 static const struct freq_tbl ftbl_gcc_oxili_gfx3d_clk
[] = {
473 F(19200000, P_XO
, 1, 0, 0),
474 F(50000000, P_GPLL0_AUX
, 16, 0, 0),
475 F(80000000, P_GPLL0_AUX
, 10, 0, 0),
476 F(100000000, P_GPLL0_AUX
, 8, 0, 0),
477 F(160000000, P_GPLL0_AUX
, 5, 0, 0),
478 F(177780000, P_GPLL0_AUX
, 4.5, 0, 0),
479 F(200000000, P_GPLL0_AUX
, 4, 0, 0),
480 F(266670000, P_GPLL0_AUX
, 3, 0, 0),
481 F(294912000, P_GPLL1
, 3, 0, 0),
482 F(310000000, P_GPLL2
, 3, 0, 0),
483 F(400000000, P_GPLL0_AUX
, 2, 0, 0),
487 static struct clk_rcg2 gfx3d_clk_src
= {
490 .parent_map
= gcc_xo_gpll0a_gpll1_gpll2a_map
,
491 .freq_tbl
= ftbl_gcc_oxili_gfx3d_clk
,
492 .clkr
.hw
.init
= &(struct clk_init_data
){
493 .name
= "gfx3d_clk_src",
494 .parent_names
= gcc_xo_gpll0a_gpll1_gpll2a
,
496 .ops
= &clk_rcg2_ops
,
500 static const struct freq_tbl ftbl_gcc_camss_vfe0_clk
[] = {
501 F(50000000, P_GPLL0
, 16, 0, 0),
502 F(80000000, P_GPLL0
, 10, 0, 0),
503 F(100000000, P_GPLL0
, 8, 0, 0),
504 F(160000000, P_GPLL0
, 5, 0, 0),
505 F(177780000, P_GPLL0
, 4.5, 0, 0),
506 F(200000000, P_GPLL0
, 4, 0, 0),
507 F(266670000, P_GPLL0
, 3, 0, 0),
508 F(320000000, P_GPLL0
, 2.5, 0, 0),
509 F(400000000, P_GPLL0
, 2, 0, 0),
510 F(465000000, P_GPLL2
, 2, 0, 0),
514 static struct clk_rcg2 vfe0_clk_src
= {
517 .parent_map
= gcc_xo_gpll0_gpll2_map
,
518 .freq_tbl
= ftbl_gcc_camss_vfe0_clk
,
519 .clkr
.hw
.init
= &(struct clk_init_data
){
520 .name
= "vfe0_clk_src",
521 .parent_names
= gcc_xo_gpll0_gpll2
,
523 .ops
= &clk_rcg2_ops
,
527 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk
[] = {
528 F(19200000, P_XO
, 1, 0, 0),
529 F(50000000, P_GPLL0
, 16, 0, 0),
533 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src
= {
536 .parent_map
= gcc_xo_gpll0_map
,
537 .freq_tbl
= ftbl_gcc_blsp1_qup1_6_i2c_apps_clk
,
538 .clkr
.hw
.init
= &(struct clk_init_data
){
539 .name
= "blsp1_qup1_i2c_apps_clk_src",
540 .parent_names
= gcc_xo_gpll0
,
542 .ops
= &clk_rcg2_ops
,
546 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk
[] = {
547 F(100000, P_XO
, 16, 2, 24),
548 F(250000, P_XO
, 16, 5, 24),
549 F(500000, P_XO
, 8, 5, 24),
550 F(960000, P_XO
, 10, 1, 2),
551 F(1000000, P_XO
, 4, 5, 24),
552 F(4800000, P_XO
, 4, 0, 0),
553 F(9600000, P_XO
, 2, 0, 0),
554 F(16000000, P_GPLL0
, 10, 1, 5),
555 F(19200000, P_XO
, 1, 0, 0),
556 F(25000000, P_GPLL0
, 16, 1, 2),
557 F(50000000, P_GPLL0
, 16, 0, 0),
561 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src
= {
565 .parent_map
= gcc_xo_gpll0_map
,
566 .freq_tbl
= ftbl_gcc_blsp1_qup1_6_spi_apps_clk
,
567 .clkr
.hw
.init
= &(struct clk_init_data
){
568 .name
= "blsp1_qup1_spi_apps_clk_src",
569 .parent_names
= gcc_xo_gpll0
,
571 .ops
= &clk_rcg2_ops
,
575 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src
= {
578 .parent_map
= gcc_xo_gpll0_map
,
579 .freq_tbl
= ftbl_gcc_blsp1_qup1_6_i2c_apps_clk
,
580 .clkr
.hw
.init
= &(struct clk_init_data
){
581 .name
= "blsp1_qup2_i2c_apps_clk_src",
582 .parent_names
= gcc_xo_gpll0
,
584 .ops
= &clk_rcg2_ops
,
588 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src
= {
592 .parent_map
= gcc_xo_gpll0_map
,
593 .freq_tbl
= ftbl_gcc_blsp1_qup1_6_spi_apps_clk
,
594 .clkr
.hw
.init
= &(struct clk_init_data
){
595 .name
= "blsp1_qup2_spi_apps_clk_src",
596 .parent_names
= gcc_xo_gpll0
,
598 .ops
= &clk_rcg2_ops
,
602 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src
= {
605 .parent_map
= gcc_xo_gpll0_map
,
606 .freq_tbl
= ftbl_gcc_blsp1_qup1_6_i2c_apps_clk
,
607 .clkr
.hw
.init
= &(struct clk_init_data
){
608 .name
= "blsp1_qup3_i2c_apps_clk_src",
609 .parent_names
= gcc_xo_gpll0
,
611 .ops
= &clk_rcg2_ops
,
615 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src
= {
619 .parent_map
= gcc_xo_gpll0_map
,
620 .freq_tbl
= ftbl_gcc_blsp1_qup1_6_spi_apps_clk
,
621 .clkr
.hw
.init
= &(struct clk_init_data
){
622 .name
= "blsp1_qup3_spi_apps_clk_src",
623 .parent_names
= gcc_xo_gpll0
,
625 .ops
= &clk_rcg2_ops
,
629 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src
= {
632 .parent_map
= gcc_xo_gpll0_map
,
633 .freq_tbl
= ftbl_gcc_blsp1_qup1_6_i2c_apps_clk
,
634 .clkr
.hw
.init
= &(struct clk_init_data
){
635 .name
= "blsp1_qup4_i2c_apps_clk_src",
636 .parent_names
= gcc_xo_gpll0
,
638 .ops
= &clk_rcg2_ops
,
642 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src
= {
646 .parent_map
= gcc_xo_gpll0_map
,
647 .freq_tbl
= ftbl_gcc_blsp1_qup1_6_spi_apps_clk
,
648 .clkr
.hw
.init
= &(struct clk_init_data
){
649 .name
= "blsp1_qup4_spi_apps_clk_src",
650 .parent_names
= gcc_xo_gpll0
,
652 .ops
= &clk_rcg2_ops
,
656 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src
= {
659 .parent_map
= gcc_xo_gpll0_map
,
660 .freq_tbl
= ftbl_gcc_blsp1_qup1_6_i2c_apps_clk
,
661 .clkr
.hw
.init
= &(struct clk_init_data
){
662 .name
= "blsp1_qup5_i2c_apps_clk_src",
663 .parent_names
= gcc_xo_gpll0
,
665 .ops
= &clk_rcg2_ops
,
669 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src
= {
673 .parent_map
= gcc_xo_gpll0_map
,
674 .freq_tbl
= ftbl_gcc_blsp1_qup1_6_spi_apps_clk
,
675 .clkr
.hw
.init
= &(struct clk_init_data
){
676 .name
= "blsp1_qup5_spi_apps_clk_src",
677 .parent_names
= gcc_xo_gpll0
,
679 .ops
= &clk_rcg2_ops
,
683 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src
= {
686 .parent_map
= gcc_xo_gpll0_map
,
687 .freq_tbl
= ftbl_gcc_blsp1_qup1_6_i2c_apps_clk
,
688 .clkr
.hw
.init
= &(struct clk_init_data
){
689 .name
= "blsp1_qup6_i2c_apps_clk_src",
690 .parent_names
= gcc_xo_gpll0
,
692 .ops
= &clk_rcg2_ops
,
696 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src
= {
700 .parent_map
= gcc_xo_gpll0_map
,
701 .freq_tbl
= ftbl_gcc_blsp1_qup1_6_spi_apps_clk
,
702 .clkr
.hw
.init
= &(struct clk_init_data
){
703 .name
= "blsp1_qup6_spi_apps_clk_src",
704 .parent_names
= gcc_xo_gpll0
,
706 .ops
= &clk_rcg2_ops
,
710 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk
[] = {
711 F(3686400, P_GPLL0
, 1, 72, 15625),
712 F(7372800, P_GPLL0
, 1, 144, 15625),
713 F(14745600, P_GPLL0
, 1, 288, 15625),
714 F(16000000, P_GPLL0
, 10, 1, 5),
715 F(19200000, P_XO
, 1, 0, 0),
716 F(24000000, P_GPLL0
, 1, 3, 100),
717 F(25000000, P_GPLL0
, 16, 1, 2),
718 F(32000000, P_GPLL0
, 1, 1, 25),
719 F(40000000, P_GPLL0
, 1, 1, 20),
720 F(46400000, P_GPLL0
, 1, 29, 500),
721 F(48000000, P_GPLL0
, 1, 3, 50),
722 F(51200000, P_GPLL0
, 1, 8, 125),
723 F(56000000, P_GPLL0
, 1, 7, 100),
724 F(58982400, P_GPLL0
, 1, 1152, 15625),
725 F(60000000, P_GPLL0
, 1, 3, 40),
729 static struct clk_rcg2 blsp1_uart1_apps_clk_src
= {
733 .parent_map
= gcc_xo_gpll0_map
,
734 .freq_tbl
= ftbl_gcc_blsp1_uart1_6_apps_clk
,
735 .clkr
.hw
.init
= &(struct clk_init_data
){
736 .name
= "blsp1_uart1_apps_clk_src",
737 .parent_names
= gcc_xo_gpll0
,
739 .ops
= &clk_rcg2_ops
,
743 static struct clk_rcg2 blsp1_uart2_apps_clk_src
= {
747 .parent_map
= gcc_xo_gpll0_map
,
748 .freq_tbl
= ftbl_gcc_blsp1_uart1_6_apps_clk
,
749 .clkr
.hw
.init
= &(struct clk_init_data
){
750 .name
= "blsp1_uart2_apps_clk_src",
751 .parent_names
= gcc_xo_gpll0
,
753 .ops
= &clk_rcg2_ops
,
757 static const struct freq_tbl ftbl_gcc_camss_cci_clk
[] = {
758 F(19200000, P_XO
, 1, 0, 0),
762 static struct clk_rcg2 cci_clk_src
= {
766 .parent_map
= gcc_xo_gpll0a_map
,
767 .freq_tbl
= ftbl_gcc_camss_cci_clk
,
768 .clkr
.hw
.init
= &(struct clk_init_data
){
769 .name
= "cci_clk_src",
770 .parent_names
= gcc_xo_gpll0a
,
772 .ops
= &clk_rcg2_ops
,
776 static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk
[] = {
777 F(100000000, P_GPLL0
, 8, 0, 0),
778 F(200000000, P_GPLL0
, 4, 0, 0),
782 static struct clk_rcg2 camss_gp0_clk_src
= {
786 .parent_map
= gcc_xo_gpll0_gpll1a_sleep_map
,
787 .freq_tbl
= ftbl_gcc_camss_gp0_1_clk
,
788 .clkr
.hw
.init
= &(struct clk_init_data
){
789 .name
= "camss_gp0_clk_src",
790 .parent_names
= gcc_xo_gpll0_gpll1a_sleep
,
792 .ops
= &clk_rcg2_ops
,
796 static struct clk_rcg2 camss_gp1_clk_src
= {
800 .parent_map
= gcc_xo_gpll0_gpll1a_sleep_map
,
801 .freq_tbl
= ftbl_gcc_camss_gp0_1_clk
,
802 .clkr
.hw
.init
= &(struct clk_init_data
){
803 .name
= "camss_gp1_clk_src",
804 .parent_names
= gcc_xo_gpll0_gpll1a_sleep
,
806 .ops
= &clk_rcg2_ops
,
810 static const struct freq_tbl ftbl_gcc_camss_jpeg0_clk
[] = {
811 F(133330000, P_GPLL0
, 6, 0, 0),
812 F(266670000, P_GPLL0
, 3, 0, 0),
813 F(320000000, P_GPLL0
, 2.5, 0, 0),
817 static struct clk_rcg2 jpeg0_clk_src
= {
820 .parent_map
= gcc_xo_gpll0_map
,
821 .freq_tbl
= ftbl_gcc_camss_jpeg0_clk
,
822 .clkr
.hw
.init
= &(struct clk_init_data
){
823 .name
= "jpeg0_clk_src",
824 .parent_names
= gcc_xo_gpll0
,
826 .ops
= &clk_rcg2_ops
,
830 static const struct freq_tbl ftbl_gcc_camss_mclk0_1_clk
[] = {
831 F(9600000, P_XO
, 2, 0, 0),
832 F(23880000, P_GPLL0
, 1, 2, 67),
833 F(66670000, P_GPLL0
, 12, 0, 0),
837 static struct clk_rcg2 mclk0_clk_src
= {
841 .parent_map
= gcc_xo_gpll0_gpll1a_sleep_map
,
842 .freq_tbl
= ftbl_gcc_camss_mclk0_1_clk
,
843 .clkr
.hw
.init
= &(struct clk_init_data
){
844 .name
= "mclk0_clk_src",
845 .parent_names
= gcc_xo_gpll0_gpll1a_sleep
,
847 .ops
= &clk_rcg2_ops
,
851 static struct clk_rcg2 mclk1_clk_src
= {
855 .parent_map
= gcc_xo_gpll0_gpll1a_sleep_map
,
856 .freq_tbl
= ftbl_gcc_camss_mclk0_1_clk
,
857 .clkr
.hw
.init
= &(struct clk_init_data
){
858 .name
= "mclk1_clk_src",
859 .parent_names
= gcc_xo_gpll0_gpll1a_sleep
,
861 .ops
= &clk_rcg2_ops
,
865 static const struct freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk
[] = {
866 F(100000000, P_GPLL0
, 8, 0, 0),
867 F(200000000, P_GPLL0
, 4, 0, 0),
871 static struct clk_rcg2 csi0phytimer_clk_src
= {
874 .parent_map
= gcc_xo_gpll0_gpll1a_map
,
875 .freq_tbl
= ftbl_gcc_camss_csi0_1phytimer_clk
,
876 .clkr
.hw
.init
= &(struct clk_init_data
){
877 .name
= "csi0phytimer_clk_src",
878 .parent_names
= gcc_xo_gpll0_gpll1a
,
880 .ops
= &clk_rcg2_ops
,
884 static struct clk_rcg2 csi1phytimer_clk_src
= {
887 .parent_map
= gcc_xo_gpll0_gpll1a_map
,
888 .freq_tbl
= ftbl_gcc_camss_csi0_1phytimer_clk
,
889 .clkr
.hw
.init
= &(struct clk_init_data
){
890 .name
= "csi1phytimer_clk_src",
891 .parent_names
= gcc_xo_gpll0_gpll1a
,
893 .ops
= &clk_rcg2_ops
,
897 static const struct freq_tbl ftbl_gcc_camss_cpp_clk
[] = {
898 F(160000000, P_GPLL0
, 5, 0, 0),
899 F(320000000, P_GPLL0
, 2.5, 0, 0),
900 F(465000000, P_GPLL2
, 2, 0, 0),
904 static struct clk_rcg2 cpp_clk_src
= {
907 .parent_map
= gcc_xo_gpll0_gpll2_map
,
908 .freq_tbl
= ftbl_gcc_camss_cpp_clk
,
909 .clkr
.hw
.init
= &(struct clk_init_data
){
910 .name
= "cpp_clk_src",
911 .parent_names
= gcc_xo_gpll0_gpll2
,
913 .ops
= &clk_rcg2_ops
,
917 static const struct freq_tbl ftbl_gcc_crypto_clk
[] = {
918 F(50000000, P_GPLL0
, 16, 0, 0),
919 F(80000000, P_GPLL0
, 10, 0, 0),
920 F(100000000, P_GPLL0
, 8, 0, 0),
921 F(160000000, P_GPLL0
, 5, 0, 0),
925 static struct clk_rcg2 crypto_clk_src
= {
928 .parent_map
= gcc_xo_gpll0_map
,
929 .freq_tbl
= ftbl_gcc_crypto_clk
,
930 .clkr
.hw
.init
= &(struct clk_init_data
){
931 .name
= "crypto_clk_src",
932 .parent_names
= gcc_xo_gpll0
,
934 .ops
= &clk_rcg2_ops
,
938 static const struct freq_tbl ftbl_gcc_gp1_3_clk
[] = {
939 F(19200000, P_XO
, 1, 0, 0),
943 static struct clk_rcg2 gp1_clk_src
= {
947 .parent_map
= gcc_xo_gpll0_gpll1a_sleep_map
,
948 .freq_tbl
= ftbl_gcc_gp1_3_clk
,
949 .clkr
.hw
.init
= &(struct clk_init_data
){
950 .name
= "gp1_clk_src",
951 .parent_names
= gcc_xo_gpll0_gpll1a_sleep
,
953 .ops
= &clk_rcg2_ops
,
957 static struct clk_rcg2 gp2_clk_src
= {
961 .parent_map
= gcc_xo_gpll0_gpll1a_sleep_map
,
962 .freq_tbl
= ftbl_gcc_gp1_3_clk
,
963 .clkr
.hw
.init
= &(struct clk_init_data
){
964 .name
= "gp2_clk_src",
965 .parent_names
= gcc_xo_gpll0_gpll1a_sleep
,
967 .ops
= &clk_rcg2_ops
,
971 static struct clk_rcg2 gp3_clk_src
= {
975 .parent_map
= gcc_xo_gpll0_gpll1a_sleep_map
,
976 .freq_tbl
= ftbl_gcc_gp1_3_clk
,
977 .clkr
.hw
.init
= &(struct clk_init_data
){
978 .name
= "gp3_clk_src",
979 .parent_names
= gcc_xo_gpll0_gpll1a_sleep
,
981 .ops
= &clk_rcg2_ops
,
985 static struct clk_rcg2 byte0_clk_src
= {
988 .parent_map
= gcc_xo_gpll0a_dsibyte_map
,
989 .clkr
.hw
.init
= &(struct clk_init_data
){
990 .name
= "byte0_clk_src",
991 .parent_names
= gcc_xo_gpll0a_dsibyte
,
993 .ops
= &clk_byte2_ops
,
994 .flags
= CLK_SET_RATE_PARENT
,
998 static const struct freq_tbl ftbl_gcc_mdss_esc0_clk
[] = {
999 F(19200000, P_XO
, 1, 0, 0),
1003 static struct clk_rcg2 esc0_clk_src
= {
1004 .cmd_rcgr
= 0x4d05c,
1006 .parent_map
= gcc_xo_dsibyte_map
,
1007 .freq_tbl
= ftbl_gcc_mdss_esc0_clk
,
1008 .clkr
.hw
.init
= &(struct clk_init_data
){
1009 .name
= "esc0_clk_src",
1010 .parent_names
= gcc_xo_dsibyte
,
1012 .ops
= &clk_rcg2_ops
,
1016 static const struct freq_tbl ftbl_gcc_mdss_mdp_clk
[] = {
1017 F(50000000, P_GPLL0
, 16, 0, 0),
1018 F(80000000, P_GPLL0
, 10, 0, 0),
1019 F(100000000, P_GPLL0
, 8, 0, 0),
1020 F(160000000, P_GPLL0
, 5, 0, 0),
1021 F(177780000, P_GPLL0
, 4.5, 0, 0),
1022 F(200000000, P_GPLL0
, 4, 0, 0),
1023 F(266670000, P_GPLL0
, 3, 0, 0),
1024 F(320000000, P_GPLL0
, 2.5, 0, 0),
1028 static struct clk_rcg2 mdp_clk_src
= {
1029 .cmd_rcgr
= 0x4d014,
1031 .parent_map
= gcc_xo_gpll0_dsiphy_map
,
1032 .freq_tbl
= ftbl_gcc_mdss_mdp_clk
,
1033 .clkr
.hw
.init
= &(struct clk_init_data
){
1034 .name
= "mdp_clk_src",
1035 .parent_names
= gcc_xo_gpll0_dsiphy
,
1037 .ops
= &clk_rcg2_ops
,
1041 static struct clk_rcg2 pclk0_clk_src
= {
1042 .cmd_rcgr
= 0x4d000,
1045 .parent_map
= gcc_xo_gpll0a_dsiphy_map
,
1046 .clkr
.hw
.init
= &(struct clk_init_data
){
1047 .name
= "pclk0_clk_src",
1048 .parent_names
= gcc_xo_gpll0a_dsiphy
,
1050 .ops
= &clk_pixel_ops
,
1051 .flags
= CLK_SET_RATE_PARENT
,
1055 static const struct freq_tbl ftbl_gcc_mdss_vsync_clk
[] = {
1056 F(19200000, P_XO
, 1, 0, 0),
1060 static struct clk_rcg2 vsync_clk_src
= {
1061 .cmd_rcgr
= 0x4d02c,
1063 .parent_map
= gcc_xo_gpll0a_map
,
1064 .freq_tbl
= ftbl_gcc_mdss_vsync_clk
,
1065 .clkr
.hw
.init
= &(struct clk_init_data
){
1066 .name
= "vsync_clk_src",
1067 .parent_names
= gcc_xo_gpll0a
,
1069 .ops
= &clk_rcg2_ops
,
1073 static const struct freq_tbl ftbl_gcc_pdm2_clk
[] = {
1074 F(64000000, P_GPLL0
, 12.5, 0, 0),
1078 static struct clk_rcg2 pdm2_clk_src
= {
1079 .cmd_rcgr
= 0x44010,
1081 .parent_map
= gcc_xo_gpll0_map
,
1082 .freq_tbl
= ftbl_gcc_pdm2_clk
,
1083 .clkr
.hw
.init
= &(struct clk_init_data
){
1084 .name
= "pdm2_clk_src",
1085 .parent_names
= gcc_xo_gpll0
,
1087 .ops
= &clk_rcg2_ops
,
1091 static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk
[] = {
1092 F(144000, P_XO
, 16, 3, 25),
1093 F(400000, P_XO
, 12, 1, 4),
1094 F(20000000, P_GPLL0
, 10, 1, 4),
1095 F(25000000, P_GPLL0
, 16, 1, 2),
1096 F(50000000, P_GPLL0
, 16, 0, 0),
1097 F(100000000, P_GPLL0
, 8, 0, 0),
1098 F(177770000, P_GPLL0
, 4.5, 0, 0),
1102 static struct clk_rcg2 sdcc1_apps_clk_src
= {
1103 .cmd_rcgr
= 0x42004,
1106 .parent_map
= gcc_xo_gpll0_map
,
1107 .freq_tbl
= ftbl_gcc_sdcc1_apps_clk
,
1108 .clkr
.hw
.init
= &(struct clk_init_data
){
1109 .name
= "sdcc1_apps_clk_src",
1110 .parent_names
= gcc_xo_gpll0
,
1112 .ops
= &clk_rcg2_floor_ops
,
1116 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk
[] = {
1117 F(144000, P_XO
, 16, 3, 25),
1118 F(400000, P_XO
, 12, 1, 4),
1119 F(20000000, P_GPLL0
, 10, 1, 4),
1120 F(25000000, P_GPLL0
, 16, 1, 2),
1121 F(50000000, P_GPLL0
, 16, 0, 0),
1122 F(100000000, P_GPLL0
, 8, 0, 0),
1123 F(200000000, P_GPLL0
, 4, 0, 0),
1127 static struct clk_rcg2 sdcc2_apps_clk_src
= {
1128 .cmd_rcgr
= 0x43004,
1131 .parent_map
= gcc_xo_gpll0_map
,
1132 .freq_tbl
= ftbl_gcc_sdcc2_apps_clk
,
1133 .clkr
.hw
.init
= &(struct clk_init_data
){
1134 .name
= "sdcc2_apps_clk_src",
1135 .parent_names
= gcc_xo_gpll0
,
1137 .ops
= &clk_rcg2_floor_ops
,
1141 static const struct freq_tbl ftbl_gcc_apss_tcu_clk
[] = {
1142 F(155000000, P_GPLL2
, 6, 0, 0),
1143 F(310000000, P_GPLL2
, 3, 0, 0),
1144 F(400000000, P_GPLL0
, 2, 0, 0),
1148 static struct clk_rcg2 apss_tcu_clk_src
= {
1149 .cmd_rcgr
= 0x1207c,
1151 .parent_map
= gcc_xo_gpll0a_gpll1_gpll2_map
,
1152 .freq_tbl
= ftbl_gcc_apss_tcu_clk
,
1153 .clkr
.hw
.init
= &(struct clk_init_data
){
1154 .name
= "apss_tcu_clk_src",
1155 .parent_names
= gcc_xo_gpll0a_gpll1_gpll2
,
1157 .ops
= &clk_rcg2_ops
,
1161 static const struct freq_tbl ftbl_gcc_bimc_gpu_clk
[] = {
1162 F(19200000, P_XO
, 1, 0, 0),
1163 F(100000000, P_GPLL0
, 8, 0, 0),
1164 F(200000000, P_GPLL0
, 4, 0, 0),
1165 F(266500000, P_BIMC
, 4, 0, 0),
1166 F(400000000, P_GPLL0
, 2, 0, 0),
1167 F(533000000, P_BIMC
, 2, 0, 0),
1171 static struct clk_rcg2 bimc_gpu_clk_src
= {
1172 .cmd_rcgr
= 0x31028,
1174 .parent_map
= gcc_xo_gpll0_bimc_map
,
1175 .freq_tbl
= ftbl_gcc_bimc_gpu_clk
,
1176 .clkr
.hw
.init
= &(struct clk_init_data
){
1177 .name
= "bimc_gpu_clk_src",
1178 .parent_names
= gcc_xo_gpll0_bimc
,
1180 .flags
= CLK_GET_RATE_NOCACHE
,
1181 .ops
= &clk_rcg2_ops
,
1185 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk
[] = {
1186 F(80000000, P_GPLL0
, 10, 0, 0),
1190 static struct clk_rcg2 usb_hs_system_clk_src
= {
1191 .cmd_rcgr
= 0x41010,
1193 .parent_map
= gcc_xo_gpll0_map
,
1194 .freq_tbl
= ftbl_gcc_usb_hs_system_clk
,
1195 .clkr
.hw
.init
= &(struct clk_init_data
){
1196 .name
= "usb_hs_system_clk_src",
1197 .parent_names
= gcc_xo_gpll0
,
1199 .ops
= &clk_rcg2_ops
,
1203 static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk
[] = {
1204 F(3200000, P_XO
, 6, 0, 0),
1205 F(6400000, P_XO
, 3, 0, 0),
1206 F(9600000, P_XO
, 2, 0, 0),
1207 F(19200000, P_XO
, 1, 0, 0),
1208 F(40000000, P_GPLL0
, 10, 1, 2),
1209 F(66670000, P_GPLL0
, 12, 0, 0),
1210 F(80000000, P_GPLL0
, 10, 0, 0),
1211 F(100000000, P_GPLL0
, 8, 0, 0),
1215 static struct clk_rcg2 ultaudio_ahbfabric_clk_src
= {
1216 .cmd_rcgr
= 0x1c010,
1219 .parent_map
= gcc_xo_gpll0_gpll1_sleep_map
,
1220 .freq_tbl
= ftbl_gcc_ultaudio_ahb_clk
,
1221 .clkr
.hw
.init
= &(struct clk_init_data
){
1222 .name
= "ultaudio_ahbfabric_clk_src",
1223 .parent_names
= gcc_xo_gpll0_gpll1_sleep
,
1225 .ops
= &clk_rcg2_ops
,
1229 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk
= {
1230 .halt_reg
= 0x1c028,
1232 .enable_reg
= 0x1c028,
1233 .enable_mask
= BIT(0),
1234 .hw
.init
= &(struct clk_init_data
){
1235 .name
= "gcc_ultaudio_ahbfabric_ixfabric_clk",
1236 .parent_names
= (const char *[]){
1237 "ultaudio_ahbfabric_clk_src",
1240 .flags
= CLK_SET_RATE_PARENT
,
1241 .ops
= &clk_branch2_ops
,
1246 static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk
= {
1247 .halt_reg
= 0x1c024,
1249 .enable_reg
= 0x1c024,
1250 .enable_mask
= BIT(0),
1251 .hw
.init
= &(struct clk_init_data
){
1252 .name
= "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
1253 .parent_names
= (const char *[]){
1254 "ultaudio_ahbfabric_clk_src",
1257 .flags
= CLK_SET_RATE_PARENT
,
1258 .ops
= &clk_branch2_ops
,
1263 static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk
[] = {
1264 F(128000, P_XO
, 10, 1, 15),
1265 F(256000, P_XO
, 5, 1, 15),
1266 F(384000, P_XO
, 5, 1, 10),
1267 F(512000, P_XO
, 5, 2, 15),
1268 F(576000, P_XO
, 5, 3, 20),
1269 F(705600, P_GPLL1
, 16, 1, 80),
1270 F(768000, P_XO
, 5, 1, 5),
1271 F(800000, P_XO
, 5, 5, 24),
1272 F(1024000, P_XO
, 5, 4, 15),
1273 F(1152000, P_XO
, 1, 3, 50),
1274 F(1411200, P_GPLL1
, 16, 1, 40),
1275 F(1536000, P_XO
, 1, 2, 25),
1276 F(1600000, P_XO
, 12, 0, 0),
1277 F(1728000, P_XO
, 5, 9, 20),
1278 F(2048000, P_XO
, 5, 8, 15),
1279 F(2304000, P_XO
, 5, 3, 5),
1280 F(2400000, P_XO
, 8, 0, 0),
1281 F(2822400, P_GPLL1
, 16, 1, 20),
1282 F(3072000, P_XO
, 5, 4, 5),
1283 F(4096000, P_GPLL1
, 9, 2, 49),
1284 F(4800000, P_XO
, 4, 0, 0),
1285 F(5644800, P_GPLL1
, 16, 1, 10),
1286 F(6144000, P_GPLL1
, 7, 1, 21),
1287 F(8192000, P_GPLL1
, 9, 4, 49),
1288 F(9600000, P_XO
, 2, 0, 0),
1289 F(11289600, P_GPLL1
, 16, 1, 5),
1290 F(12288000, P_GPLL1
, 7, 2, 21),
1294 static struct clk_rcg2 ultaudio_lpaif_pri_i2s_clk_src
= {
1295 .cmd_rcgr
= 0x1c054,
1298 .parent_map
= gcc_xo_gpll1_epi2s_emclk_sleep_map
,
1299 .freq_tbl
= ftbl_gcc_ultaudio_lpaif_i2s_clk
,
1300 .clkr
.hw
.init
= &(struct clk_init_data
){
1301 .name
= "ultaudio_lpaif_pri_i2s_clk_src",
1302 .parent_names
= gcc_xo_gpll1_epi2s_emclk_sleep
,
1304 .ops
= &clk_rcg2_ops
,
1308 static struct clk_branch gcc_ultaudio_lpaif_pri_i2s_clk
= {
1309 .halt_reg
= 0x1c068,
1311 .enable_reg
= 0x1c068,
1312 .enable_mask
= BIT(0),
1313 .hw
.init
= &(struct clk_init_data
){
1314 .name
= "gcc_ultaudio_lpaif_pri_i2s_clk",
1315 .parent_names
= (const char *[]){
1316 "ultaudio_lpaif_pri_i2s_clk_src",
1319 .flags
= CLK_SET_RATE_PARENT
,
1320 .ops
= &clk_branch2_ops
,
1325 static struct clk_rcg2 ultaudio_lpaif_sec_i2s_clk_src
= {
1326 .cmd_rcgr
= 0x1c06c,
1329 .parent_map
= gcc_xo_gpll1_esi2s_emclk_sleep_map
,
1330 .freq_tbl
= ftbl_gcc_ultaudio_lpaif_i2s_clk
,
1331 .clkr
.hw
.init
= &(struct clk_init_data
){
1332 .name
= "ultaudio_lpaif_sec_i2s_clk_src",
1333 .parent_names
= gcc_xo_gpll1_esi2s_emclk_sleep
,
1335 .ops
= &clk_rcg2_ops
,
1339 static struct clk_branch gcc_ultaudio_lpaif_sec_i2s_clk
= {
1340 .halt_reg
= 0x1c080,
1342 .enable_reg
= 0x1c080,
1343 .enable_mask
= BIT(0),
1344 .hw
.init
= &(struct clk_init_data
){
1345 .name
= "gcc_ultaudio_lpaif_sec_i2s_clk",
1346 .parent_names
= (const char *[]){
1347 "ultaudio_lpaif_sec_i2s_clk_src",
1350 .flags
= CLK_SET_RATE_PARENT
,
1351 .ops
= &clk_branch2_ops
,
1356 static struct clk_rcg2 ultaudio_lpaif_aux_i2s_clk_src
= {
1357 .cmd_rcgr
= 0x1c084,
1360 .parent_map
= gcc_xo_gpll1_emclk_sleep_map
,
1361 .freq_tbl
= ftbl_gcc_ultaudio_lpaif_i2s_clk
,
1362 .clkr
.hw
.init
= &(struct clk_init_data
){
1363 .name
= "ultaudio_lpaif_aux_i2s_clk_src",
1364 .parent_names
= gcc_xo_gpll1_esi2s_emclk_sleep
,
1366 .ops
= &clk_rcg2_ops
,
1370 static struct clk_branch gcc_ultaudio_lpaif_aux_i2s_clk
= {
1371 .halt_reg
= 0x1c098,
1373 .enable_reg
= 0x1c098,
1374 .enable_mask
= BIT(0),
1375 .hw
.init
= &(struct clk_init_data
){
1376 .name
= "gcc_ultaudio_lpaif_aux_i2s_clk",
1377 .parent_names
= (const char *[]){
1378 "ultaudio_lpaif_aux_i2s_clk_src",
1381 .flags
= CLK_SET_RATE_PARENT
,
1382 .ops
= &clk_branch2_ops
,
1387 static const struct freq_tbl ftbl_gcc_ultaudio_xo_clk
[] = {
1388 F(19200000, P_XO
, 1, 0, 0),
1392 static struct clk_rcg2 ultaudio_xo_clk_src
= {
1393 .cmd_rcgr
= 0x1c034,
1395 .parent_map
= gcc_xo_sleep_map
,
1396 .freq_tbl
= ftbl_gcc_ultaudio_xo_clk
,
1397 .clkr
.hw
.init
= &(struct clk_init_data
){
1398 .name
= "ultaudio_xo_clk_src",
1399 .parent_names
= gcc_xo_sleep
,
1401 .ops
= &clk_rcg2_ops
,
1405 static struct clk_branch gcc_ultaudio_avsync_xo_clk
= {
1406 .halt_reg
= 0x1c04c,
1408 .enable_reg
= 0x1c04c,
1409 .enable_mask
= BIT(0),
1410 .hw
.init
= &(struct clk_init_data
){
1411 .name
= "gcc_ultaudio_avsync_xo_clk",
1412 .parent_names
= (const char *[]){
1413 "ultaudio_xo_clk_src",
1416 .flags
= CLK_SET_RATE_PARENT
,
1417 .ops
= &clk_branch2_ops
,
1422 static struct clk_branch gcc_ultaudio_stc_xo_clk
= {
1423 .halt_reg
= 0x1c050,
1425 .enable_reg
= 0x1c050,
1426 .enable_mask
= BIT(0),
1427 .hw
.init
= &(struct clk_init_data
){
1428 .name
= "gcc_ultaudio_stc_xo_clk",
1429 .parent_names
= (const char *[]){
1430 "ultaudio_xo_clk_src",
1433 .flags
= CLK_SET_RATE_PARENT
,
1434 .ops
= &clk_branch2_ops
,
1439 static const struct freq_tbl ftbl_codec_clk
[] = {
1440 F(9600000, P_XO
, 2, 0, 0),
1441 F(12288000, P_XO
, 1, 16, 25),
1442 F(19200000, P_XO
, 1, 0, 0),
1443 F(11289600, P_EXT_MCLK
, 1, 0, 0),
1447 static struct clk_rcg2 codec_digcodec_clk_src
= {
1448 .cmd_rcgr
= 0x1c09c,
1451 .parent_map
= gcc_xo_gpll1_emclk_sleep_map
,
1452 .freq_tbl
= ftbl_codec_clk
,
1453 .clkr
.hw
.init
= &(struct clk_init_data
){
1454 .name
= "codec_digcodec_clk_src",
1455 .parent_names
= gcc_xo_gpll1_emclk_sleep
,
1457 .ops
= &clk_rcg2_ops
,
1461 static struct clk_branch gcc_codec_digcodec_clk
= {
1462 .halt_reg
= 0x1c0b0,
1464 .enable_reg
= 0x1c0b0,
1465 .enable_mask
= BIT(0),
1466 .hw
.init
= &(struct clk_init_data
){
1467 .name
= "gcc_ultaudio_codec_digcodec_clk",
1468 .parent_names
= (const char *[]){
1469 "codec_digcodec_clk_src",
1472 .flags
= CLK_SET_RATE_PARENT
,
1473 .ops
= &clk_branch2_ops
,
1478 static struct clk_branch gcc_ultaudio_pcnoc_mport_clk
= {
1479 .halt_reg
= 0x1c000,
1481 .enable_reg
= 0x1c000,
1482 .enable_mask
= BIT(0),
1483 .hw
.init
= &(struct clk_init_data
){
1484 .name
= "gcc_ultaudio_pcnoc_mport_clk",
1485 .parent_names
= (const char *[]){
1486 "pcnoc_bfdcd_clk_src",
1489 .ops
= &clk_branch2_ops
,
1494 static struct clk_branch gcc_ultaudio_pcnoc_sway_clk
= {
1495 .halt_reg
= 0x1c004,
1497 .enable_reg
= 0x1c004,
1498 .enable_mask
= BIT(0),
1499 .hw
.init
= &(struct clk_init_data
){
1500 .name
= "gcc_ultaudio_pcnoc_sway_clk",
1501 .parent_names
= (const char *[]){
1502 "pcnoc_bfdcd_clk_src",
1505 .ops
= &clk_branch2_ops
,
1510 static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk
[] = {
1511 F(100000000, P_GPLL0
, 8, 0, 0),
1512 F(160000000, P_GPLL0
, 5, 0, 0),
1513 F(228570000, P_GPLL0
, 3.5, 0, 0),
1517 static struct clk_rcg2 vcodec0_clk_src
= {
1518 .cmd_rcgr
= 0x4C000,
1521 .parent_map
= gcc_xo_gpll0_map
,
1522 .freq_tbl
= ftbl_gcc_venus0_vcodec0_clk
,
1523 .clkr
.hw
.init
= &(struct clk_init_data
){
1524 .name
= "vcodec0_clk_src",
1525 .parent_names
= gcc_xo_gpll0
,
1527 .ops
= &clk_rcg2_ops
,
1531 static struct clk_branch gcc_blsp1_ahb_clk
= {
1532 .halt_reg
= 0x01008,
1533 .halt_check
= BRANCH_HALT_VOTED
,
1535 .enable_reg
= 0x45004,
1536 .enable_mask
= BIT(10),
1537 .hw
.init
= &(struct clk_init_data
){
1538 .name
= "gcc_blsp1_ahb_clk",
1539 .parent_names
= (const char *[]){
1540 "pcnoc_bfdcd_clk_src",
1543 .ops
= &clk_branch2_ops
,
1548 static struct clk_branch gcc_blsp1_sleep_clk
= {
1549 .halt_reg
= 0x01004,
1551 .enable_reg
= 0x01004,
1552 .enable_mask
= BIT(0),
1553 .hw
.init
= &(struct clk_init_data
){
1554 .name
= "gcc_blsp1_sleep_clk",
1555 .parent_names
= (const char *[]){
1559 .flags
= CLK_SET_RATE_PARENT
,
1560 .ops
= &clk_branch2_ops
,
1565 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk
= {
1566 .halt_reg
= 0x02008,
1568 .enable_reg
= 0x02008,
1569 .enable_mask
= BIT(0),
1570 .hw
.init
= &(struct clk_init_data
){
1571 .name
= "gcc_blsp1_qup1_i2c_apps_clk",
1572 .parent_names
= (const char *[]){
1573 "blsp1_qup1_i2c_apps_clk_src",
1576 .flags
= CLK_SET_RATE_PARENT
,
1577 .ops
= &clk_branch2_ops
,
1582 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk
= {
1583 .halt_reg
= 0x02004,
1585 .enable_reg
= 0x02004,
1586 .enable_mask
= BIT(0),
1587 .hw
.init
= &(struct clk_init_data
){
1588 .name
= "gcc_blsp1_qup1_spi_apps_clk",
1589 .parent_names
= (const char *[]){
1590 "blsp1_qup1_spi_apps_clk_src",
1593 .flags
= CLK_SET_RATE_PARENT
,
1594 .ops
= &clk_branch2_ops
,
1599 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk
= {
1600 .halt_reg
= 0x03010,
1602 .enable_reg
= 0x03010,
1603 .enable_mask
= BIT(0),
1604 .hw
.init
= &(struct clk_init_data
){
1605 .name
= "gcc_blsp1_qup2_i2c_apps_clk",
1606 .parent_names
= (const char *[]){
1607 "blsp1_qup2_i2c_apps_clk_src",
1610 .flags
= CLK_SET_RATE_PARENT
,
1611 .ops
= &clk_branch2_ops
,
1616 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk
= {
1617 .halt_reg
= 0x0300c,
1619 .enable_reg
= 0x0300c,
1620 .enable_mask
= BIT(0),
1621 .hw
.init
= &(struct clk_init_data
){
1622 .name
= "gcc_blsp1_qup2_spi_apps_clk",
1623 .parent_names
= (const char *[]){
1624 "blsp1_qup2_spi_apps_clk_src",
1627 .flags
= CLK_SET_RATE_PARENT
,
1628 .ops
= &clk_branch2_ops
,
1633 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk
= {
1634 .halt_reg
= 0x04020,
1636 .enable_reg
= 0x04020,
1637 .enable_mask
= BIT(0),
1638 .hw
.init
= &(struct clk_init_data
){
1639 .name
= "gcc_blsp1_qup3_i2c_apps_clk",
1640 .parent_names
= (const char *[]){
1641 "blsp1_qup3_i2c_apps_clk_src",
1644 .flags
= CLK_SET_RATE_PARENT
,
1645 .ops
= &clk_branch2_ops
,
1650 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk
= {
1651 .halt_reg
= 0x0401c,
1653 .enable_reg
= 0x0401c,
1654 .enable_mask
= BIT(0),
1655 .hw
.init
= &(struct clk_init_data
){
1656 .name
= "gcc_blsp1_qup3_spi_apps_clk",
1657 .parent_names
= (const char *[]){
1658 "blsp1_qup3_spi_apps_clk_src",
1661 .flags
= CLK_SET_RATE_PARENT
,
1662 .ops
= &clk_branch2_ops
,
1667 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk
= {
1668 .halt_reg
= 0x05020,
1670 .enable_reg
= 0x05020,
1671 .enable_mask
= BIT(0),
1672 .hw
.init
= &(struct clk_init_data
){
1673 .name
= "gcc_blsp1_qup4_i2c_apps_clk",
1674 .parent_names
= (const char *[]){
1675 "blsp1_qup4_i2c_apps_clk_src",
1678 .flags
= CLK_SET_RATE_PARENT
,
1679 .ops
= &clk_branch2_ops
,
1684 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk
= {
1685 .halt_reg
= 0x0501c,
1687 .enable_reg
= 0x0501c,
1688 .enable_mask
= BIT(0),
1689 .hw
.init
= &(struct clk_init_data
){
1690 .name
= "gcc_blsp1_qup4_spi_apps_clk",
1691 .parent_names
= (const char *[]){
1692 "blsp1_qup4_spi_apps_clk_src",
1695 .flags
= CLK_SET_RATE_PARENT
,
1696 .ops
= &clk_branch2_ops
,
1701 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk
= {
1702 .halt_reg
= 0x06020,
1704 .enable_reg
= 0x06020,
1705 .enable_mask
= BIT(0),
1706 .hw
.init
= &(struct clk_init_data
){
1707 .name
= "gcc_blsp1_qup5_i2c_apps_clk",
1708 .parent_names
= (const char *[]){
1709 "blsp1_qup5_i2c_apps_clk_src",
1712 .flags
= CLK_SET_RATE_PARENT
,
1713 .ops
= &clk_branch2_ops
,
1718 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk
= {
1719 .halt_reg
= 0x0601c,
1721 .enable_reg
= 0x0601c,
1722 .enable_mask
= BIT(0),
1723 .hw
.init
= &(struct clk_init_data
){
1724 .name
= "gcc_blsp1_qup5_spi_apps_clk",
1725 .parent_names
= (const char *[]){
1726 "blsp1_qup5_spi_apps_clk_src",
1729 .flags
= CLK_SET_RATE_PARENT
,
1730 .ops
= &clk_branch2_ops
,
1735 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk
= {
1736 .halt_reg
= 0x07020,
1738 .enable_reg
= 0x07020,
1739 .enable_mask
= BIT(0),
1740 .hw
.init
= &(struct clk_init_data
){
1741 .name
= "gcc_blsp1_qup6_i2c_apps_clk",
1742 .parent_names
= (const char *[]){
1743 "blsp1_qup6_i2c_apps_clk_src",
1746 .flags
= CLK_SET_RATE_PARENT
,
1747 .ops
= &clk_branch2_ops
,
1752 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk
= {
1753 .halt_reg
= 0x0701c,
1755 .enable_reg
= 0x0701c,
1756 .enable_mask
= BIT(0),
1757 .hw
.init
= &(struct clk_init_data
){
1758 .name
= "gcc_blsp1_qup6_spi_apps_clk",
1759 .parent_names
= (const char *[]){
1760 "blsp1_qup6_spi_apps_clk_src",
1763 .flags
= CLK_SET_RATE_PARENT
,
1764 .ops
= &clk_branch2_ops
,
1769 static struct clk_branch gcc_blsp1_uart1_apps_clk
= {
1770 .halt_reg
= 0x0203c,
1772 .enable_reg
= 0x0203c,
1773 .enable_mask
= BIT(0),
1774 .hw
.init
= &(struct clk_init_data
){
1775 .name
= "gcc_blsp1_uart1_apps_clk",
1776 .parent_names
= (const char *[]){
1777 "blsp1_uart1_apps_clk_src",
1780 .flags
= CLK_SET_RATE_PARENT
,
1781 .ops
= &clk_branch2_ops
,
1786 static struct clk_branch gcc_blsp1_uart2_apps_clk
= {
1787 .halt_reg
= 0x0302c,
1789 .enable_reg
= 0x0302c,
1790 .enable_mask
= BIT(0),
1791 .hw
.init
= &(struct clk_init_data
){
1792 .name
= "gcc_blsp1_uart2_apps_clk",
1793 .parent_names
= (const char *[]){
1794 "blsp1_uart2_apps_clk_src",
1797 .flags
= CLK_SET_RATE_PARENT
,
1798 .ops
= &clk_branch2_ops
,
1803 static struct clk_branch gcc_boot_rom_ahb_clk
= {
1804 .halt_reg
= 0x1300c,
1805 .halt_check
= BRANCH_HALT_VOTED
,
1807 .enable_reg
= 0x45004,
1808 .enable_mask
= BIT(7),
1809 .hw
.init
= &(struct clk_init_data
){
1810 .name
= "gcc_boot_rom_ahb_clk",
1811 .parent_names
= (const char *[]){
1812 "pcnoc_bfdcd_clk_src",
1815 .ops
= &clk_branch2_ops
,
1820 static struct clk_branch gcc_camss_cci_ahb_clk
= {
1821 .halt_reg
= 0x5101c,
1823 .enable_reg
= 0x5101c,
1824 .enable_mask
= BIT(0),
1825 .hw
.init
= &(struct clk_init_data
){
1826 .name
= "gcc_camss_cci_ahb_clk",
1827 .parent_names
= (const char *[]){
1828 "camss_ahb_clk_src",
1831 .flags
= CLK_SET_RATE_PARENT
,
1832 .ops
= &clk_branch2_ops
,
1837 static struct clk_branch gcc_camss_cci_clk
= {
1838 .halt_reg
= 0x51018,
1840 .enable_reg
= 0x51018,
1841 .enable_mask
= BIT(0),
1842 .hw
.init
= &(struct clk_init_data
){
1843 .name
= "gcc_camss_cci_clk",
1844 .parent_names
= (const char *[]){
1848 .flags
= CLK_SET_RATE_PARENT
,
1849 .ops
= &clk_branch2_ops
,
1854 static struct clk_branch gcc_camss_csi0_ahb_clk
= {
1855 .halt_reg
= 0x4e040,
1857 .enable_reg
= 0x4e040,
1858 .enable_mask
= BIT(0),
1859 .hw
.init
= &(struct clk_init_data
){
1860 .name
= "gcc_camss_csi0_ahb_clk",
1861 .parent_names
= (const char *[]){
1862 "camss_ahb_clk_src",
1865 .flags
= CLK_SET_RATE_PARENT
,
1866 .ops
= &clk_branch2_ops
,
1871 static struct clk_branch gcc_camss_csi0_clk
= {
1872 .halt_reg
= 0x4e03c,
1874 .enable_reg
= 0x4e03c,
1875 .enable_mask
= BIT(0),
1876 .hw
.init
= &(struct clk_init_data
){
1877 .name
= "gcc_camss_csi0_clk",
1878 .parent_names
= (const char *[]){
1882 .flags
= CLK_SET_RATE_PARENT
,
1883 .ops
= &clk_branch2_ops
,
1888 static struct clk_branch gcc_camss_csi0phy_clk
= {
1889 .halt_reg
= 0x4e048,
1891 .enable_reg
= 0x4e048,
1892 .enable_mask
= BIT(0),
1893 .hw
.init
= &(struct clk_init_data
){
1894 .name
= "gcc_camss_csi0phy_clk",
1895 .parent_names
= (const char *[]){
1899 .flags
= CLK_SET_RATE_PARENT
,
1900 .ops
= &clk_branch2_ops
,
1905 static struct clk_branch gcc_camss_csi0pix_clk
= {
1906 .halt_reg
= 0x4e058,
1908 .enable_reg
= 0x4e058,
1909 .enable_mask
= BIT(0),
1910 .hw
.init
= &(struct clk_init_data
){
1911 .name
= "gcc_camss_csi0pix_clk",
1912 .parent_names
= (const char *[]){
1916 .flags
= CLK_SET_RATE_PARENT
,
1917 .ops
= &clk_branch2_ops
,
1922 static struct clk_branch gcc_camss_csi0rdi_clk
= {
1923 .halt_reg
= 0x4e050,
1925 .enable_reg
= 0x4e050,
1926 .enable_mask
= BIT(0),
1927 .hw
.init
= &(struct clk_init_data
){
1928 .name
= "gcc_camss_csi0rdi_clk",
1929 .parent_names
= (const char *[]){
1933 .flags
= CLK_SET_RATE_PARENT
,
1934 .ops
= &clk_branch2_ops
,
1939 static struct clk_branch gcc_camss_csi1_ahb_clk
= {
1940 .halt_reg
= 0x4f040,
1942 .enable_reg
= 0x4f040,
1943 .enable_mask
= BIT(0),
1944 .hw
.init
= &(struct clk_init_data
){
1945 .name
= "gcc_camss_csi1_ahb_clk",
1946 .parent_names
= (const char *[]){
1947 "camss_ahb_clk_src",
1950 .flags
= CLK_SET_RATE_PARENT
,
1951 .ops
= &clk_branch2_ops
,
1956 static struct clk_branch gcc_camss_csi1_clk
= {
1957 .halt_reg
= 0x4f03c,
1959 .enable_reg
= 0x4f03c,
1960 .enable_mask
= BIT(0),
1961 .hw
.init
= &(struct clk_init_data
){
1962 .name
= "gcc_camss_csi1_clk",
1963 .parent_names
= (const char *[]){
1967 .flags
= CLK_SET_RATE_PARENT
,
1968 .ops
= &clk_branch2_ops
,
1973 static struct clk_branch gcc_camss_csi1phy_clk
= {
1974 .halt_reg
= 0x4f048,
1976 .enable_reg
= 0x4f048,
1977 .enable_mask
= BIT(0),
1978 .hw
.init
= &(struct clk_init_data
){
1979 .name
= "gcc_camss_csi1phy_clk",
1980 .parent_names
= (const char *[]){
1984 .flags
= CLK_SET_RATE_PARENT
,
1985 .ops
= &clk_branch2_ops
,
1990 static struct clk_branch gcc_camss_csi1pix_clk
= {
1991 .halt_reg
= 0x4f058,
1993 .enable_reg
= 0x4f058,
1994 .enable_mask
= BIT(0),
1995 .hw
.init
= &(struct clk_init_data
){
1996 .name
= "gcc_camss_csi1pix_clk",
1997 .parent_names
= (const char *[]){
2001 .flags
= CLK_SET_RATE_PARENT
,
2002 .ops
= &clk_branch2_ops
,
2007 static struct clk_branch gcc_camss_csi1rdi_clk
= {
2008 .halt_reg
= 0x4f050,
2010 .enable_reg
= 0x4f050,
2011 .enable_mask
= BIT(0),
2012 .hw
.init
= &(struct clk_init_data
){
2013 .name
= "gcc_camss_csi1rdi_clk",
2014 .parent_names
= (const char *[]){
2018 .flags
= CLK_SET_RATE_PARENT
,
2019 .ops
= &clk_branch2_ops
,
2024 static struct clk_branch gcc_camss_csi_vfe0_clk
= {
2025 .halt_reg
= 0x58050,
2027 .enable_reg
= 0x58050,
2028 .enable_mask
= BIT(0),
2029 .hw
.init
= &(struct clk_init_data
){
2030 .name
= "gcc_camss_csi_vfe0_clk",
2031 .parent_names
= (const char *[]){
2035 .flags
= CLK_SET_RATE_PARENT
,
2036 .ops
= &clk_branch2_ops
,
2041 static struct clk_branch gcc_camss_gp0_clk
= {
2042 .halt_reg
= 0x54018,
2044 .enable_reg
= 0x54018,
2045 .enable_mask
= BIT(0),
2046 .hw
.init
= &(struct clk_init_data
){
2047 .name
= "gcc_camss_gp0_clk",
2048 .parent_names
= (const char *[]){
2049 "camss_gp0_clk_src",
2052 .flags
= CLK_SET_RATE_PARENT
,
2053 .ops
= &clk_branch2_ops
,
2058 static struct clk_branch gcc_camss_gp1_clk
= {
2059 .halt_reg
= 0x55018,
2061 .enable_reg
= 0x55018,
2062 .enable_mask
= BIT(0),
2063 .hw
.init
= &(struct clk_init_data
){
2064 .name
= "gcc_camss_gp1_clk",
2065 .parent_names
= (const char *[]){
2066 "camss_gp1_clk_src",
2069 .flags
= CLK_SET_RATE_PARENT
,
2070 .ops
= &clk_branch2_ops
,
2075 static struct clk_branch gcc_camss_ispif_ahb_clk
= {
2076 .halt_reg
= 0x50004,
2078 .enable_reg
= 0x50004,
2079 .enable_mask
= BIT(0),
2080 .hw
.init
= &(struct clk_init_data
){
2081 .name
= "gcc_camss_ispif_ahb_clk",
2082 .parent_names
= (const char *[]){
2083 "camss_ahb_clk_src",
2086 .flags
= CLK_SET_RATE_PARENT
,
2087 .ops
= &clk_branch2_ops
,
2092 static struct clk_branch gcc_camss_jpeg0_clk
= {
2093 .halt_reg
= 0x57020,
2095 .enable_reg
= 0x57020,
2096 .enable_mask
= BIT(0),
2097 .hw
.init
= &(struct clk_init_data
){
2098 .name
= "gcc_camss_jpeg0_clk",
2099 .parent_names
= (const char *[]){
2103 .flags
= CLK_SET_RATE_PARENT
,
2104 .ops
= &clk_branch2_ops
,
2109 static struct clk_branch gcc_camss_jpeg_ahb_clk
= {
2110 .halt_reg
= 0x57024,
2112 .enable_reg
= 0x57024,
2113 .enable_mask
= BIT(0),
2114 .hw
.init
= &(struct clk_init_data
){
2115 .name
= "gcc_camss_jpeg_ahb_clk",
2116 .parent_names
= (const char *[]){
2117 "camss_ahb_clk_src",
2120 .flags
= CLK_SET_RATE_PARENT
,
2121 .ops
= &clk_branch2_ops
,
2126 static struct clk_branch gcc_camss_jpeg_axi_clk
= {
2127 .halt_reg
= 0x57028,
2129 .enable_reg
= 0x57028,
2130 .enable_mask
= BIT(0),
2131 .hw
.init
= &(struct clk_init_data
){
2132 .name
= "gcc_camss_jpeg_axi_clk",
2133 .parent_names
= (const char *[]){
2134 "system_noc_bfdcd_clk_src",
2137 .flags
= CLK_SET_RATE_PARENT
,
2138 .ops
= &clk_branch2_ops
,
2143 static struct clk_branch gcc_camss_mclk0_clk
= {
2144 .halt_reg
= 0x52018,
2146 .enable_reg
= 0x52018,
2147 .enable_mask
= BIT(0),
2148 .hw
.init
= &(struct clk_init_data
){
2149 .name
= "gcc_camss_mclk0_clk",
2150 .parent_names
= (const char *[]){
2154 .flags
= CLK_SET_RATE_PARENT
,
2155 .ops
= &clk_branch2_ops
,
2160 static struct clk_branch gcc_camss_mclk1_clk
= {
2161 .halt_reg
= 0x53018,
2163 .enable_reg
= 0x53018,
2164 .enable_mask
= BIT(0),
2165 .hw
.init
= &(struct clk_init_data
){
2166 .name
= "gcc_camss_mclk1_clk",
2167 .parent_names
= (const char *[]){
2171 .flags
= CLK_SET_RATE_PARENT
,
2172 .ops
= &clk_branch2_ops
,
2177 static struct clk_branch gcc_camss_micro_ahb_clk
= {
2178 .halt_reg
= 0x5600c,
2180 .enable_reg
= 0x5600c,
2181 .enable_mask
= BIT(0),
2182 .hw
.init
= &(struct clk_init_data
){
2183 .name
= "gcc_camss_micro_ahb_clk",
2184 .parent_names
= (const char *[]){
2185 "camss_ahb_clk_src",
2188 .flags
= CLK_SET_RATE_PARENT
,
2189 .ops
= &clk_branch2_ops
,
2194 static struct clk_branch gcc_camss_csi0phytimer_clk
= {
2195 .halt_reg
= 0x4e01c,
2197 .enable_reg
= 0x4e01c,
2198 .enable_mask
= BIT(0),
2199 .hw
.init
= &(struct clk_init_data
){
2200 .name
= "gcc_camss_csi0phytimer_clk",
2201 .parent_names
= (const char *[]){
2202 "csi0phytimer_clk_src",
2205 .flags
= CLK_SET_RATE_PARENT
,
2206 .ops
= &clk_branch2_ops
,
2211 static struct clk_branch gcc_camss_csi1phytimer_clk
= {
2212 .halt_reg
= 0x4f01c,
2214 .enable_reg
= 0x4f01c,
2215 .enable_mask
= BIT(0),
2216 .hw
.init
= &(struct clk_init_data
){
2217 .name
= "gcc_camss_csi1phytimer_clk",
2218 .parent_names
= (const char *[]){
2219 "csi1phytimer_clk_src",
2222 .flags
= CLK_SET_RATE_PARENT
,
2223 .ops
= &clk_branch2_ops
,
2228 static struct clk_branch gcc_camss_ahb_clk
= {
2229 .halt_reg
= 0x5a014,
2231 .enable_reg
= 0x5a014,
2232 .enable_mask
= BIT(0),
2233 .hw
.init
= &(struct clk_init_data
){
2234 .name
= "gcc_camss_ahb_clk",
2235 .parent_names
= (const char *[]){
2236 "camss_ahb_clk_src",
2239 .flags
= CLK_SET_RATE_PARENT
,
2240 .ops
= &clk_branch2_ops
,
2245 static struct clk_branch gcc_camss_top_ahb_clk
= {
2246 .halt_reg
= 0x56004,
2248 .enable_reg
= 0x56004,
2249 .enable_mask
= BIT(0),
2250 .hw
.init
= &(struct clk_init_data
){
2251 .name
= "gcc_camss_top_ahb_clk",
2252 .parent_names
= (const char *[]){
2253 "pcnoc_bfdcd_clk_src",
2256 .flags
= CLK_SET_RATE_PARENT
,
2257 .ops
= &clk_branch2_ops
,
2262 static struct clk_branch gcc_camss_cpp_ahb_clk
= {
2263 .halt_reg
= 0x58040,
2265 .enable_reg
= 0x58040,
2266 .enable_mask
= BIT(0),
2267 .hw
.init
= &(struct clk_init_data
){
2268 .name
= "gcc_camss_cpp_ahb_clk",
2269 .parent_names
= (const char *[]){
2270 "camss_ahb_clk_src",
2273 .flags
= CLK_SET_RATE_PARENT
,
2274 .ops
= &clk_branch2_ops
,
2279 static struct clk_branch gcc_camss_cpp_clk
= {
2280 .halt_reg
= 0x5803c,
2282 .enable_reg
= 0x5803c,
2283 .enable_mask
= BIT(0),
2284 .hw
.init
= &(struct clk_init_data
){
2285 .name
= "gcc_camss_cpp_clk",
2286 .parent_names
= (const char *[]){
2290 .flags
= CLK_SET_RATE_PARENT
,
2291 .ops
= &clk_branch2_ops
,
2296 static struct clk_branch gcc_camss_vfe0_clk
= {
2297 .halt_reg
= 0x58038,
2299 .enable_reg
= 0x58038,
2300 .enable_mask
= BIT(0),
2301 .hw
.init
= &(struct clk_init_data
){
2302 .name
= "gcc_camss_vfe0_clk",
2303 .parent_names
= (const char *[]){
2307 .flags
= CLK_SET_RATE_PARENT
,
2308 .ops
= &clk_branch2_ops
,
2313 static struct clk_branch gcc_camss_vfe_ahb_clk
= {
2314 .halt_reg
= 0x58044,
2316 .enable_reg
= 0x58044,
2317 .enable_mask
= BIT(0),
2318 .hw
.init
= &(struct clk_init_data
){
2319 .name
= "gcc_camss_vfe_ahb_clk",
2320 .parent_names
= (const char *[]){
2321 "camss_ahb_clk_src",
2324 .flags
= CLK_SET_RATE_PARENT
,
2325 .ops
= &clk_branch2_ops
,
2330 static struct clk_branch gcc_camss_vfe_axi_clk
= {
2331 .halt_reg
= 0x58048,
2333 .enable_reg
= 0x58048,
2334 .enable_mask
= BIT(0),
2335 .hw
.init
= &(struct clk_init_data
){
2336 .name
= "gcc_camss_vfe_axi_clk",
2337 .parent_names
= (const char *[]){
2338 "system_noc_bfdcd_clk_src",
2341 .flags
= CLK_SET_RATE_PARENT
,
2342 .ops
= &clk_branch2_ops
,
2347 static struct clk_branch gcc_crypto_ahb_clk
= {
2348 .halt_reg
= 0x16024,
2349 .halt_check
= BRANCH_HALT_VOTED
,
2351 .enable_reg
= 0x45004,
2352 .enable_mask
= BIT(0),
2353 .hw
.init
= &(struct clk_init_data
){
2354 .name
= "gcc_crypto_ahb_clk",
2355 .parent_names
= (const char *[]){
2356 "pcnoc_bfdcd_clk_src",
2359 .flags
= CLK_SET_RATE_PARENT
,
2360 .ops
= &clk_branch2_ops
,
2365 static struct clk_branch gcc_crypto_axi_clk
= {
2366 .halt_reg
= 0x16020,
2367 .halt_check
= BRANCH_HALT_VOTED
,
2369 .enable_reg
= 0x45004,
2370 .enable_mask
= BIT(1),
2371 .hw
.init
= &(struct clk_init_data
){
2372 .name
= "gcc_crypto_axi_clk",
2373 .parent_names
= (const char *[]){
2374 "pcnoc_bfdcd_clk_src",
2377 .flags
= CLK_SET_RATE_PARENT
,
2378 .ops
= &clk_branch2_ops
,
2383 static struct clk_branch gcc_crypto_clk
= {
2384 .halt_reg
= 0x1601c,
2385 .halt_check
= BRANCH_HALT_VOTED
,
2387 .enable_reg
= 0x45004,
2388 .enable_mask
= BIT(2),
2389 .hw
.init
= &(struct clk_init_data
){
2390 .name
= "gcc_crypto_clk",
2391 .parent_names
= (const char *[]){
2395 .flags
= CLK_SET_RATE_PARENT
,
2396 .ops
= &clk_branch2_ops
,
2401 static struct clk_branch gcc_oxili_gmem_clk
= {
2402 .halt_reg
= 0x59024,
2404 .enable_reg
= 0x59024,
2405 .enable_mask
= BIT(0),
2406 .hw
.init
= &(struct clk_init_data
){
2407 .name
= "gcc_oxili_gmem_clk",
2408 .parent_names
= (const char *[]){
2412 .flags
= CLK_SET_RATE_PARENT
,
2413 .ops
= &clk_branch2_ops
,
2418 static struct clk_branch gcc_gp1_clk
= {
2419 .halt_reg
= 0x08000,
2421 .enable_reg
= 0x08000,
2422 .enable_mask
= BIT(0),
2423 .hw
.init
= &(struct clk_init_data
){
2424 .name
= "gcc_gp1_clk",
2425 .parent_names
= (const char *[]){
2429 .flags
= CLK_SET_RATE_PARENT
,
2430 .ops
= &clk_branch2_ops
,
2435 static struct clk_branch gcc_gp2_clk
= {
2436 .halt_reg
= 0x09000,
2438 .enable_reg
= 0x09000,
2439 .enable_mask
= BIT(0),
2440 .hw
.init
= &(struct clk_init_data
){
2441 .name
= "gcc_gp2_clk",
2442 .parent_names
= (const char *[]){
2446 .flags
= CLK_SET_RATE_PARENT
,
2447 .ops
= &clk_branch2_ops
,
2452 static struct clk_branch gcc_gp3_clk
= {
2453 .halt_reg
= 0x0a000,
2455 .enable_reg
= 0x0a000,
2456 .enable_mask
= BIT(0),
2457 .hw
.init
= &(struct clk_init_data
){
2458 .name
= "gcc_gp3_clk",
2459 .parent_names
= (const char *[]){
2463 .flags
= CLK_SET_RATE_PARENT
,
2464 .ops
= &clk_branch2_ops
,
2469 static struct clk_branch gcc_mdss_ahb_clk
= {
2470 .halt_reg
= 0x4d07c,
2472 .enable_reg
= 0x4d07c,
2473 .enable_mask
= BIT(0),
2474 .hw
.init
= &(struct clk_init_data
){
2475 .name
= "gcc_mdss_ahb_clk",
2476 .parent_names
= (const char *[]){
2477 "pcnoc_bfdcd_clk_src",
2480 .flags
= CLK_SET_RATE_PARENT
,
2481 .ops
= &clk_branch2_ops
,
2486 static struct clk_branch gcc_mdss_axi_clk
= {
2487 .halt_reg
= 0x4d080,
2489 .enable_reg
= 0x4d080,
2490 .enable_mask
= BIT(0),
2491 .hw
.init
= &(struct clk_init_data
){
2492 .name
= "gcc_mdss_axi_clk",
2493 .parent_names
= (const char *[]){
2494 "system_noc_bfdcd_clk_src",
2497 .flags
= CLK_SET_RATE_PARENT
,
2498 .ops
= &clk_branch2_ops
,
2503 static struct clk_branch gcc_mdss_byte0_clk
= {
2504 .halt_reg
= 0x4d094,
2506 .enable_reg
= 0x4d094,
2507 .enable_mask
= BIT(0),
2508 .hw
.init
= &(struct clk_init_data
){
2509 .name
= "gcc_mdss_byte0_clk",
2510 .parent_names
= (const char *[]){
2514 .flags
= CLK_SET_RATE_PARENT
,
2515 .ops
= &clk_branch2_ops
,
2520 static struct clk_branch gcc_mdss_esc0_clk
= {
2521 .halt_reg
= 0x4d098,
2523 .enable_reg
= 0x4d098,
2524 .enable_mask
= BIT(0),
2525 .hw
.init
= &(struct clk_init_data
){
2526 .name
= "gcc_mdss_esc0_clk",
2527 .parent_names
= (const char *[]){
2531 .flags
= CLK_SET_RATE_PARENT
,
2532 .ops
= &clk_branch2_ops
,
2537 static struct clk_branch gcc_mdss_mdp_clk
= {
2538 .halt_reg
= 0x4D088,
2540 .enable_reg
= 0x4D088,
2541 .enable_mask
= BIT(0),
2542 .hw
.init
= &(struct clk_init_data
){
2543 .name
= "gcc_mdss_mdp_clk",
2544 .parent_names
= (const char *[]){
2548 .flags
= CLK_SET_RATE_PARENT
,
2549 .ops
= &clk_branch2_ops
,
2554 static struct clk_branch gcc_mdss_pclk0_clk
= {
2555 .halt_reg
= 0x4d084,
2557 .enable_reg
= 0x4d084,
2558 .enable_mask
= BIT(0),
2559 .hw
.init
= &(struct clk_init_data
){
2560 .name
= "gcc_mdss_pclk0_clk",
2561 .parent_names
= (const char *[]){
2565 .flags
= CLK_SET_RATE_PARENT
,
2566 .ops
= &clk_branch2_ops
,
2571 static struct clk_branch gcc_mdss_vsync_clk
= {
2572 .halt_reg
= 0x4d090,
2574 .enable_reg
= 0x4d090,
2575 .enable_mask
= BIT(0),
2576 .hw
.init
= &(struct clk_init_data
){
2577 .name
= "gcc_mdss_vsync_clk",
2578 .parent_names
= (const char *[]){
2582 .flags
= CLK_SET_RATE_PARENT
,
2583 .ops
= &clk_branch2_ops
,
2588 static struct clk_branch gcc_mss_cfg_ahb_clk
= {
2589 .halt_reg
= 0x49000,
2591 .enable_reg
= 0x49000,
2592 .enable_mask
= BIT(0),
2593 .hw
.init
= &(struct clk_init_data
){
2594 .name
= "gcc_mss_cfg_ahb_clk",
2595 .parent_names
= (const char *[]){
2596 "pcnoc_bfdcd_clk_src",
2599 .flags
= CLK_SET_RATE_PARENT
,
2600 .ops
= &clk_branch2_ops
,
2605 static struct clk_branch gcc_mss_q6_bimc_axi_clk
= {
2606 .halt_reg
= 0x49004,
2608 .enable_reg
= 0x49004,
2609 .enable_mask
= BIT(0),
2610 .hw
.init
= &(struct clk_init_data
){
2611 .name
= "gcc_mss_q6_bimc_axi_clk",
2612 .parent_names
= (const char *[]){
2616 .flags
= CLK_SET_RATE_PARENT
,
2617 .ops
= &clk_branch2_ops
,
2622 static struct clk_branch gcc_oxili_ahb_clk
= {
2623 .halt_reg
= 0x59028,
2625 .enable_reg
= 0x59028,
2626 .enable_mask
= BIT(0),
2627 .hw
.init
= &(struct clk_init_data
){
2628 .name
= "gcc_oxili_ahb_clk",
2629 .parent_names
= (const char *[]){
2630 "pcnoc_bfdcd_clk_src",
2633 .flags
= CLK_SET_RATE_PARENT
,
2634 .ops
= &clk_branch2_ops
,
2639 static struct clk_branch gcc_oxili_gfx3d_clk
= {
2640 .halt_reg
= 0x59020,
2642 .enable_reg
= 0x59020,
2643 .enable_mask
= BIT(0),
2644 .hw
.init
= &(struct clk_init_data
){
2645 .name
= "gcc_oxili_gfx3d_clk",
2646 .parent_names
= (const char *[]){
2650 .flags
= CLK_SET_RATE_PARENT
,
2651 .ops
= &clk_branch2_ops
,
2656 static struct clk_branch gcc_pdm2_clk
= {
2657 .halt_reg
= 0x4400c,
2659 .enable_reg
= 0x4400c,
2660 .enable_mask
= BIT(0),
2661 .hw
.init
= &(struct clk_init_data
){
2662 .name
= "gcc_pdm2_clk",
2663 .parent_names
= (const char *[]){
2667 .flags
= CLK_SET_RATE_PARENT
,
2668 .ops
= &clk_branch2_ops
,
2673 static struct clk_branch gcc_pdm_ahb_clk
= {
2674 .halt_reg
= 0x44004,
2676 .enable_reg
= 0x44004,
2677 .enable_mask
= BIT(0),
2678 .hw
.init
= &(struct clk_init_data
){
2679 .name
= "gcc_pdm_ahb_clk",
2680 .parent_names
= (const char *[]){
2681 "pcnoc_bfdcd_clk_src",
2684 .flags
= CLK_SET_RATE_PARENT
,
2685 .ops
= &clk_branch2_ops
,
2690 static struct clk_branch gcc_prng_ahb_clk
= {
2691 .halt_reg
= 0x13004,
2692 .halt_check
= BRANCH_HALT_VOTED
,
2694 .enable_reg
= 0x45004,
2695 .enable_mask
= BIT(8),
2696 .hw
.init
= &(struct clk_init_data
){
2697 .name
= "gcc_prng_ahb_clk",
2698 .parent_names
= (const char *[]){
2699 "pcnoc_bfdcd_clk_src",
2702 .ops
= &clk_branch2_ops
,
2707 static struct clk_branch gcc_sdcc1_ahb_clk
= {
2708 .halt_reg
= 0x4201c,
2710 .enable_reg
= 0x4201c,
2711 .enable_mask
= BIT(0),
2712 .hw
.init
= &(struct clk_init_data
){
2713 .name
= "gcc_sdcc1_ahb_clk",
2714 .parent_names
= (const char *[]){
2715 "pcnoc_bfdcd_clk_src",
2718 .flags
= CLK_SET_RATE_PARENT
,
2719 .ops
= &clk_branch2_ops
,
2724 static struct clk_branch gcc_sdcc1_apps_clk
= {
2725 .halt_reg
= 0x42018,
2727 .enable_reg
= 0x42018,
2728 .enable_mask
= BIT(0),
2729 .hw
.init
= &(struct clk_init_data
){
2730 .name
= "gcc_sdcc1_apps_clk",
2731 .parent_names
= (const char *[]){
2732 "sdcc1_apps_clk_src",
2735 .flags
= CLK_SET_RATE_PARENT
,
2736 .ops
= &clk_branch2_ops
,
2741 static struct clk_branch gcc_sdcc2_ahb_clk
= {
2742 .halt_reg
= 0x4301c,
2744 .enable_reg
= 0x4301c,
2745 .enable_mask
= BIT(0),
2746 .hw
.init
= &(struct clk_init_data
){
2747 .name
= "gcc_sdcc2_ahb_clk",
2748 .parent_names
= (const char *[]){
2749 "pcnoc_bfdcd_clk_src",
2752 .flags
= CLK_SET_RATE_PARENT
,
2753 .ops
= &clk_branch2_ops
,
2758 static struct clk_branch gcc_sdcc2_apps_clk
= {
2759 .halt_reg
= 0x43018,
2761 .enable_reg
= 0x43018,
2762 .enable_mask
= BIT(0),
2763 .hw
.init
= &(struct clk_init_data
){
2764 .name
= "gcc_sdcc2_apps_clk",
2765 .parent_names
= (const char *[]){
2766 "sdcc2_apps_clk_src",
2769 .flags
= CLK_SET_RATE_PARENT
,
2770 .ops
= &clk_branch2_ops
,
2775 static struct clk_rcg2 bimc_ddr_clk_src
= {
2776 .cmd_rcgr
= 0x32004,
2778 .parent_map
= gcc_xo_gpll0_bimc_map
,
2779 .clkr
.hw
.init
= &(struct clk_init_data
){
2780 .name
= "bimc_ddr_clk_src",
2781 .parent_names
= gcc_xo_gpll0_bimc
,
2783 .ops
= &clk_rcg2_ops
,
2784 .flags
= CLK_GET_RATE_NOCACHE
,
2788 static struct clk_branch gcc_apss_tcu_clk
= {
2789 .halt_reg
= 0x12018,
2791 .enable_reg
= 0x4500c,
2792 .enable_mask
= BIT(1),
2793 .hw
.init
= &(struct clk_init_data
){
2794 .name
= "gcc_apss_tcu_clk",
2795 .parent_names
= (const char *[]){
2799 .ops
= &clk_branch2_ops
,
2804 static struct clk_branch gcc_gfx_tcu_clk
= {
2805 .halt_reg
= 0x12020,
2807 .enable_reg
= 0x4500c,
2808 .enable_mask
= BIT(2),
2809 .hw
.init
= &(struct clk_init_data
){
2810 .name
= "gcc_gfx_tcu_clk",
2811 .parent_names
= (const char *[]){
2815 .ops
= &clk_branch2_ops
,
2820 static struct clk_branch gcc_gtcu_ahb_clk
= {
2821 .halt_reg
= 0x12044,
2823 .enable_reg
= 0x4500c,
2824 .enable_mask
= BIT(13),
2825 .hw
.init
= &(struct clk_init_data
){
2826 .name
= "gcc_gtcu_ahb_clk",
2827 .parent_names
= (const char *[]){
2828 "pcnoc_bfdcd_clk_src",
2831 .flags
= CLK_SET_RATE_PARENT
,
2832 .ops
= &clk_branch2_ops
,
2837 static struct clk_branch gcc_bimc_gfx_clk
= {
2838 .halt_reg
= 0x31024,
2840 .enable_reg
= 0x31024,
2841 .enable_mask
= BIT(0),
2842 .hw
.init
= &(struct clk_init_data
){
2843 .name
= "gcc_bimc_gfx_clk",
2844 .parent_names
= (const char *[]){
2848 .flags
= CLK_SET_RATE_PARENT
,
2849 .ops
= &clk_branch2_ops
,
2854 static struct clk_branch gcc_bimc_gpu_clk
= {
2855 .halt_reg
= 0x31040,
2857 .enable_reg
= 0x31040,
2858 .enable_mask
= BIT(0),
2859 .hw
.init
= &(struct clk_init_data
){
2860 .name
= "gcc_bimc_gpu_clk",
2861 .parent_names
= (const char *[]){
2865 .flags
= CLK_SET_RATE_PARENT
,
2866 .ops
= &clk_branch2_ops
,
2871 static struct clk_branch gcc_jpeg_tbu_clk
= {
2872 .halt_reg
= 0x12034,
2874 .enable_reg
= 0x4500c,
2875 .enable_mask
= BIT(10),
2876 .hw
.init
= &(struct clk_init_data
){
2877 .name
= "gcc_jpeg_tbu_clk",
2878 .parent_names
= (const char *[]){
2879 "system_noc_bfdcd_clk_src",
2882 .flags
= CLK_SET_RATE_PARENT
,
2883 .ops
= &clk_branch2_ops
,
2888 static struct clk_branch gcc_mdp_tbu_clk
= {
2889 .halt_reg
= 0x1201c,
2891 .enable_reg
= 0x4500c,
2892 .enable_mask
= BIT(4),
2893 .hw
.init
= &(struct clk_init_data
){
2894 .name
= "gcc_mdp_tbu_clk",
2895 .parent_names
= (const char *[]){
2896 "system_noc_bfdcd_clk_src",
2899 .flags
= CLK_SET_RATE_PARENT
,
2900 .ops
= &clk_branch2_ops
,
2905 static struct clk_branch gcc_smmu_cfg_clk
= {
2906 .halt_reg
= 0x12038,
2908 .enable_reg
= 0x4500c,
2909 .enable_mask
= BIT(12),
2910 .hw
.init
= &(struct clk_init_data
){
2911 .name
= "gcc_smmu_cfg_clk",
2912 .parent_names
= (const char *[]){
2913 "pcnoc_bfdcd_clk_src",
2916 .flags
= CLK_SET_RATE_PARENT
,
2917 .ops
= &clk_branch2_ops
,
2922 static struct clk_branch gcc_venus_tbu_clk
= {
2923 .halt_reg
= 0x12014,
2925 .enable_reg
= 0x4500c,
2926 .enable_mask
= BIT(5),
2927 .hw
.init
= &(struct clk_init_data
){
2928 .name
= "gcc_venus_tbu_clk",
2929 .parent_names
= (const char *[]){
2930 "system_noc_bfdcd_clk_src",
2933 .flags
= CLK_SET_RATE_PARENT
,
2934 .ops
= &clk_branch2_ops
,
2939 static struct clk_branch gcc_vfe_tbu_clk
= {
2940 .halt_reg
= 0x1203c,
2942 .enable_reg
= 0x4500c,
2943 .enable_mask
= BIT(9),
2944 .hw
.init
= &(struct clk_init_data
){
2945 .name
= "gcc_vfe_tbu_clk",
2946 .parent_names
= (const char *[]){
2947 "system_noc_bfdcd_clk_src",
2950 .flags
= CLK_SET_RATE_PARENT
,
2951 .ops
= &clk_branch2_ops
,
2956 static struct clk_branch gcc_usb2a_phy_sleep_clk
= {
2957 .halt_reg
= 0x4102c,
2959 .enable_reg
= 0x4102c,
2960 .enable_mask
= BIT(0),
2961 .hw
.init
= &(struct clk_init_data
){
2962 .name
= "gcc_usb2a_phy_sleep_clk",
2963 .parent_names
= (const char *[]){
2967 .flags
= CLK_SET_RATE_PARENT
,
2968 .ops
= &clk_branch2_ops
,
2973 static struct clk_branch gcc_usb_hs_ahb_clk
= {
2974 .halt_reg
= 0x41008,
2976 .enable_reg
= 0x41008,
2977 .enable_mask
= BIT(0),
2978 .hw
.init
= &(struct clk_init_data
){
2979 .name
= "gcc_usb_hs_ahb_clk",
2980 .parent_names
= (const char *[]){
2981 "pcnoc_bfdcd_clk_src",
2984 .flags
= CLK_SET_RATE_PARENT
,
2985 .ops
= &clk_branch2_ops
,
2990 static struct clk_branch gcc_usb_hs_system_clk
= {
2991 .halt_reg
= 0x41004,
2993 .enable_reg
= 0x41004,
2994 .enable_mask
= BIT(0),
2995 .hw
.init
= &(struct clk_init_data
){
2996 .name
= "gcc_usb_hs_system_clk",
2997 .parent_names
= (const char *[]){
2998 "usb_hs_system_clk_src",
3001 .flags
= CLK_SET_RATE_PARENT
,
3002 .ops
= &clk_branch2_ops
,
3007 static struct clk_branch gcc_venus0_ahb_clk
= {
3008 .halt_reg
= 0x4c020,
3010 .enable_reg
= 0x4c020,
3011 .enable_mask
= BIT(0),
3012 .hw
.init
= &(struct clk_init_data
){
3013 .name
= "gcc_venus0_ahb_clk",
3014 .parent_names
= (const char *[]){
3015 "pcnoc_bfdcd_clk_src",
3018 .flags
= CLK_SET_RATE_PARENT
,
3019 .ops
= &clk_branch2_ops
,
3024 static struct clk_branch gcc_venus0_axi_clk
= {
3025 .halt_reg
= 0x4c024,
3027 .enable_reg
= 0x4c024,
3028 .enable_mask
= BIT(0),
3029 .hw
.init
= &(struct clk_init_data
){
3030 .name
= "gcc_venus0_axi_clk",
3031 .parent_names
= (const char *[]){
3032 "system_noc_bfdcd_clk_src",
3035 .flags
= CLK_SET_RATE_PARENT
,
3036 .ops
= &clk_branch2_ops
,
3041 static struct clk_branch gcc_venus0_vcodec0_clk
= {
3042 .halt_reg
= 0x4c01c,
3044 .enable_reg
= 0x4c01c,
3045 .enable_mask
= BIT(0),
3046 .hw
.init
= &(struct clk_init_data
){
3047 .name
= "gcc_venus0_vcodec0_clk",
3048 .parent_names
= (const char *[]){
3052 .flags
= CLK_SET_RATE_PARENT
,
3053 .ops
= &clk_branch2_ops
,
3058 static struct gdsc venus_gdsc
= {
3063 .pwrsts
= PWRSTS_OFF_ON
,
3066 static struct gdsc mdss_gdsc
= {
3071 .pwrsts
= PWRSTS_OFF_ON
,
3074 static struct gdsc jpeg_gdsc
= {
3079 .pwrsts
= PWRSTS_OFF_ON
,
3082 static struct gdsc vfe_gdsc
= {
3087 .pwrsts
= PWRSTS_OFF_ON
,
3090 static struct gdsc oxili_gdsc
= {
3095 .pwrsts
= PWRSTS_OFF_ON
,
3098 static struct clk_regmap
*gcc_msm8916_clocks
[] = {
3099 [GPLL0
] = &gpll0
.clkr
,
3100 [GPLL0_VOTE
] = &gpll0_vote
,
3101 [BIMC_PLL
] = &bimc_pll
.clkr
,
3102 [BIMC_PLL_VOTE
] = &bimc_pll_vote
,
3103 [GPLL1
] = &gpll1
.clkr
,
3104 [GPLL1_VOTE
] = &gpll1_vote
,
3105 [GPLL2
] = &gpll2
.clkr
,
3106 [GPLL2_VOTE
] = &gpll2_vote
,
3107 [PCNOC_BFDCD_CLK_SRC
] = &pcnoc_bfdcd_clk_src
.clkr
,
3108 [SYSTEM_NOC_BFDCD_CLK_SRC
] = &system_noc_bfdcd_clk_src
.clkr
,
3109 [CAMSS_AHB_CLK_SRC
] = &camss_ahb_clk_src
.clkr
,
3110 [APSS_AHB_CLK_SRC
] = &apss_ahb_clk_src
.clkr
,
3111 [CSI0_CLK_SRC
] = &csi0_clk_src
.clkr
,
3112 [CSI1_CLK_SRC
] = &csi1_clk_src
.clkr
,
3113 [GFX3D_CLK_SRC
] = &gfx3d_clk_src
.clkr
,
3114 [VFE0_CLK_SRC
] = &vfe0_clk_src
.clkr
,
3115 [BLSP1_QUP1_I2C_APPS_CLK_SRC
] = &blsp1_qup1_i2c_apps_clk_src
.clkr
,
3116 [BLSP1_QUP1_SPI_APPS_CLK_SRC
] = &blsp1_qup1_spi_apps_clk_src
.clkr
,
3117 [BLSP1_QUP2_I2C_APPS_CLK_SRC
] = &blsp1_qup2_i2c_apps_clk_src
.clkr
,
3118 [BLSP1_QUP2_SPI_APPS_CLK_SRC
] = &blsp1_qup2_spi_apps_clk_src
.clkr
,
3119 [BLSP1_QUP3_I2C_APPS_CLK_SRC
] = &blsp1_qup3_i2c_apps_clk_src
.clkr
,
3120 [BLSP1_QUP3_SPI_APPS_CLK_SRC
] = &blsp1_qup3_spi_apps_clk_src
.clkr
,
3121 [BLSP1_QUP4_I2C_APPS_CLK_SRC
] = &blsp1_qup4_i2c_apps_clk_src
.clkr
,
3122 [BLSP1_QUP4_SPI_APPS_CLK_SRC
] = &blsp1_qup4_spi_apps_clk_src
.clkr
,
3123 [BLSP1_QUP5_I2C_APPS_CLK_SRC
] = &blsp1_qup5_i2c_apps_clk_src
.clkr
,
3124 [BLSP1_QUP5_SPI_APPS_CLK_SRC
] = &blsp1_qup5_spi_apps_clk_src
.clkr
,
3125 [BLSP1_QUP6_I2C_APPS_CLK_SRC
] = &blsp1_qup6_i2c_apps_clk_src
.clkr
,
3126 [BLSP1_QUP6_SPI_APPS_CLK_SRC
] = &blsp1_qup6_spi_apps_clk_src
.clkr
,
3127 [BLSP1_UART1_APPS_CLK_SRC
] = &blsp1_uart1_apps_clk_src
.clkr
,
3128 [BLSP1_UART2_APPS_CLK_SRC
] = &blsp1_uart2_apps_clk_src
.clkr
,
3129 [CCI_CLK_SRC
] = &cci_clk_src
.clkr
,
3130 [CAMSS_GP0_CLK_SRC
] = &camss_gp0_clk_src
.clkr
,
3131 [CAMSS_GP1_CLK_SRC
] = &camss_gp1_clk_src
.clkr
,
3132 [JPEG0_CLK_SRC
] = &jpeg0_clk_src
.clkr
,
3133 [MCLK0_CLK_SRC
] = &mclk0_clk_src
.clkr
,
3134 [MCLK1_CLK_SRC
] = &mclk1_clk_src
.clkr
,
3135 [CSI0PHYTIMER_CLK_SRC
] = &csi0phytimer_clk_src
.clkr
,
3136 [CSI1PHYTIMER_CLK_SRC
] = &csi1phytimer_clk_src
.clkr
,
3137 [CPP_CLK_SRC
] = &cpp_clk_src
.clkr
,
3138 [CRYPTO_CLK_SRC
] = &crypto_clk_src
.clkr
,
3139 [GP1_CLK_SRC
] = &gp1_clk_src
.clkr
,
3140 [GP2_CLK_SRC
] = &gp2_clk_src
.clkr
,
3141 [GP3_CLK_SRC
] = &gp3_clk_src
.clkr
,
3142 [BYTE0_CLK_SRC
] = &byte0_clk_src
.clkr
,
3143 [ESC0_CLK_SRC
] = &esc0_clk_src
.clkr
,
3144 [MDP_CLK_SRC
] = &mdp_clk_src
.clkr
,
3145 [PCLK0_CLK_SRC
] = &pclk0_clk_src
.clkr
,
3146 [VSYNC_CLK_SRC
] = &vsync_clk_src
.clkr
,
3147 [PDM2_CLK_SRC
] = &pdm2_clk_src
.clkr
,
3148 [SDCC1_APPS_CLK_SRC
] = &sdcc1_apps_clk_src
.clkr
,
3149 [SDCC2_APPS_CLK_SRC
] = &sdcc2_apps_clk_src
.clkr
,
3150 [APSS_TCU_CLK_SRC
] = &apss_tcu_clk_src
.clkr
,
3151 [USB_HS_SYSTEM_CLK_SRC
] = &usb_hs_system_clk_src
.clkr
,
3152 [VCODEC0_CLK_SRC
] = &vcodec0_clk_src
.clkr
,
3153 [GCC_BLSP1_AHB_CLK
] = &gcc_blsp1_ahb_clk
.clkr
,
3154 [GCC_BLSP1_SLEEP_CLK
] = &gcc_blsp1_sleep_clk
.clkr
,
3155 [GCC_BLSP1_QUP1_I2C_APPS_CLK
] = &gcc_blsp1_qup1_i2c_apps_clk
.clkr
,
3156 [GCC_BLSP1_QUP1_SPI_APPS_CLK
] = &gcc_blsp1_qup1_spi_apps_clk
.clkr
,
3157 [GCC_BLSP1_QUP2_I2C_APPS_CLK
] = &gcc_blsp1_qup2_i2c_apps_clk
.clkr
,
3158 [GCC_BLSP1_QUP2_SPI_APPS_CLK
] = &gcc_blsp1_qup2_spi_apps_clk
.clkr
,
3159 [GCC_BLSP1_QUP3_I2C_APPS_CLK
] = &gcc_blsp1_qup3_i2c_apps_clk
.clkr
,
3160 [GCC_BLSP1_QUP3_SPI_APPS_CLK
] = &gcc_blsp1_qup3_spi_apps_clk
.clkr
,
3161 [GCC_BLSP1_QUP4_I2C_APPS_CLK
] = &gcc_blsp1_qup4_i2c_apps_clk
.clkr
,
3162 [GCC_BLSP1_QUP4_SPI_APPS_CLK
] = &gcc_blsp1_qup4_spi_apps_clk
.clkr
,
3163 [GCC_BLSP1_QUP5_I2C_APPS_CLK
] = &gcc_blsp1_qup5_i2c_apps_clk
.clkr
,
3164 [GCC_BLSP1_QUP5_SPI_APPS_CLK
] = &gcc_blsp1_qup5_spi_apps_clk
.clkr
,
3165 [GCC_BLSP1_QUP6_I2C_APPS_CLK
] = &gcc_blsp1_qup6_i2c_apps_clk
.clkr
,
3166 [GCC_BLSP1_QUP6_SPI_APPS_CLK
] = &gcc_blsp1_qup6_spi_apps_clk
.clkr
,
3167 [GCC_BLSP1_UART1_APPS_CLK
] = &gcc_blsp1_uart1_apps_clk
.clkr
,
3168 [GCC_BLSP1_UART2_APPS_CLK
] = &gcc_blsp1_uart2_apps_clk
.clkr
,
3169 [GCC_BOOT_ROM_AHB_CLK
] = &gcc_boot_rom_ahb_clk
.clkr
,
3170 [GCC_CAMSS_CCI_AHB_CLK
] = &gcc_camss_cci_ahb_clk
.clkr
,
3171 [GCC_CAMSS_CCI_CLK
] = &gcc_camss_cci_clk
.clkr
,
3172 [GCC_CAMSS_CSI0_AHB_CLK
] = &gcc_camss_csi0_ahb_clk
.clkr
,
3173 [GCC_CAMSS_CSI0_CLK
] = &gcc_camss_csi0_clk
.clkr
,
3174 [GCC_CAMSS_CSI0PHY_CLK
] = &gcc_camss_csi0phy_clk
.clkr
,
3175 [GCC_CAMSS_CSI0PIX_CLK
] = &gcc_camss_csi0pix_clk
.clkr
,
3176 [GCC_CAMSS_CSI0RDI_CLK
] = &gcc_camss_csi0rdi_clk
.clkr
,
3177 [GCC_CAMSS_CSI1_AHB_CLK
] = &gcc_camss_csi1_ahb_clk
.clkr
,
3178 [GCC_CAMSS_CSI1_CLK
] = &gcc_camss_csi1_clk
.clkr
,
3179 [GCC_CAMSS_CSI1PHY_CLK
] = &gcc_camss_csi1phy_clk
.clkr
,
3180 [GCC_CAMSS_CSI1PIX_CLK
] = &gcc_camss_csi1pix_clk
.clkr
,
3181 [GCC_CAMSS_CSI1RDI_CLK
] = &gcc_camss_csi1rdi_clk
.clkr
,
3182 [GCC_CAMSS_CSI_VFE0_CLK
] = &gcc_camss_csi_vfe0_clk
.clkr
,
3183 [GCC_CAMSS_GP0_CLK
] = &gcc_camss_gp0_clk
.clkr
,
3184 [GCC_CAMSS_GP1_CLK
] = &gcc_camss_gp1_clk
.clkr
,
3185 [GCC_CAMSS_ISPIF_AHB_CLK
] = &gcc_camss_ispif_ahb_clk
.clkr
,
3186 [GCC_CAMSS_JPEG0_CLK
] = &gcc_camss_jpeg0_clk
.clkr
,
3187 [GCC_CAMSS_JPEG_AHB_CLK
] = &gcc_camss_jpeg_ahb_clk
.clkr
,
3188 [GCC_CAMSS_JPEG_AXI_CLK
] = &gcc_camss_jpeg_axi_clk
.clkr
,
3189 [GCC_CAMSS_MCLK0_CLK
] = &gcc_camss_mclk0_clk
.clkr
,
3190 [GCC_CAMSS_MCLK1_CLK
] = &gcc_camss_mclk1_clk
.clkr
,
3191 [GCC_CAMSS_MICRO_AHB_CLK
] = &gcc_camss_micro_ahb_clk
.clkr
,
3192 [GCC_CAMSS_CSI0PHYTIMER_CLK
] = &gcc_camss_csi0phytimer_clk
.clkr
,
3193 [GCC_CAMSS_CSI1PHYTIMER_CLK
] = &gcc_camss_csi1phytimer_clk
.clkr
,
3194 [GCC_CAMSS_AHB_CLK
] = &gcc_camss_ahb_clk
.clkr
,
3195 [GCC_CAMSS_TOP_AHB_CLK
] = &gcc_camss_top_ahb_clk
.clkr
,
3196 [GCC_CAMSS_CPP_AHB_CLK
] = &gcc_camss_cpp_ahb_clk
.clkr
,
3197 [GCC_CAMSS_CPP_CLK
] = &gcc_camss_cpp_clk
.clkr
,
3198 [GCC_CAMSS_VFE0_CLK
] = &gcc_camss_vfe0_clk
.clkr
,
3199 [GCC_CAMSS_VFE_AHB_CLK
] = &gcc_camss_vfe_ahb_clk
.clkr
,
3200 [GCC_CAMSS_VFE_AXI_CLK
] = &gcc_camss_vfe_axi_clk
.clkr
,
3201 [GCC_CRYPTO_AHB_CLK
] = &gcc_crypto_ahb_clk
.clkr
,
3202 [GCC_CRYPTO_AXI_CLK
] = &gcc_crypto_axi_clk
.clkr
,
3203 [GCC_CRYPTO_CLK
] = &gcc_crypto_clk
.clkr
,
3204 [GCC_OXILI_GMEM_CLK
] = &gcc_oxili_gmem_clk
.clkr
,
3205 [GCC_GP1_CLK
] = &gcc_gp1_clk
.clkr
,
3206 [GCC_GP2_CLK
] = &gcc_gp2_clk
.clkr
,
3207 [GCC_GP3_CLK
] = &gcc_gp3_clk
.clkr
,
3208 [GCC_MDSS_AHB_CLK
] = &gcc_mdss_ahb_clk
.clkr
,
3209 [GCC_MDSS_AXI_CLK
] = &gcc_mdss_axi_clk
.clkr
,
3210 [GCC_MDSS_BYTE0_CLK
] = &gcc_mdss_byte0_clk
.clkr
,
3211 [GCC_MDSS_ESC0_CLK
] = &gcc_mdss_esc0_clk
.clkr
,
3212 [GCC_MDSS_MDP_CLK
] = &gcc_mdss_mdp_clk
.clkr
,
3213 [GCC_MDSS_PCLK0_CLK
] = &gcc_mdss_pclk0_clk
.clkr
,
3214 [GCC_MDSS_VSYNC_CLK
] = &gcc_mdss_vsync_clk
.clkr
,
3215 [GCC_MSS_CFG_AHB_CLK
] = &gcc_mss_cfg_ahb_clk
.clkr
,
3216 [GCC_OXILI_AHB_CLK
] = &gcc_oxili_ahb_clk
.clkr
,
3217 [GCC_OXILI_GFX3D_CLK
] = &gcc_oxili_gfx3d_clk
.clkr
,
3218 [GCC_PDM2_CLK
] = &gcc_pdm2_clk
.clkr
,
3219 [GCC_PDM_AHB_CLK
] = &gcc_pdm_ahb_clk
.clkr
,
3220 [GCC_PRNG_AHB_CLK
] = &gcc_prng_ahb_clk
.clkr
,
3221 [GCC_SDCC1_AHB_CLK
] = &gcc_sdcc1_ahb_clk
.clkr
,
3222 [GCC_SDCC1_APPS_CLK
] = &gcc_sdcc1_apps_clk
.clkr
,
3223 [GCC_SDCC2_AHB_CLK
] = &gcc_sdcc2_ahb_clk
.clkr
,
3224 [GCC_SDCC2_APPS_CLK
] = &gcc_sdcc2_apps_clk
.clkr
,
3225 [GCC_GTCU_AHB_CLK
] = &gcc_gtcu_ahb_clk
.clkr
,
3226 [GCC_JPEG_TBU_CLK
] = &gcc_jpeg_tbu_clk
.clkr
,
3227 [GCC_MDP_TBU_CLK
] = &gcc_mdp_tbu_clk
.clkr
,
3228 [GCC_SMMU_CFG_CLK
] = &gcc_smmu_cfg_clk
.clkr
,
3229 [GCC_VENUS_TBU_CLK
] = &gcc_venus_tbu_clk
.clkr
,
3230 [GCC_VFE_TBU_CLK
] = &gcc_vfe_tbu_clk
.clkr
,
3231 [GCC_USB2A_PHY_SLEEP_CLK
] = &gcc_usb2a_phy_sleep_clk
.clkr
,
3232 [GCC_USB_HS_AHB_CLK
] = &gcc_usb_hs_ahb_clk
.clkr
,
3233 [GCC_USB_HS_SYSTEM_CLK
] = &gcc_usb_hs_system_clk
.clkr
,
3234 [GCC_VENUS0_AHB_CLK
] = &gcc_venus0_ahb_clk
.clkr
,
3235 [GCC_VENUS0_AXI_CLK
] = &gcc_venus0_axi_clk
.clkr
,
3236 [GCC_VENUS0_VCODEC0_CLK
] = &gcc_venus0_vcodec0_clk
.clkr
,
3237 [BIMC_DDR_CLK_SRC
] = &bimc_ddr_clk_src
.clkr
,
3238 [GCC_APSS_TCU_CLK
] = &gcc_apss_tcu_clk
.clkr
,
3239 [GCC_GFX_TCU_CLK
] = &gcc_gfx_tcu_clk
.clkr
,
3240 [BIMC_GPU_CLK_SRC
] = &bimc_gpu_clk_src
.clkr
,
3241 [GCC_BIMC_GFX_CLK
] = &gcc_bimc_gfx_clk
.clkr
,
3242 [GCC_BIMC_GPU_CLK
] = &gcc_bimc_gpu_clk
.clkr
,
3243 [ULTAUDIO_AHBFABRIC_CLK_SRC
] = &ultaudio_ahbfabric_clk_src
.clkr
,
3244 [ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC
] = &ultaudio_lpaif_pri_i2s_clk_src
.clkr
,
3245 [ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC
] = &ultaudio_lpaif_sec_i2s_clk_src
.clkr
,
3246 [ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC
] = &ultaudio_lpaif_aux_i2s_clk_src
.clkr
,
3247 [ULTAUDIO_XO_CLK_SRC
] = &ultaudio_xo_clk_src
.clkr
,
3248 [CODEC_DIGCODEC_CLK_SRC
] = &codec_digcodec_clk_src
.clkr
,
3249 [GCC_ULTAUDIO_PCNOC_MPORT_CLK
] = &gcc_ultaudio_pcnoc_mport_clk
.clkr
,
3250 [GCC_ULTAUDIO_PCNOC_SWAY_CLK
] = &gcc_ultaudio_pcnoc_sway_clk
.clkr
,
3251 [GCC_ULTAUDIO_AVSYNC_XO_CLK
] = &gcc_ultaudio_avsync_xo_clk
.clkr
,
3252 [GCC_ULTAUDIO_STC_XO_CLK
] = &gcc_ultaudio_stc_xo_clk
.clkr
,
3253 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK
] = &gcc_ultaudio_ahbfabric_ixfabric_clk
.clkr
,
3254 [GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK
] = &gcc_ultaudio_ahbfabric_ixfabric_lpm_clk
.clkr
,
3255 [GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK
] = &gcc_ultaudio_lpaif_pri_i2s_clk
.clkr
,
3256 [GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK
] = &gcc_ultaudio_lpaif_sec_i2s_clk
.clkr
,
3257 [GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK
] = &gcc_ultaudio_lpaif_aux_i2s_clk
.clkr
,
3258 [GCC_CODEC_DIGCODEC_CLK
] = &gcc_codec_digcodec_clk
.clkr
,
3259 [GCC_MSS_Q6_BIMC_AXI_CLK
] = &gcc_mss_q6_bimc_axi_clk
.clkr
,
3262 static struct gdsc
*gcc_msm8916_gdscs
[] = {
3263 [VENUS_GDSC
] = &venus_gdsc
,
3264 [MDSS_GDSC
] = &mdss_gdsc
,
3265 [JPEG_GDSC
] = &jpeg_gdsc
,
3266 [VFE_GDSC
] = &vfe_gdsc
,
3267 [OXILI_GDSC
] = &oxili_gdsc
,
3270 static const struct qcom_reset_map gcc_msm8916_resets
[] = {
3271 [GCC_BLSP1_BCR
] = { 0x01000 },
3272 [GCC_BLSP1_QUP1_BCR
] = { 0x02000 },
3273 [GCC_BLSP1_UART1_BCR
] = { 0x02038 },
3274 [GCC_BLSP1_QUP2_BCR
] = { 0x03008 },
3275 [GCC_BLSP1_UART2_BCR
] = { 0x03028 },
3276 [GCC_BLSP1_QUP3_BCR
] = { 0x04018 },
3277 [GCC_BLSP1_QUP4_BCR
] = { 0x05018 },
3278 [GCC_BLSP1_QUP5_BCR
] = { 0x06018 },
3279 [GCC_BLSP1_QUP6_BCR
] = { 0x07018 },
3280 [GCC_IMEM_BCR
] = { 0x0e000 },
3281 [GCC_SMMU_BCR
] = { 0x12000 },
3282 [GCC_APSS_TCU_BCR
] = { 0x12050 },
3283 [GCC_SMMU_XPU_BCR
] = { 0x12054 },
3284 [GCC_PCNOC_TBU_BCR
] = { 0x12058 },
3285 [GCC_PRNG_BCR
] = { 0x13000 },
3286 [GCC_BOOT_ROM_BCR
] = { 0x13008 },
3287 [GCC_CRYPTO_BCR
] = { 0x16000 },
3288 [GCC_SEC_CTRL_BCR
] = { 0x1a000 },
3289 [GCC_AUDIO_CORE_BCR
] = { 0x1c008 },
3290 [GCC_ULT_AUDIO_BCR
] = { 0x1c0b4 },
3291 [GCC_DEHR_BCR
] = { 0x1f000 },
3292 [GCC_SYSTEM_NOC_BCR
] = { 0x26000 },
3293 [GCC_PCNOC_BCR
] = { 0x27018 },
3294 [GCC_TCSR_BCR
] = { 0x28000 },
3295 [GCC_QDSS_BCR
] = { 0x29000 },
3296 [GCC_DCD_BCR
] = { 0x2a000 },
3297 [GCC_MSG_RAM_BCR
] = { 0x2b000 },
3298 [GCC_MPM_BCR
] = { 0x2c000 },
3299 [GCC_SPMI_BCR
] = { 0x2e000 },
3300 [GCC_SPDM_BCR
] = { 0x2f000 },
3301 [GCC_MM_SPDM_BCR
] = { 0x2f024 },
3302 [GCC_BIMC_BCR
] = { 0x31000 },
3303 [GCC_RBCPR_BCR
] = { 0x33000 },
3304 [GCC_TLMM_BCR
] = { 0x34000 },
3305 [GCC_USB_HS_BCR
] = { 0x41000 },
3306 [GCC_USB2A_PHY_BCR
] = { 0x41028 },
3307 [GCC_SDCC1_BCR
] = { 0x42000 },
3308 [GCC_SDCC2_BCR
] = { 0x43000 },
3309 [GCC_PDM_BCR
] = { 0x44000 },
3310 [GCC_SNOC_BUS_TIMEOUT0_BCR
] = { 0x47000 },
3311 [GCC_PCNOC_BUS_TIMEOUT0_BCR
] = { 0x48000 },
3312 [GCC_PCNOC_BUS_TIMEOUT1_BCR
] = { 0x48008 },
3313 [GCC_PCNOC_BUS_TIMEOUT2_BCR
] = { 0x48010 },
3314 [GCC_PCNOC_BUS_TIMEOUT3_BCR
] = { 0x48018 },
3315 [GCC_PCNOC_BUS_TIMEOUT4_BCR
] = { 0x48020 },
3316 [GCC_PCNOC_BUS_TIMEOUT5_BCR
] = { 0x48028 },
3317 [GCC_PCNOC_BUS_TIMEOUT6_BCR
] = { 0x48030 },
3318 [GCC_PCNOC_BUS_TIMEOUT7_BCR
] = { 0x48038 },
3319 [GCC_PCNOC_BUS_TIMEOUT8_BCR
] = { 0x48040 },
3320 [GCC_PCNOC_BUS_TIMEOUT9_BCR
] = { 0x48048 },
3321 [GCC_MMSS_BCR
] = { 0x4b000 },
3322 [GCC_VENUS0_BCR
] = { 0x4c014 },
3323 [GCC_MDSS_BCR
] = { 0x4d074 },
3324 [GCC_CAMSS_PHY0_BCR
] = { 0x4e018 },
3325 [GCC_CAMSS_CSI0_BCR
] = { 0x4e038 },
3326 [GCC_CAMSS_CSI0PHY_BCR
] = { 0x4e044 },
3327 [GCC_CAMSS_CSI0RDI_BCR
] = { 0x4e04c },
3328 [GCC_CAMSS_CSI0PIX_BCR
] = { 0x4e054 },
3329 [GCC_CAMSS_PHY1_BCR
] = { 0x4f018 },
3330 [GCC_CAMSS_CSI1_BCR
] = { 0x4f038 },
3331 [GCC_CAMSS_CSI1PHY_BCR
] = { 0x4f044 },
3332 [GCC_CAMSS_CSI1RDI_BCR
] = { 0x4f04c },
3333 [GCC_CAMSS_CSI1PIX_BCR
] = { 0x4f054 },
3334 [GCC_CAMSS_ISPIF_BCR
] = { 0x50000 },
3335 [GCC_CAMSS_CCI_BCR
] = { 0x51014 },
3336 [GCC_CAMSS_MCLK0_BCR
] = { 0x52014 },
3337 [GCC_CAMSS_MCLK1_BCR
] = { 0x53014 },
3338 [GCC_CAMSS_GP0_BCR
] = { 0x54014 },
3339 [GCC_CAMSS_GP1_BCR
] = { 0x55014 },
3340 [GCC_CAMSS_TOP_BCR
] = { 0x56000 },
3341 [GCC_CAMSS_MICRO_BCR
] = { 0x56008 },
3342 [GCC_CAMSS_JPEG_BCR
] = { 0x57018 },
3343 [GCC_CAMSS_VFE_BCR
] = { 0x58030 },
3344 [GCC_CAMSS_CSI_VFE0_BCR
] = { 0x5804c },
3345 [GCC_OXILI_BCR
] = { 0x59018 },
3346 [GCC_GMEM_BCR
] = { 0x5902c },
3347 [GCC_CAMSS_AHB_BCR
] = { 0x5a018 },
3348 [GCC_MDP_TBU_BCR
] = { 0x62000 },
3349 [GCC_GFX_TBU_BCR
] = { 0x63000 },
3350 [GCC_GFX_TCU_BCR
] = { 0x64000 },
3351 [GCC_MSS_TBU_AXI_BCR
] = { 0x65000 },
3352 [GCC_MSS_TBU_GSS_AXI_BCR
] = { 0x66000 },
3353 [GCC_MSS_TBU_Q6_AXI_BCR
] = { 0x67000 },
3354 [GCC_GTCU_AHB_BCR
] = { 0x68000 },
3355 [GCC_SMMU_CFG_BCR
] = { 0x69000 },
3356 [GCC_VFE_TBU_BCR
] = { 0x6a000 },
3357 [GCC_VENUS_TBU_BCR
] = { 0x6b000 },
3358 [GCC_JPEG_TBU_BCR
] = { 0x6c000 },
3359 [GCC_PRONTO_TBU_BCR
] = { 0x6d000 },
3360 [GCC_SMMU_CATS_BCR
] = { 0x7c000 },
3363 static const struct regmap_config gcc_msm8916_regmap_config
= {
3367 .max_register
= 0x80000,
3371 static const struct qcom_cc_desc gcc_msm8916_desc
= {
3372 .config
= &gcc_msm8916_regmap_config
,
3373 .clks
= gcc_msm8916_clocks
,
3374 .num_clks
= ARRAY_SIZE(gcc_msm8916_clocks
),
3375 .resets
= gcc_msm8916_resets
,
3376 .num_resets
= ARRAY_SIZE(gcc_msm8916_resets
),
3377 .gdscs
= gcc_msm8916_gdscs
,
3378 .num_gdscs
= ARRAY_SIZE(gcc_msm8916_gdscs
),
3381 static const struct of_device_id gcc_msm8916_match_table
[] = {
3382 { .compatible
= "qcom,gcc-msm8916" },
3385 MODULE_DEVICE_TABLE(of
, gcc_msm8916_match_table
);
3387 static int gcc_msm8916_probe(struct platform_device
*pdev
)
3390 struct device
*dev
= &pdev
->dev
;
3392 ret
= qcom_cc_register_board_clk(dev
, "xo_board", "xo", 19200000);
3396 ret
= qcom_cc_register_sleep_clk(dev
);
3400 return qcom_cc_probe(pdev
, &gcc_msm8916_desc
);
3403 static struct platform_driver gcc_msm8916_driver
= {
3404 .probe
= gcc_msm8916_probe
,
3406 .name
= "gcc-msm8916",
3407 .of_match_table
= gcc_msm8916_match_table
,
3411 static int __init
gcc_msm8916_init(void)
3413 return platform_driver_register(&gcc_msm8916_driver
);
3415 core_initcall(gcc_msm8916_init
);
3417 static void __exit
gcc_msm8916_exit(void)
3419 platform_driver_unregister(&gcc_msm8916_driver
);
3421 module_exit(gcc_msm8916_exit
);
3423 MODULE_DESCRIPTION("Qualcomm GCC MSM8916 Driver");
3424 MODULE_LICENSE("GPL v2");
3425 MODULE_ALIAS("platform:gcc-msm8916");